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44Thermocouplewith a Passive High Temperature Superconductor LegV.L.Kuznetsov University of OxfordM.V.VedernikovIoffe Physico-Technical Institute of the Russian Academy of Sciences 44.1Introduction...................................................................44-1 44.2Materials for an Active Leg...........................................44-2 44.3Materials for a Passive Leg............................................44-3 44.4Design and Properties of Thermoelementswith a Passive Leg..........................................................44-4 44.5Conclusion.....................................................................44-744.1IntroductionA semiconductor thermoelement(thermocouple)of a traditional design has two legs of n-and p-types. However,this is not a principal condition.Each leg brings positive and negative contributions to the energy conversion process.The positive one contributes in energy conversion while the negative one in energy losses due to thermal conduction through the legs and generation of Joule heat.The converted energy depends on thermoelectricﬁgure-of-merit Z of the materials of each leg.Theﬁgure-of-merit of a thermoelement Z np is maximum if Z n¼Z p¼Z np.However,in a general case Z n–Z p and the leg with worse properties signiﬁcantly reduces the thermoelement’sﬁgure-of-merit.In practice,this is not a rare situation when an efﬁcient thermoelectric material of only one type of conductivity is available for a speciﬁc temperature range,which makes it impossible to realize all the thermoelectric potential of an efﬁcient leg.The situation would change radically if an inefﬁcient leg also possesses low energy losses.In the extreme case,if the second leg possesses not only zeroﬁgure-of-merit but zero losses too,theﬁgure-of-merit of the thermoelement would be maximum because it would be equal to theﬁgure-of-merit of the efﬁcient leg.Unfortunately,this cannot be achieved using any materials with a normal conduction mechanism(with ohmic resistance),since according to the Wiedemann–Franz law,any increase in electrical conductivity will be compensated by a corresponding increase in the electronic thermal conductivity.Of course,there is no conductor in nature with zero electrical resistivity and zero thermal conductivity,but superconductor materials have zero resistivity and the thermal conduction of a semiconductor leg could be very small due to its small cross-section.Since the Seebeck coefﬁcient of a superconductor(in the superconductor state)is always zero,it is thermoelectrically passive(no contribution in energy conversion),but energy losses in this leg could be extremely low too,in comparison with those in the active leg.Thus,if a superconductor is used as a passive leg material,44-1it is possible to fabricate a thermoelement with a single efﬁcient thermoelectric material only which will realize almost all its efﬁciency.Is there a practical interest in a thermoelement with the superconductor leg?Previously,when only traditional superconductors were available,the application of the thermoelectric cooling using superconductor materials was thought impractical over the temperature range where normal superconductivity exists.The situation changed after the discovery of high temperature superconductors (HTSC).Thermoelectric cooling at temperatures near 100K becomes practically feasible if a high efﬁcient active leg material could be employed.The only thermoelectric material with a high ﬁgure-of-merit at T ,150K is n-type Bi 12x Sb x solid solution.However,good thermoelectric properties of this material have not been exploited because no efﬁcient p-type material is available for this temperature range.Thus,the situation is exactly as has been discussed above,using HTSC it would be possible to fabricate the thermoelement with a ﬁgure-of-merit value close to that of the best composition of Bi 12x Sb x solid solution.The following sections of this chapter present the properties of possible materials for active and passive legs,as well as design and testing results of thermoelements with a passive HTSC leg.44.2Materials for an Active LegFigure 44.1shows the temperature dependence of the ﬁgure-of-merit of several low-temperature thermoelectric materials.The most efﬁcient thermoelectric material at temperatures below 150K is single crystalline Bi 12x Sb x solid solution.1–3At 80K the highest ﬁgure-of-merit value of Z ¼6.5£1023K 21is reported along the trigonal axis of undoped Bi 0.85Sb 0.15single crystals.1If a magnetic ﬁeld of around 0.1T is applied along the bisectrix axes of the Bi 0.85Sb 0.15crystal,the Seebeck coefﬁcient and electrical resistivity increase simultaneously by 50to 60%,whereas the thermal conductivity slightly decreases.As a result,the ﬁgure-of-merit reaches a value of 11£1023K 21at 77K 1(Figure 44.1).To the best of the authors’knowledge this is the highest ever reported Z value among all known thermoelectric materials.N -type Bi 2Te 32x Se x ,and p-type Bi 22x Sb x Te 3solid solutions are the materials primarily used for thermoelectric cooling over a temperature range of 200to 300K.However,with decreasing temperature the ﬁgure-of-merit of these materials drops signiﬁcantly.At 120K the Bi 2Te 3based materials optimized for room-temperature applications exhibit a Z value of just 1.0£1023K 21,which decreases further to 0.6£1023K 21at 80K (Figure 44.1).4The best n-and p-type Bi 2Te 3based materials optimized for121086420050100150Temperature,KF i g u r e -o f -m e r i t Z ,x 10−3K −1200n -Bi 0.85Sb 0.15[2]n -Bi 0.85Sb 0.15(magn.field)[1]n,p -Bi 2Te 3-optimised [5,6]p -CePd 3[10,11]n -YbAl 3[9]p -CsBi 4Te 6[7,8]n,p -Bi 2Te 3-standard [4]250300350FIGURE 44.1The temperature dependence of the ﬁgure-of-merit of some low-temperature thermoelectricmaterials.Thermoelectrics Handbook:Macro to Nano44-2low-temperature applications exhibit Z value of around 2.2£1023K 21at 120K and around 1.4£1023K 21at 80K.5,6Recently Bi 22x Sb x Te 32y Se y solid solutions with Z ¼2.4£1023K 21at 100K have been developed;the results are presented in Chapter 37of this Handbook.A Z value of 3.6£1023K 21at 225K was reported for a new p-type CsBi 4Te 6thermoelectric material.7,8The ﬁgure-of-merit of CsBi 4Te 6exceeds slightly that of optimized low-temperature Bi 2Te 3-based materials over the range of 100to 250K (Figure 44.1),however,below 100K CsBi 4Te 6does not seem to offer any advantages over the optimized p-Bi 22x Sb x Te 3materials.Exceptionally large power-factor ða 2=r Þvalues were reported for several heavy fermion intermetallic materials containing Cerium and Ytterbium 9–11with the record value a 2/r ¼340£1026Wcm 21K 22observed in single crystalline YbAl 3at 100K.9Unfortunately,large thermal conductivity values (mainly due to the electronic contribution to the thermal conductivity)prevent these materials from achieving a high ﬁgure-of-merit.The highest Z values are reported for n-type YbAl 39and p-type CePd 310,11and do not exceed Z ¼1£1023K 21at 80to 130K (Figure 44.1).As seen,the best available active materials for the temperature range of around 80K are n-Bi 0.85Sb 0.15and p-Bi 22x Sb x Te 3solid solutions.However,the ﬁgure-of-merit of these materials at 80K differs by a factor of eight.Calculations indicates that the ﬁgure-of-merit of a thermoelement made of the best active materials would not exceed 4.8£1023K 21at 77K if a magnetic ﬁeld is applied,which is less than half of the corresponding Z value for n -Bi 0.85Sb 0.15.The maximum temperature drop across such a thermoelement at a hot junction temperature of 77K,as calculated from the properties of the materials,is 10.7K.However,if an ideal passive leg were used in combination with n-Bi 0.85Sb 0.15,ﬁgure-of-merit of the thermoelement would be Z ¼11£1023K 21and the temperature drop could reach 18.7K.The temperature dependence of the thermoelectric properties of the best n-Bi 0.85Sb 0.15samples along the trigonal axis is displayed in Figure 44.2.2,12The measured temperature variations of thermoelectric properties without magnetic ﬁelds are practically coincided with previously published data for the same solid solution composition.1The ﬁgure-of-merit of n-Bi 0.85Sb 0.15at 80K is 6.5£1023K 21and it tends to increase with a further decrease of temperature.The Bi 0.85Sb 0.15single crystals with properties presented in Figure 44.2were used for the fabrication of the most efﬁcient reported thermoelement with a passive HTSC leg.2,1244.3Materials for a Passive LegTo operate efﬁciently as a thermoelectrically passive leg a HTSC material should possess a low thermal conductivity to minimize thermal shunting of the active leg.There are three main classes of HTSC−60−80−100−120−140−160−180501001502002503000.08Temperature,KS e e b e c k c o e f f i c i e n t α,μV K −120253035E l e c t r i c a l r e s i s t i v i t y ρ,m Ωc mT h e r m a l c o n d u c t i v i t y λ,m W c m −1K −1400.100.120.140.160.18−200ρλαFIGURE 44.2The temperature dependence of single crystalline Bi 0.85Sb 0.15solid solution along the trigonal axis (without magnetic ﬁeld).2,12Thermocouple with a Passive High Temperature Superconductor Leg44-3suitable for practical applications,namely those based on yttrium (YBa 2Cu 3O 72x ),bismuth (a number of superconductor phases in the Bi–Sr–Ca–Cu–O system)and thallium (Tl–Ba–Ca–Cu–O system).Polycrystalline Bi-and Tl-based materials possess thermal conductivity values of around l 77K ¼7to 15mW cm 21K 21,which is two to three times lower than that of Y-based superconductors 13–15and 1.5to two times lower than the thermal conductivity of Bi 0.85Sb 0.15single crystals at liquid nitrogen temperature (Figure 44.1).The low thermal conductivity of the bismuth-and thallium-based superconductors is favorable for employing these materials as a passive leg of the thermoelement.Another important requirement for HTSC material is a high critical current density in presence of an external magnetic ﬁeld.The optimum current density,which provides the maximum cooling effect in Bi 0.85Sb 0.15single crystals is around 60Acm 22.The current density in the passive superconductor leg would be larger by a factor of S n /S p ,where S i is the leg cross-section area.In addition,to reach the maximum ﬁgure-of-merit value the active leg should be placed in a magnetic ﬁeld of around 0.1T and the magnet’s stray ﬁeld could affect the critical current density of the superconductor passive leg.Available today,pristine polycrystalline samples of HTSC exhibit the critical current density j c in the range of 103to 104Acm 22at 77K and in a magnetic ﬁeld of up to 1T,while in single crystalline HTSC samples j c can reach 105Acm 22.The highest critical current densities of j c ¼106Acm 22at 77K are achieved in epitaxial HTSC thin ﬁlms.16However,the high thermal conductivity of the substrate materials (180to 200mW cm 21K 21for SrTiO 3and around 800mW cm 21K 21for sapphire at 77K)imposes a serious limitation on the cross-section of the substrate of HTSC thin ﬁlms for an efﬁcient operation as a passive leg.It has been shown experimentally that a high temperature superconductor material can operate efﬁciently as a passive leg of the thermoelement at current densities higher than its critical current density.17,18As the current density in a HTSC sample exceeds the critical level,the material enters the mixed state and its resistivity has a ﬁnite but very small value,which increases slightly with increasing current density,and magnetic ﬁeld strength.While Joule heat dissipation does occur in HTSC material in the mixed state,at certain current densities and magnetic ﬁelds it is still smaller than the increment of the Peltier heat absorbed at the cold junction due to the current increment.Thus the limit to which the current through the passive leg can be increased is determined not by the critical current density of the HTSC material but rather by the allowable level of Joule heat dissipation.An important condition for the fabrication of an efﬁcient thermoelement is a low electrical contact resistance.An analysis of the dependence of Z value of a thermoelement on electrical contact resistance (per unit area)to a HTSC leg indicates that if the contact resistance exceeds 1£1025V cm 2,the Joule heat dissipated in the contacts dramatically degrades the thermoelement characteristics.At a contact resistance of 1£1026V cm 2the Joule heat dissipation at the contacts is negligible and the ﬁgure-of-merit of the thermoelement practically reaches its maximum value.Starting from the earlier stages of investigation of HTSC a lot of efforts have been focused on the development of low-resistance electrical contacts to HTSC materials.The best results were obtained by deposition of silver or gold on the sample surface followed by annealing;the electrical contact resistance as low as 10210V cm 2has been achieved using this procedure.1944.4Design and Properties of Thermoelements with a Passive LegTo date there have been several attempts to fabricate and test thermoelements with a passive leg made of HTSC materials.2,12,17,18,20–26Figure 44.3.shows the geometry of the thermoelement with the highest achieved coefﬁcient of performance.2,12The aligned arrangement of active and passive legs was suggested earlier 20in order to prevent deterioration of critical current density in the HTSC leg by removing it from the area of a strong magnetic ﬁeld.If HTSC materials with relatively low critical current density are employed,such an arrangement was found to lead to a higher coefﬁcient of performance of the thermoelement comparing to traditional P shaped geometry.2,12,17Without aThermoelectrics Handbook:Macro to Nano44-4magnetic ﬁeld,traditional P shaped thermoelements exhibit practically the same maximum temperature drop as that of the aligned thermoelements.2,12It should be pointed out that available now polycrystalline HTSC samples with critical current density of 104Acm 22in a ﬁeld of up to 1T would not require protection from the stray magnetic ﬁeld and could be employed in thermoelements with traditional P shape geometry.Figure 44.2presents the thermoelectric properties of the single crystalline Bi 0.85Sb 0.15used as the active legs material for fabrication of thermoelements with the aligned geometry (Figure 44.3).Polycrystalline molten BiSrCaCu 2O x samples with critical temperature of 87K and critical current density of j c ¼120Acm 22at 77K in zero magnetic ﬁeld were used as the passive leg material.Electrical contacts with contact resistance of r c ¼1£1026V cm 2at 77K were fabricated by electrolytic deposition of a silver layer on the surface of HTSC material followed by subsequent annealing.The parameters of the thermoelement displayed in Figure 44.3were measured in a small evacuated brass cell fully immersed in liquid nitrogen.The temperatures of the hot and cold junctions were measured with copper-constantan thermocouples;the copper and constantan wires had a diameter of 0.02mm and 0.1mm,respectively.The reference junctions of the measuring copper-constantan thermocouples were placed in liquid nitrogen and the temperature difference along the thermoelement was determined with accuracy of better than 0.05K.To increase the ﬁgure-of-merit of the active Bi 0.85Sb 0.15leg,permanent ferrite magnets were placed close to the active leg (Figure 44.3).The optimum magnetic ﬁeld of 0.14T,which provides the maximum ﬁgure-of-merit of the active leg,was determined experimentally by varying the magnetic pole gap.The experimental and calculated properties of the thermoelement are presented in Table 44.1(lines one,two).The hot-side temperature (T hot ),magnetic ﬁeld strength (H ),and the maximum temperaturedifference along the thermoelement ðD T expmaxÞwere determined experimentally.The ﬁgure-of-merit of the thermoelement Z exp was calculated from D T expmax using the relation Z exp ¼2D T exp max=ðT hot 2D T exp max Þ2:Thus,Z exp values take into account parasitic effects like heat ﬂow through the passive leg and Joule heat generation due to a nonzero contact resistance,whereas Z calc was calculated from the material properties,contact resistance,heat losses,and heat load introduced by measuring copper-constantan wires.As seen from Table 44.1,the Z exp and Z calc values without magnetic ﬁeld are in a good agreement,and the measured ﬁgure-of-merit of the thermoelement is very close to that of the Bi 0.85Sb 0.15active leg.In a magnetic ﬁeld the experimental value of Z exp ¼8.6£1023K 21is somewhat less than Z calc ¼11£1023K 21of the Bi 0.85Sb 0.15active leg calculated from the material’s properties.1This difference could be attributed to the transition of the superconductor leg into a mixed state with the corresponding generation of additional Joule heat.The properties of the thermoelement with a passive leg were also measured at temperatures below 77K.The temperature was lowered by pumping off the liquid nitrogen vapor and maintained at aFIGURE 44.3The geometry of a thermoelement with the aligned arrangement of the active and passive legs;the active leg is placed between magnet poles.44-5constant level during the measurements using an electrical heater located on the casing of the measuring brass cell.The experimental results are presented in Figure 44.4,which display the maximumtemperature drop along the thermoelement D T expmax and the ﬁgure-of-merit of the thermoelement Z calccalculated from D T expmax as a function of hot-side temperature.A slight increase in Z calc observed during the measurements with and without magnetic ﬁeld could be attributed to a combination of a possible increase in the ﬁgure-of-merit of the Bi 0.85Sb 0.15active leg at T ,77K,and an increase in the critical current density of the passive leg with decreasing temperature.In lines three to six in Table 44.1is presented a comparison of experimental results for thermoelements with a passive HTSC and active p -type Bi 22x Sb x Te 3legs.18Employing HTSC leg leads to a 50%increase in D T expmaxvalues with and without magnetic ﬁeld.Since n-type Bi 0.93Sb 0.07used in the thermoelements is less efﬁcient than Bi 0.85Sb 0.15,the achieved D T expmax is lower than that reported later in Refs.[2,27].In 1992,several papers were published on the development of one-and two-stage modules with a passive leg made of HTSC thin ﬁlm.21,25,26The maximum temperature drop from 77to 61.3K was achieved in a magnetic ﬁeld using a one-stage module,while a two-stage module demonstrated cooling from 85to 61.2K.Although Bi 0.91Sb 0.09crystals used for the fabrication of modules do not exhibit the highest ﬁgure-of-merit among Bi 12x Sb x solid solutions,employing high j c HTSC ﬁlms on a thin substrate enabled achieving temperature drop of 15.7K for one-stage module.TABLE 44.1Experimental and Calculated Properties of Thermoelements with Passive HTSC LegsNo ThermoelementT hot (K)H ,T D T exp max (K)Z exp (K 21)Z calc (K 21)Refs.1Bi 0.85Sb 0.15–BiSrCaCu 2O x 78.5013.4 6.3£10236.5£10232,122Bi 0.85Sb 0.15–BiSrCaCu 2O x78.30.1416.48.6£1023—2,123Bi 0.93Sb 0.07–Bi 22x Sb x Te 32y Se y 78.60 2.9 1.1£1023 1.1£1023184Bi 0.93Sb 0.07–Bi 22x Sb x Te 32y Se y 78.60.10 4.2 1.6£1023—185Bi 0.93Sb 0.07–BiSrCaCu 2O x 78.10 6.5 2.6£1023 2.6£1023186Bi 0.93Sb 0.07–BiSrCaCu 2O x78.20.109.1 4.0£1023—187Bi 0.91Sb 0.09–YBa 2Cu 3O 72d (ﬁlm)8509.5 3.3£1023—218Bi 0.91Sb 0.09–YBa 2Cu 3O 72d (ﬁlm)850.0714.4 5.8£1023—219Bi 0.91Sb 0.09–YBa 2Cu 3O 72d 77011.4 5.3£1023—2110Bi 0.91Sb 0.09–YBa 2Cu 3O 72d 770.0715.78.4£1023—2111Bi 12x Sb x –YBa 2Cu 3O 72d770 5.4 2.1£1023 2.0£10232212Bi 0.89Sb 0.11–(Bi,Pb)2Sr 2Ca 2Cu 3O y 7807.1 2.8£1023—2313Bi 0.88Sb 0.12–YBa 2Cu 3O 72d 750.077.3 3.2£1023—2414Bi 0.88Sb 0.12–YBa 2Cu 3O 72d700.076.63.3£1023—24554567891011181614121086065Hot junction temperature,KH =0TH =0.14TT e m p e r a t u r e d i f f e r e n c e ∆T m a x ,KF i g u r e -o f -m e r i t Z ,10−3K −170758085FIGURE 44.4Figure-of-merit and maximum temperature difference of the thermoelement with a passive leg as a function of hot junction temperature with magnetic ﬁeld (open symbols)and without magnetic ﬁeld (solid symbols).Lines are a guide for the eyes only.Thermoelectrics Handbook:Macro to Nano44-6Thermocouple with a Passive High Temperature Superconductor Leg44-7Some later articles22–24presented the results of testing different versions of thermoelements with a passive superconductor leg.The reported D T exp max values did not exceed7.3K due to nonoptimized composition of active Bi12x Sb x legs as well as a low critical current density of superconductor materials.44.5ConclusionIt is of interest to note that Goldsmid in1986in his book“Electronic Refrigeration”4discussed in details the topic of thermoelectric cooling at very low temperatures.He referred to some earlier considerations that it would be necessary to have only one thermoelectric material for a thermoelement if a superconductor leg is used.However,there were no further comments or analysis of such thermoelements.In1989,Goldsmid with coauthors made theﬁrst attempt to realize experimentally a thermoelement with a passive HTSC leg.20The attempt failed due to the absence of good high temperature superconductor materials with a high critical current density,although the problem was analyzed correctly.Before long,thermoelements,which exhibit maximum temperature drops very close to the calculated value based on measured thermoelectric properties of the used Bi0.85Sb0.15material, have been constructed and tested.2,12,17,18,27It means that the superconductor material in these thermoelements operates as almost an ideal passive leg and the high thermoelectricﬁgure-of-merit of the active leg is realized completely.Thermoelements with active Bi12x Sb x and passive HTSC legs offer an opportunity to extend thermoelectric cooling to cryogenic temperatures and could have practical applications for a small-scale cooling of sensors and other devices by10to15K below the liquid nitrogen temperature without employing expensive cryogenic techniques.An example of a liquid nitrogen-ﬁlled cryostat incorporating a Bi12x Sb x–YBa2Cu3O72x thermoelement has been described,which is capable of cooling and stabilizing the operating temperature of a photodetector array.28Another area of practical applications could be highly sensitive photo-thermoelectric bolometers employing Bi12x Sb x–YBa2Cu3O72xﬁlm thermoelements.29References1.Yim,W.M.and Amith,A.,Bi–Sb alloys for magneto–thermoelectric and thermomagneticcooling,Solid-State Electron.,15,1141–1165,1972.2.Kuznetsov,V.L.,Vedernikov,M.V.,Jandl,P.,and Birkholz,U.,Present limit of thermoelectriccooling at liquid-nitrogen temperature,Sov.J.Tech.Phys.Lett.,20(18),75–80,1994.3.Zemskov,V.S.,Belaya,A.D.,Beluy,U.S.,and Kozhemyakin,G.N.,Growth and investigation ofthermoelectric properties of Bi–Sb alloy single crystals,J.Cryst.Growth,212(1-2),161–166,2000.4.Goldsmid,H.J.,Electronic Refrigeration,p.227.Pion Ltd.,London,1986.5.Vedernikov,M.V.,Kutasov,V.A.,Kuznetsov,V.L.,Luk’yanova,L.N.,Konstantinov,P.P.,Ageev,Yu.A.,Alexeeva,G.T.,Ravich,Yu.I.,Fedorov,M.I.,Izupak,E.A.,Gladkikh,L.M.,and Bash,I.M., Thermoelectric cooling to130K and lower temperature,pp.185–190.In Proceedings of the XIII International Conference on Thermoelectrics,Kansas City,MO,1994.6.Yim,W.M.and Rosi,F.D.,Compound tellurides and their alloys for Peltier cooling,a review,Solid-State Electron.,15,1121–1140,1972.7.Chung,D.Y.,Hogan,T.,Brazis,P.,Rocci-Lane,M.,Kannewurf,C.,Bastea,M.,Uher,C.,andKanatzidis,M.G.,CsBi4Te6:a high-performance thermoelectric material for low-temperature applications,Science,287(5455),1024–1027,2000.8.Chung,D.Y.,Hogan,T.,Rocci-Lane,M.,Brazis,P.,Ireland,J.R.,Kannewurf,C.,Bastea,M.,Uher,C.,and Kanatzidis,M.G.,A new thermoelectric material:CsBi4Te6,J.Am.Chem.Soc., 126(20),6414–6428,2004.9.Rowe,D.M.,Kuznetsov,V.L.,Kuznetsova,L.A.,and Min,G.,Electrical and thermal transportproperties of intermediate-valence YbAl3,J.Phys.D:Appl.Phys.,35(17),2183–2186,2002.10.Gambino,R.J.,Grobman,W.D.,and Toxen,A.M.,Anomalously large thermoelectric cooling ﬁgure-of-merit in the Kondo systems CePd 3and CeIn 3,Appl.Phys.Lett.,22(10),506–507,1973.11.Schneider,H.and Wohlleben,D.,Electrical and thermal conductivity of CePd 3,YPd 3,GdPd 3and dome dilute alloys of CePd 3,with Y and Gd,Z,Phys.B Condens.Matter ,44,193–202,1981.12.Kuznetsov,V.L.,Vedernikov,M.V.,Birkholz,U.,and Jandl,P .,Investigation of maximal possibility of thermoelectric cooling at liquid nitrogen temperature,pp.423–428.Proceedings of the XII International Conference on Thermoelectrics ,Yokohama,Japan,1993.13.Uher,C.,Thermal-conductivity of high T c superconductors,J.Supercond.,3(4),337–389,1990.14.Castello,D.,Jaime,M.,and Regueiro,M.N.,Thermal conductivity of high-temperature superconductor TlBaCaCuO,Solid-State Commun.,79(11),967–970,1991.15.Regueiro,M.D.N.and Castello,D.,Thermal-conductivity of high-temperature superconductors,Int.J.Mod.Phys.,5(12),2003–2035,1991.16.Fedotov,Y.V.,Ryabchenko,S.M.,Pashitskii,E.A.,Semenov,A.V.,Vakaryuk,V.I.,Pan,V.M.,and Flis,V.S.,Magnetic-ﬁeld and temperature dependence of the critical current in thin epitaxial ﬁlms of the high-temperature superconductor YBa 2Cu 3O 72d ,Low Temp.Phys.,28(3),172–183,2002.17.Kuznetsov,V.L.,Vedernikov,M.V.,Ditman,A.V.,Melekh,B.T.,and Burkov,A.T.,The effective thermoelement with thermoelectrically passive leg from high T c superconductor,Supercond.:Phys.Chem.Technol (In Russian),4(3),616–625,1991.18.Vedernikov,M.V.,Kuznetsov,V.L.,Ditman,A.V.,Melech,B.T.,and Burkov,A.T.,Efﬁcient thermoelectric cooler with a thermoelectrically passive high T c superconducting leg,pp.96–101.Proceedings of the X International Conference on Thermoelectrics ,Cardiff,UK,1991.19.Ekin,J.W.,Larson,T.M.,Bergren,N.F.,Nelson,A.J.,Swartzlander,A.B.,Kazmerski,L.L.,Panson,A.J.,and Blankenship,B.A.,High T c superconductor/noble-metal contacts with surface resistivities in the 1026V cm 2range,Appl.Phys.Lett.,52(21),1819–1821,1988.20.Goldsmid,H.J.,Gopinathan,K.K.,Matthews,D.N.,Taylor,K.N.R.,and Baird,C.A.,High T c superconductors as passive thermo-elements,J.Phys.D:Appl.Phys.,21(2),344–348,1988.21.Mosolov,A.B.and Sidorenko,N.A.,Application of high T c superconducting materials in cryogenic Peltier coolers,Cryogenics ,32,36–39,1992.22.Fee,M.G.,Peltier refrigerator using a high T c superconductor,Appl.Phys.Lett.,62(10),1161–1163,1993.23.Nakano,T.and Hashimoto,T.,Refrigeration character of new-type Peltier refrigerator using high T c (Bi,Pb)2Sr 2Ca 2Cu 3O y superconductor,Jpn.J.Appl.Phys.,Part 2Lett.,33(12A),L1728–L1731,1994.24.Mino,C.C.,Cochrane,J.W.,Volckmann,E.H.,and Russell,G.J.,Cryogenic thermoelectric cooler with a passive branch,J.Electron.Mater.,26(8),915–921,1997.25.Dashevskii,Z.M.,Sidorenko,N.A.,Tsvetkova,N.A.,Skipidarov,C.Y.,and Mosolov,A.V.,Cryogenic thermoelectric coolers with passive high T c superconductor branches,Supercond.Sci.Technol.,5(11),690–693,1992.26.Sidorenko,N.A.,Thermoelectric-materials for Peltier cryogenic coolers,Cryogenics ,32,40–43,1992.27.Vedernikov,M.V.and Kuznetsov,V.L.,Cooling thermoelements with superconducting leg.In CRC Handbook of Thermoelectrics ,D.M.Rowe,ed.,pp.609–616.CRC Press,Boca Raton,New York,London,Tokyo,1995.28.Sidorenko,N.A.,Example of application of thermoelectric cooler with high T c superconducting elements,pp.438-441.Proceedings of the XIII International Conference on Thermoelectrics ,Kansas City,MO,1994.29.Kaila,M.M.and Russell,G.J.,A photo-thermoelectrical YBCO-BiSb thick ﬁlm bolometer,J.Phys.D:Appl.Phys.,31(16),1987–1990,1998.Thermoelectrics Handbook:Macro to Nano44-8。

PT2264-S中文资料

Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 DESCRIPTIONPT2264 is a remote control encoder paired with PT2294 utilizing CMOS Technology. It encodes data and address pins into a serial coded waveform suitable for RF modulation. PT2264 has a maximum of 12 bits of tri-state address pins providing up to 531,441 (or 312) address codes; thereby, drastically reducing any code collision and unauthorized code scanning possibilities.FEATURES• CMOS Technology•Low Power Consumption•Very High Noise Immunity•Up to 12 Tri-State Code Address Pins•Up to 4 Data Pins•Wide Range of Operating Voltage: VCC = 8 ~ 15 V•Single Resistor Oscillator•Latch or Momentary Output Type•Available in DIP and SO PackageAPPLICATIONS•Remote Control Fan•Home Security/Automation System•Remote Control Toys•Remote Control for Door BellFax: 886-2-29174598 URL: Remote Control Encoder IC PT2264BLOCK DIAGRAMAddressSystem TimingControl LogicCode GenerationOSCA0A1A2A3A4A5A6A7A8/D3A9/D2A10/D1A11/D0OSC1OSC2/TEDOUTA0A1A2VCC A9/D2DOUT A8/D3OSC2NCA5A11/D0A6A3OSC1A10/D1A4/TE 1202193184178131011714912615516PT2264-SA7VSS NCA0A1A2VCC A9/D2DOUT A8/D3OSC2A5A11/D0A6A3OSC1A10/D1A4/TE 118217316415811712910613514PT2264PT2264-18SA7VSSFax: 886-2-29174598 URL: Remote Control Encoder IC PT2264PIN DESCRIPTIONPin No.Pin NameI/ODescription18 Pins 20 Pins A0~A7 ICode Address Pin Nos.0 ~ 7These ten tri-state pins are detected by PT2264 todetermine the encoded waveform bit 0 ~ bit 9. Each pin can be set to “0”, “1” or “f” (floating ).1 ~ 81 ~ 8A8/D3 ~A11/D0I Code Address Pin Nos.8 ~ 11/Data Pin Nos.0 ~ 3.These four tri-state pins are detected by PT2264 to determine the encoded waveform bit10, bit11.When these pins are used as address pins, theycan be set to “0”, “1”, or “f” (floating).When these pins are used as data pins, they can be set only to “0” or “1”. 10 ~ 13 12 ~ 15/TE I Transmission Enable.Active Low Signal. PT2264 outputs the encodedwaveform to DOUT when this pin is pulled to low.14 16 OSC 1 O Oscillator Pin No.1 1517OSC 2 I Oscillator Pin No.2A resistor connectedbetween these two pinsdetermine thefundamental frequency of the PT2264.16 18DOUT OData Output Pin.The encoded waveform is serially outputted to thispin. When PT2264 is not transmitting, DOUT outputs low (VSS) voltage.17 19 VCC - Positive Power Supply 18 20 VSS - Negative Power Supply 99Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 FUNCTIONAL DESCRIPTIONPT2264 encodes the code address and data set at A0 ~ A7 and A8/D3 ~ A11/D0 into a special waveform and outputs it to the DOUT when /TE is pulled to “0” (Low State). This waveform is fed to either the RF modulator for transmission. The transmitted radio frequency is received by the RF demodulator receiver and reshaped to the special waveform. PT2294 is then used to decode the waveform and set the corresponding output pin(s). Thus completing a remote control encoding and decoding function.RF OPERATIONCODE BITSA Code Bit is the basic component of the encoded waveform, and can be classified as either an AD (Address/Data) Bit or a SYNC (Synchronous) Bit.Address/Data (AD) Bit WaveformAn AD Bit can be designated as Bit “0”, “1” or “f” if it is in low, high or floating state respectively. One bit waveform consists of 2 pulse cycles. Each pulse cycle has 16 oscillating time periods. For further details, please refer to the diagram below:OSC1 bit = 32BIT 04BIT 1124BIT fFloatingwhere: = Oscillating Clock PeriodSynchronous (Sync.) Bit WaveformThe Synchronous Bit Waveform is 4 bits long with 1/8 bit width pulse. Please refer to the diagram below:1/8 bit width = 44 bit width = 128Note: 1 bit = 32Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 CODE WORDA group of Code Bits is called a Code Word. A Code Word consists of 12 AD bits followed by one Sync Bit. The 12 AD bits are determined by the corresponding states of A0 ~ A7 and A8/D3 ~ A11/D0 pins at the time of transmission. When Data Type of PT2264 is used, the address bits will decrease accordingly.For example: In the 4 Datas Type where the address has eight (8) bits, the transmitting format is:8 Address Bits 4 Data Bits Sync. BitPT2264 / PT2294 have a maximum of twelve (12) Address Bits, four (4) Address/Data bits. The following diagram shows the code bits with their corresponding pins.First bit transmitted↓A0 A1 A2 A3 A4 A5 A6 A7 A8/D3 A9/D2 A10/D1 A11/D0 SYNC BITCodeWordCompleteOneData A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SyncBit 0Bit Data A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D0 Sync1Data A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D1 D0 SyncBit 2Bit Data A0 A1 A2 A3 A4 A5 A6 A7 A8 D2 D1 D0 Sync3Bit Data A0 A1 A2 A3 A4 A5 A6 A7 D3 D2 D1 D0 Sync4The Code Bits A0 ~ A7 and A8/D3 ~ A11/D0 are determined by the states of A0 ~ A7 and A8/D3 ~A11/D0 pins. For example, when the A0 (Pin No. 1) is set to “1” (VCC), the Code Bit A0 is synthesized as “1” bit. In the same manner, when it (A0 Pin) is set to “0” (VSS) or left floating, the Code Bit A0 is synthesized as a “0” or “f” bit respectively.Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 CODE FRAMEA Code Frame consists of four (4) continuous Code Words. When PT2264 detects “0” on the /TE (meaning, the /TE is active “low”), it outputs a Code Frame at DOUT. If /TE is still active at the time the Code Frame transmission ends, PT2264 outputs another Code Frame. It should be noted that the Code Frame is synthesized at the time of transmission./TEDOUTone frame (=4 word)one frame one frameSIGNAL RESISTOR OSCILLATORThe built–in oscillator circuitry of PT2264 allows a precision oscillator to be constructed by connecting an external resistor between OSC1 and OSC2 pins. For PT2294 to decode correctly the received waveform, the oscillator frequency of PT2294 must be 2.5 ~ 8 times that of transmitting PT2264. The typical oscillator with various resistor values are shown below for PT2264 and PT2294.100101KHz3 6 9 12 15V O L T A G E R = 510 KR = 1 M R = 2 MR = 3.3 M R = 4.7 MPT2264 Encoder OSC FrequencyFax: 886-2-29174598 URL: Remote Control Encoder IC PT2264PT2294 DECODER OSC FREQUENCYSuggested oscillator resistor values are shown below.PT2264 PT2294 1.2M Ω 120K Ω 1.5M Ω 160K Ω 3.3M Ω 390K Ω2040608010012014016018024681012VOLTAGE (V)F R E Q U E N C Y (K H z )Rosc =510K ΩRosc=620K ΩRosc=1.0M ΩRosc=1.2M ΩRosc=2.2 M ΩFax: 886-2-29174598 URL: Remote Control Encoder IC PT2264OPERATION FLOW CHARTPower ONStand-by Mode/TE Enable/TE Still Enable4 Words of Address/Data TransmittedYesYesYesNoNoFax: 886-2-29174598URL: Remote Control Encoder IC PT2264 ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Ratings Unit Supply Voltage VCC -0.3 ~ 16.0 VInput Voltage VI -0.3 ~ VCC+0.3 VOutput Voltage VO -0.3 ~ VCC+0.3 VMaximum Power Dissipation Pa VCC = 12 V 300 mWOperating Temperature Topr -40 ~ +85 ℃Storage Temperature Tstg -65 ~ +150 ℃DC ELECTRICAL CHARACTERISTICSParameter Symbol Conditions Min. Typ. Max. Unit Supply Voltage VCC 8.0 - 15 VStand-by Current ISBVCC=12VOSC2=12VA0 ~ A11 Open- 0.1 1 µAVCC = 8VVOH = 4V-6 - - mADOUT Output Driving Current IOHVCC = 12VVOH = 6V-10 - - mAVCC = 8V VOL = 4V 5 - - mADOUT Output Sinking Current IOLVCC = 12VVOL = 6V9 - - mAFax: 886-2-29174598 URL: Remote Control Encoder IC PT2264APPLICATION CIRCUIT4 Datas transmitter circuit is recommended. Pin 1~8 Address Datas can be selected by custom’s design.A0A1A2VCC A9/D2DOUT A8/D3OSC2A5A11/D0A6A3OSC1A10/D1A4/TE 118217316415811712910613514A7VSSRF+-SW0SW112VRoscPT2264SW3SW22.7K x 410K x 4IN4148 x 4Note: Suggested oscillator resistor values (Rosc), please refer to page 7.Fax: 886-2-29174598 URL: Remote Control Encoder IC PT2264Zero Data transmitter circuit is recommended. Pin 1~8, Pin 10~13 Address Datas can be selected by custom’s design.A0A1A2VCC A9/D2DOUT A8/D3OSC2A5A11/D0A6A3OSC1A10/D1A4/TE 118217316415811712910613514A7VSSRFSWVCCPT2264RoscNote: Suggested oscillator resistor values (Rosc), please refer to page 7.Zero-Stand-by transmitter circuit is recommended. Pin 1~8, Pin 10~13 Address Datas can be selected by custom’s design.A0A1A2VCC A9/D2DOUT A8/D3OSC2A5A11/D0A6A3OSC1A10/D1A4/TE 118217316415811712910613514A7VSSRFSWPT2264+-12VRoscNote: Suggested oscillator resistor values (Rosc), please refer to page 7.Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 ORDERING INFORMATIONOrder Part Number Package Type Top odePT2264 18 Pins, DIP Package, 300mil PT2264PT2264-18S 18 Pins, SOP Package, 300mil PT2264-18SPT2264-S 20 Pins, SOP Package, 300mil PT2264-SPT2264 (L) 18 Pins, DIP Package, 300mil PT2264PT2264-18S (L) 18 Pins, SOP Package, 300mil PT2264-18SPT2264-S (L) 20 Pins, SOP Package, 300mil PT2264-SNotes:1. (L) = Lead Free2. The Lead Free mark is put in front of the date code.Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 PACKAGE INFORMATION18 PINS DIP PACKAGE, 300MILFax: 886-2-29174598URL: Remote Control Encoder IC PT2264Symbol Min. Nom. Max.0.210AA1 0.015A2 0.115 0.1300.1950.022b 0.0140.0180.0180.020b1 0.0140.0600.070b2 0.0450.0450.039b3 0.0300.014c 0.0080.0100.0100.011c1 0.0080.920D 0.8800.900D1 0.005E 0.3000.3250.3100.280E1 0.240 0.250e 0.100bsc.bsc.eA 0.300eB 0.430eC 0.000 0.0600.150L 0.1150.130Notes：1. All dimensions are in INCHS.2. Dimensioning and tolerancing per ANSI Y14.5M-1982.3. Dimensions “A”, “A1” and “L” are measured with the package seated in JEDEC Seating PlaneGauge GS-3.4. “D”, “D1” and “E1” dimensions do not include mold flash or protrusions. Mold flash or protrusionsshall not exceed 0.010 inch.5. “E” and “eA” measured with the leads constrained to be perpendicular to datum -c-.6. “eB” and “eC” are measured at the lead tips with the loads unconstrained.7. “N” is the number of terminal positions. (N=18)8. Pointed or rounded lead tips are preferred to ease insertion.9. “b2” and “b3” maximum dimensions are not include dambar protrusions. Dambar protrusions shallnot exceed 0.010 inch (0.25 mm).10. Distance between leads including Dambar protrusions to be 0.005 inch minimum.11. Datum plane -H- coincident with the bottom of lead, where lead exits body.12. Refer to JEDEC MS-001 Variation AC.JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.Fax: 886-2-29174598 URL: Remote Control Encoder IC PT226418 PINS SOP PACKAGE, 300MIL-B-E H .25 (.010) M B M.25 (.010) M C A M B SA1A SEATING PLANE-C-.10 (.004)-A-D-e-BLh X 45C∞N123INDEX AREASymbol Min. Nom. Max. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 11.35 11.75 E 7.40 7.60 e 1.27 bsc. H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0°8°Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 Notes：1. Dimensioning and tolerancing per ANSI Y14.5M-1982.2. Dimension〝D〞does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate burrs shall not exceed 0.15 mm (0.006 in) per side.3. Dimension〝E〞does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm (0.010 in) per side.4. The chamfer on the body is optional. It is not present, a visual index feature must be located within the crosshatched area.5.〝L〞is the length of the terminal for soldering to a substrate.6. N is the number of the terminal positions (N=18)7. The lead width〝B〞as measured 0.36 mm (0.014 in) or greater above the seating plane, shall notexceed a maximum value of 0.61 mm (0.24 in).8. Controlling dimension：MILLIMETER.9. Refer to JEDEC MS-013, Variation AB.JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.Fax: 886-2-29174598 URL: Remote Control Encoder IC PT226420 PINS, SOP PACKAGE, 300MIL-B-E H .25 (.010) M B M.25 (.010) M C A M B SA1A SEATING PLANE-C-.10 (.004)-A-D-e-BLh X 45C∞N123INDEX AREASymbol Min. Nom. Max. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 bsc. H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0°8°Fax: 886-2-29174598URL: Remote Control Encoder IC PT2264 Notes：1. Dimensioning and tolerancing per ANSI Y14.5M-1982.2. Dimension〝D〞does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate burrs shall not exceed 0.15 mm (0.006 in) per side.3. Dimension〝E〞does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm (0.010 in) per side.4. The chamfer on the body is optional. It is not present, a visual index feature must be located within the crosshatched area.5.〝L〞is the length of the terminal for soldering to a substrate.6. N is the number of the terminal positions (N=20)7. The lead width〝B〞as measured 0.36 mm (0.014 in) or greater above the seating plane, shall notexceed a maximum value of 0.61 mm (0.24 in).8. Controlling dimension：MILLIMETER.9. Refer to JEDEC MS-013, Variation AC.JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.。

商品编码：商品归类代码说明（26）

-商品名称编码附加编码附加序号说明磁铁矿粉 26011100 - 001 未烧结铁矿粉 26011100 - 002 未烧结铁矿砂 26011100 - 003 未烧结铁矿砂精矿 26011100 - 004 -铁矿⽯ 26011100 - 005 未烧结未烧结铁矿砂 26011100 - 006 -已烧结铁矿砂 26011200 - 001 -焙烧黄铁矿 26012000 - 001 -⼆氧化锰矿 26020000 - 001 -褐锰矿 26020000 - 002 -⿊锰矿 26020000 - 003 -菱锰矿 26020000 - 004 -锰矿 26020000 - 005 -软锰矿 26020000 - 006 -⽔合⼆氧化锰矿 26020000 - 007 -⽔合氧化锰矿 26020000 - 008 -⽔锰矿 26020000 - 009 -碳酸锰矿 26020000 - 010 -盐⽔氧化锰矿 26020000 - 011 -氧化锰矿 26020000 - 012 -硬锰矿 26020000 - 013 -黝锰矿 26020000 - 014 -斑铜矿 26030000 90 001 ⾮黄⾦价值部分车轮矿 26030000 90 002 ⾮黄⾦价值部分⾚铜矿 26030000 90 003 ⾮黄⾦价值部分靛铜矿 26030000 90 004 ⾮黄⾦价值部分硅孔雀⽯ 26030000 90 005 ⾮黄⾦价值部分硅酸铜矿 26030000 90 006 ⾮黄⾦价值部分⿊铜矿 26030000 90 007 ⾮黄⾦价值部分黄铜矿 26030000 90 008 ⾮黄⾦价值部分辉铜矿 26030000 90 009 ⾮黄⾦价值部分碱式硫酸铜矿 26030000 90 010 ⾮黄⾦价值部分碱式碳酸铜矿 26030000 90 011 ⾮黄⾦价值部分孔雀⽯ 26030000 90 012 ⾮黄⾦价值部分蓝铜矿 26030000 90 013 ⾮黄⾦价值部分硫化铜矿 26030000 90 014 ⾮黄⾦价值部分硫砷铜矿 26030000 90 015 ⾮黄⾦价值部分氯铜矿 26030000 90 016 ⾮黄⾦价值部分砷黝铜矿 26030000 90 017 ⾮黄⾦价值部分⽔胆矾矿 26030000 90 018 ⾮黄⾦价值部分⽔合硅酸铜矿 26030000 90 019 ⾮黄⾦价值部分⽔硫酸铜矿 26030000 90 020 ⾮黄⾦价值部分天然羟基氯化铜矿 26030000 90 021 ⾮黄⾦价值部分铜精矿 26030000 90 022 ⾮黄⾦价值部分铜矿粉 26030000 90 023 ⾮黄⾦价值部分铜矿砂 26030000 90 024 ⾮黄⾦价值部分铜矿砂精矿 26030000 90 025 ⾮黄⾦价值部分铜铅锑硫化物矿 26030000 90 026 ⾮黄⾦价值部分铜砷硫化物矿 26030000 90 027 ⾮黄⾦价值部分铜锑硫化物矿 26030000 90 028 ⾮黄⾦价值部分铜铁硫化物矿 26030000 90 029 ⾮黄⾦价值部分氧化正铜矿 26030000 90 030 ⾮黄⾦价值部分黝铜矿 26030000 90 031 ⾮黄⾦价值部分硅镁镍矿 26040000 - 001 -含镍磁黄铁矿 26040000 - 002 -镍铁硫化物矿 26040000 - 008 -砷化镍矿 26040000 - 009 -辉钴矿 26050000 - 001 -硫钴矿 26050000 - 002 -砷钴矿(砷化钴矿) 26050000 - 003 - ⽔合氧化钴 26050000 - 004 -⽔钴矿 26050000 - 005 -钴矿砂 26050000 - 006 -钴硫化物矿 26050000 - 007 -钴镍硫化物矿 26050000 - 008 -钴砷化物矿 26050000 - 009 -铝矿砂 26060000 - 001 -铝⼟矿 26060000 - 002 -⽩铅矿 26070000 - 001 -⽅铅矿 26070000 - 002 -磷氯铅矿 26070000 - 003 -铅矾 26070000 - 004 -铅精矿 26070000 - 005 -铅矿粉 26070000 - 006 -铅矿砂 26070000 - 007 -铅矿⽯ 26070000 - 008 -碳酸铅矿 26070000 - 009 -红锌矿 26080000 - 001 -菱锌矿 26080000 - 002 -硫化锌矿 26080000 - 003 -氢化硅酸锌矿 26080000 - 004 -闪锌矿 26080000 - 005 -碳酸锌矿 26080000 - 006 -锌精矿 26080000 - 007 -锌矿粉 26080000 - 008 -锌矿砂 26080000 - 009 -氧化锌矿 26080000 - 010 -异极矿 26080000 - 011 -黄锡矿 26090000 - 001 -锡矿砂 26090000 - 002 -锡⽯ 26090000 - 003 -锡铜铁硫化物矿 26090000 - 004 - 氧化锡矿 26090000 - 005 -铬矿 26100000 - 001 -铬矿(铬铁矿) 26100000 - 002 -铬矿砂 26100000 - 003 -铬铁氧化物矿 26100000 - 004 -⽩钨矿 26110000 - 001 -⿊钨矿 26110000 - 002 -铁锰钨酸盐矿 26110000 - 003 -钨矿砂 26110000 - 004 -钨锰矿 26110000 - 005 -钨砂 26110000 - 006 --钨酸钙矿 26110000 - 007 -钨酸锰矿 26110000 - 008 -钨酸铁矿 26110000 - 009 -钨铁矿 26110000 - 010 -钒钙铀矿 26121000 - 001 -钒钾铀矿 26121000 - 002 -⽅铀钍矿 26121000 - 003 -钙铀云母 26121000 - 004 -⽔合铀钙磷酸盐矿 26121000 - 010 - ⽔合铀钾钒酸盐矿 26121000 - 011 - ⽔合铀铅磷酸盐矿 26121000 - 012 - ⽔合铀铜磷酸盐矿 26121000 - 013 - 铜铀云母 26121000 - 014 -斜磷铅铀矿 26121000 - 015 -盐⽔氧化铀矿 26121000 - 016 -铀矿砂 26121000 - 017 -铀钍氧化物矿 26121000 - 018 -钛酸铀矿 26121000 - 019 -钛酸铀铁矿 26121000 - 020 -钛铀矿 26121000 - 021 -铈铀钛铁矿 26121000 - 022 -独居⽯ 26122000 - 001 -⽔合硅酸钍矿 26122000 - 002 -钍矿砂 26122000 - 003 -钍⽯ 26122000 - 004 -焙烧辉钼精矿 26131000 - 001 -⼆硫化钼 26131000 - 002 辉钼矿钼精矿 26131000 - 003 已焙烧钼矿砂 26131000 - 004 已焙烧钼精矿 26139000 - 001 已焙烧除外钼矿砂 26139000 - 002 已焙烧除外板钛矿 26140000 - 001 -⾦红⽯ 26140000 - 002 -锐钛矿 26140000 - 003 -氧化钛矿 26140000 - 004 -钛矿砂 26140000 - 005 -钛酸铁矿 26140000 - 006 -钛铁矿 26140000 - 007 -硅酸锆矿 26151000 - 001 -含锆砂料 26151000 - 002 -斜锆矿 26151000 - 003 -氧化锆矿 26151000 - 004 -锆粉 26151000 - 005 -锆矿砂 26151000 - 006 -锆砂 26151000 - 007 -锆⽯ 26151000 - 008 -锆英粉(微化锆砂) 26151000 - 009 - 锆英砂 26151000 - 010 -钽精矿 26159000 10 001 -钽矿 26159000 10 002 -钽矿砂 26159000 10 003 -铌精矿 26159000 10 004 -铌矿 26159000 10 005 -铌矿砂 26159000 10 006 -钒精矿 26159000 90 001 -钒矿砂 26159000 90 002 -钒铅矿 26159000 90 003 -钒铅锌矿 26159000 90 004 -钒云母 26159000 90 005 -碱式钒酸铅锌矿 26159000 90 006 - 硫化钒矿 26159000 90 007 -绿硫钒矿 26159000 90 008 -脆银矿 26161000 - 001 -淡红银矿 26161000 - 002 -辉银矿 26161000 - 003 -深红银矿 26161000 - 008 -银碘化物矿 26161000 - 009 -银矿砂 26161000 - 010 -银氯化物矿 26161000 - 011 -银锑硫化物矿 26161000 - 012 -碲⾦矿 26161000 - 013 -黄⾦矿砂精矿 26169000 10 001 -⾦精矿 26169000 10 002 -含铂矿砂 26169000 90 001 -⽣锑 26171010 - 001 -⽅锑矿 26171090 - 001 -黄锑矿 26171090 - 002 -辉锑矿 26171090 - 003 -桔红硫锑矿 26171090 - 004 -硫化锑矿 26171090 - 005 -硫酸氧化锑矿 26171090 - 006 -锑华矿 26171090 - 007 -锑矿砂 26171090 - 008 -氧化锑矿 26171090 - 009 -朱砂(⾠砂) 26179010 - 001 -汞矿 26179090 - 001 -汞硫化物矿 26179090 - 002 -辉铋矿 26179090 - 003 -硫化铋矿 26179090 - 004 -绿柱⽯ 26179090 - 005 宝⽯形状除外泡铋矿 26179090 - 006 -⽔合碳酸铋矿 26179090 - 007 -⽔合氧化铋矿 26179090 - 008 -铜锗硫化物矿 26179090 - 009 -锗⽯ 26179090 - 010 -铋矿砂 26179090 - 011 -铍矿砂 26179090 - 012 -赭铋矿 26179090 - 013 -熔渣砂 26180000 - 001 粒状浮渣 26190000 - 001 ⾮粒状熔渣 26190000 - 002 ⾮粒状氧化⽪ 26190000 - 003 -硬锌块 26201100 - 001 -废铝灰渣 2620 4 0 0 0 - 0 0 1 -。

XCR3064-10PC44C资料

DS036 (v1.3) October 9, 2000 11-800-255-7778This product has been discontinued. Please see /partinfo/notify/pdn0007.htm for details.Features•Industry's first TotalCMOS™ PLD - both CMOS design and process technologies•Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed •High speed pin-to-pin delays of 10 ns •Ultra-low static power of less than 50 µA•100% routable with 100% utilization while all pins and all macrocells are fixed•Deterministic timing model that is extremely simple to use•Four clocks available•Programmable clock polarity at every macrocell •Support for asynchronous clocking•Innovative XPLA™ architecture combines high speed with extreme flexibility•1000 erase/program cycles guaranteed •20 years data retention guaranteed •Logic expandable to 37 product terms •PCI compliant•Advanced 0.5µ E 2CMOS process•Security bit prevents unauthorized access•Design entry and verification using industry standard and Xilinx CAE tools•Reprogrammable using industry standard device programmers•Innovative control term structure provides either sum terms or product terms in each logic block for:-Programmable 3-state buffer-Asynchronous macrocell register preset/reset•Programmable global 3-state pin facilitates ‘bed of nails' testing without using logic resources•Available in PLCC, VQFP , and PQFP packages •Available in both commercial and industrial gradesDescriptionThe XCR3064 CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner ® CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design tech-nique, the XCR3064 offers true pin-to-pin speeds of 10 ns,while simultaneously delivering power that is less than 50µA at standby without the need for “turbo-bits ” or other power-down schemes. By replacing conventional sense amplifier methods for implementing product terms (a tech-nique that has been used in PLDs since the bipolar era)with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD.These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Xilinx also offers the high speed XCR5064 CPLD that offers these features in a full 5V implementation.The Xilinx FZP CPLDs utiize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA archi-tecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allo-cation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 10 ns PAL path with five dedi-cated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 prod-uct terms to a fully programmable OR array that can allo-cate the PLA product terms to any output in the logic block.This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns,regardless of the number of PLA product terms used, which results in worst case t PD 's of only 12.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.The XCR3064 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design ver-ification uses industry standard simulators for functional and timing simulation. Development is supported on per-sonal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).The XCR3064 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.XCR3064: 64 Macrocell CPLDDS036 (v1.3) October 9, 2000Product SpecificationDS036 (v1.3) October 9, 2000 21-800-255-7778XPLA ArchitectureFigure 1 shows a high level block diagram of a 64 macro-cell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-tual cross point switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macro-cells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins.From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks.The contents of the logic block will be described next.Logic Block ArchitectureFigure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the six control terms can individually be con-figured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 mac-rocells ’ flip-flops. The PAL array consists of a programma-ble AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programma-ble OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density.Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin t PD of the XCR3064 device through the PAL array is 10 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32product terms, which are available for use by all 16 macro-cells. The additional propagation delay incurred by a mac-rocell using one or all 32 PLA product terms is just 2.5 ns.So the total pin-to-pin t PD for the XCR3064 using six to 37product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the PLA).Figure 1: Xilinx XPLA CPLD ArchitectureFigure 2: Xilinx XPLA Logic Block Architecture DS036 (v1.3) October 9, 20001-800-255-7778DS036 (v1.3) October 9, 2000 41-800-255-7778Macrocell ArchitectureFigure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner fam-ily members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are fours clocks available on the XCR3064 device. Clock 0(CLK0) is designated as the “synchronous ” clock and must be driven by an external source. Clock 1 (CLK1), Clock 2(CLK2), and Clock 3 (CLK3) can either be used as a syn-chronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the t CO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t SU time is reduced.Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Pre-set/Reset feature for each macrocell can also be disabled.Note that the Power-on Reset leaves all macrocells in the “zero ” state when power is properly applied. The other four control terms (CT2-CT5) can be used to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-State (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device.This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails" testing.There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path,while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the mac-rocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic imple-mented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated.TerminationsThe CoolRunner XCR3064 CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the lin-ear region of the CMOS input structures, which can increase the power consumption of the device. The XCR3064A CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automati-cally activated by the fitter software for all unused I/O pins.Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3064device be left unconnected.There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k Ωpull-up resistors. These pins can be directly connected to V CC or GND, but using the external pull-up resistors main-tains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes.Figure 3: XCR3064 Macrocell Architecture5 DS036 (v1.3) October 9, 20001-800-255-7778Simple Timing ModelFigure 4 shows the CoolRunner Timing Model. The Cool-Runner timing model looks very much like a 22V10 timing model in that there are three main timing parameters,including t PD , t SU , and t CO . In other CPLD architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of other CPLD architectures are very complex and include such things as timing dependen-cies on the number of parallel expanders borrowed, shar-able expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR3064 device, the user knows up front that if a given output uses five product termsor less, the t PD = 10 ns, the t SU_PAL = 6 ns, and the t CO = 7ns. If an output is using six to 37 product terms, an addi-tional 2.5 ns must be added to the t PD and t SU timing parameters to account for the time to propagate through the PLA array.TotalCMOS Design Technique for Fast Zero PowerXilinx is the first to offer a TotalCMOS CPLD, both in pro-cess technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum-of-Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs which are both high performance and low power, breaking the para-digm that to have low power, you must have low perfor-mance. Refer to Figure 5 and Table 1 showing the I CC vs.Frequency of our XCR3064 T otalCMOS CPLD.Figure 4: CoolRunner Timing ModelDS036 (v1.3) October 9, 2000 61-800-255-7778Figure 5: I CC vs. Frequency @ VCC = 3.3V, 25°C Table 1: I CC vs. Frequency (V CC = 3.3V, 25°C)Frequency (Mhz)020*********Typical I CC (mA)0.041326405063Absolute Maximum Ratings1Symbol Parameter Min.Max.Units V CC Supply voltage2-0.57.0VV I Input voltage-1.2V CC + 0.5V V OUT Output voltage-0.5V CC + 0.5VI IN Input current-3030mAI OUT Output current-100100mAT J Maximum junction temperature-40150°C T STR Storage temperature-65150°C Notes:1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.Functional operation at these or any other condition above those indicated in the operational and programmingspecification is not implied.2. The chip supply voltage must rise monotonically.Operating RangeProduct Grade Temperature VoltageCommercial0 to +70°C 3.3V ± 10%Industrial-40 to +85°C 3.3V±10% DS036 (v1.3) October 9, 20001-800-255-7778DS036 (v1.3) October 9, 2000 81-800-255-7778DC Electrical Characteristics For Commercial Grade DevicesCommercial: 0°C ≤ T AMB ≤ +70°C; 3.0V ≤ V CC ≤ 3.6V Symbol ParameterTest ConditionsMin.Max.Unit V IL Input voltage Low V CC = 3.0V 0.8V V IH Input voltage High V CC = 3.6V2.0VV I Input clamp voltage V CC = 3.0V, I IN = -18 mA -1.2V V OL Output voltage Low V CC = 3.0V, I OL = 8 mA 0.5V V OH Output voltage High V CC = 3.0V, I OH = -8 mA 2.4V I I Input leakage currentV IN = 0 to V CC -1010µA I OZ 3-stated output leakage current V IN = 0 to V CC-1010µA I CCQ 1Standby current V CC = 3.6V, T AMB = 0°C50µA I CCD 1, 2Dynamic currentV CC = 3.6V, T AMB = 0°C at 1 MHz 1mA V CC = 3.6V, T AMB = 0°C at 50 MHz40mA I OS Short circuit output current 3One pin at a time for no longer than 1 second-5-100mA C IN Input pin capacitance 3T AMB = 25°C, f = 1 MHz 8pF C CLK Clock input capacitance 3T AMB = 25°C, f = 1 MHz 512pF C I/OI/O pin capacitance 3T AMB = 25°C, f = 1 MHz10pFNotes:1. See Table 1 on page 6 for typical value.2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.3. Typical values, not tested.9 DS036 (v1.3) October 9, 20001-800-255-7778AC Electrical Characteristics For Commercial Grade DevicesCommercial: 0°C ≤ T AMB ≤ +70°C; 3.0V ≤ V CC ≤ 3.6VSymbol Parameter1012Unit Min.Max.Min.Max.t PD_PAL Propagation delay time, input (or feedback node) to output through PAL210212ns t PD_PLA Propagation delay time, input (or feedback node) to output through PAL + PLA312.5314.5ns t COClock to out (global synchronous clock from pin)2728ns t SU_PAL Setup time (from input or feedback node) through PAL 5.57ns t SU_PLA Setup time (from input or feedback node) through PAL + PLA 89.5ns t H Hold time00ns t CH Clock High time 45ns t CL Clock Low time 45ns t R Input Rise time 2020ns t FInput Fall time2020ns f MAX1Maximum FF toggle rate 2 (1/t CH + t CL )125100MHz f MAX2Maximum internal frequency 2 (1/t SUPAL + t CF )9174MHz f MAX3Maximum external frequency 2 (1/t SUPAL + t CO )8067MHz t BUFOutput buffer delay time1.5 1.5ns t PDF_PAL Input (or feedback node) to internal feedback node delay time through PAL8.510.5ns t PDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA1113ns t CF Clock to internal feedback node delay time 5.5 6.5ns t INIT Delay from valid V CC to valid reset 5050µs t ER Input to output disable 312.514ns t EA Input to output valid 12.514ns t RP Input to register preset 1516ns t RRInput to register reset1516nsNotes:1. Specifications measured with one output switching. See Figure 6 and Table 2 for derating.2. This parameter guaranteed by design and characterization, not by test.3. Output C L = 5 pF.DS036 (v1.3) October 9, 2000 101-800-255-7778DC Electrical Characteristics For Industrial Grade DevicesIndustrial: -40°C ≤ T AMB ≤ +85°C; ≤.0V ≤ V CC ≤ 3.6V Symbol Parameter Test ConditionsMin.Max.Unit V IL Input voltage Low V CC = 3.0V 0.8V V IH Input voltage High V CC = 3.6V2.0VV I Input clamp voltage V CC = 3.0V, I IN = -18 mA -1.2V V OL Output voltage Low V CC = 3.0V, I OL = 8 mA 0.5V V OH Output voltage High V CC = 3.0V, I OH = -8 mA 2.4V I I Input leakage currentV IN = 0 to V CC -1010µA I OZ 3-stated output leakage current V IN = 0 to V CC-1010µA I CCQ1Standby current V CC = 3.6V, T AMB = -40°C50µA I CCD 1, 2Dynamic currentV CC = 3.6V, T AMB = -40°C at 1 MHz1mA V CC = 3.6V, T AMB = -40°C at 50 MHz 40mA I OS Short circuit output current One pin at a time for no longer than 1 second-5-130mA C IN Input pin capacitance T AMB = 25°C, f = 1MHz 8pF C CLK Clock input capacitance T AMB = 25°C, f = 1MHz 512pF C I/OI/O pin capacitanceT AMB = 25°C, f = 1MHz10pFNotes:1. See Table 1 on page 6 for typical values.2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.3. Typical values, not tested.AC Electrical Characteristics For Industrial Grade Devices Industrial: -40°C ≤ T AMB≤ +85°C; 3.0V ≤ V CC≤ 3.6VSymbol Parameter1215Unit Min.Max.Min.Max.t PD_PAL Propagation delay time, input (or feedback node) to output throughPAL212215nst PD_PLA Propagation delay time, input (or feedback node) to output throughPAL + PLA314.5317.5ns t CO Clock to out (global synchronous clock from pin)2829ns t SU_PAL Setup time (from input or feedback node) through PAL78ns t SU_PLA Setup time (from input or feedback node) through PAL + PLA9.510.5ns t H Hold time00ns t CH Clock High time55ns t CL Clock Low time55ns t R Input Rise time2020ns t F Input Fall time2020nsf MAX1Maximum FF toggle rate 2 (1/t CH + t CL)100100MHzf MAX2Maximum internal frequency 2 (1/t SUPAL + t CF)7465MHzf MAX3Maximum external frequency 2 (1/t SUPAL + t CO)6758MHzt BUF Output buffer delay time 1.5 1.5ns t PDF_PAL Input (or feedback node) to internal feedback node delay timethrough PAL10.513.5nst PDF_PLA Input (or feedback node) to internal feedback node delay timethrough PAL+PLA1316ns t CF Clock to internal feedback node delay time 6.57.5ns t INIT Delay from valid V CC to valid reset5050µs t ER Input to output disable 31415ns t EA Input to output valid1415ns t RP Input to register preset1617ns t RR Input to register reset1617ns Notes:1. Specifications measured with one output switching. See Figure6 and Table2 for derating.2. This parameter guaranteed by design and characterization, not by test.3. Output C L = 5 pF.Switching CharacteristicsThe test load circuit and load values for the AC Electrical Characteristics are illustrated below.Figure 6: t PD_PAL vs. Output SwitchingFigure 7: Voltage WaveformTable 2: t PD_PAL vs # of Outputs Switching(V CC = 3.3 V, T = 25°C)#of Outputs12481216 Typical (ns)8.08.48.89.29.610.0Pin Function and LayoutXCR3064 I/O PinsXCR3064 Global, Power, and No connect Pins(1) Global 3-State pin facilitates bed of nails testing withoutusing logic resources.Func-tion BlockMacro-cellPC44VQ44PC68PC84PQ100Notes11442449412---59513543569614--789815--89991664491010017---11318--10124197112146110---158111--1316101128214171111393151812114115172014115---211511612618221621211533413922---403823201432393724191330373525181229363426--28353327---343228--273331291711253127210---30252111610242923212--232822213--222721214148202519215---241821613719231731241836444232---454333251937464434262039484635272140494736--41504837---5149382822425250392923445454310---5556311--455658312--465759313--4758603143125496062315---6163316322650626441413565818742---808643403464798544--62778345--61768246---758147--607478483933597377493832577175410--567073411---6971412373155687041336305467694143428526567415---64664163327516365Pin TypePC44VQ44PC68PC84PQ100NotesIN0433*******IN11391191IN24438688490IN32402292gtsn 4438688490(1)CLK0433*******CLK12418364442CLK22115334139CLK34424494Vcc3, 15, 23, 359, 17, 29, 413, 11, 21, 31,35, 43, 53, 633, 13, 26, 38, 43, 53, 66, 785, 20, 36, 41, 53, 68, 84, 93GND10, 22, 30, 424, 16, 24, 366, 16, 26, 34,38, 48, 58, 667, 19, 32, 42, 47, 59, 72, 8213, 28, 40, 45, 61, 76, 88, 97No Connects1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80Func-tion BlockMacro-cellPC44VQ44PC68PC84PQ100NotesXCR3064: 44-pin PLCCXCR3064: 44-pin VQFPXCR3064: 68-pin PLCCXCR3064: 84-pin PLCCXCR3064: 100-pin PQFPOrdering InformationRevisionTableComponent AvailabilityPins 446884100Type Plastic VQFPPlastic PLCCPlastic PLCCPlastic PLCCPlastic PQFPCodeVQ44PC44PC68PC84PQ100XCR3064-15 I I I I I -12C, I C, I C, I C, I C, I -10CCCCCExample: XCR3064 -10 PC 44 CT emperature Range Number of Pins Package TypeSpeed Options-15: 15 ns pin-to-pin delay -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delayTemperature RangeC = Commercial, T A = 0°C to +70°C I = Industrial, T A = –40°C to +85°C Packaging Options VQ44: 44-pin VQFP PC44: 44-pin PLCC PC68: 68-pin PLCC PC84: 84-pin PLCC PQ100: 100-pin PQFPDevice Type Speed Options。

5-532469-9中文资料

5-532469-9 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer Support Home > Products > By Type > Two-Piece Connector > Product Feature Selector > Product Details5-532469-9Active .050, .075, .100 Box ConnectorsAlways EU RoHS/ELV Compliant (Statement of Compliance)Product Highlights:?Receptacle Assembly? 2.54 mm Centerline?Number of Rows = 2?Number of Positions = 100?Post Styles = Wrap-TypeView all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?RECEPTACLE ASSEMBLY, .100 X .100 GRID, RIGHT ANGLE, ...(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?Connector, Using Box Type Contacts(PDF, English)Application Specifications:?Box Connectors With Contacts On .075 And .100 Inch C...(PDF, English)Instruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Product Type = Receptacle Assembly?Number of Positions = 100?Post Size (mm [in]) = 0.64 [.025]?Sealed = No?Strain Relief = Without?Mount Angle = Right Angle?PCB Mount Style = Thru Hole?Color = Blue?Comment = Rows of solder posts will not be ofequal lengthTermination Related Features:?Termination (Solder) Post Length (mm [in]) =5.08 [0.200]?Solder Tail Contact Plating = Tin over NickelBody Related Features:?Centerline (mm [in]) = 2.54 [0.100]?Number of Rows = 2?Post Styles = Wrap-Type?Staggered Rows = No?Number of Terminations per Post = 1 High?Gasket = Without?Pin Protection = Without?Hybrid = No?Jackscrews = Without?Stabilizers = With?Post Stabilizer Material = Glass-filled Polyester Contact Related Features:?Contact Mating Area Plating Material = Gold(30)?Contact Material = Beryllium Copper?Contact Shape = SquareHousing Related Features:?Housing Material = Diallyl PhthalateIndustry Standards:?Government/Industry Qualification = No?RoHS/ELV Compliance = RoHS compliant, ELVcompliant?Lead Free Solder Processes = Not relevant forlead free process?RoHS/ELV Compliance History = Always wasRoHS compliantOperation/Application:?Application = PC Solder MountOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。

J2264_201401

__________________________________________________________________________________________________________________________________________ SAE Technical Standards Board Rules provide that: “This report is published by SAE to advance the state of technical and engineering sciences. The use of this report is entirely voluntary, and its applicability and suitability for any particular use, including any patent infringement arising t herefrom, is the sole responsibility of the user.”SAE reviews each technical report at least every five years at which time it may be revised, reaffirmed, stabilized, or cancelled. SAE invites your written comments and suggestions.Copyright © 2014 SAE InternationalAll rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical,photocopying, recording, or otherwise, without the prior written permission of SAE.TO PLACE A DOCUMENT ORDER: Tel: 877-606-7323 (inside USA and Canada)Tel: +1 724-776-4970 (outside USA)Fax: 724-776-0790Email: CustomerService@SAE WEB ADDRESS: SURFACE VEHICLE RECOMMENDED PRACTICE J2264 JAN2014 Issued 1995-04Revised 2014-01 Superseding J2264 APR1995Chassis Dynamometer Simulation of Road Load Using Coastdown TechniquesRATIONALEThis procedure has been revised to include a new fixed-run test option, provisions for four-wheel drive dynamometer and 20°F testing, and updates to definitions and nomenclature aimed at harmonizing these quantities across related SAE documents.FOREWORDElectric chassis roll dynamometers provide the means for rapid, accurate, automatic adjustment of dynamometer loading to simulate vehicle road load over the entire speed range through which the vehicle is tested. Precise calibration of chassis roll torque measurement and speed instrumentation, accurate measurement of base inertia, and controls employing valid algorithms have resulted in accurate dynamometer load coefficient measurements using coastdown techniques without requiring onerous computation and data manipulation by users. Variability of each dynamometer and between dynamometers is low, permitting load coefficients obtained on one dynamometer to be used on other similar dynamometers. To achieve this interchangeability of loading coefficients, operational factors are specified with the objective of keeping test variability at the low levels of the dynamometer.This procedure was originally developed in conjunction with the introduction of the 1.219 m (48 in) diameter single-roll electric dynamometer for vehicle emissions and fuel economy testing, however, the methodology is generic to any dynamometer capable of carrying out the road load derivation described, regardless of roll size, geometry, or roll surface roughness and is intended to provide a standard of best practice for all vehicle testing requiring accurate road load simulation.Downloaded from SAE International by Beijing Univ of Technology, Wednesday, August 17, 2016TABLE OF CONTENTS1.SCOPE (2)1.1Purpose (2)2.REFERENCES (3)2.1Applicable Documents (3)2.2Related Publications (3)3.DEFINITIONS (4)4.EQUIPMENT (8)4.1Dynamometer (8)4.2Restraint System (9)4.3Air Circulation/Cooling (9)5.COASTDOWN COMPUTATIONS (9)5.1Integration for Analytically-Obtained Values of t (10)5.2Example Calculation Sequence (10)6.ROAD LOAD DERIVATION PROCEDURE (13)6.1Summary (13)6.2Recommended Pre-Test Calibration Check (13)6.3Vehicle Preparation (13)6.4Dynamometer Set-Up (14)6.5Vehicle Installation on Dynamometer (14)6.6Vehicle Preconditioning (15)6.7Road Load Derivation Runs (15)6.8Iterative Procedure (15)6.9Fixed-Run Procedure (16)6.10Dynamometer Calibration Verification Coastdown (17)6.11Special provisions for Testing at20°F (-7°c) (17)6.12Road Load Derivation Report (17)7.NOTES (18)7.1Conversion Factors (18)7.2Marginal Indicia (19)APPENDIX A SAMPLE REPORTS (20)FIGURE 1 FLOW CHART OF COASTDOWN CALCULATION AND ERROR CORRECTION SEQUENCE (12)FIGURE A1 ROAD LOAD DERIVATION DISPLAY (21)FIGURE A2 TYPICAL MEASURED-TARGET COASTDOWN REPORT (22)1. SCOPEThis procedure covers vehicle operation and electric dynamometer load coefficient adjustment to simulate track road load within dynamometer inertia and road load simulation capabilities.1.1 PurposeTo provide a uniform procedure for adjusting an electric chassis roll dynamometer to provide accurate simulation of the resistance which must be overcome by the vehicle powertrain to maintain steady speed on a flat road, as determined by track coastdown tests on that vehicle.2. REFERENCES2.1 Applicable DocumentsThe following publications form a part of this specification to the extent specified herein. Unless otherwise indicated, the latest issue of SAE publications shall apply.2.1.1 HWFET PublicationAvailable from the Superintendent of Documents, U.S. Government Printing Office, Mail Stop: SSOP, Washington, DC 20402-9320.HWFET, Highway Fuel Economy Test, 40 CFR Part 600, Subpart B and Appendix I2.1.2 Other PublicationsDynamometer Performance Evaluation and Quality Assurance Procedures (AMA) for a 48 inch Single Roll, Electric Light Duty Chassis Dynamometer2.2 Related PublicationsThe following publications are provided for information purposes only and are not a required part of this SAE Technical Report.2.2.1 SAE PublicationsAvailable from SAE International, 400 Commonwealth Drive, Warrendale, PA 15096-0001, Tel: 877-606-7323 (inside USA and Canada) or 724-776-4970 (outside USA), .SAE J1263 Road Load Measurement and Dynamometer Simulation Using Coastdown TechniquesSAE Paper 780257 DeRaad, L., "The Influence of Road Surface Texture on Tire Rolling Resistance," SAE Technical Paper 780257, 1978, doi:10.4271/780257.SAE Paper 810166 Oswald, A. and Browne, L., "The Airflow Field Around An Operating Tire and Its Effect on Tire Power Loss," SAE Technical Paper 810166, 1981, doi:10.4271/810166.SAE Paper 900760 Metz, L., Akouris, C., Agney, C., and Clark, M., "Moments of Inertia of Mounted and Unmounted Passenger Car and Motorcycle Tires," SAE Technical Paper 900760, 1990, doi:10.4271/900760. SAE Paper 930391 D'Angelo, S., Mears, W., and Brownell, C., "Large-Roll Chassis Dynamometer with AC Flux-Vector PEU and Friction-Compensated Bearings," SAE Technical Paper 930391, 1993,doi:10.4271/930391.SAE Paper 930392 Mears, W., D'Angelo, S., and Paulsell, C., "Performance Tests of a Large-Roll Chassis Dynamometer with AC Flux-Vector PEU and Friction-Compensated Bearings," SAE Technical Paper930392, 1993, doi:10.4271/930392.SAE Paper 940486 Brownell, C., Brownell, C., D'Angelo, S., Fagerman, T. et al., "Simulation of 8.65″ Uncoupled Twin-Roll Hydrokinetic Dynamometer Operation on a 48″ Single-Roll Electric Dynamometer," SAETechnical Paper 940486, 1994, doi:10.4271/940486.2.2.2 Other PublicationsDifferential and Integral Calculus, C. E. Love, Macmillan Co., 19483. DEFINITIONS3.1 AVERAGE DECELERATING FORCE (F AVG)(Eq. 1) 3.23.3speed is 3.4The the lower 3.53.6The inertiatest cellAssurance 3.73.83.9 TEST VEHICLE MASS (M VEH)The mass of an individual test vehicle as determined by weighing. Note: Regulatory testing uses weight classes, not individual vehicle test mass.3.10 ROTATIONAL AXLE INERTIA (I ROT ) The effective linear inertia of the rotating components (e.g. wheels, axles). For light-duty vehicles, the rotational inertia per axle is typically estimated to be equal to 1.5% of the vehicles weight, or in the case of regulatory testing, 1.5% of ETW: axle per ETW] or M [015.0F VEH ROT ⋅= (Eq. 2) This estimate is not applicable for vehicles with other than single, normal-sized wheels, such as dual-wheel trucks, or other driveline components which are likely to increase result in an effective rotational inertia greater than 1.5% per axle. These vehicles require a more appropriate estimation or determination of the actual effective mass of the rotating drivetrain components. Axle-specific naming conventions for I ROT are given below:I ROT_F = I ROT for front wheel/axleI ROT_R = I ROT for rear wheel/axleI ROT_D = I ROT for the drive axle (2WD dynamometer)I ROT_ND = I ROT for the non-drive (static) axle (2WD dynamometer)I ROT_T = total rotating axle/wheel mass = I ROT_D for 2WD dynamometer testing= I ROT_F + I ROT_R for 4WD dynamometer or track testing3.11 EFFECTIVE TEST TRACK MASS (M T )The effective mass of an individual test vehicle, including the vehicle’s mass (as determined by weighing) plus the effective mass of the wheels, tires and other rotating components:ROT_R ROT_F VEH T I I M M ++= (Eq. 3) Using Eq. 2 from Section 3.10 to estimate the effective inertia of the front and rear axles, M T can be calculated as follows: VEH T M 03.1M ⋅=(Eq. 4) where M VEH is determined following track test mass provisions specified in SAE J2263.3.12 DYNAMOMETER SET INERTIA (M SET )The setting that specifies the inertia that is to be simulated by the dynamometer. The appropriate method for determining M SET depends on the testing intent as described below in Sections 3.12.1 and 3.12.2.3.12.1 General Experimental Testing: Simulation of Individual Test Vehicle WeightFor general experimental testing, M SET equals the test vehicle’s mass (M VEH ) plus the effective mass of the wheels, tires, and other rotating components on the static, non-driving axle (I ROT ). Using Eq. 2 (section 3.10) for I ROT , M SET for 2WD dynamometer testing is:VEH SET M 015.1M ⋅= (Eq. 5)For tests conducted using a 4WD dynamometer, M SET equals the test vehicle mass:VEH SET M M =(Eq. 6)3.12.2 Regulatory Testing: Simulation of Vehicle Weight ClassThis case applies to regulatory testing that is based on a vehicle’s ETW class as dictated by U.S. Federal Register regulations 40 CFR § 86.129-80, § 86.129-94, 40 CFR Subpart C §1066.201 through §1066.290,. For testing conducted on a 2WD dynamometer, M SET equals the ETW class:ETW M SET = (Eq. 7)In order to achieve the same total inertial load for the vehicle-dyno system (M E , Section 3.13) whether a vehicle is tested on a 2WD or 4WD dynamometer, M SET for 4WD dynamometer testing must be set equal to the ETW class minus the effective mass of the wheels, tires, and other rotating components associated with what would be the static, non-driving axle of the vehicle when tested on a 2WD dynamometer (I ROT_ND ). Using Equation 2 (section 3.10), M SET for 4WD dynamometer testing is:ETW 985.0M _4WD SET ⋅= (Eq. 8) 3.13 EFFECTIVE TEST MASS (M E )Effective Test Mass (M E ) is the total effective inertia associated with the vehicle-dynamometer system. M E is the sum of 1) the dyno-simulated inertia (M SET , see Section 3.12) and 2) the effective inertia of the vehicle components (e.g. wheels, axles) that are rotated on the dynamometer (I ROT ):ROT_T SET E I M M += (Eq. 9)where I ROT_T includes one or two axles (Section 3.11) depending on whether the test is conducted on a 2WD or 4WD dynamometer, respectively. M E is used together with the measured coastdown times in order to calculate the forces acting to decelerate the system during a dynamometer coastdown.Using Equation 2 (Section 3.10), Equation 9 can be written, for 40 CFR Subpart C §1066.201 through §1066.290, regulatory testing, (Section 3.12.1) as follows:ETW 015.1M E ⋅= (Eq. 10)Because M SET_4WD is defined as 0.985 x ETW in Section 3.12.2, the total inertia load is the same for 4WD and 2WD test modes (i.e., M E_4WD = M E_2WD ) and Equation10 applies to both 2WD and 4WD dynamometer testing.3.14 FORCE COEFFICIENTSSeveral specific sets of force coefficients are used, each of which describes a second-order force-versus-speed relationship. A generic set is represented as C x , where the subscript “x” refers to the entire set of three coefficients, individually designated as C 0, C 1 and C 2. The force at speed V is calculated as C 0 + C 1V + C 2V 2. Each specific set of coefficients is represented by a different letter.3.14.1 Dyno Target Coefficients: F x (F 0, F 1, and F 2)The Target coefficients describe the total force (tire, drivetrain and aerodynamic drag) acting to decelerate a vehicle during an on-road coastdown. These coefficients are developed from track data (or equivalent analytical methodology), corrected to standard conditions, and possibly adjusted to account for differences between vehicle weight as tested on the track and weight represented by an ETW class assigned for dynamometer testing.3.14.2 Dyno Set (Dyno) Coefficients: D x (D 0, D 1, and D 2)The Set coefficients (also known as A, B and C, respectively) describe the contribution to the road load force that is simulated by the dynamometer.3.14.3 Dyno Measured (Resultant) Coefficients: R x (R0, R1, and R2)The Measured coefficients represent the total force acting to decelerate a vehicle during an on-dynamometer coastdown. They represent the combined effects of the Set coefficients and the vehicle’s own inherent parasitics. These coefficients are computed from the effective mass of the vehicle-dynamometer system (M E) and the coastdown times measured as the dynamometer-vehicle system coasts through each speed interval. For coastdown calculations with a vehicle on the rolls, M E is used for mass. For coastdowns without vehicle, the M SET is used.3.14.4 Dyno Vehicle (Loss) Coefficients: L x (L0, L1, and L2)Vehicle coefficients represent a vehicle’s drivetrain losses (i.e., parasitic friction) while on the dynamometer. They describe the contribution to a vehicle’s road load that does not need to be simulated by the dynamometer. They are calculated by subtracting the dyno coefficients from the resultant coefficients for a particular coastdown run.3.15 MID-SPEED FORCEThe force at the midpoint of a speed interval.3.16 ROAD LOAD DERIVATIONThe procedure in which the dynamometer conducts coastdown tests with vehicle wheels on the rolls and adjusts its Set coefficients so that the Measured coefficients match the Target coefficients.3.16.1 Iterative ProcedureA road-load derivation procedure in which the Set coefficients are adjusted after each coastdown, based on the resultant coefficients for that coastdown.3.16.2 Fixed-Run ProcedureA road-load derivation (RLD) procedure in which the Set coefficients are fixed at the beginning of the procedure, and Vehicle coefficients are determined for a fixed number of coastdowns (at least 4 coastdowns and average the last 3). The final Set coefficients are determined from the averaged Vehicle coefficients.3.17 SIMULATION MODEThe operating mode where the dynamometer simulates the vehicle inertia and road load commanded by dynamometer set inertia (M SET) and the Set coefficients (D x), respectively, so that a vehicle driven on the dynamometer operates as it would on the road.3.18 UNLOADED COASTDOWNA dynamometer coastdown run without a vehicle.3.19 POWER INTEGRAL (PI)The integral of power-versus-speed over the coastdown speed range. This can be used to compare individual coastdown results during the procedure, to indicate potential problems with the vehicle or dynamometer. The power versus speed relationship is determined from the road-load coefficients that describe the force-versus-speed relationship.3.20 PI METRIC (PIM)The standard deviation of the power integral values calculated for each of the runs in the fixed-run procedure.4. EQUIPMENT4.1 Dynamometer4.1.1 Requirements for Regulatory TestingFor North American compliance and certification testing, the dynamometer must meet all requirements outlined in 40 CFR, Part 1066, Subpart C- “Dynamometer Specifications.”4.1.2 Recommendations for General TestingFor non-regulatory testing, it is recommended that the dynamometer be able to accelerate the vehicle at approximately 3.6 km/h/s (2.2 mi/h/s) to a speed 10 km/h (6 mi/h) above the highest data speed for the coastdown. The dynamometer must also be able to utilize software that can perform the automated coastdown algorithms described in this procedure.a. Roll Diameter - 1.219 m (48 in)b. Roll Surface Roughness - Surface should represent a dry road and be sufficiently rough to minimize slippagebetween the tire and roll surface without introducing excessive tire wear.c. Roll Diameter Accuracy - ± 0.254 mm of nominal.d. Speed Resolution and Accuracy - 0.01 km/he. Time Resolution - 0.01 sf. Time Accuracy - 0.001%g. Acceleration Accuracy - 1%4.1.3 Coastdown Load Measurement Requirementsa. Making automatic accelerations at controlled acceleration rate.b. Initiating, running, and terminating coastdowns using dyno coefficients to control road load and the inertia settingto control mass simulation throughout the coastdown.c. Computing resultant coefficients.d. Comparing force curve obtained using resultant coefficients to that obtained using target coefficients.e. Adjusting dyno coefficients.f. Determining Vehicle coefficients.g. Displaying, recording, and reporting results.4.1.4 Coefficient ResolutionNumber of decimal digits.C0xxx.xx N or lbfC1x.xxxx N/(km/h) or lbf/(mi/h)C20.xxxxx N/(km/h)2 or lbf/(mi/h)2Inertia 1 kg or 1 lb4.1.5 Motoring CapabilitySufficient to accelerate dynamometer and vehicle drivetrain to maximum required speed at 3.6 km/h/s ± 0.5 km/h/s (2.2 (mi/h)/s ± 0.3 (mi/h)/s).4.1.6 Data AcquisitionSufficient to record all data required to conduct a complete coastdown road load derivation test.4.1.7 ComputationAs specified under 6.10 and illustrated in Appendix A.4.1.8 Calibration Verification (40 CFR § 86.118-00, 40 CFR §1066.215, §1066.240, §1066.260, §1066.270,§1066.280,)Calibration can be verified by running an unloaded coastdown immediately following the road load coefficient derivation using the final dynamometer settings and coast speed interval schedule from the road load derivation. The maximum load error at the center of any coastdown speed interval may not exceed ±10 N (2.2 lb).4.2 Restraint SystemThe dynamometer should be equipped with a centering device which aligns the drive wheels perpendicular to the dynamometer roll axis. After installation, the restraint system should maintain the centered drive wheel position within the following recommended limits throughout the coastdown portions of the road load derivation.4.2.1 Lateral Position (Side to side)Vehicle should remain aligned and lateral movement minimized to ensure vehicle repeatability.4.2.2 Front-Rear PositionWithin ±25 mm (1 in) of top of roll.4.2.3 Vertical ForceThe restraint system should be designed to impose no vertical force on the drive wheels. No more than ±5 mm (0.2 in) vertical drive axle suspension static deflection should be caused by restraint installation on the vehicle.4.3 Air Circulation/CoolingAn air circulation and cooling system is required for engine cooling and maintaining repeatable ambient temperature and airflow conditions around the vehicle drivetrain. It is recommended that the test cell ambient temperature not change more than ±5 °C (9 °F) during the warm-up and road load derivation. Air temperature and flow around the vehicle tires and drivetrain will affect warm-up, and should approximate those conditions present during subsequent testing using the dynamometer setting coefficients obtained in this derivation. Some exceptions to these temperature and flow recommendations may be permitted by government regulations.5. COASTDOWN COMPUTATIONSThis section describes calculations which can be used to obtain resultant coefficients (R x) from the data acquired during a coastdown (alternative methods yielding equivalent or more representative results may be used consistent with good engineering judgment). The dynamometer measures speed to 0.016 km/h (or 0.01 mi/h) accuracy during coastdown and records the time to coast through each speed interval, ∆t. These coast times are used with the effective test mass to calculate the average measured decelerating force over each speed interval. Although it is technically the speed, V, and coast time, ∆t, that are measured, the resulting force is referred to as the “measured” force in order to distinguish it from other intermediate force quantities that are calculated as part of the error correction procedure.The error correction procedure allows the mid-speed “measured” decelerating force to be estimated from t he average measured decelerating force for a given interval. First, the Set coefficients (D x ) are used to calculate a mid-speed force value and average force value for the interval. The average force value is calculated using an analytically-obtained value of ∆force, on these 5.1 (Eq. 11)5.2 The (Eq. 12) (Eq. 13)(Eq. 14)4: Calculate F MidSet as:2Mid 2Mid 10MidSet V D V D D F ++= (Eq. 15) This is the force at the mid-point of the speed interval as calculated using the Set coefficients.5: Calculate F MidApp as:)F F (F F MidSet Av gSet Av gMeas MidApp --=(Eq. 16)Thismeasured to obtain(Eq. 17)(Eq. 18)(Eq. 19)(Eq. 20)This measuredMid V toFIGURE 1 - FLOW CHART OF COASTDOWN CALCULATION AND ERROR CORRECTION SEQUENCE6. ROAD LOAD DERIVATION PROCEDURE6.1 SummaryThe vehicle and dynamometer should be conditioned and configured in accordance with Sections 6.2 and 6.6 of this document and is preconditioned to stabilize parasitic friction. A pre-test coastdown without a vehicle (unloaded coastdown) may be run to verify dynamometer calibration. The vehicle test weight is adjusted if necessary, it is soaked to test temperature, and tire pressure is set to the specified value. After installation on the dynamometer, two HWFET cycles are driven to warm up the vehicle tir es and drivetrain. Then, either the “iterative” or the “fixed-run” derivation procedure is run by the dynamometer to determine the final dynamometer coefficients. For non-CFR testing, other methods and parameters may be used to determine that the vehicle is in a repeatable state (i.e. tire temperature, time at steady state speed or repeating other driving traces.). Care should be taken to use the same criteria for all testing in any given program.The vehicle is then removed, and an unloaded coastdown may be performed to verify dynamometer calibration. The test results from the dynamometer are stored to archive, and reports printed out.6.2 Recommended Pre-Test Calibration CheckTo minimize errors in road load derivation results, it is essential that dynamometer calibration is correct. To verify the dynamometer calibration, the following steps are recommended.6.2.1 Dynamometer PreconditioningFollow dynamometer manufacturer’s recommended practice or laboratory procedure to stabilize the dynamome ter parasitic friction.6.2.2 Calibration Verification CoastdownFor regulatory testing, CFR 40 Part §1066.215 and §1066.270 require that unloaded dynamometer coastdowns be performed within 7 days of testing and after major maintenance. Additionally, CFR 40 Part §1066.280 requires that a single point unloaded dynamometer coastdown be performed within 1 day of testing. For non-regulatory testing where the dynamometer is not verified by a similarly robust laboratory quality assurance program, it is recommended that an unloaded coastdown be performed directly following the test using the test coastdown speed intervals with dyno-set inertia (M SET) and dyno-set coefficients (D x) appropriate for the test vehicle. Run one coastdown test. If maximum load error at any of the mid-interval speed points over the coastdown speed range is greater than ±10 N (2.2 lb), review the dynamometer for mechanical problems, correct and rerun coastdowns until the maximum error is less than ±10 N, then re-run the previous Road Load Derivation.6.3 Vehicle Preparation6.3.1 Temperature SoakSoak vehicle and test tires at test temperature ±3 °C (5 °F) for at least 4 h.6.3.2 Tire Pressure AdjustmentAfter tires have soaked for at least 4 h at test temperature, set tire pressure to manufacturer’s recommendation. .6.4 Dynamometer Set-Up6.4.1 Estimated Set Coefficients for Vehicle Preconditioning and Initial Coastdown Run (D x_EST)If Set coefficients are available from road load derivation results on similar vehicles, use these settings for the simulation mode set up. If none are available, approximate Set coefficients may be estimated from the target coefficients as follows: For regulatory testing on a 2WD dynamometer:D0_EST = 0.5 x F0D1_EST = 0.2 x F1D2_EST = F2For regulatory testing on a 4WD dynamometer:D0_EST = 0D1_EST = 0D2_EST = F26.4.2 Dynamometer Settings for Road Load Derivationa. Dyno-Target Coefficients (F x: F0,F1,F2)b. Dyno-Set Inertia (M SET)c. Effective Mass(M E, typically calculated automatically by the dynamometer software using the M SET)d. Coastdown Speed Intervals - Set up coastdown speed intervals that cover a coastdown speed range from 115 to15 km/h (or from 70 to 10 mi/h). Historically, testing based on 40 CFR § 86 & §1066 uses 10 mi/h intervals(approx. 16 km/h), but smaller intervals may be used.e. Acceleration Rate Between Coastdowns - Set at 3.6 (km/h)/s (2 (mi/h)/s). For vehicle-driven accelerations theminimum average acceleration rate should be greater than 1 (mi/h)/s.f. Force Tolerance (iterative option only) - Set the maximum acceptable force difference between the force-versus-speed curves calculated using the Target coefficients and the Measured coefficients.g. Number of Runs - Set the number of coastdown runs to be performed for a valid test.Iterative Procedure: Set the maximum number of runs to be performed, and the required number of verification runs. Recommended values: 15 maximum, 2 verification runs.Fixed-Run Procedure: Set the number of runs, N, for which Vehicle coefficients should be averaged together.Recommended value: At least 3 consecutive runs (not including initial stabilization run).6.5 Vehicle Installation on Dynamometer6.5.1 Restraint and AlignmentInstall vehicle as outlined in 4.2.6.5.2 Vehicle CoolingProvide vehicle cooling as outlined in 4.3.6.6 Vehicle PreconditioningDrive two consecutive HWFET cycles (Reference 2.1.1) with dynamometer operating in simulation mode. Each HWFET is 16.5 km (10.25 miles) long. Total time is 25 min, 28 s.6.7 Road Load Derivation RunsStart the dynamometer road load derivation procedure within 2 minutes of completing the vehicle preconditioning.Any accessories which were operated during track coastdowns should be activated, and any operating procedures which may be required for identical engine and transmission operation to that of the track coastdown should be carried out.A road load derivation “run” is defined by the following sequence:1) For dynamometer-driven accelerations, the transmission is placed in neutral with the engine idling. For vehicle-driven accelerations, the vehicle should be placed in the appropriate gear before beginning acceleration, and shifted as necessary to continue the acceleration until a speed of 10 kph (6 mph) above the highest data speed for the vehicle coastdown is attained.2) For vehicle-driven accelerations, at this point the vehicle should be shifted into neutral.3) The driver must either remain in the vehicle, or exit and add appropriate compensating ballast.The road load derivation sequence should be performed without interruption.6.8 Iterative ProcedureThe iterative road-load derivation procedure is to be performed as follows:1) For the first run, the dynamometer software will use the Set coefficients that represent a best guess for thevehicle. Initial coefficients may be obtained using the method described in Section 6.4.1.2) The software will calculate the Measured coefficients from the run, and compare them to the Target values. If thecurves described by the coefficients agree to within specified limits, the run is considered to “pass”. Otherwise, it is considered to “fail”.3) If a run fails, the software will quantify the Measured coefficients’ difference from the Target coefficients, adjustthe Set coefficients accordingly and perform another run. Steps 2 and 3 will be repeated until a run passes.4) When a run passes, the software will perform verification runs, keeping the same Set coefficients, until therequired number of consecutive verification runs passes.5) If a verification run fails, steps 3 through 5 will be repeated until the required number of consecutive verificationruns passes, or until it is no longer possible to pass within the predetermined maximum total number of runs.6) When the required number of consecutive verification runs passes, the current Set coefficients will be used fortesting.7) If the required number of consecutive verification runs does not pass within the predetermined maximum numberof runs, the dyno will stop the coastdown procedure. The vehicle and dyno should be checked for correct operation.8) If the dynamometer and the vehicle are both operating correctly, the test procedure should be repeated, includingthe vehicle preparation described in Section 6.3. As an alternative, the Vehicle coefficients from runs 2 through 4 may be used to determine the final Set coefficients as indicated in steps 5 and 6 of the fixed-run procedure below.Note that these Vehicle coefficients will have been obtained with varying Set coefficients, unlike in the fixed-run procedure. However, this should not affect the representative nature of the results.。

24AA512-EP资料

© 2007 Microchip Technology Inc.DS21930B-page 124AA00/24LC00/24C00 24AA01/24LC01B 24AA014/24LC01424C01C 24AA02/24LC02B 24C02C24AA024/24LC024 24AA025/24LC02524AA04/24LC04B 24AA08/24LC08B 24AA16/24LC16B 24AA32A/24LC32A 24AA64/24LC64/24FC6424AA128/24LC128/24FC12824AA256/24LC256/24FC256 24AA512/24LC512/24FC512Features:•128-bit through 512 Kbit devices•Single supply with operation down to 1.7V for 24AAXX devices•Low-power CMOS technology:-1mA active current, typical-1μA standby current, typical (I-temp)•2-wire serial interface bus, I 2C™ compatible •Schmitt Trigger inputs for noise suppression •Output slope control to eliminate ground bounce •100kHz (1.7V) and 400kHz (≥ 2.5V) compatibility • 1 MHz for 24FCXX products•Self-timed write cycle (including auto-erase)•Page write buffer•Hardware write-protect available on most devices •Factory programming (QTP) available •ESD protection > 4,000V • 1 million erase/write cycles •Data retention > 200 years•8-lead PDIP , SOIC, TSSOP and MSOP packages •5-lead SOT-23 package (most 1-16 Kbit devices)•8-lead 2x3mm and 5x6mm DFN packages available•Pb-free and RoHS compliant•Available for extended temperature ranges:-Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°CDescription:The Microchip Technology Inc. 24CXX, 24LCXX,24AAXX and 24FCXX (24XX*) devices are a family of 128-bit through 512 Kbit Electrically Erased PROMs.The devices are organized in blocks of x8-bit memory with 2-wire serial interfaces. Low-voltage design permits operation down to 1.7V (for 24AAXX devices),with standby and active currents of only 1 μA and 1mA, respectively. Devices 1 Kbit and larger have page write capability. Parts having functional address lines allow connection of up to 8 devices on the same bus.The 24XX family is available in the standard 8-pin PDIP , surface mount SOIC, TSSOP and MSOP pack-ages. Most 128-bit through 16 Kbit devices are also available in the 5-lead SOT-23 package. DFN packages (2x3mm or 5x6mm) are also available. All packages are Pb-free (Matte Tin) finish.*24XX is used in this document as a generic part number for 24 series devices in this data sheet.24XX64, for example, represents all voltages of the 64Kbit device.Package Types (1)A0A1A2V SS12348765V CC WP (3)SCL SDAPDIP/SOICA0A1A2V SS12348765V CC WP (3)SCL SDA TSSOP/MSOP (2)1543SCL V SS SDAV CCNC 2SOT-23-5(24XX00)SOT-23-51543SCL V SS SDAWPV CC 2(all except 24XX00)A0A1A2V SS WP (3)SCL SDA56784321V CC DFNNote 1:Pins A0, A1, A2 and WP are not used by some devices (no internal connections). See Table 1-1,Device Selection Table, for details.2:Pins A0 and A1 are no-connects for the 24XX128and 24XX256 MSOP devices.3:Pin 7 is “not used” for 24XX00, 24XX025 and 24C01C.I 2C ™ Serial EEPROM Family Data Sheet24AAXX/24LCXX/24FCXXDS21930B-page 2© 2007 Microchip Technology Inc.TABLE 1-1:DEVICE SELECTION TABLEPart Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)128-bit devices 24AA00 1.7-5.5V 400 kHz (1)—NoneNoneI P , SN, ST, OT, MC24LC00 2.5-5.5V 400 kHz (1)I 24C00 4.5-5.5V400 kHzI, E1 Kb devices 24AA01 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC01B 2.5-5.5V 400 kHz I, E 24AA014 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC014 2.5-5.5V400 kHzI 24C01C 4.5V-5.5V 400 kHz16 bytesNoneA0, A1, A2I, EP , SN, ST, MC 2 Kb devices 24AA02 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC02B 2.5-5.5V 400 kHz I, E 24AA024 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC024 2.5-5.5V 400 kHz I 24AA025 1.7-5.5V 400 kHz (2)16 bytes None A0, A1, A2I P , SN, ST,MS, MC 24LC025 2.5-5.5V 400 kHz I 24C02C 4.5-5.5V400 kHz16 bytesUpper Half of ArrayA0, A1, A2I, EP , SN, ST, MC 4 Kb devices 24AA04 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC04B 2.5-5.5V400 kHzI, E8 Kb devices 24AA08 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC08B 2.5-5.5V400 kHzI, E16 Kb devices 24AA16 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC16B 2.5-5.5V400 kHzI, E32 Kb devices 24AA32A 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC32A 2.5-5.5V400 kHzI, E64 Kb devices 24AA64 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC64 2.5-5.5V 400 kHz I, E 24FC641.7-5.5V1 MHz (3)INote 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.© 2007 Microchip Technology Inc.DS21930B-page 324AAXX/24LCXX/24FCXX128 Kb devices 24AA128 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC128 2.5-5.5V 400 kHz I, E 24FC128 1.7-5.5V1 MHz (3)I256 Kb devices 24AA256 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC256 2.5-5.5V 400 kHz I, E 24FC256 1.7-5.5V1 MHz (3)I512 Kb devices 24AA512 1.7-5.5V 400 kHz (2)128 bytesEntire ArrayA0, A1, A2IP , SM, MF, ST1424LC512 2.5-5.5V400 kHzI, E 24FC5121.7-5.5V (3) 1 MHzITABLE 1-1:DEVICE SELECTION TABLE (CONTINUED)Part Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)Note 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.24AAXX/24LCXX/24FCXXDS21930B-page 4© 2007 Microchip Technology Inc.2.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings (†)V CC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. V SS .........................................................................................................-0.6V to V CC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥4kVTABLE 2-1:DC CHARACTERISTICS† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.DC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsD1—A0, A1, A2, SCL, SDA and WP pins:————D2V IH High-level input voltage 0.7 V CC—V —D3V IL Low-level input voltage—0.3 V CC 0.2 V CCV V V CC ≥ 2.5V V CC < 2.5V D4V HYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins)0.05 V CC —V (Note 1)D5V OL Low-level output voltage —0.40V I OL = 3.0mA @ V CC = 2.5V D6I LI Input leakage current —±1μA V IN = V SS or V CC D7I LO Output leakage current —±1μA V OUT = V SS or V CC D8C IN , C OUTPin capacitance (all inputs/outputs)—10pF V CC = 5.0V (Note 1)T A = 25°C, F CLK = 1MHz D9I CC Read Operating current—4001μA mA 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHzAll except 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHz I CC Write—35mA mA V CC = 5.5V, All except 24XX512V CC = 5.5V, 24XX512D10I CCSStandby current—1μAT A = -40°C to +85°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —5μAT A = -40°C to 125°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —50μA24C01C and 24C02C only SCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CCNote 1:This parameter is periodically sampled and not 100% tested.24AAXX/24LCXX/24FCXX TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01CAND 24C02CAC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.Characteristic Min.Max.Units Conditions1F CLK Clock frequency————1004004001000kHz 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX2T HIGH Clock high time4000600600500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX3T LOW Clock low time470013001300500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX4T R SDA and SCL rise time(Note1)———1000300300ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX5T F SDA and SCL fall time(Note1)——300100ns All except 24FCXXX1.7V ≤ V CC≤ 5.5V 24FCXXX6T HD:STA Start condition hold time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX7T SU:STA Start condition setup time4700600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX8T HD:DAT Data input hold time0—ns(Note2)9T SU:DAT Data input setup time250100100———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX10T SU:STO Stop condition setup time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX11T SU:WP WP setup time4000600600———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX12T HD:WP WP hold time470013001300———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXXNote1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.© 2007 Microchip Technology Inc.DS21930B-page 524AAXX/24LCXX/24FCXXDS21930B-page 6© 2007 Microchip Technology Inc.13T AAOutput valid from clock (Note 2)————3500900900400ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 14T BUFBus free time: Time the bus must be free before a new transmission can start 470013001300500————ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 15T OF Output fall time from V IH minimum to V IL maximum C B ≤ 100pF10 + 0.1C B250250nsAll except 24FCXXX (Note 1)24FCXXX (Note 1)16T SP Input filter spike suppression (SDA and SCL pins)—50ns All except 24FCXXX (Note 1)17T WC Write cycle time (byte or page)—5ms18—Endurance1,000,000—cycles 25°C (Note 3)TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C AND 24C02C (CONTINUED)AC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsNote 1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.24AAXX/24LCXX/24FCXX TABLE 2-3:AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02CAll Parameters apply across all recommended operating ranges unless otherwise noted Industrial (I):T A = -40°C to +85°C, V CC = 1.7V to 5.5V Automotive (E):T A = -40°C to +125°C, V CC = 4.5V to 5.5VParameter Symbol Min.Max.Units ConditionsClock frequency F CLK———100100400kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock high time T HIGH40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock low time T LOW470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL rise time (Note1)T R———10001000300ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL fall time T F—300ns(Note1)Start condition hold time T HD:STA40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStart condition setup time T SU:STA47004700600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VData input hold time T HD:DAT0—ns(Note2)Data input setup time T SU:DAT250250100———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStop condition setup time T SU:STO40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput valid from clock (Note2)T AA———35003500900ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VBus free time: Time the bus must be free before a new transmis-sion can start T BUF470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput fall time from V IH minimum to V IL maximum T OF20+0.1CB250ns(Note1), CB ≤ 100 pFInput filter spike suppression(SDA and SCL pins)T SP—50ns(Note1)Write cycle time T WC—41.5ms24XX0024C01C, 24C02CEndurance1,000,000—cycles(Note3)Note1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained at .© 2007 Microchip Technology Inc.DS21930B-page 724AAXX/24LCXX/24FCXXDS21930B-page 8© 2007 Microchip Technology Inc.FIGURE 2-1:BUS TIMING DATA(unprotected)(protected)SCL SDA INSDA OUTWP 57616328913D441011121424AAXX/24LCXX/24FCXX3.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table3-1.TABLE 3-1:PIN FUNCTION TABLE3.1A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pins are not used by the 24XX01 through 24XX16 devices.The A0, A1 and A2 inputs are used by the 24C01C, 24C02C, 24XX014, 24XX024, 24XX025 and the 24XX32 through 24XX512 for multiple device opera-tions. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.For the 24XX128 and 24XX256 in the MSOP package only, pins A0 and A1 are not connected.Up to eight devices (two for the 24XX128 and 24XX256 MSOP package) may be connected to the same bus by using different Chip Select bit combinations.In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.3.2Serial Data (SDA)This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to V CC (typical 10kΩ for 100kHz, 2kΩ for 400kHz and1MHz).For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.3.3Serial Clock (SCL)This input is used to synchronize the data transfer to and from the device.3.4Write-Protect (WP)This pin must be connected to either V SS or V CC. If tied to V SS, write operations are enabled. If tied to V CC, write operations are inhibited but read operations are not affected. See Table1-1 for the write-protect scheme of each device.3.5Power Supply (V CC)A V CC threshold detect circuit is employed which disables the internal erase/write logic if V CC is below 1.5V at nominal conditions. For the 24C00, 24C01C and 24C02C devices, the erase/write logic is disabled below 3.8V at nominal conditions.Pin Name8-PinPDIP andSOIC8-PinTSSOP andMSOP5-Pin SOT-2324XX005-Pin SOT-23All except24XX0014-PinTSSOP8-Pin5x6 DFN and2x3 DFNFunctionA011(1)——11User configurable Chip Select(3) A122(1)——22User configurable Chip Select(3) A233——63User configurable Chip Select(3) V SS442274GroundSDA553385Serial DataSCL661196Serial Clock(NC)——4—3, 4, 5,10, 11, 12—Not ConnectedWP7(2)7(2)—5137Write-Protect InputV CC8854148Power SupplyNote1:Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.2:Pin 7 is not used for 24XX00, 24XX025 and 24C01C.3:Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table1-1 for details.© 2007 Microchip Technology Inc.DS21930B-page 924AAXX/24LCXX/24FCXXDS21930B-page 10© 2007 Microchip Technology Inc.4.0FUNCTIONAL DESCRIPTIONEach 24XX device supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which gener-ates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.Block DiagramHV GeneratorEEPROM Array Page Latches*YDECXDECSense Amp.R/W ControlM emory C ontrol L ogicI/O C ontrol L ogic I/OA0*A1*A2*SDASCLV CC V SSWP** A0, A1, A2, WP and page latches are not used by some devices.See Table 1-1, Device Selection Table, for details.5.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the busis not busy.•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure5-1).5.1Bus Not Busy (A)Both data and clock lines remain high.5.2Start Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.5.3Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.5.4Data Valid (D)The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device.5.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end-of-data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave.In this case, the slave (24XX) will leave the data line high to enable the master to generate the Stop condition (Figure 5-2).FIGURE 5-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSFIGURE 5-2:ACKNOWLEDGE TIMINGNote:During a write cycle, the 24XX will not acknowledge commands.SCLSDA(A)(B)(D)(D)(A)(C)Start ConditionAddress or AcknowledgeValid Data Allowed to ChangeStop ConditionSCL 987654321123Transmitter must release the SDA line at this point,allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.Receiver must release the SDA line at this point so the Transmitter can continue sending data.Data from transmitterSDA AcknowledgebitData from transmitter5.6Device Addressing For Devices Without Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-3).The control byte begins with a four-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the block-select bits (B2, B1, B0). They are used by the master device to select which of the 256-word blocks of memory are to be accessed. These bits are in effect the three Most Significant bits of the word address. Note that B2, B1 and B0 are “don’t care” for the 24XX00, the 24XX01 and 24XX02. B2 and B1 are “don’t care” for the 24XX04. B2 is “don’t care” for the 24XX08.The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’ a write operation is selected.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, the block Acknowledge signal on the SDA line. The address byte follows the acknowledge.FIGURE 5-3:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITHOUT ADDRESS PINSS 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x xB0R/W ACK S 1010xB1B0R/W ACK S11B2B1B0R/WACK24XX0124XX0224XX0424XX0824XX016x = “don’t care” bitAcknowledge Control CodeStart bitControl ByteBlock Select bitsAddress Byte24XX00Read/Write bit (read = 1, write = 0)x x x x A3..A0x A6.....A0A7......A0A7......A0A7......A0A7......A0bit5.7Device Addressing For Devices With Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-4).The control byte begins with a 4-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX devices on the same bus and are used to select which device is accessed.The Chip Select bits in the control byte must corre-spond to the logic levels on the corresponding A2, A1and A0 pins for the device to respond. These bits are,in effect, the three Most Significant bits of the word address.For 24XX128 and 24XX256 in the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figure 5-4)should be set to ‘0’. Only two 24XX128 or 24XX256MSOP packages can be connected to the same bus.The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected.For higher density devices (24XX32 through 24XX512), the next two bytes received define the address of the first data byte. Depending on the prod-uct density, not all bits in the address high byte are used. A15, A14, A13 and A12 are “don’t care” for 24XX32. A15, A14 and A13 are “don’t care” for 24XX64. A15 and A14 are “don’t care” for 24XX128.A15 is “don’t care” for 24XX256. All address bits are used for the 24XX512. The upper address bits are transferred first, followed by the Less Significant bits.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, appropriate device select bits and the R/W bit, the slave device out-puts an Acknowledge signal on the SDA line. The address byte(s) follow the acknowledge.FIGURE 5-4:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITH ADDRESS PINSS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S110A2A1A0R/W ACK24XX6424XX12824XX25624XX512x = “don’t care” bitAcknowledgeControl Code Start bitControl ByteChip Select bits*Address High Byte24XX32Read/Write bitx x x x A11A10A9A8x x xA12A11A10A9A8x xA13A12A11A10A9A8xA14A13A12A11A10A9A8A15A14A13A12A11A10A9A8bitS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S11A2A1A0R/WACKx A6.....A0A7......A0A7......A024XX024/02524C02C 24C01C Address ByteA7......A0A7......A0A7......A0A7......A0A7......A0Address Low Byte* Chip Select bits A1 and A0 must be set to ‘0’ for 24XX128/256 devices in the MSOP package.Control Byte(Read = 1, Write = 0)。

ROM-0524SP中文资料

Efficiency / Load
100 80 60
0512
1212
1215
3.312 Efficiency %
40 20 0
0515 3.315
Efficiency %
20 0
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
Total Output current (%)
Total Output current (%)
DC/DC-Converter
Typical Characteristics
ROM Series
ROM-xx09S
Efficiency / Load
100 80 60
ROM-xx05S
Efficiency / Load
100 80 60 40
3.305
1205
0509
0505 Efficiency %
Detailed Information see Application Notes chapter "MTBF"
100 80
Derating-Graph
(Ambient Temperature)
Output Power (%)
60 40 30 20 0
Safe Operating Area
85 Operating Temperature °C
ECONOLINE
DC/DC-Converter
ROM Series
1 Watt SIP4 Micro Size Single Output
Selection Guide

CDRH64BNP-561MB中文资料

1．外形1-1．寸法図(mm)＊公差のない寸法は参考値とする。

1-2．捺印表示例 O-3．推奨ランド図(mm)2．コイル仕様2-1．端子接続図(裏面図)電極（端子）間の隙間はシルク処理をして御使用下さい。

捺印位置不定製造密番頭部直捺印100電極側電極側compliance Cd:Max.0.01wt%others:Max.0.1wt%RoHS12-2.電気的特性Ⅰ(リール梱包の場合)NO. 品名表示インダクタンス［以内］※1D.C.R.(Ω)[以下](at 20℃)※2定格電流(Ａ)※3スミダコード0102 CDRH64BNP-1ØØMCCDRH64BNP-12ØMC10012010μH ± 20%12μH ± 20%0.12 (88m)0.13 (97m)1.351.204745-01454745-01460304 CDRH64BNP-15ØMCCDRH64BNP-18ØMC15018015μH ± 20%18μH ± 20%0.18 (0.13)0.24 (0.18)1.101.004745-01474745-01480506 CDRH64BNP-22ØMCCDRH64BNP-27ØMC22027022μH ± 20%27μH ± 20%0.27 (0.20)0.30 (0.22)0.910.824745-01494745-01500708 CDRH64BNP-33ØMCCDRH64BNP-39ØMC33039033μH ± 20%39μH ± 20%0.33 (0.25)0.37 (0.27)0.750.694745-01514745-01520910 CDRH64BNP-47ØMCCDRH64BNP-56ØMC47056047μH ± 20%56μH ± 20%0.52 (0.38)0.56 (0.41)0.620.584745-01544745-01551112 CDRH64BNP-68ØMCCDRH64BNP-82ØMC68082068μH ± 20%82μH ± 20%0.63 (0.47)0.71 (0.53)0.520.474745-01564745-01571314 CDRH64BNP-1Ø1MCCDRH64BNP-121MC101121100μH ± 20%120μH ± 20%1.03 (0.76)1.15 (0.85)0.430.394745-01584745-01591516 CDRH64BNP-151MCCDRH64BNP-181MC151181150μH ± 20%180μH ± 20%1.68 (1.29)1.87 (1.44)0.350.324745-01604745-01611718 CDRH64BNP-221MCCDRH64BNP-271MC221271220μH ± 20%270μH ± 20%2.08 (1.60)2.37 (1.82)0.290.264745-01624745-01631920 CDRH64BNP-331MCCDRH64BNP-391MC331391330μH ± 20%390μH ± 20%2.67 (2.05)2.94 (2.26)0.230.224745-01654745-01662122 CDRH64BNP-471MCCDRH64BNP-561MC471561470μH ± 20%560μH ± 20%3.93 (3.02)5.43 (4.18)0.200.184745-01674745-01682324 CDRH64BNP-681MCCDRH64BNP-821MC681821680μH ± 20%820μH ± 20%7.32 (5.63)8.24 (6.34)0.170.154745-01694745-017025 CDRH64BNP-1Ø2MC 102 1 mH ± 20% 9.26 (7.13) 0.14 4745-0171※1: 測定周波数Ｌ at 1 kHz※2: ( )内は、標準値とする。

asco 电磁阀综合选型中文样本

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常见编译错误信息

常见编译错误信息A.1 visual c++ 6.0的错误信息概述visual C++ 6.0的编译连接错误信息分为三种类型：致命错误、一般错误和警告。

其中，致命错误是内部编译和连接器出错，一般错误指程序的语法错误，磁盘、文件或内存存取错误或命令行错误等，警告则只指出一些值得怀疑的情况，它并不阻止编译的进行。

Visual C++ 6.0的编译连接错误信息分为下列类型：编译器错误，错误代码 C999－C3999.编译器警告，错误代码C4000－C4999.连接器错误，错误代码LNK1000－LNK2035.连接器警告，错误代码LNK4001-LNK4255.C运行时错误，错误代码R6002－R6035.C运行时警告，错误代码CRT1001.资源编译器错误，错误代码RC1000－RC2236.资源编译器警告，错误代码RC4000-RC4413.资源编译器警告，错误代码RW1004-RW4004.NMAKE错误，错误代码U1000-U4014.ATL提供程序错误和警告，错误代码ATL2004-ATL4111.命令行错误，错误代码D8000-D8046.命令行警告，错误代码D9000-D9044.配置优化错误和警告，错误代码PG0001-PG1087.项目生成错误和警告，错误代码PRJ0002-PRJ0051.CVTRES错误，错误代码CVT1100-CVT4001.BSCMAKE错误，错误代码BK1500-BK4503.表达式计算错误，错误代码CXX0000-CXX0072数学错误，错误代码M6101-M6205.SPROXY错误，错误代码SDL0000-SDL1030.SPROXY警告，错误代码SDL4000-SDL4009.Web部署错误和警告，错误代码VCD0001-VCD0048.XDCMake错误和警告，错误代码VCD0001-VCD0048.其中最常用的是编译器错误和警告。

Visual C++ 6.0的编译连接错误信息数量庞大，而且是英文版的。

脑外伤患者急性期血浆白蛋白和前白蛋白的改变

脑外伤患者急性期血浆白蛋白和前白蛋白的改变石磊;张曙光;潘天鸿;李晓良【摘要】目的：检测脑外伤患者急性期外周血中血浆白蛋白和前白蛋白的表达水平。

方法：脑外伤患者126例，根据格拉斯哥昏迷量表（GCS）评分分为轻型组63例，中型组53例，重型组46例。

于伤后6 h内检测患者血浆白蛋白和前白蛋白，伤后6个月对患者预后程度进行评价；比较不同病情患者血浆白蛋白和前白蛋白水平，分析血浆白蛋白、前白蛋白表达水平与预后相关性。

结果：轻型组外周血血浆白蛋白为（40.37依3.62）g/L，前白蛋白（320.36依23.17）mg/L；中型组外周血血浆白蛋白为（38.13依7.27）g/L，前白蛋白（260.33依37.12）mg/L；重型组外周血血浆白蛋白为（32.17依2.36）g/L，前白蛋白（213.67依21.16）mg/L。

轻型组和中型组的血浆白蛋白差异无统计学意义（>0.05），前白蛋白差异有统计学意义（<0.05）。

重型组和其他2组之间急性期血浆白蛋白和前白蛋白差异有统计学意义（<0.05）。

本组预后良好107例，预后不良55例。

脑外伤后血浆白蛋白（=0.731）和前白蛋白（=0.903）水平与患者预后呈明显相关（<0.05）。

结论：脑外伤后急性期血浆前白蛋白和白蛋白水平明显下降，可能提示患者预后不良。

【期刊名称】《神经损伤与功能重建》【年(卷),期】2014(000)005【总页数】2页(P431-432)【关键词】脑外伤;前白蛋白;白蛋白【作者】石磊;张曙光;潘天鸿;李晓良【作者单位】昆山市第一人民医院神经外科江苏昆山 215300;昆山市第一人民医院神经外科江苏昆山 215300;昆山市第一人民医院神经外科江苏昆山 215300;昆山市第一人民医院神经外科江苏昆山 215300【正文语种】中文【中图分类】R741;R651.1+5在临床工作中，医生们发现格拉斯哥昏迷量表（Glasgow coma scale，GCS）常常不能很好地预测脑外伤患者的预后[1]。

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元器件交易网
P-CapTM Model 2264 Analog Accelerometer Module
SIGNAL DESCRIPTIONS
(28 gauge wires + shield)
Power: +Exc (Red) and -Exc (Black): +Exc (+3 to +11 VDC) and -Exc (-3 to -11 VDC). +Out (Green) and -Out (White): +Out minus -Out voltage is proportional to acceleration; +Out voltage increases and -Out decreases with positive acceleration. At zero acceleration both outputs are nominally equal to mid-way between the +Exc and the -Exc values. The device experiences positive (+1g) acceleration with its lid (part number) facing up in the Earth’s gravitational field. Either output can be used individually or the two outputs can be used differentially. (See output response plot below)
2264-005
±5 0 - 600 100 9
2264-010±10 0 Nhomakorabea- 1000 50 10
2264-025
±25 0 - 1500 20 25
2264-050
±50 0 - 2000 10 50
2264-100
±100 0 - 2500 5 100
2264-200
+/-200 0 - 3000 2.5 200
元器件交易网
SILICON DESIGNS, INC
P-CapTM Model 2264 ANALOG ACCELEROMETER MODULE
! Accurate, Easy-to-Use Alternative to Piezoresistive Accelerometers ! Sensitivity Insensitive to Variations in Excitation Voltage, Temperature and Cable Resistance ! Frequency Response Insensitive to Temperature ! 6 to 22V Excitation (dual or single supply) ! Differential Output Signal / EMI Resistant ! Capacitive Micromachined ! Nitrogen Damped to 0.7 (nominal) ! Sensitivity Accurate to 2% (typical) ! -40 to +85EC Operation ! Traditional Four Wire Connection ! Responds to DC and AC Accelerations ! Rugged Anodized Aluminum Module & PTFE Cable ! Serialized for Traceability ! Non-Standard g Ranges Available ! Other Output Sensitivities Available
DESCRIPTION
The P-CapTM model 2264 accelerometer is a high performance and wide temperature range accelerometer intended to directly replace piezoresistive units for existing and new applications. It uses a capacitive sensing element and an advanced ASIC to simulate the operation of a piezoresistive bridge. It is tailored for zero to medium frequency instrumentation applications. The anodized aluminum case is epoxy sealed and is easily mounted via two #4 (or M3) screws. Internal regulation is provided to eliminate the effects of excitation voltage variation. Unlike piezoresistive elements, its sensitivity, bias and frequency response are insensitive to temperature changes or thermal gradients. The cable’s shield is electrically connected to the case while the ground (GND) wire is isolated from the case. An optional initial calibration sheet (2264-CAL) and periodic calibration checking are also available.
OPERATION
The P-CapTM model 2264 can be operated from supply voltages ranging from ±3 to ±11 VDC. It produces two analog voltage outputs which vary with acceleration as shown in the graph on the next page. The sensitive axis is perpendicular to the bottom of the package, with positive acceleration resulting from a force pushing on the bottom of the package. The signal outputs are fully differential about a common mode voltage that is midway between the two supply voltages which is 0 volts when equal plus and minus supplies are used. The output sensitivity or scale factor is independent of changes in the excitation voltage. At zero acceleration, the output differential voltage is nominally 0 volts DC; at ±full scale acceleration the output differential voltage is ±0.5 volts DC respectively. Single supply operation is also possible by connecting -Exc to ground and +Exc to +6 to +22 VDC but the average value of the +OUT and -OUT signals will be at ½ the supply voltage and each output will swing from ±0.25 volts around the ½ supply voltage level. Standard cable length is 1 meter.
PERFORMANCE - By Model: +Exc=+5, -Exc=-5VDC, TC=25EC
MODEL NUMBER Input Range Frequency Response (Nominal, -3 dB) Sensitivity, Differential Output Noise, Differential (RMS, typical) Max. Mechanical Shock (0.1 ms)
APPLICATIONS
! CRASH TESTING ! VIBRATION MONITORING ! VIBRATION ANALYSIS ! MACHINE CONTROL
P-Cap is a trademark of Silicon Designs, Inc.
! MODAL ANALYSIS ! ROBOTICS ! FLIGHT TESTING ! MACHINERY INSTRUMENTATION
2
MIN
TYP 2 50
MAX 3 5 200 5 +250 0.5 1.0 1.5 0.3 +0.25 ±11 13 624
UNITS % % of span (ppm of span)/EC % ppm/EC % of span % Ω VDC VDC mA DC mA/volt µV/µA grams grams/meter