ADC0808S125资料

CLOCK DRIVER
ADC0808S
LATCH
17 26
CCS CCSSEL
IN INN
33 32
TRACK AND HOLD
8
RESISTOR LADDERS
ADC CORE
LATCH
8
D0 to D7 21 OTC
FSIN/ REFSEL
30 U/I LATCH
20
IR
INTERNAL REFERENCE
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ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
Rev. 02 — 7 October 2008 Product data sheet
1. General description
The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC) optimized for telecommunication transmission control systems and tape drive applications. It allows signal sampling frequencies up to 250 MHz. The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output signal levels are 1.8 V CMOS. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V CMOS compatible. The ADC0808S offers the most flexible acquisition control system possible due to its programmable Complete Conversion Signal (CCS) which allows the delay time of the acquisition clock and acquisition clock frequency to be adjusted. The ADC0808S is supplied in an HTQFP48 package.
43 VCCO4(1v8)
46 OGND4
OGND1 D3 i.c. VCCO1(1V8) D4 i.c. OGND2 D5 i.c.
1 2 3 4 5 6 7 8 9 DGND
37 CLK+ 36 CLKSEL 35 i.c. 34 VCCA1(3V3) 33 IN 32 INN 31 AGND2 30 FSIN/REFSEL 29 CMADC 28 AGND1 27 NC1V8 26 CCSSEL 25 n.c. n.c. 24
HTQFP48 plastic thermal enhanced thin quad flat package; SOT545-2 48 leads; body 7 × 7 × 1 mm; exposed die pad
5. Block diagram
CLKSEL 36 CLK+ CLK− 37 38 39 40 DEL0 DEL1
4. Ordering information
Table 1. Ordering information Sampling frequency Package (MHz) Name 125 250 Description Version Type number ADC0808S125HW/C1 ADC0808S250HW/C1
© NXP B.V. 2008. Ata sheet
Rev. 02 — 7 October 2008
VCCD1(1V8) 23
38 CLK−
41 D0
42 i.c.
48 i.c.
45 i.c.
47 D2
44 D1
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NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
Pin description …continued Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type[1] G O I(CMOS) O(CMOS) I(CMOS) G P I(CMOS) I G O I G I I P I(CMOS) I I I(CMOS) I(CMOS) O P O G O G Description internally connected; leave open data output ground 3 complete conversion signal output internally connected; leave open chip enable input (active LOW) in-range output control input for 2’s complement output digital ground 1 digital supply voltage 1 (1.8 V) not connected not connected control input for CCS frequency selection not connected or connected to VCCD1(1V8) analog ground 1 regulator common-mode ADC output full-scale reference voltage input/internal or external reference selection analog ground 2 complementary analog input analog input analog supply voltage 1 (3.3 V) internally connected; leave open control input for clock input selection clock input complementary clock input complete conversion signal delay input 0 complete conversion signal delay input 1 data output bit 0 internally connected; leave open data output supply voltage 4 (1.8 V) data output bit 1 internally connected; leave open data output ground 4 data output bit 2 internally connected; leave open digital ground; exposed die pad
3. Applications
I 2.5G and 3G cellular base infrastructure radio transceivers I Wireless access systems I Fixed telecommunications
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6.2 Pin description
Table 2. Symbol OGND1 D3 i.c. VCCO1(1V8) D4 i.c. OGND2 D5 i.c. VCCO2(1V8) D6 i.c. VCCO3(1V8) D7
ADC0808S125_ADC0808S250_2
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Type[1] G O P O G O P O P O Description data output ground 1 data output bit 3 internally connected; leave open data output supply voltage 1 (1.8 V) data output bit 4 internally connected; leave open data output ground 2 data output bit 5 internally connected; leave open data output supply voltage 2 (1.8 V) data output bit 6 internally connected; leave open data output supply voltage 3 (1.8 V) data output bit 7
2. Features
I I I I I I I I I I I I I I 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external control for analog input full-scale Integrated voltage regulator for input common-mode reference Selectable 1.8 V CMOS or LVDS clock input 1.8 V CMOS digital outputs 1.8 V CMOS compatible static digital inputs Binary or 2’s complement CMOS outputs Only 2 clock cycles latency Industrial temperature range from −40 °C to +85 °C HTQFP48 package
Rev. 02 — 7 October 2008
2 of 23
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NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
6. Pinning information
6.1 Pinning
001aai268
40 DEL1 OTC 21
39 DEL0 DGND1 22
ADC0808S
VCCO2(1V8) 10 D6 11 i.c. 12 VCCO3(1V8) 13 D7 14 i.c. 15 OGND3 16 CCS 17 i.c. 18 CE_N 19 IR 20
Fig 2.
Pin configuration
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
I Optical networking I Wireless Local Area Network (WLAN) infrastructure I Tape drive applications
CMADC REFERENCE 29 CMADC
OUTPUTS ENABLE 19
001aai267
CE_N
Fig 1.
Block diagram
ADC0808S125_ADC0808S250_2
© NXP B.V. 2008. All rights reserved.
Product data sheet