FPGA可编程逻辑器件芯片XC3S1600E-5FG484C中文规格书

Figure 99: QSPI High-level Block Diagram
X23020-072920
Functional Units
The high-level block diagram includes several major functional units.
TXFIFO and RXFIFO
The controller has a 64-word TXFIFO for sending content to the I/O interface and a 64-word RXFIFO for receiving data from the I/O interface. Use the QSPI.TXD register data port to write data to the TXFIFO and the RXD register data port to read data from the RXFIFO.
Command FIFO
Software writes 20-bit command words to QSPI.GEN_FIFO to configure and initiate transactions
on the I/O interface. The command generator initiates transactions that are driven by the command fields. The controller transmits data written to the TXFIFO and receives data read from the RXFIFO.
Polling
The controller can repeatedly read the status of a the flash device looking for a specific pattern. This can be used to monitor the status of a flash device operation or other purpose.
DMA Controller
The DMA controller is used to move large blocks of data from the flash device to system memory. This is a master, write-only DMA controller on the AXI bus interface. It can only be used
to read data from the flash device and write the data to system memory.
Interfaces
The controller has two system interfaces and a single I/O interface.
32-bit APB Slave Programming Interface
•Memory mapped, programming registers
•Control, status, and interrupt registers
•FIFO data ports
AXI Master Interface for DMA Controller Memory Writes
•44-bit physical address with 32-word data bursts
•AxCACHE defines coherency and buffer-ability of the transaction
Flash Memory I/O Interface
• 4 and 8-bit data I/O (one or two devices)
•Chip select
•QSPI_CLK clock
•Loopback clock
System Interfaces
The DMA is a burst-enabled, 32-bit AXI master on the PMC IOP interconnect. There are several PMC_IOP_SLCR registers available to control the AxCACHE and AxUSER transaction parameters. The AXI write transactions include three options:
•Coherent or non-coherent with the FPD CCI
•Buffer-ability in the system
•Quality of service (QoS) settings
Coherent and Bufferable Transactions
The AXI coherency and bufferable transaction attribute can be programmed using the
QSPI_AXI_COH register. If hardware coherency with the APU L2 cache is needed, the transaction must be routed through the FPU CCI using the register. If coherency is not enabled, the FPD CCI can be bypassed for higher performance.
Note: In most applications, coherency is managed by software. The hardware coherency through the CCI slows down the DMA transfers and can severely impact the performance of the APU.
Section XIII: Flash Memory Controllers
Chapter 74: Quad SPI Controller
QoS
There are three classes of QoS transactions, which are explained in Quality of Service. Normally, the best effort class is chosen. The class selection is controlled by the
QSPI_IOP_INTERCONNECT_QOS register.
System Signals
The system signals connected to the QSPI controller include:
•Clocks
•Controller Resets
•System Interrupt
•System Error
The controller connects to several signals coming from and going to the system.
Clocks
The controller receives two clocks from the system.
IOP Switch Interface Clock
The three system interfaces are clocked by the IOP_IRO_CLK clock used for the IOP switch. Reference Clock
The controller reference clock is generated by the PMC clock controller using a CRP register.•OSPI_REF_CLK controlled by the OSPI_REF_CTRL register
Controller Resets
Other resets are used to clear separate parts of the controller under software control by writing to the QSPI.FIFO_CTRL register. The QSPI-specific resets include:
•[RST_GEN_FIFO]
•[RST_TX_FIFO]
•[RST_RX_FIFO]
System Interrupt
The QSPI register module OR's the individual controller interrupts and generates a single system interrupt, IRQ #157.。