Alisertib_1028486-01-2_DataSheet_MedChemExpress
KSZ8851-16MLL DEMO BOARD 48-PIN ETHERNET CONTROLLE
SD13
SD7 40
CPU_D14 3
6
SD14
SD8 39
CPU_D15 4
5
SD15
SD9 36
SD10 35
33
SD11 34
CPU_CMD
33
SD12 33
R10
SD13 32
CPU_CSN
33
SD14 31
R12
SD15 30
CPU_WRN
33
CMD
11
R14
CPU_RDN
33
CSN
12
R16
5 6 7 8
TANT
C27
R28 10uF
470pF 2.49K
Power 3.3V 0.1uF (red LED)
CSN CMD
4.7K R27 4.7K R29
GBLC03C_0 D3
GND 2 GND
VR 5 3.3VA
INTRN 4.7K R30
VOUT = 1.24 X [ 1 + ( 2.49k/ 1.5K ) ]
5
4
3
KSZ8851-16MLL (48-pin) Demo Board Black Diagram
D
Headers 20x2
RJ45
LAN1 T
KSZ8851-16MLL
Reset
Power
+1.8V
+2.5V
+3.3V
STATUS LEDs
OSC
EEPROM
C
MIC5209YM
25 MHz
AT93C46
x2
2
1
DATE:
ALC5621_DataSheet_1.0
ALC5621I2S AUDIO CODEC + 1.3W CLASS AB/D MONO SPEAKER AMPLIFIERDATASHEETRev. 1.027 December 2007Track ID: JATR-1076-21Realtek Semiconductor Corp.No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, TaiwanTel.: +886-3-578-0211. Fax: +886-3-577-6047I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifierii Track ID: JATR-1076-21 Rev. 1.0COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.DISCLAIMERRealtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.TRADEMARKSRealtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.USING THIS DOCUMENTThis document is intended for the hardware and software engineer’s general information on the Realtek ALC5621 Audio Codec IC.Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORYRevision Release Date Summary1.0 2007/12/27 First releaseTable of Contents1.GENERAL DESCRIPTION (1)2.FEATURES (2)3.SYSTEM APPLICATIONS (2)4.BLOCK DIAGRAMS (3)4.1.F UNCTION B LOCK (3)4.2.A UDIO M IXER P ATH (4)5.PIN ASSIGNMENTS (5)5.1.G REEN P ACKAGE AND V ERSION I DENTIFICATION (5)6.PIN DESCRIPTIONS (6)6.1.D IGITAL I/O P INS (6)6.2.A NALOG I/O P INS (6)6.3.F ILTER/R EFERENCE (7)6.4.P OWER/G ROUND (7)7.FUNCTIONAL DESCRIPTION (8)7.1.P OWER (8)7.2.R ESET (8)7.2.1.Power-On Reset (POR) (8)7.3.C LOCKING (9)7.3.1.Phase-Locked Loop (9)7.3.2.I2C and Stereo I2S (10)7.4.D IGITAL D ATA I NTERFACE (11)7.4.1.Stereo I2S/PCM Interface (11)7.5.A UDIO D ATA P ATH (14)7.5.1.Vref (14)7.5.2.Stereo ADC (14)7.5.3.Stereo DAC (14)7.6.M IXERS (15)7.6.1.Headphone Mixer (15)7.6.2.MONO Mixer (16)7.6.3.Speaker Mixer (16)7.6.4.ADC Record Mixer (17)7.7.A NALOG A UDIO I NPUT P ATH (18)7.7.1.Line Input (18)7.7.2.AUXiliary Input (18)7.7.3.Microphone Input (18)7.8.A NALOG A UDIO O UTPUT D ATA P ATH (19)7.8.1.Speaker Output (19)7.8.2.Headphone Output (20)7.8.3.MONO Output (20)7.9.AVC C ONTROL (21)7.10.H ARDWARE S OUND E FFECTS (23)7.10.1.Equalizer Block (23)7.10.2.Pseudo Stereo and Spatial 3D Sound (23)7.11.I2C C ONTROL I NTERFACE (24)7.11.1.Addressing Setting (24)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier iii Track ID: JATR-1076-21 Rev. 1.0plete Data Transfer (24)7.12.O DD-A DDRESSED R EGISTER A CCESS (25)7.13.P OWER M ANAGEMENT (25)7.14.GPIO AND J ACK D ETECT F UNCTION (26)7.15.I NTERNAL E VENT S IGNAL I NTERRUPTS (27)7.16.H EADPHONE D EPOP (27)8.MIXER REGISTERS LIST (28)8.1.R EG-00H:R ESET (28)8.2.R EG-02H:S PEAKER O UTPUT V OLUME (28)8.3.R EG-04H:H EADPHONE O UTPUT V OLUME (29)8.4.R EG-06H:MONO_OUT/AUXOUT V OLUME (30)8.5.R EG-08H:AUXIN V OLUME (30)8.6.R EG-0A H:LINE_IN V OLUME (31)8.7.R EG-0C H:STEREO DAC V OLUME (31)8.8.R EG-0E H:MIC V OLUME (32)8.9.R EG-10H:MIC R OUTING C ONTROL (32)8.10.R EG-12H:ADC R ECORD G AIN (33)8.11.R EG-14H:ADC R ECORD M IXER C ONTROL (33)8.12.R EG-16H:A VOL S OFT V OLUME C ONTROL T IME (34)8.13.R EG-1C H:O UTPUT M IXER C ONTROL (34)8.14.R EG-22H:M ICROPHONE C ONTROL (35)8.15.R EG-34H:D IGITAL A UDIO I NTERFACE C ONTROL (35)8.16.R EG-36A H:S TEREO AD/DA C LOCK C ONTROL (36)8.17.R EG-38H:C OMPANDING C ONTROL (37)8.18.R EG-3A H:P OWER M ANAGEMENT A DDITION 1 (37)8.18.1.Headphone Output Amplifier Configuration (38)8.18.2.Auxiliary Output Amplifier Configuration (38)8.19.R EG-3C H:P OWER M ANAGEMENT A DDITION 2 (39)8.20.R EG-3E H:P OWER M ANAGEMENT A DDITION 3 (40)8.21.R EG-40H:A DDITIONAL C ONTROL R EGISTER (41)8.22.R EG-42H:G LOBAL C LOCK C ONTROL R EGISTER (42)8.23.R EG-44H:PLL C ONTROL R EGISTER (42)8.23.1.Reg-44h: PLL Control Register (42)8.23.2.PLL Clock Setting Table for 48K: (Unit: MHz) (43)8.23.3.PLL Clock Setting Table for 44.1K: (Unit: MHz) (43)8.24.R EG-4A H:GPIO_O UTPUT P IN C ONTROL (43)8.25.R EG-4C H:GPIO P IN C ONFIGURATION (44)8.26.R EG-4E H:GPIO P IN P OLARITY (44)8.27.R EG-50H:GPIO P IN S TICKY (45)8.28.R EG-52H:GPIO P IN W AKE-U P (45)8.29.R EG-54H:GPIO P IN S TATUS (46)8.30.R EG-56H:P IN S HARING (46)8.31.R EG-58H:O VER-C URRENT S TATUS (47)8.32.R EG-5A H:J ACK D ETECT C ONTROL R EGISTER (47)8.33.R EG-5E H:MISC C ONTROL (48)8.34.R EG-60H:S TEREO AND S PATIAL E FFECT B LOCK C ONTROL (49)8.35.R EG-62H:EQ C ONTROL (50)8.36.R EG-66H:EQ M ODE C HANGE E NABLE (51)8.37.R EG-68H:AVC C ONTROL (51)8.38.R EG-6A H:I NDEX A DDRESS (52)8.39.R EG-6C H:I NDEX D ATA (52)8.40.I NDEX-00H:EQ B AND-0C OEFFICIENT (LP0: A1) (52)8.41.I NDEX-01H:EQ B AND-0G AIN (LP0:H O) (52)8.42.I NDEX-02H:EQ B AND-1C OEFFICIENT (BP1: A1) (53)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier iv Track ID: JATR-1076-21 Rev. 1.08.43.I NDEX-03H:EQ B AND-1C OEFFICIENT (BP1: A2) (53)8.44.I NDEX-04H:EQ B AND-1G AIN (BP1:H O) (53)8.45.I NDEX-05H:EQ B AND-2C OEFFICIENT (BP2: A1) (53)8.46.I NDEX-06H:EQ B AND-2C OEFFICIENT (BP2: A2) (54)8.47.I NDEX-07H:EQ B AND-2G AIN (BP2:H O) (54)8.48.I NDEX-08H:EQ B AND-3C OEFFICIENT (BP3: A1) (54)8.49.I NDEX-09H:EQ B AND-3C OEFFICIENT (BP3: A2) (54)8.50.I NDEX-0A H:EQ B AND-3G AIN (BP3:H O) (55)8.51.I NDEX-0B H:EQ B AND-4C OEFFICIENT (HPF: A1) (55)8.52.I NDEX-0C H:EQ B AND-4G AIN (HPF:H O) (55)8.53.I NDEX-11H:EQ I NPUT V OLUME C ONTROL (55)8.54.I NDEX-12H:EQ O UTPUT V OLUME C ONTROL (56)8.55.I NDEX-21H:A UTO V OLUME C ONTROL R EGISTER 1 (56)8.56.I NDEX-22H:A UTO V OLUME C ONTROL R EGISTER 2 (56)8.57.I NDEX-23H:A UTO V OLUME C ONTROL R EGISTER 3 (56)8.58.I NDEX-24H:A UTO V OLUME C ONTROL R EGISTER 4 (57)8.59.I NDEX-25H:A UTO V OLUME C ONTROL R EGISTER 5 (57)8.60.I NDEX-39H:D IGITAL I NTERNAL R EGISTER (57)8.61.I NDEX-46H:C LASS D I NTERNAL R EGISTER (58)8.62.R EG-7C H:VENDOR ID1 (58)8.63.R EG-7E H:VENDOR ID2 (58)9.ELECTRICAL CHARACTERISTICS (59)9.1.DC C HARACTERISTICS (59)9.1.1.Absolute Maximum Ratings (59)9.1.2.Recommended Operating Conditions (59)9.1.3.Static Characteristics (59)9.2.A NALOG P ERFORMANCE C HARACTERISTICS (60)9.3.S IGNAL T IMING (62)9.3.1.I2C Control Interface (62)9.3.2.I2S Master Mode (63)9.3.3.I2S Slave Mode (64)10.APPLICATION CIRCUIT (65)11.MECHANICAL DIMENSIONS (66)12.APPENDIX A: STEREO I2S CLOCK TABLE (68)13.ORDERING INFORMATION (69)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier v Track ID: JATR-1076-21 Rev. 1.0List of TablesT ABLE 1.D IGITAL I/O P INS (6)T ABLE 2.A NALOG I/O P INS (6)T ABLE 3.F ILTER/R EFERENCE (7)T ABLE 4.P OWER/G ROUND (7)T ABLE 5.R ESET O PERATION (8)T ABLE 6.P OWER-O N R ESET V OLTAGE (8)T ABLE 7.C LOCK S ETTING T ABLE FOR 48K(U NIT:MH Z) (9)T ABLE 8.C LOCK S ETTING T ABLE FOR 44.1K(U NIT:MH Z) (10)T ABLE 9.MONO/AUXOUT O UTPUT S IGNAL T ABLE (20)T ABLE 10.A DDRESSING S ETTING (24)T ABLE 11.W RITE WORD P ROTOCOL (25)T ABLE 12.R EAD WORD P ROTOCOL (25)T ABLE 13.R EG-00H:R ESET (28)T ABLE 14.R EG-02H:S PEAKER O UTPUT V OLUME (28)T ABLE 15.R EG-04H:H EADPHONE O UTPUT V OLUME (29)T ABLE 16.R EG-06H:MONO_OUT/AUXOUT V OLUME (30)T ABLE 17.R EG-08H:AUXIN V OLUME (30)T ABLE 18.R EG-0A H:LINE_IN V OLUME (31)T ABLE 19.R EG-0C H:STEREO DAC V OLUME (31)T ABLE 20.R EG-0E H:MIC V OLUME (32)T ABLE 21.R EG-10H:MIC R OUTING C ONTROL (32)T ABLE 22.R EG-12H:ADC R ECORD G AIN (33)T ABLE 23.R EG-14H:ADC R ECORD M IXER C ONTROL (33)T ABLE 24.R EG-16H:A VOL S OFT V OLUME C ONTROL T IME (34)T ABLE 25.R EG-1C H:O UTPUT M IXER C ONTROL (34)T ABLE 26.R EG-22H:M ICROPHONE C ONTROL (35)T ABLE 27.R EG-34H:A UDIO I NTERFACE (35)T ABLE 28.R EG-36H:S TEREO AD/DA C LOCK C ONTROL (36)T ABLE 29.R EG-38H:C OMPANDING C ONTROL (37)T ABLE 30.R EG-3A H:P OWER M ANAGEMENT A DDITION 1 (37)T ABLE 31.H EADPHONE O UTPUT A MPLIFIER C ONFIGURATION (38)T ABLE 32.A UXILIARY O UTPUT A MPLIFIER C ONFIGURATION (38)T ABLE 33.R EG-3C H:P OWER M ANAGEMENT A DDITION 2 (39)T ABLE 34.R EG-3E H:P OWER M ANAGEMENT A DDITION 3 (40)T ABLE 35.R EG-40H:A DDITIONAL C ONTROL R EGISTER (41)T ABLE 36.R EG-42H:G LOBAL C LOCK C ONTROL R EGISTER (42)T ABLE 37.R EG-44H:PLL C ONTROL R EGISTER (42)T ABLE 38.PLL C LOCK S ETTING T ABLE FOR 48K:(U NIT:MH Z) (43)T ABLE 39.PLL C LOCK S ETTING T ABLE FOR 44.1K:(U NIT:MH Z) (43)T ABLE 40.R EG-4C H:GPIO_O UTPUT P IN C ONTROL (43)T ABLE 41.R EG-4C H:GPIO P IN C ONFIGURATION (44)T ABLE 42.R EG-4E H:GPIO P IN P OLARITY (44)T ABLE 43.R EG-50H:GPIO P IN S TICKY (45)T ABLE 44.R EG-52H:GPIO P IN W AKE-U P (45)T ABLE 45.R EG-54H:GPIO P IN S TATUS (46)T ABLE 46.R EG-56H:P IN S HARING (46)T ABLE 47.R EG-58H:O VER-C URRENT S TATUS (47)T ABLE 48.R EG-5A H:J ACK D ETECT C ONTROL R EGISTER (47)T ABLE 49.R EG-5E H:MISC C ONTROL (48)T ABLE 50.R EG-60H:S TEREO AND S PATIAL E FFECT B LOCK C ONTROL (49)T ABLE 51.R EG-62H:EQ C ONTROL (50)T ABLE 52.R EG-66H:EQ M ODE C HANGE E NABLE (51)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier vi Track ID: JATR-1076-21 Rev. 1.0T ABLE 53.R EG-68H:AVC C ONTROL (51)T ABLE 54.R EG-6A H:I NDEX A DDRESS (52)T ABLE 55.R EG-6C H:I NDEX D ATA (52)T ABLE 56.I NDEX-00H:EQ B AND-0C OEFFICIENT (LP0: A1) (52)T ABLE 57.I NDEX-01H:EQ B AND-0G AIN (LP0:H O) (52)T ABLE 58.I NDEX-02H:EQ B AND-1C OEFFICIENT (BP1: A1) (53)T ABLE 59.I NDEX-03H:EQ B AND-1C OEFFICIENT (BP1: A2) (53)T ABLE 60.I NDEX-04H:EQ B AND-1G AIN (BP1:H O) (53)T ABLE 61.I NDEX-05H:EQ B AND-2C OEFFICIENT (BP2: A1) (53)T ABLE 62.I NDEX-06H:EQ B AND-2C OEFFICIENT (BP2: A2) (54)T ABLE 63.I NDEX-07H:EQ B AND-2G AIN (BP2:H O) (54)T ABLE 64.I NDEX-08H:EQ B AND-3C OEFFICIENT (BP3: A1) (54)T ABLE 65.I NDEX-09H:EQ B AND-3C OEFFICIENT (BP3: A2) (54)T ABLE 66.I NDEX-0A H:EQ B AND-3G AIN (BP3:H O) (55)T ABLE 67.I NDEX-0B H:EQ B AND-4C OEFFICIENT (HPF: A1) (55)T ABLE 68.I NDEX-0C H:EQ B AND-4G AIN (HPF:H O) (55)T ABLE 69.I NDEX-11H:EQ I NPUT V OLUME C ONTROL (55)T ABLE 70.I NDEX-12H:EQ O UTPUT V OLUME C ONTROL (56)T ABLE 71.I NDEX-21H:A UTO V OLUME C ONTROL R EGISTER 1 (56)T ABLE 72.I NDEX-22H:A UTO V OLUME C ONTROL R EGISTER 2 (56)T ABLE 73.I NDEX-23H:A UTO V OLUME C ONTROL R EGISTER 3 (56)T ABLE 74.I NDEX-24H:A UTO V OLUME C ONTROL R EGISTER 4 (57)T ABLE 75.I NDEX-25H:A UTO V OLUME C ONTROL R EGISTER 5 (57)T ABLE 76.I NDEX-39H:D IGITAL I NTERNAL R EGISTER (57)T ABLE 77.I NDEX-46H:C LASS D I NTERNAL R EGISTER (58)T ABLE 78.R EG-7C H:VENDOR ID1 (58)T ABLE 79.R EG-7E H:VENDOR ID2 (58)T ABLE 80.A BSOLUTE M AXIMUM R ATINGS (59)T ABLE 81.R ECOMMENDED O PERATING C ONDITIONS (59)T ABLE 82.S TATIC C HARACTERISTICS (59)T ABLE 83.A NALOG P ERFORMANCE C HARACTERISTICS (60)T ABLE 84.I2C T IMING (62)T ABLE 85.T IMING OF I2S M ASTER M ODE (63)T ABLE 86.I2S S LAVE M ODE T IMING (64)T ABLE 87.O RDERING I NFORMATION (69)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier vii Track ID: JATR-1076-21 Rev. 1.0List of FiguresF IGURE 1.B LOCK D IAGRAM (3)F IGURE 2.A UDIO M IXER P ATH (4)F IGURE 3.P IN A SSIGNMENTS (5)F IGURE 4.A UDIO SYSCLK (9)F IGURE 5.PCM M ONO D ATA M ODE A F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=0) (11)F IGURE 6.PCM M ONO D ATA M ODE A F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=1, PCM_MODE_SEL=0) (11)F IGURE 7.PCM M ONO D ATA M ODE B F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=1) (12)F IGURE 8.PCM S TEREO D ATA M ODE A F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=0) (12)F IGURE 9.PCM S TEREO D ATA M ODE B F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0, PCM_MODE_SEL=1) (12)F IGURE 10.I2S D ATA F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0) (13)F IGURE 11.L EFT J USTIFIED D ATA F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0) (13)F IGURE 12.R IGHT J USTIFIED D ATA F ORMAT (STEREO_I2S_BCLK_POLARITY_CTRL=0) (13)F IGURE 13.A UTO V OLUME C ONTROL B LOCK D IAGRAM (22)F IGURE 14.AVC B EHAVIOR (22)F IGURE 15.D ATA T RANSFER O VER I2C C ONTROL I NTERFACE (24)F IGURE 16.GPIO I MPLEMENTATION (26)F IGURE 17.J ACK D ETECT AND IRQ L OGIC (27)F IGURE 18.P OWER C ONTROL TO MIC I NPUT (41)F IGURE 19.J ACK-I NSERT-D ETECT P ULL U P R ESISTER I MPLEMENTED VIA AN E XTERNAL C IRCUIT (49)F IGURE 20.I2C C ONTROL I NTERFACE (62)F IGURE 21.T IMING OF I2S M ASTER M ODE (63)F IGURE 22.I2S S LAVE M ODE T IMING (64)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier viii Track ID: JATR-1076-21 Rev. 1.01.General DescriptionThe ALC5621 is a highly-integrated I2S/PCM interface audio codec with multiple input/output ports and is designed for mobile computing and communications. It provides a Stereo Hi-Fi DAC for playback and Stereo ADC for recording via the I2S/PCM interface.To reduce component count, the device can connect directly to:•MONO or stereo differential analog inputs•LINE_IN stereo Single-Ended analog inputs•AUX_IN Single-Ended analog inputs•Stereo Headphone Output•Single-end stereo configurable to AUXOUT or BTL MONO_OUT•MONO or Stereo Bridge-Tied Load (BTL) speakerMultiple analog input and output pins are provided for seamless integration with analog connected wireless communication devices. Differential input/output connections efficiently reduce noise interference, providing better sound quality. Class AB or Class D amplifiers are easily swapped via simple register configuration, and the 1.3 Watt Mono speaker removes the need for an additional amplifier, further cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with configurable gain, bandwidth, and center frequency, enriches the sound experience.The ALC5621 AVDD operates at supply voltages from 2.3V to 3.6V. DVDD operates from 1.71 to 3.6V, and SPKVDD operates from 2.3 to 5V. To extend battery life, each section of the device can be powered down individually under software control. Leakage current in maximum power saving state is less than 10µA.The ALC5621 is available in a 5x5mm ‘Green’ QFN-32 package, making it ideal for use in handheld portable systems.I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 1Track ID: JATR-1076-21 Rev. 1.0I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 2Track ID: JATR-1076-21 Rev. 1.0 2. FeaturesDigital-to-Analog Converter with 92dB SNR and –85dB THD+N Analog-to-Digital Converter with 85dB SNR and –80dB THD+N Two analog stereo single-ended inputs, LINE-IN_L/R and AUXIN_L/R Stereo differential analog microphone inputs, with boost pre-amplifiers (+20/+30/+40dB) BTL (Bridge-Tied Load) Speaker output with on-chip 1.3W speaker driver (SPKVDD=5V, 4.7Ω load with THD+N=40dB) Mono Speaker output supports Class AB or Class D optional Stereo headphone output with on-chip 45mW headphone driver (AVDD=3.3V, 16Ω load) 25mW SE or 75mW BTL Single-Ended differential MONO_OUT configurable to AUXOUT (AVDD=3.3V, 32Ω load)Audio jack insert detection and microphoneswitch detectionPower management and enhanced powersavingSupports digital 5-band equalizer (EQ) Supports digital spatial sound and pseudostereo effectSupports pop noise suppressionInternal PLL can receive wide range of clockinputDigital power supplies from 1.71V to 3.6V;speaker amplifier power supplies from 2.3V to 5VAnalog power and headphone power suppliedfrom 2.3V to 3.6VSupports soft-mute function32-pin QFN package3. System Applications Tablet PC system/Ultra-Mobile PC (UMPC) Personal Digital Assistants (PDA) or PDA Phone Multimedia Phone ApplicationsPortable Navigation Device (PND)Bluetooth HeadphoneI S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier3Track ID: JATR-1076-21 Rev. 1.04.Block Diagrams4.1.Function BlockMICBIASSDAM C L KSCLK SPK_OUT_NSPK_OUT AUXOUT_RAUXOUT_L LINE_IN_R LINE_IN_L MIC1P MIC1N MIC2P MIC2N ALC5621D A C D A TA D C D A TB C L KL R C KAUXIN_L AUXIN_RG P I O /I R QPLL_OUTFigure 1. Block DiagramI S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 4Track ID: JATR-1076-21 Rev. 1.04.2.Audio Mixer Path)10[1210[4]5]L +R+RR+RFigure 2. Audio Mixer PathI S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 5Track ID: JATR-1076-21 Rev. 1.0M I C 1PM I C 2PM I C 1NL I N E _I N _L /J D 1M I C 2NL I N E _I N _R /J D 2L R C KB C L KADCDATDACDAT MCLK DGND DCVDD DBVDD GPIO/IRQ/PLL_OUT SCLKS D AC d e p o pA U X I N _LA U X I N _RA U X O U T _L /M O N O _O U TA U X O U T _R /M O N O _O U T _NS P K _O U TS P K G N DSPKVDD SPK_OUT_NVREF AGND HP_OUT_R HP_OUT_LAVDD MICBIASN C /Figure 3. Pin Assignments5.1. Green Package and Version IdentificationGreen package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shownin the location marked ‘V’.6.1.Digital I/O PinsTable 1. Digital I/O PinsName Type Pin Description Characteristic DefinitionLRCK IO7DigitalAudioSynchronousSignal Master:V OL =0.1*DVDD, V OH =0.9*DVDDSlave: Schmitt triggerBCLK IO8DigitalAudioSerialClock Master:V OL =0.1*DVDD, V OH =0.9*DVDDSlave: Schmitt triggerADCDAT O 9 SerialADCDataOutput V OL =0.1*DVDD, V OH =0.9*DVDD DACDAT I 10 Serial DAC Data Input Schmitt triggerMCLK I 11 Master Clock Input Schmitt triggerGPIO/ IRQ/PLL_OUT IO/O/O15 General Purpose Input And Output/Interrupt Output/PLL OutputGPIO: Input/OutputIRQOUT: OutputPLL_OUT: OutputSCLK I16I2C Clock Schmitt triggerSDA IO17I2C Data Schmitt triggerTotal: 8 Pins6.2.Analog I/O PinsTable 2. Analog I/O PinsName Type Pin Description Characteristic Definition MIC1P I 1 First Mic Positive Input Analog Input (1Vrms) MIC1N I 2 First Mic Negative Input Analog Input (1Vrms) LINE_IN_L/JD1 I 3 Line Input Left Channel/Jack DetectInput_1Analog Input (1Vrms) MIC2P I 4 Second Mic Positive Input Analog Input (1Vrms) MIC2N I 5 Second Mic Negative Input Analog Input (1Vrms) LINE_IN_R/JD2 I 6 Line Input Right Channel/Jack DetectInput_2Analog Input (1Vrms) AUXIN_L I 19 Auxiliary Input Left Channel Analog Input (1Vrms) AUXIN_R I 20 Auxiliary Input Right Channel Analog Input (1Vrms)AUXOUT_L/ MONO_OUT O 21 Positive Mono Output/AuxiliaryOutput Left ChannelAnalog Output (1Vrms)AUXOUT_R/ MONO_OUT_N O 22 Negative Mono Output/AuxiliaryOutput Right ChannelAnalog Output (1Vrms)SPK_OUT O 23 Speaker Output Analog Output (1.5Vrms, SPKVDD=5V) SPK_OUT_N O 25 Negative Speaker Output Analog Output (1.5Vrms, SPKVDD=5V) HP_OUT_R O 29 Headphone Output Right Channel Analog Output (1Vrms)HP_OUT_L O 30 Headphone Output Left Channel Analog Output (1Vrms)Total: 14 PinsI S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 6Track ID: JATR-1076-21 Rev. 1.0I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 7Track ID: JATR-1076-21 Rev. 1.06.3. Filter/ReferenceTable 3. Filter/ReferenceName Type Pin Description Characteristic Definition NC/Cdepop IO 18 NC/De-Pop Capacitor 1µf capacitor to analog ground VREF O 27 Internal Reference V oltage 1µf capacitor to analog ground MICBIAS O 32 MIC BIAS V oltage Output Programmable Analog DC output with 3mA drive Total: 3 Pins6.4. Power/GroundTable 4. Power/Ground Name Type Pin Description Characteristic Definition DGND P 12 Digital GND - DCVDD P 13 Digital VDD 1.71V~3.6V (Core) DBVDD P 14 Digital VDD 1.71V~3.6V (IO Buffer) SPKGND P 24 Analog GND for Speaker Amps - SPKVDD P 26 Analog VDD for Speaker Amps 2.3V~5V AGND P 28 Analog GND - A VDD P 31 Analog VDD 2.3V~3.6V Total: 7 Pins7.Functional Description7.1.PowerThe ALC5621 has many power blocks. SPKVDD operates between 2.3V and 3.0V for weak Class AB amplifiers, and between 3.0V and 5V for strong Class AB amplifiers. The full range is available for ClassD amplifiers.AVDD operates between 2.3V and 3.6V. DBVDD and DCVDD operate between 1.71V and 3.6V. TheALC5621 must handle ratio control between the different power blocks. The power supplier limit conditions are DBVDD ≥ DCVDD, and SPKVDD ≥ AVDD ≥ DCVDD.7.2.ResetThere are two types of reset operation: Power-On Reset (POR) and Register reset.Table 5. Reset OperationReset Type Trigger Condition CODEC ResponsePOR Monitor digital power supply voltage reach V POR Reset all hardware logic and all registers to defaultvalues.Register Reset Write Reg-00h Reset all registers to default values except PLLrelated register7.2.1.Power-On Reset (POR)When powered on, DCVDD passes through the V POR band of ALC5621 (V PORH ~V PORL). A Power-On Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.Table 6. Power-On Reset VoltageSymbol Min Typical Max UnitV POR_ON 1.0 - 1.6 V V POR_OFF- 1.3 - V Note: V POR_OFF must be below V POR_ON.I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 8Track ID: JATR-1076-21 Rev. 1.0I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 9Track ID: JATR-1076-21 Rev. 1.07.3. ClockingThe Audio SYSCLK can be selected from MCLK or PLL. The clock source of PLL can be selected from MCLK or BCLK. The ALC5621 only supports 256Fs or 384Fs as Audio SYSCLK (used as Stereo I 2Sclock).Figure 4. Audio SYSCLK7.3.1. Phase-Locked LoopA Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. Typicalchoices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to MCLK or BCLK by setting pll_sour_sel (Reg42[14]).The source clock of MCLK must be able to drive I 2C, and F/W can setup PLL to output the desired frequency as the SYSCLK.The PLL transmit formula is: F OUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}Table 7. Clock Setting Table for 48K (Unit: MHz)MCLK N M F VCO K F OUT13 66 7 98.222 2 24.555 3.6864 78 1 98.304 2 24.576 2.048 94 0 98.304 2 24.576 4.096 70 1 98.304 2 24.576 12 80 8 98.4 2 24.6 15.36 81 11 98.068 2 24.517 16 78 11 98.462 2 24.615 19.2 80 14 98.4 2 24.6 19.68 78 14 98.4 2 24.6Table 8. Clock Setting Table for 44.1K (Unit: MHz)MCLK N M F VCO K F OUT13 68 8 91 2 22.753.6864 72 1 90.931 2 22.7332.048 86 0 90.112 2 22.5284.096 64 1 90.112 2 22.52812 66 7 90.667 2 22.66715.36 63 9 90.764 2 22.69116 66 10 90.667 2 22.66719.2 64 12 90.514 2 22.62919.68 67 13 90.528 2 22.632 After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to default values after a soft-reset (write Reg00).7.3.2.I2C and Stereo I2SThe ALC5621 supports the I2S digital interface for Stereo Audio. The stereo audio digital interface is used to input data to the stereo DAC or output data from the stereo ADC. The Stereo Audio Digital Interface can be configured as Master mode or Slave mode. For the Stereo I2S Interface, the source system clock is always input from MCLK. Refer to section 12 Appendix A: Stereo I2S Clock Table, page 68 for details.Master ModeIn master mode (stereo_i2s_mode_sel=0), BCLK and LRCK are configured as output. Whensel_sysclk=0, MCLK is used as Stereo SYSCLK. When PLL is enabled and sel_sysclk=1, MCLK is suggested to provide frequencies shown in Table 7 Clock Setting Table for 48K (Unit: MHz) and Table 8 Clock Setting Table for 44.1K (Unit: MHz). PLL can be configured to support 44.1K and 48K base sampling rate.Slave ModeIn slave mode (stereo_i2s_mode_sel=1), BCLK/LRCK is configured as input. MCLK should provide the BCLK synchronized clock externally as the Stereo_SYSCLK.Note: The ALC5621 does not support different sample rates between SDAC and ADC in Stereo_I2S/PCM.I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 10Track ID: JATR-1076-21 Rev. 1.0I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 11Track ID: JATR-1076-21 Rev. 1.07.4.Digital Data Interface7.4.1.Stereo I 2S/PCM InterfaceThe stereo I 2S/PCM interface can be configured as Master mode or Slave mode. Four audio data formats are supported: • PCM mode • Left justified mode • Right justified mode • I 2S modeFigure 5. PCM Mono Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=0)Figure 6. PCM Mono Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=1, pcm_mode_sel=0)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 12Track ID: JATR-1076-21 Rev. 1.0Figure 7. PCM Mono Data Mode B Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=1)Figure 8. PCM Stereo Data Mode A Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=0)Figure 9. PCM Stereo Data Mode B Format (stereo_i2s_bclk_polarity_ctrl=0, pcm_mode_sel=1)I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier13Track ID: JATR-1076-21 Rev. 1.0Figure 10. I 2S Data Format (stereo_i2s_bclk_polarity_ctrl=0)Figure 11. Left Justified Data Format (stereo_i2s_bclk_polarity_ctrl=0)Figure 12. Right Justified Data Format (stereo_i2s_bclk_polarity_ctrl=0)7.5.Audio Data Path7.5.1.VrefVref is the reference voltage for all analog blocks. An external 1µF Capacitor connected to AGND is required. The default status of Vref is enabled after power on. Driver can set Index-39[11]=0b in order to enable power control bit of Reg-3C[13]:pow_vref.7.5.2.Stereo ADCThe stereo ADC is used for recording stereo sound. The sample rate of the stereo ADC is independent of the stereo DAC sample rate. In order to save power, the left and right ADC can be powered down separately by setting adc_l_vol & adc_r_volThe sample rate of the Stereo ADC is the same as the sample rate of Stereo DAC (described in the following section).7.5.3.Stereo DACThe stereo DAC can be configured to different sample rates by driving 256Fs/384Fs into audio SYSCLK with setting divider properly (Reg36). adda_osr is used to control the over sample rate clock divider of the DA filter to 128Fs or 64Fs.Performance of 128Fs is better than 64Fs but with much higher power consumption. Refer to section 12 Appendix A: Stereo I2S Clock Table, page 68 for detailed settings.dac_l_vol & dac_r_vol can be used to control the DAC output volume.I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 14Track ID: JATR-1076-21 Rev. 1.07.6.MixersThe ALC5621 supports four mixers for all audio function requirements:•Headphone mixer for 2 channels•MONO mixer•Speaker mixer•ADC record mixer7.6.1.Headphone MixerThe headphone mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT, and MONO_OUT (AUXOUT_L/R). The output of the headphone mixer can be input to the ADC record mixer.The following signals can be mixed into the headphone mixer:•LINE-IN_L/R (Controlled by Reg0A)•PHONEP/N (Controlled by Reg08)•MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)•Stereo DAC output (Controlled by Reg0C)•ADC record mixer output (Controlled by Reg12 & Reg14).When the SPK_OUT source is from the HP_mixer, SPK_OUT can be configured to L/R, L+R, and L/LN by setting spk_outn_source. The headphone mixer can be powered down by setting pow_mix_hp_l & pow_mix_hp_r.I S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 15Track ID: JATR-1076-21 Rev. 1.0。
MagellanTM 8300 8400 Quick Reference Guide
Magellan TM 8300/8400Quick Reference GuideDatalogic ADC, Inc.959 Terry StreetEugene, OR 97402USATelephone: (541) 683-5700Fax: (541) 345-7140©2006-2013 Datalogic ADC, Inc.An Unpublished Work - All rights reserved. No part of the contents of this documentation or the procedures described therein may be reproduced or transmitted in any form or by any means without prior written permission of Datalogic ADC, Inc. or its subsidiaries or affiliates ("Datalogic" or “Datalogic ADC”). Owners of Datalogic products are hereby granted a non-exclusive, revocable license to reproduce and transmit this documentation for the purchaser's own internal busi-ness purposes. Purchaser shall not remove or alter any proprietary notices, including copyright notices, contained in this documentation and shall ensure that all notices appear on any reproductions of the documentation.Should future revisions of this manual be published, you can acquire printed versions by contacting your Datalogic repre-sentative. Electronic versions may either be downloadable from the Datalogic website () or provided on appropriate media. If you visit our website and would like to make comments or suggestions about this or other Dat-alogic publications, please let us know via the "Contact Datalogic" page.DisclaimerDatalogic has taken reasonable measures to provide information in this manual that is complete and accurate, however, Datalogic reserves the right to change any specification at any time without prior notice.Datalogic and the Datalogic logo are registered trademarks of Datalogic S.p.A. in many countries, including the U.S.A. and the E.U. All other brand and product names may be trademarks of their respective owners.Magellan is a registered trademark of Datalogic ADC, Inc. in many countries, including the U.S.A. and All-Weighs, First-Strike and SurroundScan are registered trademarks of Datalogic ADC, Inc. in the U.S.A. OmegaTek, Produce Rail, Produc-tivity Index Reporting and SmartSentry are all trademarks of Datalogic ADC, Inc.This product may be covered by one or more of the following patents:4603262 • 4639606 • 4652750 • 4672215 • 4699447 • 4709369 • 4749879 • 4786798 • 4792666 • 4794240 • 4798943 • 4799164 • 4820911 • 4845349 • 4861972 • 4861973 • 4866257 • 4868836 • 4879456 • 4939355 • 4939356 • 4943127 • 4963719 • 4971176 • 4971177 • 4991692 • 5001406 • 5015831 • 5019697 • 5019698 • 5086879 • 5115120 • 5144118 • 5146463 • 5179270 • 5198649 • 5200597 • 5202784 • 5208449 • 5210397 • 5212371 • 5212372 • 5214270 • 5229590 • 5231293 • 5232185 • 5233169 • 5235168 • 5237161 • 5237162 • 5239165 • 5247161 • 5256864 • 5258604 • 5258699 • 5260554 • 5274219 • 5296689 • 5298728 • 5311000 • 5327451 • 5329103 • 5330370 • 5347113 • 5347121 • 5371361 • 5382783 • 5386105 • 5389917 • 5410108 • 5420410 • 5422472 • 5426507 • 5438187 • 5440110 • 5440111 • 5446271 • 5446749 • 5448050 • 5463211 • 5475206 • 5475207 • 5479011 • 5481098 • 5491328 • 5493108 • 5504350 • 5508505 • 5512740 • 5541397 • 5552593 • 5557095 • 5563402 • 5565668 • 5576531 • 5581707 • 5594231 • 5594441 • 5598070 • 5602376 • 5608201 • 5608399 • 5612529 • 5629510 • 5635699 • 5641958 • 5646391 • 5661435 • 5664231 • 5666045 • 5671374 • 5675138 • 5682028 • 5686716 • 5696370 • 5703347 • 5705802 • 5714750 • 5717194 • 5723852 • 5750976 • 5767502 • 5770847 • 5786581 • 5786585 • 5787103 • 5789732 • 5796222 • 5804809 • 5814803 • 5814804 • 5821721 • 5822343 • 5825009 • 5834708 • 5834750 • 5837983 • 5837988 • 5852286 • 5864129 • 5869827 • 5874722 • 5883370 • 5905249 • 5907147 • 5923023 • 5925868 • 5929421 • 5945670 • 5959284 • 5962838 • 5979769 • 6000619 • 6006991 • 6012639 • 6016135 • 6024284 • 6041374 • 6042012 • 6045044 • 6047889 • 6047894 • 6056198 • 6065676 • 6069696 • 6073849 • 6073851 • 6094288 • 6112993 • 6129279 • 6129282 • 6134039 • 6142376 • 6152368 • 6152372 • 6155488 • 6166375 • 6169614 • 6173894 • 6176429 • 6188500 • 6189784 • 6213397 • 6223986 • 6230975 • 6230976 • 6244510 • 6259545 • 6260763 • 6266175 • 6273336 • 6276605 • 6279829 • 6290134 • 6290135 • 6293467 • 6303927 • 6311895 • 6318634 • 6328216 • 6332576 • 6332577 • 6343741 • 6454168 • 6478224 • 6568598 • 6578765 • 6705527 • 6857567 • 6974084 • 6991169 • 7051940 • 7170414 • 7172123 • 7201322 • 7204422 • 7215493 • 7224540 • 7234641 • 7243850 • 7374092 • 7407096 • 7490770 • 7495564 • 7506816 • 7527198 • 7527207 • 7537166 • 7562817 • 601 26 118.6 • AU703547 • D312631 • D313590 • D320011 • D320012 • D323492 • D330707 • D330708 • D349109 • D350127 • D350735 • D351149 • D351150 • D352936 • D352937 • D352938 • D352939 • D358588 • D361565 • D372234 • D374630 • D374869 • D375493 • D376357 • D377345 • D377346 • D377347 • D377348 • D388075 • D446524 • D606544 •EP0256296 • EP0260155 •EP0260156 • EP0295936 • EP0325469 • EP0349770 • EP0368254 • EP0442215 • EP0498366 • EP0531645 • EP0663643 • EP0698251 • EP01330772 • EP870761 • GB2252333 • GB2284086 • GB2301691 • GB2304954 • GB2307093 • GB2308267 • GB2308678 • GB2319103 • GB2333163 • GB2343079 • GB2344486 • GB2345568 • GB2354340 • ISR107546 • ISR118507 • ISR118508 • JP1962823 • JP1971216 •JP2513442 • JP2732459 • JP2829331 • JP2953593 • JP2964278 • MEX185552 • MEX187245 • RE37166 • RE40071Additional patents pendingDATALOGIC ADC, INC. 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Government Restricted Rights; International Use.9.1 Use, duplication, or disclosure of the Software by the U.S. Government is subject to the restrictions for computer software developed at privateexpense as set forth in the U.S. Federal Acquisition Regulations at FAR 52.227-14(g), or 52.227-19 or in the Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013(c)(1)(ii), whichever is applicable.9.2 If End User is using the Datalogic Product outside of the United States, End User must comply with the applicable local laws of the country in which theDatalogic Product is used, with U.S. export control laws, and with the English language version of this Agreement. The provisions of the "United Nations Convention on International Sale of Goods" shall not apply to this Agreement.10. Termination.10.1 Either party may terminate this Agreement or any license granted under this Agreement at any time upon written notice if the other party breaches anyprovision of this Agreement.10.2 Upon termination of this Agreement, End User immediately shall cease using any non-embedded software and shall return to Datalogic or destroy allnon-embedded software covered by this Agreement, and shall furnish Datalogic with a certificate of compliance with this provision signed by an officer or authorized representative of End User. For embedded software, End User agrees to sign a waiver prepared by Datalogic concerning further use of the embedded Software. End User's resumed or continued use of the embedded Software after termination shall constitute End User's agreement to be bound by the terms and conditions of this Agreement for such use.11. General Provisions.11.1 Entire Agreement; Amendment. This document contains the entire agreement between the parties relating to the licensing of the Software and super-sedes all prior or contemporaneous agreements, written or oral, between the parties concerning the licensing of the Software. This Agreement may not be changed, amended, or modified except by written document signed by Datalogic.11.2 Notice. All notices required or authorized under this Agreement shall be given in writing, and shall be effective when received, with evidence of receipt.Notices to Datalogic shall be sent to the attention of Contract Administration, Datalogic Holdings, Inc., 959 T erry Street, Eugene, OR 97402, or such other address as may be specified by Datalogic in writing.11.3 Waiver. A party's failure to enforce any of the terms and conditions of this Agreement shall not prevent the party's later enforcement of such terms andconditions.11.4Governing Law; Venue: This Agreement and the rights of the parties hereunder shall be governed by and construed in accordance with the laws of theState of Oregon U.S.A, without regard to the rules governing conflicts of law. The state or federal courts of the State of Oregon located in either Mult-nomah or Lane counties shall have exclusive jurisdiction over all matters regarding this Agreement, except that Datalogic shall have the right, at its absolute discretion, to initiate proceedings in the courts of any other state, country, or territory in which End User resides, or in which any of End User's assets are located.11.5 Attorneys’ Fees. In the event an action is brought to enforce the terms and conditions of this Agreement, the prevailing party shall be entitled to reason-able attorneys' fees, both at trial and on appeal.- END -ii Magellan® 8300/8400Quick Reference Guide1Quick ReferenceThe object of this manual is to provide general operational information for the user. For more product details, including installation, set-up, programming and advanced user information, reference the Product Reference Guide (PRG), which is available for viewing and download from the website listed on the back cover of this manual.Controls and IndicatorsThe control panel consists of an indicator LED and two push buttons as shown in Figure 1. The bottom-most button also serves as an indicator LED for scale func-tions (scale models ONLY). The unit also includes a speaker (beeper) which can be configured to sound indications of scanning and weighing activities. Refer to LED and Beeper Indications for more information about the functions of the push buttons and indicators.Figure 1. Controls and IndicatorsSpea (BeePortScale Z Button & LVolume/TBu LED IndicatorPower Supply Array The scanner may require either a Listed Class 2 or Listed LPS powersource which supplies power directly to the unit. It is sometimes pos-sible for a scanner to receive power directly from the terminal(P.O.T.). See the current product data sheet for more informationabout P.O.T.Scanning ItemsPush or slide items through the 360° scan zone (shown here) in either a left-to-right or right-to-left motion. The scanner has the ability to “see” a bar codelocated on any side (left, right, front, back or bottom) of a product, so there’srarely a need to reorient an item in order to scan it.For best scanning results...•Move items through the scan zone in their natural orientation. It’s notnecessary to reorient the bar code toward either the horizontal or verticalscan window.•Sliding or pushing items rather than picking them up will avoid thegripping, twisting and rotating movements that can cause repetitivemotion injuries to hands and wrists. The strain of lifting potentiallythousands of pounds per day can also be relieved using this technique.2Magellan TM 8300/8400With the 360° scan pattern and advanced FirstStrike® decoding software, theMagellan® 8300/8400 can read most hard-to-read codes quickly and withoutexcess orientation.Weighing Items Using the All-Weighs® PlatterItems to be weighed can be placed anywhere on the L-shaped All-Weighs® platter(weigh platter) surface. Oversized items can even be accurately weighed whileleaned against the center of its vertical section as shown.The optional, raised Produce Bar or Produce Rail™ features conveniently ensurethat items do not rest on the counter or other non-weighing surfaces. Withweighed items in place, enter PLU (Price Look-Up) data as described in the POSinstructions for your system. Weight data will be displayed on the Remote ScaleDisplay and/or the host display.with the All-Weighs® PlatterFigure 3. Weighing ItemsLED IndicatorsThe scanner LED (top-most) indicates scanner status, and the scale button/LED(scale models ONLY) is used to show scale status. See Table 1 for a listing of LEDindications.Quick Reference Guide 3Table 1. Scanner and Scale Indicationsa.Certain functions of the Green and Y ellow LEDs are selectable to be enabled or disabled. Y our scannermay not be programmed to display all indications.4Magellan TM 8300/8400Volume/Tone Push ButtonThe Volume/Tone Push Button also performs multiple functions depend-ing upon the duration of time it is pressed:Table 2. Volume/Tone Push Button FunctionsPRESSDURATIONFUNCTION COMMENTMomentary (when scanner is in Sleep Mode)Wakes scanner fromSleep ModeAlternatively, the scanner can be awakened by:- Moving an object through the scan zone.- A weight change on the scale.- Scanning with an attached auxiliary scanner.Momentary (whenscanner is in Normal Operating Mode)Increments volumePress the push button momentarily to increase speaker vol-ume. When the loudest volume is reached, a repeated pressof the push button cycles volume back to the lowest setting,then volume increases on subsequent press(es). Four vol-ume levels are available.Hold, then releasewhen the beeper sounds Increments tonePress the push button for approximately 2 seconds, thenrelease. Each time this is done, the beeper will sound at oneof three tones. Stop when the desired tone (high, medium orlow) is sounded.4 Seconds Scanner DiagnosticsMode aThis mode allows system support personnel to troubleshootproblems with the scanner. Generally diagnostics are initiatedafter noting a Field Replaceable Unit (FRU) Warning (seeTable 1). Cycle power to exit Scanner Diagnostics Mode.8 Seconds Resets Scanner b Only system support personnel should perform a reset.a.By standard default, this function is normally disabled to prevent accidental activation by users.ers should not perform scanner resets except under the direction of trained systems support person-nel.Quick Reference Guide 56Magellan TM 8300/8400Scale Zero Push ButtonThe Scale Zero Push Button is used for two functions as described in Table 3. This button has no function on “scanner-only” models.Table 3. Scale Zero Push Button FunctionsEAS-Enabled SystemsElectronic Article Surveillance (EAS) systems are aftermarket options, and are installed by either Sensormatic ® or Checkpoint ® technicians at your site depending upon which EAS product package is purchased to use with your scanner.Once the system is activated, EAS security tags are automatically deactivated by passing items over the EAS antenna located beneath the scanner’s platter.PRESS DURATIONFUNCTION COMMENTMomentary Zero ScaleWhen programmed to do so, the yellow Scale LED should be lit when no weight is on the scale, indicating scale at zero. If it is not, press the switch to zero the scale. The unit will sound a “click” upon pressing the button.Momentary (when the scale’s primary indication shows an under zero condition)Scale power cycleWhen programmed to do so, and when certain conditions are met, pressing this button will initiate a scale power cycle. When the scale zero button is pushed and the weight on the scale is close to zero, the scale will zero normally like the zero scale function above. Otherwise, the scale will go through a power cycle. If the scale is able to find zero after the power cycle, the scale will perform normally. Otherwise, the scale’s primary indication will display a non-weight indication.4 SecondsScale Diag-nostics Mode aThis mode allows system support personnel to troubleshoot problems with the scale. Cycle power to exit Scale Diagnostics Mode.a.Diagnostics Mode is meant for use by trained systems support personnel. Users should not need to ini-tiate this function under normal circumstances.NOTE。
AT88SC0104CA-SU_datasheet
1.Features•One of a Family of Devices with User Memories from 1-Kbit to 8-Kbits •1-Kbit (128-byte) EEPROM User Memory–Four 256-bit (32-byte) Zones –Self-timed Write Cycle–Single Byte or 16-byte Page Write Mode–Programmable Access Rights for Each Zone •2-Kbit Configuration Zone–37-byte OTP Area for User-defined Codes–160-byte Area for User-defined Keys and Passwords •High Security Features–64-bit Mutual Authentication Protocol (Under License of ELVA)–Cryptographic Message Authentication Codes (MAC)–Stream Encryption–Four Key Sets for Authentication and Encryption –Eight Sets of Two 24-bit Passwords –Anti-Tearing Function–Voltage and Frequency Monitors •Smart Card Features–ISO 7816 Class B (3V) Operation–ISO 7816-3 Asynchronous T=0 Protocol (Gemplus ® Patent)–Multiple Zones, Key Sets and Passwords for Multi-application Use –Synchronous 2-wire Serial Interface for Faster Device Initialization –Programmable 8-byte Answer-To-Reset Register –ISO 7816-2 Compliant Modules •Embedded Application Features–Low Voltage Operation: 2.7V – 3.6V–Secure Nonvolatile Storage for Sensitive System or User Information –2-wire Serial Interface–1.0 MHz Compatibility for Fast Operation –Standard 8-lead Plastic Packages–Same Pin Configuration as AT24CXXX Serial EEPROM in SOIC and PDIP Packages •High Reliability–Endurance: 100,000 Cycles –Data Retention: 10 years –ESD Protection: 2,000V minTable 1-1.PadsPad Description ISO Module“SOIC, PDIP”TSSOP VCC Supply Voltage C188GND GroundC541SCL/CLK Serial Clock Input C366SDA/IO Serial Data Input/Output C753RSTReset InputC2NCNCCryptoMemory AT88SC0104CASummary5200AS–CRYPT–7/0825200AS–CRYPT–7/08AT88SC0104CA2.DescriptionThe AT88SC0104CA member of the CryptoMemory ® family is a high-performance secure mem-ory providing 1 Kbit of user memory with advanced security and cryptographic features built in.The user memory is divided into four 32-byte zones, each of which may be individually set with different security access rights or effectively combined together to provide space for 1 to 4 data files. The AT88SC0104CA features an enhanced command set that allows direct communica-tion with microcontroller hardware 2-Wire interface thereby allowing for faster firmware development with reduced code space requirements.3.Smart Card ApplicationsThe AT88SC0104CA provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. The embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0104CA offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gem-plus Patent) defined in ISO 7816-3.4.Embedded ApplicationsThrough dynamic, symmetric-mutual authentication, data encryption, and the use of crypto-graphic Message Authentication Codes (MAC), the AT88SC0104CA provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this informa-tion remains safe even under attack. A 2-wire serial interface running at speeds up to 1.0 MHz provides fast and efficient communications with up to 15 individually addressable devices. The AT88SC0104CA is available in industry standard 8-lead packages with the same familiar pin configuration as AT24CXXX serial EEPROM devices.Note:Does not apply to TSSOP pinout.35200AS–CRYPT–7/08AT88SC0104CAFigure 4-1.Block Diagram5.Pin Descriptions5.1Supply Voltage (VCC)The V CC input is a 2.7V to 3.6V positive voltage supplied by the host.5.2Clock (SCL/CLK)When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a carrier frequency f . The nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f .When using the synchronous protocol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the clock when reading from the device.5.3Reset (RST)The AT88SC0104CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR)sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64-bit Answer-To-Reset register. An internal pull-up on the RST input pad allows the device to oper-ate in synchronous mode without bonding RST. The AT88SC0104CA does not support an Answer-To-Reset sequence in the synchronous mode of operation.5.4Serial Data (SDA/IO)The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices. An external pull-up resistor should be connected between SDA/IO and V CC . The value of this resistor and the system capac-itance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power supply current. SDA/IO infor-mation applies to both asynchronous and synchronous protocols.45200AS–CRYPT–7/08AT88SC0104CA6.Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper-ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.Absolute Maximum RatingsOperating T emperature.....................................-40⋅C to +85⋅C Storage T emperature ..........................................−65⋅C to +150⋅C Voltage on Any Pinwith Respect to Ground ....................................−0.7 to V cc +0.7V Maximum Operating Voltage.............................................6.0V DC Output Current........................................................5.0 mATable 6-1.DC Characteristics Applicable over recommended operating range from V CC = +2.7 to 3.6V, T AC = -40⋅C to +85⋅C(unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.73.6V I CC Supply Current Async READ at 3.57MHz 5mA I CC Supply Current Async WRITE at 3.57MHz 5mA I CC Supply Current Synch READ at 1MHz 5mA I CC Supply Current Synch WRITE at 1MHz 5mA I SB Standby CurrentVIN = VCC or GND100uA V IL SDA/IO Input Low Voltage 0VCC x 0.2V V IL CLK Input Low Voltage 0VCC x 0.2V V IL RST Input Low Voltage 0VCC x 0.2V V IH SDA/IO Input High Voltage VCC x 0.7VCC V V IH SCL/CLK Input High Voltage VCC x 0.7VCC V V IH RST Input High Voltage VCC x 0.7VCC V I IL SDA/IO Input Low Current 0 < VIL < VCC x 0.1515uA I IL SCL/CLK Input Low Current 0 < VIL < VCC x 0.1515uA I IL RST Input Low Current 0 < VIL < VCC x 0.1550uA I IH SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20uA I IH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100uA I IH RST Input High Current VCC x 0.7 < VIH < VCC 150uA V OH SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7VCC V V OL SDA/IO Output Low Voltage IOL = 1mA 0VCC x 0.15V I OH SDA/IO Output High Current VOH 20uA I OLSDA/IO Output Low CurrentVOL10mA55200AS–CRYPT–7/08AT88SC0104CA7.Device Operations for Synchronous Protocols7.1Clock and Data TransitionsThe SDA pin is normally pulled high with an external device. Data on the SDA pin may changeonly during SCL low time periods (see Figure 7-3 on page 6). Data changes during SCL high periods will indicate a start or stop condition as defined below.7.1.1Start ConditionA high-to-low transition of SDA with SCL high defines a START condition which must precede all commands (see Figure 7-4 on page 7).7.1.2Stop ConditionA low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence,the STOP condition will place the EEPROM in a standby power mode (see Figure 7-4 on page 7).7.1.3ACKNOWLEDGEAll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero to acknowledge that it has received each word. This happens dur-ing the ninth clock cycle (see Figure 7-5 on page 7).Table 6-2.AC CharacteristicsApplicable over recommended operating range from V CC = +2.7 to 3.6V , T AC = -40⋅C to +85⋅C, CL = 30pF (unless otherwise noted)ParameterMin Max Units f CLKAsync Clock Frequency14MHz f CLK SynchClock Frequency 01MHz Clock Duty cycle4060%t R “Rise Time - SDA/IO, RST”1uS t F “Fall Time - SDA/IO, RST”1uS t R Rise Time - SCL/CLK 9% x period uS t F Fall Time - SCL/CLK 9% x perioduS t AA Clock Low to Data Out Valid 250nS t HD.ST A Start Hold Time 200nS t SU.ST A Start Set-up Time 200nS t HD.DA T Data In Hold Time 10nS t SU.DAT Data In Set-up Time 100nS t SU.STO Stop Set-up Time 200nS t DH Data Out Hold Time 20nS t WRWrite Cycle Time5mS65200AS–CRYPT–7/08AT88SC0104CA7.2Memory ResetAfter an interruption in communication due protocol errors, power loss or any reason, perform "Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of sending a start condition followed by a valid CryptoMemory command byte and determining if the device responded with an ACKNOWLEDGE.Figure 7-1.Bus Time for 2-Wire Serial Communications. SCL: Serial Clock, SDA: Serial Data I/OFigure 7-2.Write Cycle Timing. SCL: Serial Clock, SDA: Serial Data I/ONote:The Write Cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 7-3.Data Validity75200AS–CRYPT–7/08AT88SC0104CAFigure 7-4.START and STOP DefinitionsFigure 7-5.Output Acknowledge85200AS–CRYPT–7/08AT88SC0104CA8.Device Architecture8.1User ZonesThe EEPROM user memory is divided into 4 zones of 256 bits each. Multiple zones allow for storage of different types of data or files in different zones. Access to user zones is permitted only after meeting proper security requirements. These security requirements are user definable in the configuration memory during device personalization. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone.Figure 8-1.User ZonesZONE$0$1$2$3$4$5$6$7User 0$00-32 Bytes-$18User 1$00-32 Bytes-$18User 2$00-32 Bytes-$18User 3$00-32 Bytes-$1895200AS–CRYPT–7/08AT88SC0104CA9.Control LogicAccess to the user zones occur only through the control logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. Also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device.10.Configuration MemoryThe configuration memory consists of 2048 bits of EEPROM memory used for storage of pass-words, keys, codes, and also used for definition of security access rights for the user zones.Access rights to the configuration memory are defined in the control logic and are not alterable by the user after completion of personalization.Figure 10-1.Configuration Memory$0$1$2$3$4$5$6$7$00Answer To ResetIdentification $08Fab Code MTZCard Manufacturer Code$10Lot History CodeRead Only$18DCR Identification Number NcAccess Control$20AR0PR0AR1PR1AR2PR2AR3PR3$28Reserved$30$38$40Issuer Code$48$50For Authentication and Encryption use Cryptography$58$60$68$70$78$80$88$90For Authentication and Encryption use Secret$98$A0$A8$B0P ACWrite 0P AC Read 0Password$B8P AC Write 1P AC Read 1$C0P AC Write 2P AC Read 2$C8P AC Write 3P AC Read 3$D0P AC Write 4P AC Read 4$D8P AC Write 5P AC Read 5$E0P AC Write 6P AC Read 6$E8P AC Write 7P ACRead 7$F0ReservedForbidden$F8105200AS–CRYPT–7/08AT88SC0104CA10.1Security FusesThere are three fuses on the device that must be blown during the device personalization pro-cess. Each fuse locks certain portions of the configuration zone as OTP (One-Time Programmable) memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step.munication Security ModesCommunications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation fol-lowing a successful authentication.Note:1.Configuration data include viewable areas of the Configuration Zone except the passwords:MDC: Modification Detection Code.MAC: Message Authentication Code.12.Security Options12.1Anti-TearingIn the event of a power loss during a write cycle, the integrity of the device’s stored data is recov-erable. This function is optional: the host may choose to activate the anti-tearing function,depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data is limited to a maxi-mum of eight bytes for each write request.Data is written first into a buffer zone in EEPROM instead of the intended destination address,but with the same access conditions. The data is then written in the required location. If this sec-ond write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. Non-volatile buffering of the data is done automatically by the device.During power-up in applications using Anti-Tearing, the host is required to perform ACK polling in the event that the device needs to carry out the data recovery process.Table 11-1.Communication Security Modes (1)Mode Configuration DataUser Data Passwords Data Integrity CheckStandardClear Clear Clear MDC (1)Authentication Clear Clear Encrypted MAC (1)Encryption ClearEncryptedEncryptedMAC (1)AT88SC0104CA12.2Write LockIf a user zone is configured in the write lock mode, the lowest address byte of an 8-byte pageconstitutes a write access byte for the bytes of that page. For example, the write lock byte at$080 controls the bytes from $081 to $087.Figure 12-1.Write Lock ExampleAddress$0$1$2$3$4$5$6$7 $08011011001xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxxlocked locked lockedThe Write-Lock byte itself may be locked by writing its least significant (rightmost) bit to “0”.Moreover, when write lock mode is activated, the write lock byte can only be programmed – thatis, bits written to “0” cannot return to “1”.In the write lock configuration, write operations are limited to writing only one byte at a time.Attempts to write more than one byte will result in writing of just the first byte into the device.12.3Password VerificationPasswords may be used to protect READ and/or WRITE access of any user zone. When a validpassword is presented, it is memorized and active until power is turned off, unless a new pass-word is presented or RST becomes active. There are eight password sets that may be used toprotect any user zone. Only one password is active at a time.Presenting the correct WRITE password also grants READ access privileges.12.4Authentication ProtocolThe access to a user zone may be protected by an authentication protocol. Any one of four keysmay be selected to use with a user zone.Authentication success is memorized and active as long as the chip is powered, unless a newauthentication is initialized or RST becomes active. If the new authentication request is not vali-dated, the card loses its previous authentication which must be presented again to gain access.Only the latest request is memorized.11Figure 12-2.Password and Authentication OperationsNote:Authentication and password verification may be attempted at any time and in any order. Exceeding corresponding authentica-tion or password attempts trial limit renders subsequent authentication or password verification attempts futile.12.5Cryptographic Message Authentication CodesAT88SC0104CA implements a data validity check function in the standard, authentication orencryption modes of operation.In the standard mode, data validity check is done through a Modification Detection Code (MDC),in which the host may read an MDC from the device in order to verify that the data sent wasreceived correctly.In authentication and encryption modes, the data validity check becomes more powerful since itprovides a bidirectional data integrity check and data origin authentication capability in the formof a Message Authentication Codes (MAC). Only the host/device that carried out a valid authen-tication is capable of computing a valid MAC. While operating in the authentication or encryptionmodes, the use of MAC is required. For an ingoing command, if the device calculates a MAC dif-ferent from the MAC transmitted by the host, not only is the command abandoned but thesecurity privilege is revoked. A new authentication and/or encryption activation will be requiredto reactivate the MAC.12AT88SC0104CAAT88SC0104CA12.6EncryptionThe data exchanged between the device and the host during read, write and verify passwordcommands may be encrypted to ensure data confidentiality.The issuer may choose to require encryption for a user zone by settings made in the configura-tion memory. Any one of four keys may be selected for use with a user zone. In this case,activation of the encryption mode is required in order to read/write data in the zone and onlyencrypted data will be transmitted. Even if not required, the host may still elect to activateencryption provided the proper keys are known.12.7Supervisor ModeEnabling this feature allows the holder of one specific password to gain full access to all eightpassword sets, including the ability to change passwords.12.8Modify ForbiddenNo write access is allowed in a user zone protected with this feature at any time. The user zonemust be written during device personalization prior to blowing the security fuses.12.9Program OnlyFor a user zones protected by this feature, data can only be programmed (bits change from a “1”to a “0”), but not erased (bits change from a “0” to a “1”).13.Protocol SelectionThe AT88SC0104CA supports two different communication protocols.Smartcard Applications:Smartcard applications use ISO 7816-B protocol in asynchronous T = 0 mode for compatibil-ity and interoperability with industry standard smartcard readers.Embedded Applications:A 2-wire serial interface provides fast and efficient connectivity with other logic devices ormicrocontrollers.The power-up sequence determines establishes the communication protocol for use within thatpower cycle. Protocol selection is allowed only during power-up.13.1Synchronous 2-Wire Serial InterfaceThe synchronous mode is the default mode after power up. This is due to the presence of aninternal pull-up on RST. For embedded applications using CryptoMemory in standard plasticpackages, this is the only available communication protocol.Power-up V CC, RST goes high also.After stable V CC, SCL(CLK) and SDA(I/O) may be driven.13Once synchronous mode has been selected, it is not possible to switch to asynchronous modewithout first powering off the device.Figure 13-1.Synchronous 2-Wire ProtocolNote:Five clock pulses must be sent before the first command is issued.13.2Asynchronous T = 0 ProtocolThis power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications.V CC goes high; RST, I/O (SDA) and CLK (SCL) are low.Set I/O (SDA) in receive mode.Provide a clock signal to CLK (SCL).RST goes high after 400 clock cycles.The device will respond with a 64-bit ATR code, including historical bytes to indicate the memorydensity within the CryptoMemory family.Once asynchronous mode has been selected, it is not possible to switch to synchronous modewithout first powering off the device.Figure 13-2.Asynchronous T = 0 Protocol (Gemplus Patent)14.Initial Device ProgrammingEnabling the security features of CryptoMemory requires prior personalization. Personalizationentails setting up of desired access rights by zones, passwords and key values, programmingthese values into the configuration memory with verification using simple WRITE and READcommands, and then blowing fuses to lock this information in place.Gaining access to the configuration memory requires successful presentation of a secure (ortransport) code. The initial signature of the secure (transport) code for the AT88SC0104CA 14AT88SC0104CA15AT88SC0104CAdevice is $DD 42 97. This is the same as the WRITE 7 password. The user may elect to change the signature of the secure code anytime after successful presentation.After writing and verifying data in the configuration memory, the security fuses MUST be blown to lock this information in the device. For additional information on personalizing CryptoMemory,please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications from the product page at /products/securemem .15.Ordering InformationNote:1.Formal drawings may be obtained from an Atmel sales office.Ordering Code Package Voltage Range Temperature Range A T88SC0104CA-MJ A T88SC0104CA-MP M2 – J Module M2 – P Module 2.7V–3.6VCommercial (0°C to 70°C)A T88SC0104CA-PU A T88SC0104CA-SU A T88SC0104CA-TU 8P38S18A2 2.7V–3.6V Lead-free/Halogen-free/Industrial(−40°C to 85°C)A T88SC0104CA-WI7 mil wafer2.7V–3.6VIndustrial (−40°C to 85°C)Package Type (1)DescriptionM2 – J Module M2 ISO 7816 Smart Card ModuleM2 – P Module M2 ISO 7816 Smart Card Module with Atmel ® Logo 8P38-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8A28-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)16.Packaging Information.16AT88SC0104CAAT88SC0104CA 17.Ordering Code: SU17.18-lead SOIC1718.Ordering Code: PU 18.18-lead PDIP18AT88SC0104CAAT88SC0104CA 18.28-lead TSSOP19Headquarters InternationalAtmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USATel: 1(408) 441-0311 Fax: 1(408) 487-2600Atmel AsiaRoom 1219Chinachem Golden Plaza77 Mody Road TsimshatsuiEast KowloonHong KongTel: (852) 2721-9778Fax: (852) 2722-1369Atmel EuropeLe Krebs8, Rue Jean-Pierre TimbaudBP 30978054 Saint-Quentin-en-Yvelines CedexFranceTel: (33) 1-30-60-70-00Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Product ContactWeb Site/products/securememTechnical Supportcryptomemory@Sales Contact/contactsLiterature Requests/literatureDisclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.© 2008 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, Cryptomemory® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。
华特自动链接设备兼容性指南说明书
2560x1440
iOS devices^.
Model A1429 A1586 A1522 A1660
Name iPhone5 iPhone6 iPhone6+ iPhone7
Manufacturer Apple Apple Apple Apple
OS Ver 8.1.3 10.2.1 10.2.1 10.2.1
Connectivity Bluetooth 4.2 Bluetooth 4.2 Bluetooth 4.2 Bluetooth 4.2
Resolution 1136x640 1334x750 1920x1080 1334x750
Guide current as at 17 May2017.
Samsung
Galaxy S4 Zoom Samsung
Galaxy On7
Samsung
Galaxy ALPHA Samsung
Galaxy S5
Samsung
Galaxy S6
Samsung
Galaxy S6 Edge+ Samsung
Galaxy J5 2016 Samsung
Galaxy Note3 Neo
Connectivity Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 3.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 3.0 Bluetooth 3.0 Bluetooth 3.0 Bluetooth 4.0 Bluetooth 4.0 Bluetooth 4.0
HS8916_V0.6_Datasheet Preliminary
QUAD-BAND GSM/GPRS/EDGE W Multi-Mode Transmit Module with Fourteen Linear TRx Switch Ports andDual-Band TD-SCDMA B34/39 and TDD LTE B39HS8916 Preliminary DatasheetVersion 0.62016-03-21HS8916 Front-end ModuleProduct Features ApplicationsG N DG N DG N DG N DG N DC P LG NDN CTRX10ANT TRX9TRX8GND GNDGND TRX11TRX12TRX13TRX14•LGA: 5.5 mm x 5.3 mm x 0.85 mm Max•Fully programmable MIPI RFFE control •Fourteen low -insertion-loss TRx ports (fiveultra-low loss) with enhanced linearity, for state-of-the-art 4G performance and GPS /•Cellular handsets encompassing Quad -Band GSM/EDGE, Dual-Band TD-SCDMA, and TDD LTE- Class 4 GSM850/900 - Class 1 DCS1800/PCS1900Product DescriptionThe HS8916 is a high-power, high-efficiency Front-End Module for GSM850/900, DCS1800, PCS1900 operation. The FEM supports Class.12 General Packet Radio Service (GPRS), EDGE multi-slot operation, and TD-SCDMA and TDD LTE linear transmission.The module provides 50 ohm impedance at input and output ports, consists of a CMOS Controller, a SP16T RF switch, a power amplifier supporting GSM850/900, DCS1800/PCS1900, TD-SCDMA bands 34/39, and TDD LTE band 39. The module integrated Tx low pass harmonic filtering can achieve best harmonic performance.The HS8916 provides high-power and high-efficiency Pout for GSM850/900, DCS1800, PCS1900 operation mode. In EDGE and TD-SCDMA / TDD LTE linear modes, VRAMP voltage and MIPI-based bias settings optimize PA linearity and efficiency.Absolute Maximum RatingsMIPI RFFE REGISTER MAP (1 OF 2)MIPI RFFE REGISTER MAP (2 OF 2)Electrical Specifications – TX GSM850/900 Band, GSMK ModeElectrical Specifications – TX GSM850/900 Band, EDGE ModeElectrical Specifications – TX DCS1800/1900 Band, GMSK ModeElectrical Specifications – TX DCS1800/1900 Band, EDGE ModeElectrical Specifications – TX TD-SCDMA B39 BandElectrical Specifications – TX TDD LTE B39 BandElectrical Specifications – TX TD-SCDMA B34 BandElectrical Specifications – Ports TRx1 to TRx14 ModePin-Out DiagramT R X 7T R X 6T R X 5G N DT R X 1T R X 2T R X 3T R X 4HS8916 Application CircuitT R X 7T R X 6T R X 5G N DR X 1T R X 2T R X 3T R X 4Package DrawingThe HS8916 is encapsulated in a 5.5×5.3×0.85mm Land Grid Array (LGA) package on a laminate substrate. The HS8916 is RoHS compliant.。
亿佰特E28-2G4M27S 产品规格书说明书
E28-2G4M27S产品规格书SX1280 2.4GHz 500mW SPI 高速LoRa模块目录第一章产品概述 (2)1.1 产品简介 (2)1.2 特点功能 (2)1.3 应用场景 (2)第二章规格参数 (3)2.1 极限参数 (3)2.2 工作参数 (3)第三章机械尺寸与引脚定义 (4)第四章基本操作 (5)4.1硬件设计 (5)4.2软件编写 (5)第五章基本应用 (6)5.1 基本电路 (6)第六章常见问题 (7)6.1 传输距离不理想 (7)6.2 模块易损坏 (7)6.3 误码率太高 (7)第七章焊接作业指导 (8)7.1 回流焊温度 (8)7.2 回流焊曲线图 (8)第八章相关型号 (9)第九章天线指南 (9)9.1 天线推荐 (9)9.2天线选择 (9)修订历史 (10)关于我们 (11)第一章产品概述1.1 产品简介E28-2G4M27S是亿佰特公司设计生产的2.4GHz射频收发模块，发射功率500mW，SPI接口，具有极低的低功耗模式流耗；该模块为小体积贴片型(引脚间距1.27mm)，自带高性能PCB板载天线，采用52MHz工业级高精度低温漂晶振，保证其工业特性和其稳定性能。
采用Semtech公司的SX1280射频芯片，此芯片包含多样的物理层以及多种调制方式，如LoRa、FLRC、GFSK，并可兼容蓝牙协议；特殊的调制和处理方式使得LoRa和FLRC调制的传输距离有显著提升，在原有基础上内置了功率放大器（PA）与低噪声放大器（LNA），使得最大发射功率达到500mW的同时接收灵敏度也获得进一步的提升，在整体的通信稳定性上较没有功率放大器与低噪声放大器的产品大幅度提升；出色的低功耗性能、片上DC-DC和Time-of-flight使得此芯片功功能强大，可用于智能家居、安全系统、定位追踪、无线测距、穿戴设备、智能手环与健康管理等等。
SX1280支持RSSI，用户可以根据需要实现深度的二次开发，亦集成飞行时间(Time of flight)，适用于测距功能。
FLEXI-GUARD фи Installation Care Use Manual
EBFATL8*1A, LIEATL8*1AWith FLEXI-GUARD®Installation/Care/Use ManualUSES HFC-134A REFRIGERANTFIG. 1603534SEE FIG. 350, 51,52, 53566145, 46, 5837495726, 27552118, 192822, 23,24, 25SEE FIG. 5473844405441, 42, 43365940203948EBFATL8*1A, LIEATL8*1AF IG . 2F I N I S H E D F L O O R P I S O A C A B A D O P L A N C H E R F I N ID =E L E C T R I C A L S U P P L Y (3) W I R E R E C E S S E D B O X C A J A R E C E S I V A D E A L A M B R E S (3) D E S U M I N I S T R O E L ÉC T R I C O B O ÎT E E N C A S T R ÉE D A L I M E N T A T I O N ÉL E C T R I Q U E (3)F I L S E = I N S U R E P R O P E R V E N T I L A T I O N B Y M A I N T A I N I NG 6" (152m m ) (M I N .) C L E A R A N C E F R O M C A B I N E T L O U V E R S T O W A L L .A S E G U R E U N A V E N T I L A C I ÓN A D E C U A D A M A N T E N I E N D O U N E S P A C I O E 6" (152m m ) (M ÍN .) D EH O L G U R A E N T R E L A R E JI L L A D E V E N T I L A C I ÓN D E L M U E B L E Y L A P A R E D A S S U R E Z -V O U S U N E B O N N E V E N T I L A T I O N E N G A R D A N T 6" (152m m ) (M I N .) E N T R E L E S ÉV E N T S D E L E N C E I N T E E T L E M U R .F = 7/16 B O L T H O L E S F O R F A S T E N I N G U N I T T O W A L L A G UJ E R O S D E L A S T U E R C A S D E 7/16 P A R A S U J E T A R L A U N I D A D A L A P A R E D T R O U S D ÉC R O U S 7/16 P O U R F I X E R L A P P A R E I L A U M U RL E G E N D /L E Y E N D A /L ÉG E N D E A = R E C O M M E N D E D W A T E R S U P P L Y L O C A T I O N 3/8 O .D . T U B E C O N N E C T S T U B 1-1/2 I N . (38m m ) O U T F R O M W A L L S H U T O F F B Y O T H E R S U B I C A C I ÓN R E C O M E N D A D A P A R A L A S E C C I ÓN D E T U B O D E 3/8" D E D I A M E T R O D E S U M I N I S T R O D E A G U A R E S A L T A D O 1½ (38 m m ) D E L A P A R E D E M P L A C E M E N T R E C O M M A N D É P O U R L A L I M E N T A T I O N E N E A U . T I G E D E P O /S 3/8" - S O R T I D U M U R 1-1/2" (38m m )B = R E C O M M E N D E D L O C A T I O N F O R W A S T E O U T L E T 1-1/2 O .D . D R A I N U B I C A C I ÓN R E C O M E N D A D A P A R A E L D R E N A J E D E S A L I D A D E A G U A , D E 1-1/2 D E D I ÁM E T R O .E M P L A C E M E N T R E C O M M A N D É P O U R L E D R A I N D E D .E . 1-1/2" D E S O R T I E D E A U .C = 1-1/2 T R A P N O T F U R N I S H E D P U R G A D O R D E 1-1/2 N O P R O P O R C I O N A D O S I P H O N 1-1/2 N O N F O U R N I*A D A R E Q U I R E M E N T *R E Q U I S I T O D E A .D .A .*E X I G E N C E A D AEBFATL8*1A, LIEATL8*1A WATER VALVE MECHANISM - ADJUSTMENT PROCEDURE:- Turn adjustment screw (Item 16) "Counter-Clockwise" until water flow from bubbler starts.- Turn adjustment screw "Clockwise" until water flow stops, THEN turn an additional 1/2 turn.NOTE: Adjustments stated above are viewed from underneath unit (bottom side of dispenser panel Item 1).NOTE: If continuous flow occurs at the end of the compressor cycle, turn cold control (Item 54) counter- clockwise 1/4 turn.LEGEND - A: NOTE: Water flow direction.B: Adjust this screw to eliminate mechanism "Free Play" or continuous flow from bubbler conditions (SEE ADJUSTMENT PROCEDURE).C: Stream height adjustment (SEE NOTE 8).FIG. 3HANGER BRACKETS & TRAPINSTALLATION1)Remove hanger bracket fastened to back of cooler by re-moving one (1) screw.2)Mount the hanger bracket and trap as shown in Figure 2.NOTE: Hanger Bracket MUST be supported securely. Add fixture support carrier if wall will not provide adequate sup-port.IMPORTANT:7-3/4 in. (197mm) dimension from wall to centerline of trap must be maintained for proper fit.Anchor hanger securely to wall using all six (6) 1/4 in. dia.mounting holes.3)Install straight valve for 3/8" O.D. tube.INSTALLATION OF COOLER4)Hang the cooler on the hanger bracket. Be certain the hanger bracket is engaged properly in the slots on the cooler back as shown in Figure 2.5)Loosen the two (2) screws holding the lower front panel at the bottom of cooler base and two (2) screws at the top.Remove the front panel and set aside.6)Connect water inlet line--See Note 4 of General Instruc-tions.7)Remove the slip nut and gasket from the trap and install them on the cooler waste line making sure that the end of the waste line fits into the trap. Assemble the slip nut and gasket to the trap and tighten securely.START UPAlso See General Instructions8)Stream height is factory set at 35 PSI. If supply pressure varies greatly from this, adjust screw, ac-cessible by removing front panel (Item 6, Fig. 3).CW adjustment will raise stream and CCW adjust-ment will lower stream. For best adjustment, stream should hit basin approximately 6-1/2 (165mm) from bubbler.9)Replace the front panel and secure by retightening four (4) screws.ITEM NO.PART NO.Panel-Bottom Dispenser Block-PivotNut-1/4", Self Threading Panel-Right Side Panel-Left Side Panel-FrontInsert-Pushbar, Gray Insert-Pushbar, Brown Bracket-Front PushScrew-#8 x 5/8" Lg. Torx/Slot Bumper-Pressbar Hex NutBracket-Regulator Mounting Retaining Nut RegulatorHolder-RegulatorScrew-Shoulder x 1/2" Lg.Screw-Regulator Mtg. Brkt.22897C 51531C 111411743620See Color Table See Color Table See Color Table51559C 51560C 22900C 70864C 51667C 40045C 23003C 15005C 61314C 50986C 70935C 112627543890Item No. 4Part No.COLOR TABLEBronzetone Gray Beige AlmondStainless Stl Sandalwood Granite23014C 23015C 23016C 22822C 23017C 23020C23007C 23008C 23009C 22814C 23010C 23013C22931C 22932C 22933C 22934C 22935C 27211CPANEL COLORItem No. 5Part No.Item No. 6Part No.1234567891011121314151617DESCRIPTION87A394561016 (B)14116191791213152PUSHBAR MECHANISMC1Item No. 40Part No.22952C 22953C 22954C 22955C 22956C 27214CNOTE:WHEN INSTALLING REPLACEMENT BUBBLER AND PEDESTAL, TIGHTEN NUT (ITEM 33) ONLY TO HOLD PARTS SNUG IN POSITION.DO NOT OVER TIGHTEN.BASIN 3031323329FIG. 5CAUTION: Cleaning of Bronzetone Models requiresspecial care. Outer surfaces must be cleaned with a mild detergent or mixture of vinegar and water only, rinsed and wiped dry. Abrasive and acidic cleaners may eventually damage the Bronzetone finish.Item No. 55Part No.Item No. 60Part No.Item No. 6151552C 51551C 51552C 51551C 51552C 51551C26841C 26842C 26843C 26847C 26844C 27223CFIG. 4PART NO.DESIGN 2000®FILTER PARTS LIST 1234567851294C 70792C 70823C 70822C 51295C 70818C 70817C 70683CFilter Head AssyScrew-#8-18 x .75" PHFitting-Superseal 3/8" (10mm)Fitting-Superseal 1/4" (6mm)Filter AssyElbow-3/8" (10mm)Elbow-1/4" (6mm)Union-1/4"ITEM NO.DESCRIPTION143725When Provided 800-518-5388。
iTEMP TMT82 温度变送器，带双输入通道 HART通信协议 操作手册说明书
Products Solutions Services操作手册iTEMP TMT82温度变送器，带双输入通道HART ®通信协议BA01028T/28/ZH/25.22-00715964312022-04-04自下列版本起生效01.02（版本号）iTEMP TMT82目录Endress+Hauser 3目录1文档信息 (4)1.1文档功能 (4)1.2《安全指南》(XA) (4)1.3信息图标 (4)1.4工具图标 (5)1.5文档资料 (6)1.6注册商标 (6)2基本安全指南 (7)2.1人员要求 (7)2.2指定用途 (7)2.3工作场所安全 (7)2.4操作安全 (7)2.5产品安全 (8)2.6IT 安全 (8)3到货验收和产品标识 (9)3.1到货验收 (9)3.2产品标识 (9)3.3制造商名称和地址 (10)3.4供货清单 (11)3.5证书和认证 (11)3.6储存和运输 (11)4安装 (12)4.1安装要求 (12)4.2安装仪表 (12)4.3安装后检查 (18)5电气连接 (19)5.1接线要求 (19)5.2快速接线指南 (20)5.3连接传感器电缆 (22)5.4连接变送器 (23)5.5特殊接线指南 (23)5.6保证防护等级 (24)5.7连接后检查 (24)6操作方式 (26)6.1操作方式概览 (26)6.2操作菜单的结构和功能 (27)6.3测量值显示与操作单元 (28)6.4通过调试软件访问操作菜单 (30)7变送器的HART ®集成 (33)7.1HART 设备参数和测量值 (33)7.2HART 设备参数和测量值 (33)7.3支持的HART ®命令 (34)8仪表调试..........................368.1安装后检查..........................368.2打开变送器..........................368.3激活设置............................369维护..............................3610维修..............................3710.1概述...............................3710.2备件...............................3710.3处置...............................3711附件..............................3711.1设备专用附件........................3711.2通信专用附件........................3811.3服务专用附件........................3811.4系统产品............................3912诊断和故障排除...................4012.1故障排除............................4012.2诊断事件............................4112.3返厂...............................4512.4软件历史和兼容性概述.................4513技术参数..........................4613.1输入...............................4613.2输出...............................4713.3电源...............................4813.4性能参数............................4913.5环境条件............................5613.6机械结构............................5713.7证书和认证..........................6113.8文档资料............................6214操作菜单和菜单参数说明...........6314.1“Setup”菜单.........................7014.2“Diagnostics”菜单.....................8814.3“Expert ”菜单........................97索引. (115)文档信息iTEMP TMT824Endress+Hauser1 文档信息1.1 文档功能《操作手册》包含设备生命周期内各个阶段所需的所有信息：从产品标识、到货验收和储存，至安装、电气连接、操作和调试，以及故障排除、维护和废弃。
CS5460A中文数据手册
Cirrus Lohai benhong Electronics Technologies Co.,Ltd Contactee: Zhoubenhong Addr: Rm1101,No 47,Lane 1111,Lianhua South Rd,Shanghai China, P.R.China. 201100
2．综述 ..................................................................................................................................................... 12 2.1 操作原理 ..................................................................................................................................... 12 2.1.1 ÄÓ 调制器 .......................................................................................................................... 12 2.1.2 高速数字低通滤波器......................................................................................................... 12 2.1.3 数字补偿滤波器 ................................................................................................................ 12 2.1.4 数字高通滤波器 ................................................................................................................ 12 2.1.5 总的滤波器响应 ................................................................................................................ 12 2.1.6 增益及 DC 偏移量调整 ..................................................................................................... 12 2.1.7 有功能量及有效值计算 ..................................................................................................... 13 2.2 执行测量 ..................................................................................................................................... 13 2.2.1 CS5460A 线性性能 ........................................................................................................... 14 2.2.2 单计算周期（C=0 ） ....................................................................................................... 14 2.2.3 连续计算周期（C=1 ）.................................................................................................... 15 2.3 基本应用电路结构....................................................................................................................... 15
ADS8482资料
BurrĆBrown Productsfrom TexasInstrumentsFEATURES APPLICATIONSDESCRIPTIONBYTE16-/8-BitParallel DA TAOutput BusCONVSTBUSYCSRDREFOUTBUS 18/16ADS8482SLAS386A–JULY2005–REVISED JUNE2006 18-BIT,1-MSPS,PSEUDO-BIPOLAR,FULLY DIFFERENTIAL INPUT,MICROPOWERSAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE,REFERENCE•Medical Instruments•0to1-MHz Sample Rate•Optical Networking•±1.2LSB Typ,±2.5LSB Max INL•Transducer Interface•+0.75/-0.6LSB Typ,+1.5/-1LSB Max DNL•High Accuracy Data Acquisition Systems •18-Bit NMC Ensured Over Temperature•Magnetometers•±0.05-mV Offset Error•±0.05-PPM/°C Offset Error Drift•±0.035%FSR Gain ErrorThe ADS8482is an18-bit,1-MSPS A/C converter •±0.5-PPM/°C Gain Error Drift with an internal 4.096-V reference and a•99dB SNR,-121dB THD,123dB SFDR pseudo-bipolar,fully differential input.The deviceincludes a18-bit capacitor-based SAR A/D converter •Zero Latencywith inherent sample and hold.The ADS8482offers •Low Power:225mW at1MSPS a full18-bit interface,a16-bit option where data is•Unipolar Differential Input Range:V ref to–Vref read using two read cycles,or an8-bit bus optionusing three read cycles.•Onboard Reference with6PPM/°C Drift•Onboard Reference Buffer The ADS8482is available in a48-lead7x7QFNpackage and is characterized over the industrial •High-Speed Parallel Interface–40°C to85°C temperature range.•Wide Digital Supply2.7V to5.25V•8-/16-/18-Bit Bus Transfer•48-Pin7x7QFN PackageHIGH SPEED SAR CONVERTER FAMILYTYPE/SPEED500kHz~600kHz750kHz1MHz 1.25MHz2MHz3MHz4MHzADS8383ADS8381ADS848118-Bit Pseudo-DiffADS8380(s)18-Bit Pseudo-Bipolar,Fully Diff ADS8382(s)ADS8482ADS8327ADS8370(s)ADS8371ADS8471ADS8401ADS841116-Bit Pseudo-DiffADS8328ADS8372(s)ADS8405ADS8410(s)ADS8472ADS8402ADS8412ADS842216-Bit Pseudo-Bipolar,Fully DiffADS8406ADS8413(s)14-Bit Pseudo-Diff ADS7890(s)ADS789112-Bit Pseudo-Diff ADS7886ADS7883ADS7881Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2005–2006,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGS (1)ADS8482SLAS386A–JULY 2005–REVISED JUNE 2006These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATION (1)MAXIMUM MAXIMUM INTEGRAL NO MISSING CODES PACKAGE PACKAGE TEMPER-ATUREORDERING TRANS-PORT MODELDIFFERENTIAL LINEARITY RESOLUTION (BIT)TYPEDESIGNATORRANGEINFORMATIONMEDIA QTY.LINEARITY (LSB)(LSB)Tape and reelADS8482IRGZT2507x748Pin ADS8482I ±4–1to +1.518RGZ–40°C to 85°CQFNTape and reelADS8482IRGZR 1000Tape and reelADS8482IBRGZT2507x748Pin ADS8482IB ±2.5–1to +1.518RGZ–40°C to 85°CQFNTape and reelADS8482IBRGZR1000(1)For the most current specifications and package information,refer to our website at .over operating free-air temperature range (unless otherwise noted)VALUEUNIT +IN to AGND –0.4to +VA +0.1V –IN to AGND–0.4to +VA +0.1V Voltage+VA to AGND –0.3to 7V +VBD to BDGND –0.3to 7V +VA to +VBD–0.3to 2.55V Digital input voltage to BDGND –0.3to +VBD +0.3V Digital output voltage to BDGND–0.3to +VBD +0.3V T A Operating free-air temperature range –40to 85°C T stgStorage temperature range –65to 150°C Junction temperature (T J max)150°CPower dissipation (T J Max –T A )/θJAQFN packageθJA thermal impedance 22°C/W Vapor phase (60sec)215°C Lead temperature,solderingInfrared (15sec)220°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2Submit Documentation Feedback SPECIFICATIONSADS8482 SLAS386A–JULY2005–REVISED JUNE2006T A =–40°C to85°C,+VA=5V,+VBD=3V or5V,Vref=4.096V,fSAMPLE=1MSPS(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITANALOG INPUTFull-scale input voltage(1)+IN–(–IN)–V ref V ref V+IN–0.2V ref+0.2Absolute input voltage V–IN–0.2V ref+0.2Common-mode input range(V ref)/2–0.2(V ref)/2(V ref)/2+0.2VInput capacitance65pF Input leakage current1nA SYSTEM PERFORMANCEResolution18BitsADS8482I18No missing codes BitsADS8482IB18ADS8482I–4±1.24LSB Integral linearity(2)(18bit)(3)ADS8482IB–2.5±1.2 2.5ADS8482I–1–0.6/0.75 1.5LSB Differential linearity(18bit)ADS8482IB–1–0.6/0.75 1.5ADS8482I–0.5±0.050.5Offset error(4)mVADS8482IB–0.5±0.050.5ADS8482I±0.05Offset error temperature drift ppm/°CADS8482IB±0.05ADS8482I V ref=4.096V–0.1±0.0350.1%FS Gain error(4)(5)ADS8482IB V ref=4.096V–0.1±0.0350.1%FSADS8482I±0.5Gain error temperature drift ppm/°CADS8482IB±0.5At dc(±0.2V around V ref/2)60Common-mode rejection ratio dB+IN–(–IN)=1Vpp at1MHz55Noise25µV RMS Power supply rejection ratio At1FFFFh output code60dB SAMPLING DYNAMICSConversion time625650ns Acquisition time320350ns Throughput rate1MHz Aperture delay4ns Aperture jitter5psStep response150nsOver voltage recovery150ns(1)Ideal input span,does not include gain or offset error.(2)This is endpoint INL,not best fit.(3)LSB means least significant bit(4)Measured relative to an ideal full-scale input[+IN–(–IN)]of8.192V(5)This specification does not include the internal reference voltage error and drift.3Submit Documentation FeedbackSPECIFICATIONS (Continued)ADS8482SLAS386A–JULY 2005–REVISED JUNE 2006T A =–40°C to 85°C,+VA =5V,+VBD =3V or 5V,V ref =4.096V,f SAMPLE =1MSPS (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITDYNAMIC CHARACTERISTICSADS8482I –120V IN =8V pp at 2kHz ADS8482IB–121ADS8482I –105Total harmonic distortion (THD)(1)V IN =8V pp at 20kHz dBADS8482IB –110ADS8482I –100V IN =8V pp at 100kHz ADS8482IB –103ADS8482I 9698.6V IN =8V pp at 2kHz ADS8482IB97.599ADS8482I 98Signal to noise ratio (SNR)(1)V IN =8V pp at 20kHz dB ADS8482IB 98.5ADS8482I 95V IN =8V pp at 100kHz ADS8482IB 97ADS8482I 9698.5V IN =8V pp at 2kHz ADS8482IB97.599ADS8482I 97Signal to noise +distortion (SINAD)(1)V IN =8V pp at 20kHz dB ADS8482IB 98ADS8482I 93V IN =8V pp at 100kHz ADS8482IB 95ADS8482I 120V IN =8V pp at 2kHz ADS8482IB123ADS8482I 107Spurious free dynamic range (SFDR)(1)V IN =8V pp at 20kHz dB ADS8482IB 113ADS8482I 102V IN =8V pp at 100kHzADS8482IB105–3dB Small signal bandwidth15MHz (1)Calculated on the first nine harmonics of the input frequency.4Submit Documentation Feedback SPECIFICATIONS(Continued)ADS8482 SLAS386A–JULY2005–REVISED JUNE2006T A =–40°C to85°C,+VA=5V,+VBD=3V or5V,Vref=4.096V,fSAMPLE=1MSPS(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITVOLTAGE REFERENCE INPUTReference voltage at REFIN,V ref 3.0 4.096+VA–0.8VReference resistance(1)500kΩReference current drain f s=1MHz1mAINTERNAL REFERENCE OUTPUTInternal reference start-up time From95%(+VA),with1-µF storage capacitor120msReference voltage range,V ref I O=0 4.081 4.096 4.111VSource current Static load10µALine regulation+VA=4.75V~5.25V60µVDrift I O=0±6PPM/°CDIGITAL INPUT/OUTPUTLogic family–CMOSV IH I IH=5µA+VBD–1+VBD+0.3V IL I IL=5µA–0.30.8Logic level V V OH I OH=2TTL loads+VBD–0.6V OL I OL=2TTL loadsData format–Straight BinaryPOWER SUPPLY REQUIREMENTS+VBD 2.7 3.3 5.25V Power supplyvoltage+VA 4.755 5.25V Supply current(2)f s=1MHz4550mA Power dissipation(2)f s=1MHz225250mW TEMPERATURE RANGEOperating free-air–4085°C(1)Can vary±20%(2)This includes only+VA current.+VBD current is typical1mA with5pF load capacitance on all output pins.5Submit Documentation FeedbackTIMING CHARACTERISTICSADS8482SLAS386A–JULY 2005–REVISED JUNE 2006All specifications typical at –40°C to 85°C,+VA =+VBD =5V(1)(2)(3)PARAMETERMIN TYP MAX UNIT t (CONV)Conversion time 650ns t (ACQ)Acquisition time320ns t (HOLD)Sample capacitor hold time 25ns t pd1CONVST low to BUSY high40ns t pd2Propagation delay time,end of conversion to BUSY low15ns t pd3Propagation delay time,start of convert state to rising edge of BUSY 15ns t w1Pulse duration,CONVST low 40ns t su1Setup time,CS low to CONVST low 20ns t w2Pulse duration,CONVST high 20ns CONVST falling edge jitter 10ps t w3Pulse duration,BUSY signal low t (ACQ)minns t w4Pulse duration,BUSY signal high650ns t h1Hold time,first data bus transition (RD low,or CS low for read cycle,or BYTE or 40ns BUS18/16input changes)after CONVST low t d1Delay time,CS low to RD low 0ns t su2Setup time,RD high to CS high 0ns t w5Pulse duration,RD low50ns t en Enable time,RD low (or CS low for read cycle)to data valid 20ns t d2Delay time,data hold from RD high5ns t d3Delay time,BUS18/16or BYTE rising edge or falling edge to data valid 1020ns t w6Pulse duration,RD high 20ns t w7Pulse duration,CS high20ns t h2Hold time,last RD (or CS for read cycle )rising edge to CONVST falling edge 50ns t pd4Propagation delay time,BUSY falling edge to next RD (or CS for read cycle)falling 0ns edget d4Delay time,BYTE edge to BUS18/16edge skew0ns t su3Setup time,BYTE or BUS18/16transition to RD falling edge 10ns t h3Hold time,BYTE or BUS18/16transition to RD falling edge 10ns t dis Disable time,RD high (CS high for read cycle)to 3-stated data bus 20ns t d5Delay time,BUSY low to MSB data valid delay 0ns t d6Delay time,CS rising edge to BUSY falling edge 50ns t d7Delay time,BUSY falling edge to CS rising edge50ns t su5BYTE transition setup time,from BYTE transition to next BYTE transition,or BUS18/1650ns transition setup time,from BUS18/16to next BUS18/16.t su(ABORT)Setup time from the falling edge of CONVST (used to start the valid conversion)to thenext falling edge of CONVST (when CS =0and CONVST are used to abort)or to the 60550nsnext falling edge of CS (when CS is used to abort).(1)All input signals are specified with t r =t f =5ns (10%to 90%of +VBD)and timed from a voltage level of (V IL +V IH )/2.(2)See timing diagrams.(3)All timing are measured with 20pF equivalent loads on all data bits and BUSY pins.6Submit Documentation FeedbackTIMING CHARACTERISTICSADS8482 SLAS386A–JULY2005–REVISED JUNE2006All specifications typical at–40°C to85°C,+VA=5V+VBD=3V(1)(2)(3)PARAMETER MIN TYP MAX UNITt(CONV)Conversion time650nst(ACQ)Acquisition time310nst(HOLD)Sample capacitor hold time25nst pd1CONVST low to BUSY high40nst pd2Propagation delay time,end of conversion to BUSY low25nst pd3Propagation delay time,start of convert state to rising edge of BUSY25nst w1Pulse duration,CONVST low40nst su1Setup time,CS low to CONVST low20nst w2Pulse duration,CONVST high20nsCONVST falling edge jitter10pst w3Pulse duration,BUSY signal low t(ACQ)min nst w4Pulse duration,BUSY signal high650nst h1Hold time,first data bus transition(RD low,or CS low for read cycle,or BYTE or40ns BUS18/16input changes)after CONVST lowt d1Delay time,CS low to RD low0nst su2Setup time,RD high to CS high0nst w5Pulse duration,RD low50nst en Enable time,RD low(or CS low for read cycle)to data valid30nst d2Delay time,data hold from RD high5nst d3Delay time,BUS18/16or BYTE rising edge or falling edge to data valid1030nst w6Pulse duration,RD high20nst w7Pulse duration,CS high20nst h2Hold time,last RD(or CS for read cycle)rising edge to CONVST falling edge50nst pd4Propagation delay time,BUSY falling edge to next RD(or CS for read cycle)falling0ns edget d4Delay time,BYTE edge to BUS18/16edge skew0nst su3Setup time,BYTE or BUS18/16transition to RD falling edge10nst h3Hold time,BYTE or BUS18/16transition to RD falling edge10nst dis Disable time,RD high(CS high for read cycle)to3-stated data bus30nst d5Delay time,BUSY low to MSB data valid delay0nst d6Delay time,CS rising edge to BUSY falling edge50nst d7Delay time,BUSY falling edge to CS rising edge50nst su5BYTE transition setup time,from BYTE transition to next BYTE transition,or BUS18/1650ns transition setup time,from BUS18/16to next BUS18/16.t su(ABORT)Setup time from the falling edge of CONVST(used to start the valid conversion)to thenext falling edge of CONVST(when CS=0and CONVST are used to abort)or to the70550nsnext falling edge of CS(when CS is used to abort).(1)All input signals are specified with t r=t f=5ns(10%to90%of+VBD)and timed from a voltage level of(V IL+V IH)/2.(2)See timing diagrams.(3)All timing are measured with20pF equivalent loads on all data bits and BUSY pins.7Submit Documentation FeedbackPIN ASSIGNMENTSRGZ PACKAGE (TOP VIEW)R E F I R E F O U N +V A G N +I −I +V +V A G N A G N A G N U S Y B 0B 1B 2B 3B 4B 5B 6B 7B 9D G N DNC − No internal connectionNOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.B 8ADS8482SLAS386A–JULY 2005–REVISED JUNE 2006TERMINAL FUNCTIONSNAME NO I/O DESCRIPTION8,9,17,20,AGND 23,24,26,–Analog ground27BDGND 37–Digital ground for bus interface digital supply BUSY48OStatus output.High when a conversion is in progress.Bus size select ed for selecting 18-bit or 16-bit wide bus transfer.0:Data bits output on the 18-bit data bus pins DB[17:0].BUS18/162I1:Last two data bits D[1:0]from 18-bit wide bus output on:a)the low byte pins DB[9:2]if BYTE =0b)the high byte pins DB[17:10]if BYTE =1Byte select ed for 8-bit bus reading.BYTE 3I 0:No fold back1:Low byte D[9:2]of the 16most significant bits is folded back to high byte of the 16most significant pins DB[17:10].CONVST 4I Convert start.The falling edge of this input ends the acquisition period and starts the hold period.CS6IChip select.The falling edge of this input starts the acquisition period.8-BIT BUS16-BIT BUS18-BIT BUS Data Bus BYTE =0BYTE =1BYTE =1BYTE =0BYTE =0BYTE =0BUS18/16=0BUS18/16=0BUS18/16=1BUS18/16=0BUS18/16=1BUS18/16=0DB1728O D17(MSB)D9All ones D17(MSB)All ones D17(MSB)DB1629O D16D8All ones D16All ones D16DB1530O D15D7All ones D15All ones D15DB1431O D14D6All ones D14All ones D14DB1332O D13D5All ones D13All ones D13DB1233O D12D4All ones D12All ones D12DB1134O D11D3D1D11All ones D11DB1035O D10D2D0(LSB)D10All ones D10DB938OD9All onesAll onesD9All onesD98Submit Documentation FeedbackTYPICAL CHARACTERISTICSSupply Voltage - VR e f e r e n c e V o l t a g e - V5001000150020002500300035004000Output CodeF r e q u e n c y4.0954.09554.0964.09654.0974.098T - Free-Air Temperature - °CA R e f e r e n c e V o l t a g e - VADS8482SLAS386A–JULY 2005–REVISED JUNE 2006TERMINAL FUNCTIONS (continued)NAME NO I/O DESCRIPTIONDB839O D8All ones All ones D8All ones D8DB740O D7All ones All ones D7All ones D7DB641O D6All ones All ones D6All ones D6DB542O D5All ones All ones D5All ones D5DB443O D4All ones All ones D4All ones D4DB344O D3All ones All ones D3D1D3DB245O D2All ones All ones D2D0(LSB)D2DB146O D1All ones All ones D1All ones D1DB047O D0(LSB)All onesAll onesD0(LSB)All onesD0(LSB)–IN 19I Inverting input channel +IN 18INoninverting input channel NC 15No connection REFIN 13I Reference inputREFOUT 14O Reference output.Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used.REFM 11,12I Reference groundSynchronization pulse for the parallel output.When CS is low,this serves as output enable and puts the previous RD 5I conversion results on the bus.7,10,16,+VA –Analog power supplies,5-V DC 21,22,25+VBD1,36–Digital power supply for busINTERNAL REFERENCE VOLTAGEINTERNAL REFERENCE VOLTAGEDC HISTOGRAMvsvs(8192Conversion Outputs)FREE-AIR TEMPERATURESUPPLY VOLTAGEFigure 1.Figure 2.Figure 3.9Submit Documentation Feedback40Sample Rate - KSPSS u p p l y C u r r e n t - m A5.15Supply Voltage - VS u p p l y C u r r e n t - m AT - Free-Air Temperature - °CA S u p p l y C u r r e n t - m ASupply Voltage - VD N L - L S B sT - Free-Air Temperature - °CA I N L - L SB s-40-25-1052035506580T - Free-Air Temperature - °CA D N L - L SB sReference Voltage - VI N L - L S B s-1.5024.754.854.955.05 5.15 5.25Supply Voltage - VI N L - L S B sReference Voltage - VD N L - L S B sADS8482SLAS386A–JULY 2005–REVISED JUNE 2006TYPICAL CHARACTERISTICS (continued)SUPPLY CURRENTSUPPLY CURRENTSUPPLY CURRENTvsvsvsFREE-AIR TEMPERATURESUPPLY VOLTAGESAMPLE RATEFigure 4.Figure 5.Figure 6.DIFFERENTIAL NONLINEARITYINTEGRAL NONLINEARITYDIFFERENTIAL NONLINEARITYvsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATURESUPPLY VOLTAGEFigure 7.Figure 8.Figure 9.INTEGRAL NONLINEARITYDIFFERENTIAL NONLINEARITYINTEGRAL NONLINEARITYvsvsvsSUPPLY VOLTAGEREFERENCE VOLTAGEREFERENCE VOLTAGEFigure 10.Figure 11.Figure 12.10Submit Documentation FeedbackSupply Voltage - VO f f s e t E r r o r - m V33.23.4 3.6 3.844.2Reference Voltage - VO f f s e t E r r o r - m V-0.09-0.08-0.07-0.06-0.05-0.04-0.03-0.02-0.01-40-25-1052035506580T - Free-Air Temperature - °CA O f f s e t E r r o r - m V-0.04Supply Voltage - VG a i n E r r o r - %F SG a i n E r r o r - %F ST - Free-Air Temperature - °CA Reference Voltage - VG a i n E r r o r - %F SOffset Drift - ppm/CF r e q u e n c y0.030.190.350.500.660.90Gain Error Drift - ppm/CF r eq u e n c y-123-121-11933.23.4 3.6 3.844.2V - Reference Voltage - Vref T H D - d BSLAS386A–JULY 2005–REVISED JUNE 2006TYPICAL CHARACTERISTICS (continued)OFFSET ERROROFFSET ERROROFFSET ERRORvsvsvsFREE-AIR TEMPERATURESUPPLY VOLTAGEREFERENCE VOLTAGEFigure 13.Figure 14.Figure 15.GAIN ERRORGAIN ERRORGAIN ERRORvsvsvsSUPPLY VOLTAGEFREE-AIR TEMPERATUREREFERENCE VOLTAGEFigure 16.Figure 17.Figure 18.TOTAL HARMONIC DISTORTIONOFFSET ERROR TEMPERATURE GAIN ERROR TEMPERATURE vsDRIFT DISTRIBUTION (35Samples)DRIFT DISTRIBUTION (35Samples)REFERENCE VOLTAGEFigure 19.Figure 20.Figure 21.V - Reference Voltage - Vref S I N A D - S i g n a l -t o -n o i s e + D i s t o r t i o n - d B96.59797.59898.59999.5V - Reference Voltage - Vref S N R - S i g n a l -t o -N o i s e R a t i o - d B-40-25-1052035506580T - Free-Air Temperature - °CA T H D - T o t a l H a r m o n i c D i s t o r t i o n - d BS N R - S i g n a l -t o -N o i s e R a t i o - d BT - Free-Air Temperature - °CAS I N A D - S i g n a l -t o -N o i s e + D i s t o r t i o n - d BT - Free-Air Temperature - °CAT - Free-Air Temperature - °CA S F D R - S p u r i o u s F r e e D y n a m i c R a n g e - d B-1.5-1-0.500.511.5-131072-6553665536131072Output CodeD N L - L S B sSLAS386A–JULY 2005–REVISED JUNE 2006TYPICAL CHARACTERISTICS (continued)SIGNAL-TO-NOISE RATIOSIGNAL-TO-NOISE +DISTORTIONTOTAL HARMONIC DISTORTIONvsvsvsREFERENCE VOLTAGEREFERENCE VOLTAGEFREE-AIR TEMPERATUREFigure 22.Figure 23.Figure 24.SPURIOUS FREE DYNAMIC RANGESIGNAL-TO-NOISE RATIOSIGNAL-TO-NOISE +DISTORTIONvsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 25.Figure 26.Figure 27.DNLFigure 28.-2.5-2-1.5-1-0.500.511.522.5-131072-6553665536131072Output CodeI N L - L S BsSLAS386A–JULY 2005–REVISED JUNE 2006TYPICAL CHARACTERISTICS (continued)INLFigure 29. SLAS386A–JULY2005–REVISED JUNE2006TIMING DIAGRAMS†Signal internal to deviceFigure30.Timing for Conversion and Acquisition Cycles With CS and RD TogglingDB[17:12]CONVSTBUSYCS CONVERT †(When CS Toggle)BYTEBUS 18/16RD = 0t †t DB[11:10]DB[9:0]SLAS386A–JULY 2005–REVISED JUNE 2006Figure 31.Timing for Conversion and Acquisition Cycles With CS Toggling,RD Tied to BDGNDSLAS386A–JULY2005–REVISED JUNE2006Figure32.Timing for Conversion and Acquisition Cycles With CS Tied to BDGND,RD TogglingSLAS386A–JULY2005–REVISED JUNE2006Figure33.Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND-Auto ReadSLAS386A–JULY2005–REVISED JUNE2006RDBYTEBUS 18/16DB[17:0]Figure34.Detailed Timing for Read CyclesAPPLICATION INFORMATIONMICROCONTROLLER INTERFACINGADS8482to 8-Bit Microcontroller InterfaceAnalog 5 VExt Ref Input Analog InputAnalog 5 VAGNDSLAS386A–JULY 2005–REVISED JUNE 2006Figure 35shows a parallel interface between the ADS8482and a typical microcontroller using the 8-bit data bus.The BUSY signal is used as a falling-edge interrupt to the microcontroller.Figure 35.ADS8482Application CircuitryFigure 36.ADS8482Using Internal ReferencePRINCIPLES OF OPERATIONREFERENCESLAS386A–JULY 2005–REVISED JUNE 2006The ADS8482is a high-speed successive approximation register (SAR)analog-to-digital converter (ADC).The architecture is based on charge redistribution which inherently includes a sample/hold function.See Figure 35for the application circuit for the ADS8482.The conversion clock is generated internally.The conversion time of 650ns is capable of sustaining a 1MHz throughput.The analog input is provided to two input pins:+IN and –IN.When a conversion is initiated,the differential input on these pins is sampled on the internal capacitor array.While a conversion is in progress,both inputs are disconnected from any internal function.The ADS8482can operate with an external reference with a range from 3.0V to 4.2V.The reference voltage on the input pin #13(REFIN)of the converter is internally buffered.A clean,low noise,well-decoupled reference voltage on this pin is required to ensure good performance of the converter.A low noise band-gap reference like the REF3240can be used to drive this pin.A 0.1-µF decoupling capacitor is required between REFIN and REFM pins (pin #13and pin #12)of the converter.This capacitor should be placed as close as possible to the pins of the device.Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter.An RC network can also be used to filter the reference voltage.A 100-Ωseries resistor and a 0.1-µF capacitor,which can also serve as the decoupling capacitor can be used to filter the reference voltage.Figure 37.ADS8482Using External ReferenceThe ADS8482also has limited low pass filtering capability built into the converter.The equivalent circuitry on the REFIN input ia as shown in Figure 38.Figure 38.Simplified Reference Input CircuitThe REFM input of the ADS8482should always be shorted to AGND.A 4.096-V internal reference is included.When internal reference is used,pin 14(REFOUT)is connected to pin 13(REFIN)with an 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 14(REFOUT)and pins 11and 12(REFM)(see Figure 36).The internal reference of the converter is double buffered.If an external reference is used,the second buffer provides isolation between the external reference and the CDAC.This buffer is also used to recharge all of the capacitors of the CDAC during conversion.Pin 14(REFOUT)can be left unconnected (floating)if external reference is used. ANALOG INPUTADS8482SLAS386A–JULY2005–REVISED JUNE2006 PRINCIPLES OF OPERATION(continued)When the converter enters the hold mode,the voltage difference between the+IN and–IN inputs is captured on the internal capacitor array.Both+IN and–IN input has a range of–0.2V to Vref+0.2V.The input span[+IN–(–IN)]is limited to–V ref to V ref.The input current on the analog inputs depends upon a number of factors:sample rate,input voltage,and source impedance.Essentially,the current into the ADS8482charges the internal capacitor array during the sample period.After this capacitance has been fully charged,there is no further input current.The source of the analog input must be able to charge the input capacitance(65pF)to an18-bit settling level within the acquisition time(320ns)of the device.When the converter goes into the hold mode,the input impedance is greater than1 GΩ.Care must be taken regarding the absolute analog input voltage.To maintain the linearity of the converter,the +IN and–IN inputs and the span[+IN–(–IN)]must be within the limits specified.Outside of these ranges,the converter's linearity may not meet specifications.To minimize noise,low bandwidth input signals with low-pass filters are used.Care must be taken to ensure that the output impedance of the sources driving the+IN and–IN inputs are matched.If this is not observed,the two inputs could have different setting times.This may result in offset error, gain error,and linearity error which varies with temperature and input voltage.The analog input to the converter needs to be driven with a low noise,high-speed op-amp like the THS4031.An RC filter is recommended at the input pins to low-pass filter the noise from the source.The input to the converter is a uni-polar input voltage in the range0to V ref.The THS4031can be used in the source follower configuration to drive the converter.21Submit Documentation Feedback(+)IN+VIN (-)INADS8482SLAS386A–JULY 2005–REVISED JUNE 2006PRINCIPLES OF OPERATION (continued)Figure 39.Single-Ended Input,Differential Output ConfigurationIn systems,where the input is differential,the THS4031can be used in the inverting configuration with an additional DC bias applied to its +input so as to keep the input to the ADS8482within its rated operating voltage range.The DC bias can be derived from the REF3220or the REF3240reference voltage ICs.The input configuration shown below is capable of delivering better than 97dB SNR and -103db THD at an input frequency of 100kHz.In case band-pass filters are used to filter the input,care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal.In such cases,the gain of the circuit shown below can be increased to keep the input to the ADS8482large to keep the SNR of the system high.Note that the gain of the system from the +input to the output of the THS4031in such a configuration is a function of the gain of the AC signal.A resistor divider can be used to scale the output of the REF3220or REF3240to reduce the voltage at the DC input to THS4031to keep the voltage at the input of the converter within its rated operating range.22Submit Documentation Feedback。
MBN 10284-2_2001.8_EN
August 2001DaimlerChryslerRoad vehiclesEMC requirements and tests of E/E systemsPart 2: Component test proceduresMBN 10 284-2Supersedes edition:Continued on pages 2 to 44Issued by :DaimlerChrysler AG D-70546 StuttgartNormung (EP/QDN)Technical responsibility (Name): GurtnerDepartment: EP/QDN Plant:019Telephone : (+49) 711 17- 2 08 39HPC:D652Sequence number 22 902/2Confidential! All rights reserved. Distribution and copes without written agreement by Daimler-Benz AG prohibited.Contractors may only receive standards through the responsible purchasing department.Contents 1General......................................................................................................................................................21.1Purpose.....................................................................................................................................................21.2Scope.........................................................................................................................................................21.3Normative references ..............................................................................................................................21.4Definitions.................................................................................................................................................41.5Test conditions.........................................................................................................................................41.6Test plan ...................................................................................................................................................41.7Test report and statement.......................................................................................................................41.8Test voltages............................................................................................................................................42Measuring and test equipment...............................................................................................................52.1Shielded enclosure..................................................................................................................................52.2Absorber-lined chamber..........................................................................................................................52.3Ground plane............................................................................................................................................52.4Stripline.....................................................................................................................................................52.5TEM cell.....................................................................................................................................................62.6Coupling clamp........................................................................................................................................62.7Current clamp...........................................................................................................................................62.8Artificial networks...................................................................................................................................72.8.1Transient disturbance emission.............................................................................................................72.8.2RF disturbance emission ........................................................................................................................72.9Electronic power switch..........................................................................................................................82.10ESD simulator...........................................................................................................................................82.11Coupling planes.......................................................................................................................................82.12Insulating bases.......................................................................................................................................83Emitted disturbances...............................................................................................................................93.1Conducted emissions..............................................................................................................................93.1.1Transient emissions conducted along supply lines.............................................................................93.1.2Radio disturbances conducted along supply lines............................................................................113.1.3Radio disturbance currents conducted along control/signal lines...................................................133.2Emission.................................................................................................................................................144.Immunity.................................................................................................................................................174.1Conducted disturbances......................................................................................................................174.2Radiation.................................................................................................................................................324.2.1Antenna radiation...................................................................................................................................324.2.2TEM cell...................................................................................................................................................344.2.3BCI method.............................................................................................................................................364.2.4Stripline...................................................................................................................................................384.3ESD (40)Date of translation 2002-03Page 2MBN 10 284-2 : 2001-081General1.1PurposeThe purpose of this Standard is to ensure electromagnetic compatibility (EMC) within the vehicle. In order to achieve this purpose, tests of the components alone (so-called "component tests") are described and the permissible emitted disturbances and immunity requirements defined. Deviations from the requirements contained in this Standard are only allowed if agreed explicitly in the specifications book between the supplier and the Mercedes-Benz vehicle line within DaimlerChrysler AG.The requirements are not deemed fulfilled until both the component test and the vehicle test have been passed. The purpose of component testing is a pre-qualification of components already at a time when no vehicles are yet available. Vehicle testing is authoritative for EMC approval.The Supplier shall comply with this Standard and ensure that its latest edition is used at all times.1.2ScopeThis Standard applies to all electrical and electronic components and subassemblies mounted in Mercedes-Benz vehicles.1.3Normative referencesThe EMC requirements and tests specified in this Standard are based, on principle, on the following national and international standards and statutory regulations listed below.DIN 40839-1:1992-10Elektromagnetische Verträglichkeit (EMV) in Straßenfahrzeugen.Leitungsgeführte impulsförmige Störgrößen auf Versorgungsleitungen in12-V-und 24-V-Bordnetzen.ISO 7637-3:1995-07Road vehicles, Electrical disturbance by conduction and coupling Part 3- Vehicles with nominal 12 V or 24 V supply voltage - Electrical transienttransmission by capacitive and inductive coupling via lines other thansupply lines.DIN ISO 7637-3:1999-02Straßenfahrzeuge, Elektrische Störungen durch Leitung und Kopplung,Teil 3: Fahrzeuge mit 12-V- oder 24-V-Bordnetz-Nennspannung,Übertragung von impulsförmigen elektrischen Störgrößen durchkapazitive und induktive Kopplung auf Leitungen, die keineVersorgungsleitungen sind (German translation of ISO 7637-3:1995).ISO 11452-1:1995-12Road vehicles, Electrical disturbances by narrowband radiatedelectromagnetic energy - Component test methods Part 1 - General anddefinitions.DIN ISO 11452-1:2000-03Straßenfahrzeuge, Elektrische Störung durch schmalbandige gestrahlteelektromagnetische Energie, Prüfverfahren für Komponenten, Teil 1:Allgemeines und Definitionen (German translation of ISO 11452-1:1995).ISO 11542-2:1995-12Road vehicles, Electrical disturbances by narrowband radiatedelectromagnetic energy - Component test methods Part 2 - Absorber-lined chamber.DIN ISO 11452-2:2000-03Straßenfahrzeuge, Elektrische Störungen durch schmalbandigegestrahlte elektromagnetische Energie, Prüfverfahren für Komponenten,Teil 2: Absorberraum (German translation of ISO 11452-2: 1995).ISO 11542-3:1995-12Road vehicles, Electrical disturbances by narrowband radiatedelectromagnetic energy - Component test methods Part 3 - Transverseelectromagnetic mode (TEM) cell.Page 3MBN 10 284-2 : 2001-08 DIN ISO 11452-3:2000-03Straßenfahrzeuge, Elektrische Störungen durch schmalbandigegestrahlte elektromagnetische Energie, Prüfverfahren für Komponenten,Teil 3: Transversal-Elektro-Magnetische (TEM)- Wellenleiter (Germantranslation of ISO 11452-3: 1995).ISO 11452-4:1995-12Road vehicles, Electrical disturbances by narrowband radiatedelectromagnetic energy - Component test methods Part 4 - Bulk currentinjection (BCI).DIN ISO 11452-4:2000-03Straßenfahrzeuge, Elektrische Störungen durch schmalbandigegestrahlte elektromagnetische Energie, Prüfverfahren für Komponenten,Teil 4: Stromeinspeisung (BCI) (German translation of ISO 11452-4:1995).ISO 11452-5:1995-12Road vehicles, Electrical disturbances by narrowband radiatedelectromagnetic energy - Component test methods Part 5 - Stripline.DIN ISO 11452-5:2000-03Straßenfahrzeuge, Elektrische Störungen durch schmalbandigegestrahlte elektromagnetische Energie, Prüfverfahren für Komponenten,Teil 5: Streifenleitung (German translation of ISO 11452-5: 1995).DIN VDE 0876-16-11):1998-05Anforderungen an Geräte und Einrichtungen sowie Festlegung derVerfahren zur Messung der hochfrequenten Störaussendung(Funkstörungen) und Störfestigkeit. Teil 1: Geräte und Einrichtungen zurMessung der hochfrequenten Störaussendung (Funkstörungen) undStörfestigkeit (German translation of CISPR 16-1: 1993).DIN VDE 0879-2:1999-03Grenzwerte und Messverfahren für Funkstörungen zum Schutz vonEmpfängern in Fahrzeugen (German translation of CISPR 25: 1995).ISO 106052):2000-08Road vehicles - Electrical disturbances from electrostatic discharges.ISO 16750-13):Road vehicles - Environmental conditions and testing for electrical andelectronic equipment Part 1 - General.ISO 16750-23):Road vehicles - Environmental conditions and testing for electrical andelectronic equipment Part 2 - Electrical loads.DIN EN 61000-4-2:1996-03Elektromagnetische Verträglichkeit (EMV), Teil 4: Prüf- undMessverfahren, Hauptabschnitt 2: Prüfung der Störfestigkeit gegen dieEntladung statischer Elektrizität (dt. Fassung von IEC 1000-4-2: 1995,Klassifikation VDE 0847 Teil 4-2).DIN IEC 60050-161:1990-08Internationales Elektrotechnisches Wörterbuch, Teil 161:Elektromagnetische Verträglichkeit. .1)draft at present2)DIS (Draft International Standard) at present3)CD (Committee Draft) at presentPage 4MBN 10 284-2 : 2001-081.4DefinitionsRefer to Part 1 of this Standard1.5Test conditionsRefer to Part 1 of this Standard1.6Test planRefer to Part 1 of this Standard1.7Test report and statementRefer to Part 1 of this Standard1.8Test voltagesThe permissible test voltages are indicated in Table 1.1.Table 1.1: Permissible test voltagesOnboard system U p in V12 V13,5 ± 0,224 V27 ± 0,242 V42 ± 0,5Page 5MBN 10 284-2 : 2001-08 2Measuring and test equipment2.1Shielded enclosureRefer to Part 1 of this Standard2.2Absorber-lined chamberRefer to Part 1 of this Standard2.3Ground planeThe ground plane shall be a metal panel (e.g. copper, copper zinc alloy (brass) or electroplated steel) with a minimum thickness of 1 mm. Unless otherwise indicated, the dimensions of the ground plane shall be 2 m x1 m. The size finally selected depends, however, on the dimensions of the device under test. The groundplane shall be connected to the ground of the test equipment.2.4StriplineA stripline consists of a conductive strip over a ground plane. For a schematic diagram of a strip line designrefer to Figure 2.1.terminating resistorFigure 2.1: Schematic diagram of a stripline designIt is capable of carrying a TEM mode. The impedance of the stripline primarily depends on the ratio between the strip width and the height above the ground plane. The line shall be terminated on one side (e.g. using a suitable terminating resistor). DIN ISO 11452-5 describes the design of a stripline in detail.A stripline with a nominal impedance of 90 W is preferred, whereby only the TEM mode can be propagated upto 200 MHz4). Due to the emission, the stripline shall be operated in an absorber-lined chamber (refer to 4)This restricts the maximum dimensions of the stripline.Page 6MBN 10 284-2 : 2001-082.5TEM cellA TEM cell consists of a conductive strip – the so-called septum – which is mounted insulated within a shielded enclosure. For a schematic diagram of a TEM cell refer to Fig. 2.2.conductor panelinner conductor (septum)Fig. 2.2: Schematic diagram of a TEM cell design.The design of a TEM cell is described in detail in DIN ISO 11452-3.A TEM cell with a nominal impedance of 50 W is preferred, whereby only the TEM mode can be propagatedup to 200 MHz 5). The TEM cell does not need to be operated in a shielded enclosure or an absorber-lined 2.6Coupling clampA coupling clamp allows the capacitive coupling of fast transient pulses in a harness. For a schematic diagram refer to Figure 2.3.moveableFig. 2.3: Schematic diagram of a coupling clamp.The coupling clamp to be used is described in detail in DIN ISO 7637-3. Its typical coupling capacity is approx. 100 pF and it has an impedance (without fitted harness) of 50 W .2.7Current clampCurrent clamp are current transformers which can be used both for injecting and measuring current in cables without interrupting the conductor.2.7.1Current injection clampCurrent injection clamp are optimised for the injection of currents in lines. They shall be dimensioned adequately with regard to their frequency range and injected power.5)This restricts the maximum dimensions of the TEM cell.Page 7MBN 10 284-2 : 2001-082.7.2Current measuring probeA current measuring probe is a hinged current transformer which is used to determine the strength of currents in an electrical conductor or cable. No direct (metallic) connection with the conductor is required in this process. The probe is arranged around the conductor to be tested which becomes a primary winding with one turn. The probe itself is the secondary winding with many turns. It shall have an output impedance of 50W . No saturation of the core shall occur either through the RF currents to be measured nor through the load currents.2.8Artificial networks2.8.1Transient disturbance emissionThe artificial network in accordance with DIN 40839-1 shall be used. This artificial network is intended tosimulate the harness impedance. For a schematic diagram, refer to Figure 2.4.A B BFig. 2.4: Artificial network in accordance with DIN 40839-1.2.8.2RF disturbance emissionThe artificial mains network in accordance with DIN VDE 0879-2 shall be used.The artificial mains network is intended:· to provide a defined RF impedance at the connections of the device under test,· to decouple the device under test from undesired RF signals from the power supply system, and ·to couple the RF disturbance voltage into the measuring receiver.For a schematic diagram refer to Figure 2.5.ABW(Input impedance/termination)50Fig. 2.5: Artificial network in accordance with DIN VDE 0879-2.The 50 W measuring receiver shall be connected to the measuring terminals M.Page 8MBN 10 284-2 : 2001-082.9Electronic power switchAn electronic power switch in accordance with DIN 40839-1 shall be used for defined disconnection of the battery. The specifications in accordance with Table 2.1 shall be complied with.Table 2.1: Electronic power switch specifications.Dielectric strength U max = 400 V at 25 ACurrent-carrying capacityImax= 25 Afor short periods (≤ 1 s) 100 AVoltage drop∆U≤ 1 V at 25 ATest voltages U1 = 13,5 V U2 = 27 V U3 = 42 VSwitching times 200 ... 400 ns with device under test (R = 0,6 W; L = 50 m H(at 1 kHz))2.10ESD simulatorRefer to Section 2.4 of Part 1 of this Standard2.11Coupling planesCoupling planes are used for ESD testing in order to conduct transient field tests. In this process, a discharge onto a metallic plate adjacent to the device under test using the ESD simulator is carried out. Horizontal and vertical coupling planes are used.2.11.1Vertical coupling planes (VCP)A vertical coupling plane is a metal panel with a thickness of no less than 0,25 mm and dimensions 0,5 m x0,5 m. It is conductively connected to the ground plane via 2 resistors with 470 k W and arranged in an upright position.2.11.2Horizontal coupling planes (HCP)A horizontal coupling plane is a metal panel with a thickness of no less than 0,25 mm and dimensions 1,6 mx 0,8 m. It may be larger where required by the test set-up. It is conductively connected to the ground plane via 2 resistors with 470 k W and arranged horizontally.2.12Insulating basesInsulating bases shall be between 0,5 mm and 2 mm thick and shall demonstrate a dielectric constant of between 2 and 5 (e.g. Polyethylene or Teflon). Their dielectric strength shall be maintained up to at least25 kV, and they shall rise at least 10 mm at all sides above their insulating devices.Page 9MBN 10 284-2 : 2001-083Emitted disturbances3.1Conducted emissions3.1.1Transient emissions conducted along supply linesThe test shall be carried out in analogy with DIN 40839-1. The disturbance voltage emission conducted along the supply lines of devices is measured whereby the device (or the coupled devices) shall be operated as intended.An autonomous measurement of inductive loads can be dispensed with, if · these are only ever installed together in an electrical/electronic system across all platforms,· the disturbance suppression circuit to limit the voltage transient is integrated in an electrical / electronic system,·crosstalk through the wiring harness is impossible.3.1.1.1Test set-upFor a schematic diagram of the test set-up refer to Figures 3.1 and 3.2.Fig. 3.1: Transient emission measurement. Device under test with one supply voltage connection.Fig. 3.2: Transient emission measurement. Device under test with two supply voltage connections.·Devices under test where the ground connection in the vehicle is via the vehicle body, shall be placed directly on the ground plane and connected with it. The ground plane serves as ground connection of the test under device with the artificial network.Page 10MBN 10 284-2 : 2001-08·Devices under test where the ground connection in the vehicle is via dedicated cable shall be placed ona 50 mm high insulating base.·Lines between devices under test and artificial mains network(s) shall be routed at a height of 50 mm above the ground plane and should be 200 mm long.·Switches shall be designed in accordance with DIN 40839-1 (refer to Section 2.9).·Artificial networks in accordance with DIN 40839-1 (refer to Section 2.8.1, integrated in switch, if possible) shall be used.·Selection of equivalent resistance R s: unless otherwise specified, 40 W shall be used for 12 V and 24 V connections and 120 W for 42 V connections.·The storage oscilloscopes shall have a sampling rate of at least 2 GS/s and an analog bandwidth of 500 MHz.·The probes shall be placed as close to the device under test as possible.·The battery shall be buffered, i.e. the battery voltage shall be maintained at the relevant test voltage by constant charging.3.1.1.2Test procedure·Electric motors which can be run to the locked status in normal operation shall be measured in their locked state.·Continuous disturbance sources shall be measured with closed switch.·Where the disturbance voltage is a consequence of switching off, the measurement shall commence at the moment when the switch is opened and record the complete disturbance emission.·In case of devices under test with two supply voltage connections, two measurements (switch-off of U1 / U2) shall be carried out.3.1.1.3Requirement·12 V and 42 V devices under testDeviating from DIN 40839-1, no classification of the disturbances emitted is made. The voltage shall not exceed the value of U tr,max = 75 V irrespective of the pulse shape.·24 V devices under testSeverity level III defined in DIN 40839-1 shall be achieved, i.e. the limit values indicated in Table 3.1 depending on the pulse shape (see test pulses in Section 4.1.1.2) shall not be exceeded.Table 3.1: Limit values for 24 V devices under test.Characteristic pulse shape Test pulsePermissible pulse amplitudeV1-150 275 3a75 3b-140 5a1503.1.2Radio disturbances conducted along supply linesRadio disturbance emissions conducted along supply lines shall be measured in analogy with DIN VDE 0879-2 within the frequency range of 150 kHz ... 110 MHz using one or several Artificial networks allowing the decoupling of the disturbance voltage.3.1.2.1Test set-upTest set-ups are illustrated in Figure 3.3.if requireda) Device under test with long ground line.b) Device under test with short ground line.c) Alternators and generatorsif requiredInsulating spacer,if requiredFig. 3.3: RF emissions conducted along supply lines: Test set-up.· The ground plane shall be no smaller than 400 mm x 1000 mm.·Artificial networks in accordance with DIN VDE 0879-2 (refer to Section 2.8.2) shall be used.· A measuring receiver in accordance with DIN VDE 0876-16-16)shall be connected to the measuringterminals M of the artificial mains network.· The cables between the device under test and the artificial mains network shall be routed at a height of50 mm above the ground plane and shall be no longer than 200 mm.· The test set-ups for devices under test with several supply voltage connections shall be supplementedaccordingly.6)see page 33.1.2.2Test conditionsAction shall be taken to ensure that the device under test emits its maximum disturbance power (occurring during normal operation) during the measurement.Broadband measurements shall be carried out using a quasi-peak detector, while an average detector shall be used for narrowband measurements.3.1.2.3RequirementThe measured values shall be below the limit values indicated in Table 3.2.Table 3.2: RF emissions conducted along supply lines: Limit values.Test No.BandFrequency rangeMHzMeasuringbandwidthkHzNarrowbandaveragedB(m V)Broadbandquasi-peakdB(m V)1LW0,15 ... 0,39 / 105060 2MW0,53 ... 1,79 / 103450 3a SW5,8 ... 6,39 / 103340 3b SW7,1 ... 7,69 / 103340 3c SW9,3 ... 109 / 103340 3d SW11,5 ... 12,19 / 103340 3e SW13,6 ... 13,89 / 103340 3f SW15 ... 15,79 / 103340 4a11 m25 ... 359 / 1024-4b11 m25 ... 35100 / 120-245TVI/IIVHF40 ... 110100 / 120242464m65 ... 889 / 1024-74mSpecialpurpose84,015 ... 87,2559 / 1012-3.1.3Radio disturbance currents conducted along control/signal linesThe emitted radio disturbance currents shall be measured on control and signal lines in analogy with DIN VDE 0879-2 using a current probe within a frequency range of 0,15 MHz ... 110 MHz.3.1.3.1Test set-upFor a schematic diagram of the measuring set-up, refer to Fig. 3.4.Measuring instrumentTest benchFig. 3.4: Measurement of radio disturbance currents conducted along control and signal lines.·Measurements shall be carried out in a shielded enclosure (refer to Section 2.1 of Part 1 of this Standard).·The power supply shall be effected via an artificial mains network (refer to Section 2.8.2) in accordance with DIN VDE 0879-2.· A current measuring probe (refer to Section 2.7.2) shall be used designed for the frequency range 0,15 MHz ... 110 MHz.·The bench on which the device under test, the test harness and the artificial mains network(s) are arranged, shall be 900 mm high and no less than 2500 mm long. A ground plane (refer to Section 2.3) with the same dimensions shall be placed on this table and conductively connected with the wall of the shielded enclosure.·The test harness shall be 1500 mm ± 75 mm long and routed 50 mm above the ground plane.·The device under test and all parts of the harness shall be installed at a distance of 100 mm ± 10 mm away from the edge of the ground plane.·The measuring instrument shall be placed outside the shielded enclosure.3.1.3.2Test conditions·Measurements shall be taken at the following four points:- at a distance of 50 mm from the terminals of the device under test;- at a distance of 500 mm ± 10 mm from the terminals of the device under test;- at a distance of 1000 mm ± 10 mm from the terminals of the device under test;- at a distance of 50 mm from the terminals of the artificial network.·Action shall be taken to ensure that the device under test emits its maximum disturbance power (occurring during normal operation) during the measurement.·Broadband measurements shall be carried out using a quasi-peak detector, while an average detector shall be used for narrowband measurements.3.1.3.3RequirementsAll measured values shall be below the limit values indicated in Table 3.3.Table 3.3: RF emissions conducted along control and signal lines: Limit values.Test No.BandFrequency rangeMHzMeasuringbandwidthkHzNarrowbandaveragedB(m A)Broadbandquasi-peakdB(m A)1LW0,15 ... 0,39 / 103040 2MW0,53 ... 1,79 / 10622 3a SW5,8 ... 6,39 / 10- 16 3b SW7,1 ... 7,69 / 10- 16 3c SW9,3 ... 109 / 10- 16 3d SW11,5 ... 12,19 / 10- 16 3e SW13,6 ... 13,89 / 10- 16 3f SW15 ... 15,79 / 10- 16 4a11 m25 ... 359 / 10- 6-4b11 m25 ... 35100 / 120-65TVI/IIVHF40 ... 110100 / 120- 10- 1064m65 ... 889 / 10- 10-74mSpecial.purpose84,015 ... 87,2559 / 10- 16-3.2Emission3.2.1Measurement with antennaThe emission of components shall be measured in analogy with DIN VDE 0879-2 in an absorber-lined chamber (refer to Section 2.2 of Part 1 of this Standard) with an antenna in the frequency range of 80 MHz ...960 MHz.。
88E6122_88E6121-Datasheet-Part 1
Link Street™ 88E6122/88E6121 Datasheet Part 1 of 3: Overview, Pinout, Applications, Mechanical and Electrical Specifications
Doc. No. MV-S103526-01 Rev. -Page 2
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Advance
This document contains design specifications for initial product development. Specifications may
Information change without notice. Contact Marvell Field Application Engineers for more information.
LabVolt系列HART和FOUNDATION Fieldbus计ibration套件说明书
LabVolt SeriesDatasheet Calibration Kit (HART and FOUNDATION Fieldbus)588419 (46981-A0)* The product images shown in this document are for illustration purposes; actual products may vary. Please refer to the Specifications section of each product/item for all details. Festo Didactic reserves the right to change product images and specifications at any time without notice.Festo Didactic en12/2023Calibration Kit (HART and FOUNDATION Fieldbus), LabVolt SeriesTable of ContentsGeneral Description_________________________________________________________________________________3 Manual___________________________________________________________________________________________3Calibration Kit (HART and FOUNDATION Fieldbus), LabVolt Series••General DescriptionThe Calibration Kit includes the equipment required to precisely adjust the control valves, perform diagnostic tests, and interface with smart devices.This version of the kit is compatible with both HART and FOUNDATION Fieldbus. It includes the Emerson AMS Trex™ Device Communicator: a universal HART and FOUNDATION Fieldbus communicator. The kit also contains a Fluke 725 multifunction process calibrator which can act as a source and measure different parameters.It also include a test pump used to generate a wide range of pressures from vacuums at -95 kPa (-13.9 psi) to pressures up to 410 kPa (600 psi). Two pressure gauges, a low-range version (up to 34 kPa (5 psi)) and a high-range version (up to 690 kPa (100 psi)), are included and can be used with the Fluke calibrator for directmeasurement of pressure.A Calibration Kit, Model 46980 or 46981, is required to characterize and tune processes in the Pressure, Flow, Level, and Temperature Process Training Systems.Available Calibration Kits46981-0 Calibration Kit (HART)46981-A Calibration Kit (HART and FOUNDATION Fieldbus)ManualDescription Manualnumber(Workbook) ______________________________________________________________________594085 (54387-00)Calibration Kit (HART and FOUNDATION Fieldbus), LabVolt Series Reflecting the commitment of Festo Didactic to high quality standards in product, design, development, production, installation, and service, our manufacturing and distribution facility has received the ISO 9001 certification.Festo Didactic reserves the right to make product improvements at any time and without notice and is not responsible for typographical errors. Festo Didactic recognizes all product names used herein as trademarks or registered trademarks of their respective holders. © Festo Didactic Inc. 2023. All rights reserved.Festo Didactic SERechbergstrasse 373770 DenkendorfGermanyP. +49(0)711/3467-0F. +49(0)711/347-54-88500Festo Didactic Inc.607 Industrial Way WestEatontown, NJ 07724United StatesP. +1-732-938-2000F. +1-732-774-8573Festo Didactic Ltée/Ltd675 rue du CarboneQuébec QC G2N 2K7CanadaP. +1-418-849-1000F. +1-418-849-1666。
Quick Reference Guide for sbRIO-9628 Kit - 国家信息仪器（
Quick Reference GuidesbRIO-9628© 2019 National Instruments All rights reserved.Information is subject to change without notice. Refer to the NI Trademarks and Logo Guidelines at /trademarks for more information on NI trademarks. Other product and company names mentioned herein are trademarks or trade names of their respective companies. For patents covering NI products/technology, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your media, or the National Instruments Patents Notice at /patents . You can find information about end-user license agreements (EULAs) and third-party legal notices in the readme file for your NI product. Refer to the Export Compliance Information at /legal/export-compliance for the NI global trade compliance policy and how to obtain relevant HTS codes, ECCNs, and other import/export data. NI MAKES NO EXPRESS OR IMPLIED WARRANTIES AS TO THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS. U.S. Government Customers: The data contained in this manual was developed at private expense and is subject to the applicable limited rights and restricted data rights as set forth in FAR 52.227-14, DFAR 252.227-7014, and DFAR 252.227-7015.For a complete list of resources go to the following URL: ni .com/r /sbrio377897A-03 Oct19Connect to the Host Computer via Ethernet1. Power on the host computer.2. Connect the sbRIO-9628 to the host computer using a standard Category 5 (CAT-5) or better shielded, twisted-pair Ethernet cable.Connect to Power1. Ensure that your power supply is powered off.2. Insert the power connector plug into the power connector receptacle of the sbRIO-9628 until the connector latches into place.3. Turn on the power supply.Connect to the Host Computer via USB1. Power on the host computer.2. Connect the USB Type-C 2.0 device port of the sbRIO-9628 to the host computer using a Type-C to Type-A USB cable.ORsbRIO-9628 Block DiagramCAN Pinout1311. Power LED2. Status LED3. User1 LED4. User FPGA1 LED5. SD in Use LED1. Connector0 (MIO Port) 8. CAN port2. RS-485 port (ASRL3) 9. USB Type-C 2.0 device port3. RS-232 port (ASRL2) 10. USB Type C 3.1 host port4. USB Type-A 2.0 host port 11. RS-232 serial port (ASRL1)5. USB Type-A 2.0 host port 12. Ethernet ports6. MicroSD port 13. RMC Connector7. Power terminalsbRIO-9628 Parts Locator DiagramRS-485 (ASRL3) PinoutConnector0 (MIO port) Pinout。
FE1.1s (B) Data Sheet 1.0 USB HUB SSOP28
USB Multi-port Transceiver Macro Cell
12MHz Crystal 3.3V & 1.8V Regulator OSC Over Current Detection Power Switch Control POR PLL (x40) Data Transmit Data Recovery & Elastic Buffer Upstream Port Controller
1
April 24, 2012
Subject Change Without Notice
USB 2.0 4-Port Hub Product Brief Rev. B1.0
□
The TT could handle 64 periodic StartSplit transactions, 32 periodic CompleteSplit transactions, and 6 none-periodic transactions;
Ganged Power Control and Global OverCurrent Detection support; EEPROM configured options – □ □ Vendor ID, Product ID, & Device Release Number; and Number of Downstream Ports; Automatic re-enumeration when hub switches from self-powered mode to bus-powered mode; Board configured comprehensive Port Indicators support: □ Four Downstream Port Enabled indicator LED (Green, one for each port), plus one Active/Suspend indicator LED (Red); or □ One joint Downstream Port Enabled indicator LED (Green, one for all ports), plus one Active/Suspend indicator LED (Red); or
Si8410 20 21和Si8422 23型号的Silicon Labs低功耗数字隔离器数据手册说
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data SheetLow-Power, Single and Dual-Channel Digital IsolatorsSilicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-stantial data rate, propagation delay, power, size, reliability, and external BOM advan-tages when compared to legacy isolation technologies. The operating parameters ofthese products remain stable across wide temperature ranges and throughout deviceservice life for ease of design and highly uniform performance. All device versions haveSchmitt trigger inputs for high noise immunity and only require V DD bypass capacitors.Data rates up to 150 Mbps are supported, and all devices achieve worst-case propaga-tion delays of less than 10 ns. Ordering options include a choice of isolation ratings (upto 5 kV) and a selectable fail-safe operating mode to control the default output state dur-ing power loss. All products are safety certified by UL, CSA, and VDE, and products inwide-body packages support reinforced insulation withstanding up to 5 kV RMS.Applications•Industrial automation systems •Medical electronics•Hybrid electric vehicles •Isolated switch mode supplies •Isolated ADC, DAC •Motor control•Power inverters •Communication systemsSafety Regulatory Approvals•UL 1577 recognized•Up to 5000 V RMS for 1 minute •CSA component notice 5A approval •IEC 60950-1, 61010-1, 60601-1(reinforced insulation)•VDE certification conformity•IEC 60747-5-5 (VDE0884 Part 5)•EN60950-1 (reinforced insulation)1. Features List•High-speed operation•DC to 150 Mbps•No start-up initialization required •Wide Operating Supply Voltage:• 2.6 – 5.5 V•Up to 5000 V RMS isolation•High electromagnetic immunity •Ultra low power (typical)• 5 V Operation:•< 2.6 mA/channel at 1 Mbps•< 6.8 mA/channel at 100 Mbps • 2.70 V Operation:•< 2.3 mA/channel at 1 Mbps•< 4.6 mA/channel at 100 Mbps •Schmitt trigger inputs •Selectable fail-safe mode•Default high or low output •Precise timing (typical)•11 ns propagation delay max • 1.5 ns pulse width distortion•0.5 ns channel-channel skew • 2 ns propagation delay skew• 5 ns minimum pulse width •Transient immunity 45 kV/µs •AEC-Q100 qualification •Wide temperature range•–40 to 125 °C at 150 Mbps •RoHS compliant packages•SOIC-16 wide body•SOIC-8 narrow body2. Ordering GuideTable 2.1. Ordering Guide1,2,33. Functional Description3.1 Theory of OperationThe operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in the figure below.A BFigure 3.1. Simplified Channel DiagramA channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to outputB via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See the figure below for more details.Input SignalModulation SignalOutput SignalFigure 3.2. Modulation Scheme3.2 Eye DiagramThe figure below illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were captured on an oscilloscope. The re-sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.Figure 3.3. Eye Diagram4. Device OperationDevice behavior during start-up, normal operation, and shutdown is shown in Figure 4.1 Device Behavior during Normal Operation on page 6, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to determine outputs when power supply (V DD) is not present.Table 4.1. Si84xx Logic Operation Table4.1 Device StartupOutputs are held low during powerup until V DD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs.4.2 Under Voltage LockoutUnder Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when V DD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when V DD1 falls below V DD1(UVLO–) and exits UVLO when V DD1 rises above V DD1(UVLO+). Side B operates the same as Side A with respect to its V DD2 supply.VVFigure 4.1. Device Behavior during Normal Operation4.3 Layout RecommendationsTo ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V AC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V AC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5.5 Regulatory Information1 on page 20and Table 5.6 Insulation and Safety-Related Specifications on page 21detail the working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.4.3.1 Supply BypassThe Si841x/2x family requires a 0.1 μF bypass capacitor between V DD1and GND1 and V DD2and GND2. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, it is further recommended that the user also add 1μF bypass capacitors and include 100 Ω resistors in series with the inputs and outputs if the system is excessively noisy.4.3.2 Pin ConnectionsNo connect pins are not internally connected. They can be left floating, tied to V DD, or tied to GND.4.3.3 Output Pin TerminationThe nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.4.4 Fail-Safe Operating ModeSi84xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 4.1 Si84xx Logic Operation Table on page 5 and Section 2. Ordering Guide for more information.4.5 Typical Performance CharacteristicsThe typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Table 5.2 Electri-cal Characteristics on page 9 through Table 5.4 Electrical Characteristics 1 on page 17for actual specification limits.Figure 4.2. Si8410 Typical V DD1 Supply Currentvs. Data Rate 5, 3.3, and 2.70 V Operation Figure 4.3. Si8420 Typical V DD1 Supply Currentvs. Data Rate 5, 3.3, and 2.70 V OperationFigure 4.4. Si8421 Typical V DD1 or V DD2 Supply Current vs.Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)Figure 4.5. Si8410 Typical V DD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation(15 pF Load)Figure 4.6. Si8420 Typical V DD2 Supply Current vs. Data Rate5, 3.3, and 2.70 V Operation(15 pF Load)Figure 4.7. Si8422 Typical V DD1 or V DD2 Supply Current vs.Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)Figure 4.8. Si8423 Typical V DD1 Supply Currentvs. Data Rate 5, 3.3, and 2.70 V OperationFigure 4.9. Si8423 Typical V DD2 Supply Current vs. Data Rate5, 3.3, and 2.70 V Operation(15 pF Load)Figure 4.10. Propagation Delayvs. TemperatureElectrical Specifications 5. Electrical SpecificationsTable 5.1. Recommended Operating ConditionsTable 5.2. Electrical Characteristics(V DD1 = 5 V ±10%, V DD2 = 5 V ±10%, T A = –40 to 125 °C)InputTypical OutputFigure 5.1. Propagation Delay TimingTable 5.3. Electrical Characteristics (V DD1 = 3.3 V ±10%, V DD2 = 3.3 V ±10%, T A = –40 to 125 °C)Table 5.4. Electrical Characteristics1 (V DD1 = 2.70 V, V DD2 = 2.70 V, T A = –40 to 125 °C)Table 5.5. Regulatory Information1CSAThe Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.61010-1: Up to 600 V RMS reinforced insulation working voltage; up to 600 V RMS basic insulation working voltage.60950-1: Up to 600 V RMS reinforced insulation working voltage; up to 1000 V RMS basic insulation working voltage.60601-1: Up to 125 V RMS reinforced insulation working voltage; up to 380 V RMS basic insulation working voltage.VDEThe Si84xx is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.60747-5-5: Up to 891 V peak for basic insulation working voltage.60950-1: Up to 600 V RMS reinforced insulation working voltage; up to 1000 V RMS basic insulation working voltage.ULThe Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.Rated up to 5000 V RMS isolation voltage for basic insulation.Note:1.Regulatory Certifications apply to2.5 kV RMS rated devices which are production tested to3.0 kV RMS for 1 sec. Regulatory Certifi-cations apply to 5.0 kV RMS rated devices which are production tested to 6.0 kV RMS for 1 sec.For more information, see Section 2. Ordering Guide.Table 5.6. Insulation and Safety-Related SpecificationsTable 5.7. IEC 60747-5-5 Insulation Characteristics for Si84xxxx1Table 5.8. IEC Safety Limiting Values1Table 5.9. Thermal Characteristics200150********2501250Case Temperature (ºC)S a f e t y -L i m i t i n g V a l u es (m A )375Figure 5.2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Valueswith Case Temperature per DIN EN 60747-5-5200150********2001000Case Temperature (ºC)S a f e t y -L i m i t i n g V a l u es (m A )300Figure 5.3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Valueswith Case Temperature per DIN EN 60747-5-5Table 5.10. Absolute Maximum Ratings16. Pin Descriptions6.1 Pin Descriptions (Wide-Body SOIC)VVVVFigure 6.1. Wide-Body SOICTable 6.1. Pin Descriptions6.2 Pin Descriptions (Narrow-Body SOIC)V DD2V DD2Figure 6.2. Narrow-Body SOIC7. Package Outlines7.1 Package Outline (16-Pin Wide Body SOIC)The figure below illustrates the package details for the Si84xx Digital Isolator. The table below lists the values for the dimensions shown in the illustration.Figure 7.1. 16-Pin Wide Body SOICTable 7.1. Package Diagram Dimensions7.2 Package Outline (8-Pin Narrow Body SOIC)The figure below illustrates the package details for the Si84xx. The table below lists the values for the dimensions shown in the illustra-tion.Figure 7.2. 8-pin Small Outline Integrated Circuit (SOIC) PackageTable 7.2. Package Diagram Dimensions8. Land Patterns8.1 Land Pattern (16-Pin Wide-Body SOIC)The figure below illustrates the recommended land pattern details for the Si84xx in a 16-pin wide-body SOIC. The table below lists the values for the dimensions shown in the illustration.Figure 8.1. 16-Pin SOIC Land PatternTable 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions8.2 Land Pattern (8-Pin Narrow Body SOIC)The figure below illustrates the recommended land pattern details for the Si84xx in an 8-pin narrow-body SOIC. The table below lists the values for the dimensions shown in the illustration.Figure 8.2. PCB Land Pattern: 8-Pin Narrow Body SOICTable 8.2. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)9. Top Markings9.1 Top Marking (16-Pin Wide Body SOIC)Figure 9.1. Isolator Top MarkingTable 9.1. Top Marking ExplanationLine 1 Marking:Base Part NumberOrdering Options(See 2. Ordering Guide for more information).Si84 = Isolator product seriesXY = Channel ConfigurationX = # of data channels (2, 1)Y = # of reverse channels (1, 0)1,2S = Speed GradeA = 1 MbpsB = 150 MbpsV = Insulation ratingA = 1 kV;B = 2.5 kV;C = 3.75 kV;D = 5 kVLine 2 Marking:YY = YearWW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date.TTTTTT = Mfg Code Manufacturing code from assembly house. Line 3 Marking:Circle = 1.7 mm Diameter(Center-Justified)“e4” Pb-Free Symbol.Country of Origin ISO Code Abbreviation TW = Taiwan.Notes:1.The Si8422 has one reverse channel.2.The Si8423 has zero reverse channels.9.2 Top Marking (8-Pin Narrow-Body SOIC)Figure 9.2. Isolator Top MarkingTable 9.2. Top Marking ExplanationLine 1 Marking:Base Part NumberOrdering Options(See 2. Ordering Guide for more information).Si84 = Isolator product seriesXY = Channel ConfigurationX = # of data channels (2, 1)Y = # of reverse channels (1, 0)1,2S = Speed GradeA = 1 MbpsB = 150 MbpsV = Insulation ratingA = 1 kV;B = 2.5 kV;C = 3.75 kV;D = 5 kVLine 2 Marking:YY = YearWW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date.R = Product (OPN) Revision F = Wafer FabLine 3 Marking:Circle = 1.1 mm DiameterLeft-Justified “e3” Pb-Free Symbol.First two characters of the manufacturing code.A = Assembly SiteI = Internal CodeXX = Serial Lot NumberLast four characters of the manufacturing code.Notes:1.The Si8422 has one reverse channel.2.The Si8423 has zero reverse channels.Document Change List 10. Document Change List10.1 Revision 0.1•Initial release.10.2 Revision 0.1 to Revision 1.0•Updated features list.•Updated transient immunity.•Removed block diagram from front page.•Added chip graphics on front page.•Added Peak Eye Diagram jitter in Table 5.2 Electrical Characteristics on page 9through Table 5.4 Electrical Characteristics1on page 17.•Updated transient immunity•Moved Table 4.1 Si84xx Logic Operation Table on page 5 to Section 4. Device Operation.•Added Section 4. Device Operation.•Added Section 4.4 Fail-Safe Operating Mode.•Moved Section 4.5 Typical Performance Characteristics.•Deleted RF Radiated Emissions section.•Deleted RF Magnetic and Common-Mode Transient Immunity section.•Updated MSL rating to MSL2A.10.3 Revision 1.0 to Revision 1.1•Numerous text edits.•Added table notes to Table 9.1 Top Marking Explanation on page 32 and Table 9.2 Top Marking Explanation on page 33.10.4 Revision 1.1 to Revision 1.2•Updated Timing Characteristics in Table 5.2 Electrical Characteristics on page 9through Table 5.4 Electrical Characteristics1on page 17.10.5 Revision 1.2 to Revision 1.3•Added references to AEC-Q100 qualified throughout.•Changed all 60747-5-2 references to 60747-5-5.•Updated Table 2.1 Ordering Guide1,2,3 on page 2.•Added table notes 1 and 2.•Removed references to moisture sensitivity levels.•Added Revision D ordering information.•Removed older revisions.•Updated Section 9.1 Top Marking (16-Pin Wide Body SOIC).10.6 Revision 1.3 to Revision 1.4September 16, 2016•Updated data sheet format.Table of Contents1. Features List (1)2. Ordering Guide (2)3. Functional Description (3)3.1 Theory of Operation (3)3.2 Eye Diagram (4)4. Device Operation (5)4.1 Device Startup (5)4.2 Under Voltage Lockout (6)4.3 Layout Recommendations (6)4.3.1 Supply Bypass (6)4.3.2 Pin Connections (6)4.3.3 Output Pin Termination (6)4.4 Fail-Safe Operating Mode (6)4.5 Typical Performance Characteristics (7)5. Electrical Specifications (9)6. Pin Descriptions (25)6.1 Pin Descriptions (Wide-Body SOIC) (25)6.2 Pin Descriptions (Narrow-Body SOIC) (26)7. Package Outlines (27)7.1 Package Outline (16-Pin Wide Body SOIC) (27)7.2 Package Outline (8-Pin Narrow Body SOIC) (28)8. Land Patterns (30)8.1 Land Pattern (16-Pin Wide-Body SOIC) (30)8.2 Land Pattern (8-Pin Narrow Body SOIC) (31)9. Top Markings (32)9.1 Top Marking (16-Pin Wide Body SOIC) (32)9.2 Top Marking (8-Pin Narrow-Body SOIC) (33)10. Document Change List (34)10.1 Revision 0.1 (34)10.2 Revision 0.1 to Revision 1.0 (34)10.3 Revision 1.0 to Revision 1.1 (34)10.4 Revision 1.1 to Revision 1.2 (34)10.5 Revision 1.2 to Revision 1.3 (34)10.6 Revision 1.3 to Revision 1.4 (34)Silicon Laboratories Inc.400 West Cesar Chavez Austin, TX 78701USASmart.Connected.Energy-Friendly .Products/productsQuality/qualitySupport and CommunityDisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.。
NVIDIA CUDA 安装指南（Mac OS X）.pdf_1701874422.4227781说
DU-05348-001_v8.0 | September 2016Installation and Verification on Mac OS XTABLE OF CONTENTS Chapter 1. Introduction (1)1.1. System Requirements (1)1.2. About This Document (2)Chapter 2. Prerequisites (3)2.1. CUDA-capable GPU (3)2.2. Mac OS X Version (3)2.3. Xcode Version (3)2.4. Command-Line T ools (4)Chapter 3. Installation (5)3.1. Download (5)3.2. Install (5)3.3. Uninstall (6)Chapter 4. Verification (8)4.1. Driver (8)4.2. Compiler (8)4.3. Runtime (9)Chapter 5. Additional Considerations (11)CUDA® is a parallel computing platform and programming model invented by NVIDIA. It enables dramatic increases in computing performance by harnessing the power of the graphics processing unit (GPU).CUDA was developed with several design goals in mind:‣Provide a small set of extensions to standard programming languages, like C, that enable a straightforward implementation of parallel algorithms. With CUDA C/C++, programmers can focus on the task of parallelization of the algorithms rather than spending time on their implementation.‣Support heterogeneous computation where applications use both the CPU and GPU. Serial portions of applications are run on the CPU, and parallel portions are offloaded to the GPU. As such, CUDA can be incrementally applied to existingapplications. The CPU and GPU are treated as separate devices that have their own memory spaces. This configuration also allows simultaneous computation on the CPU and GPU without contention for memory resources.CUDA-capable GPUs have hundreds of cores that can collectively run thousands of computing threads. These cores have shared resources including a register file and a shared memory. The on-chip shared memory allows parallel tasks running on these cores to share data without sending it over the system memory bus.This guide will show you how to install and check the correct operation of the CUDA development tools.1.1. System RequirementsTo use CUDA on your system, you need to have:‣ a CUDA-capable GPU‣Mac OS X 10.11 or later‣the Clang compiler and toolchain installed using Xcode‣the NVIDIA CUDA Toolkit (available from the CUDA Download page)Introduction T able 1 Mac Operating System Support in CUDA 8.0Before installing the CUDA Toolkit, you should read the Release Notes, as they provide important details on installation and software functionality.1.2. About This DocumentThis document is intended for readers familiar with the Mac OS X environment andthe compilation of C programs from the command line. You do not need previous experience with CUDA or experience with parallel computation.2.1. CUDA-capable GPUTo verify that your system is CUDA-capable, under the Apple menu select About This Mac, click the More Info … button, and then select Graphics/Displays under the Hardware list. There you will find the vendor name and model of your graphics card. If it is an NVIDIA card that is listed on the CUDA-supported GPUs page, your GPU is CUDA-capable.The Release Notes for the CUDA Toolkit also contain a list of supported products.2.2. Mac OS X VersionThe CUDA Development Tools require an Intel-based Mac running Mac OSX v. 10.11 or later. To check which version you have, go to the Apple menu on the desktop and select About This Mac.2.3. Xcode VersionA supported version of Xcode must be installed on your system. The list of supported Xcode versions can be found in the System Requirements section. The latest version of Xcode can be installed from the Mac App Store.Older versions of Xcode can be downloaded from the Apple Developer Download Page. Once downloaded, the Xcode.app folder should be copied to a version-specific folder within /Applications. For example, Xcode 6.2 could be copied to /Applications/ Xcode_6.2.app.Once an older version of Xcode is installed, it can be selected for use by running the following command, replacing <Xcode_install_dir> with the path that you copied that version of Xcode to:sudo xcode-select -s /Applications/<Xcode_install_dir>/Contents/DeveloperPrerequisites 2.4. Command-Line T oolsThe CUDA Toolkit requires that the native command-line tools are already installed on the system. Xcode must be installed before these command-line tools can be installed. The command-line tools can be installed by running the following command:$ xcode-select --installNote: It is recommended to re-run the above command if Xcode is upgraded, or an older version of Xcode is selected.You can verify that the toolchain is installed by running the following command:$ /usr/bin/cc --version3.1. DownloadOnce you have verified that you have a supported NVIDIA GPU, a supported version the MAC OS, and clang, you need to download the NVIDIA CUDA Toolkit.The NVIDIA CUDA Toolkit is available at no cost from the main CUDA Downloads page. The installer is available in two formats:work Installer: A minimal installer which later downloads packages required forinstallation. Only the packages selected during the selection phase of the installer are downloaded. This installer is useful for users who want to minimize download time.2.Full Installer: An installer which contains all the components of the CUDA Toolkitand does not require any further download. This installer is useful for systemswhich lack network access.Both installers install the driver and tools needed to create, build and run a CUDA application as well as libraries, header files, CUDA samples source code, and other resources.The download can be verified by comparing the posted MD5 checksum with that of the downloaded file. If either of the checksums differ, the downloaded file is corrupt and needs to be downloaded again.To calculate the MD5 checksum of the downloaded file, run the following:$ openssl md5 <file>3.2. InstallUse the following procedure to successfully install the CUDA driver and the CUDA toolkit. The CUDA driver and the CUDA toolkit must be installed for CUDA to function. If you have not installed a stand-alone driver, install the driver provided with the CUDA Toolkit.Choose which packages you wish to install. The packages are:‣CUDA Driver: This will install /Library/Frameworks/CUDA.framework and the UNIX-compatibility stub /usr/local/cuda/lib/libcuda.dylib that refers to it.‣CUDA Toolkit: The CUDA Toolkit supplements the CUDA Driver with compilers and additional libraries and header files that are installed into /Developer/ NVIDIA/CUDA-8.0 by default. Symlinks are created in /usr/local/cuda/pointing to their respective files in /Developer/NVIDIA/CUDA-8.0/. Previous installations of the toolkit will be moved to /Developer/NVIDIA/CUDA-#.# to better support side-by-side installations.‣CUDA Samples (read-only): A read-only copy of the CUDA Samples is installed in /Developer/NVIDIA/CUDA-8.0/samples. Previous installations of the samples will be moved to /Developer/NVIDIA/CUDA-#.#/samples to better support side-by-side installations.A command-line interface is also available:‣--accept-eula: Signals that the user accepts the terms and conditions of the CUDA-8.0 EULA.‣--silent: No user-input will be required during the installation. Requires --accept-eula to be used.‣--no-window: No windows will be created during the installation. Useful for installing in environments without a display, such as via ssh. Implies --silent.Requires --accept-eula to be used.‣--install-package=<package>: Specifies a package to install. Can be used multiple times. Options are "cuda-toolkit", "cuda-samples", and "cuda-driver".‣--log-file=<path>: Specify a file to log the installation to. Default is /var/log/ cuda_installer.log.Set up the required environment variables:export PATH=/Developer/NVIDIA/CUDA-8.0/bin${PATH:+:${PATH}}export DYLD_LIBRARY_PATH=/Developer/NVIDIA/CUDA-8.0/lib\${DYLD_LIBRARY_PATH:+:${DYLD_LIBRARY_PATH}}In order to modify, compile, and run the samples, the samples must also be installed with write permissions. A convenience installation script is provided: cuda-install-samples-8.0.sh. This script is installed with the cuda-samples-8-0 package.T o run CUDA applications in console mode on MacBook Pro with both an integratedGPU and a discrete GPU, use the following settings before dropping to console mode:1.Uncheck System Preferences > Energy Saver > Automatic Graphic Switch2.Drag the Computer sleep bar to Never in System Preferences > Energy Saver3.3. UninstallThe CUDA Driver, Toolkit and Samples can be uninstalled by executing the uninstall script provided with each package:T able 2 Mac Uninstall Script LocationsAll packages which share an uninstall script will be uninstalled unless the --manifest=<uninstall_manifest> flag is used. Uninstall manifest files are located in the same directory as the uninstall script, and have filenames matching .<package_name>_uninstall_manifest_do_not_delete.txt.For example, to only remove the CUDA Toolkit when both the CUDA Toolkit and CUDA Samples are installed:$ cd /Developer/NVIDIA/CUDA-8.0/bin$ sudo perl uninstall_cuda_8.0.pl \--manifest=.cuda_toolkit_uninstall_manifest_do_not_delete.txtBefore continuing, it is important to verify that the CUDA toolkit can find and communicate correctly with the CUDA-capable hardware. To do this, you need to compile and run some of the included sample programs.Ensure the PATH and DYLD_LIBRARY_PATH variables are set correctly.4.1. DriverIf the CUDA Driver is installed correctly, the CUDA kernel extension (/System/ Library/Extensions/CUDA.kext) should be loaded automatically at boot time. To verify that it is loaded, use the commandkextstat | grep -i cuda4.2. CompilerThe installation of the compiler is first checked by running nvcc -V in a terminal window. The nvcc command runs the compiler driver that compiles CUDA programs. It calls the host compiler for C code and the NVIDIA PTX compiler for the CUDA code. The NVIDIA CUDA Toolkit includes CUDA sample programs in source form. To fully verify that the compiler works properly, a couple of samples should be built. After switching to the directory where the samples were installed, type:make -C 0_Simple/vectorAddmake -C 0_Simple/vectorAddDrvmake -C 1_Utilities/deviceQuerymake -C 1_Utilities/bandwidthTestThe builds should produce no error message. The resulting binaries will appear under <dir>/bin/x86_64/darwin/release. To go further and build all the CUDA samples, simply type make from the samples root directory.4.3. RuntimeAfter compilation, go to bin/x86_64/darwin/release and run deviceQuery. Ifthe CUDA software is installed and configured correctly, the output for deviceQuery should look similar to that shown in Figure 1.Figure 1 Valid Results from deviceQuery CUDA SampleNote that the parameters for your CUDA device will vary. The key lines are the first and second ones that confirm a device was found and what model it is. Also, the next-to-last line, as indicated, should show that the test passed.Running the bandwidthTest sample ensures that the system and the CUDA-capable device are able to communicate correctly. Its output is shown in Figure 2Figure 2 Valid Results from bandwidthT est CUDA SampleNote that the measurements for your CUDA-capable device description will vary from system to system. The important point is that you obtain measurements, and that the second-to-last line (in Figure 2) confirms that all necessary tests passed.Should the tests not pass, make sure you have a CUDA-capable NVIDIA GPU on your system and make sure it is properly installed.If you run into difficulties with the link step (such as libraries not being found), consult the Release Notes found in the doc folder in the CUDA Samples directory.To see a graphical representation of what CUDA can do, run the particles executable.Now that you have CUDA-capable hardware and the NVIDIA CUDA Toolkit installed, you can examine and enjoy the numerous included programs. To begin using CUDA to accelerate the performance of your own applications, consult the CUDA C Programming Guide.A number of helpful development tools are included in the CUDA Toolkit to assistyou as you develop your CUDA programs, such as NVIDIA® Nsight™ Eclipse Edition, NVIDIA Visual Profiler, cuda-gdb, and cuda-memcheck.For technical support on programming questions, consult and participate in the Developer Forums.NoticeALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATEL Y, "MATERIALS") ARE BEING PROVIDED "AS IS." NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND EXPRESSL Y DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE.Information furnished is believed to be accurate and reliable. However, NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. No license is granted by implication of otherwise under any patent rights of NVIDIA Corporation. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all other information previously supplied. NVIDIA Corporation products are not authorized as critical components in life support devices or systems without express written approval of NVIDIA Corporation.TrademarksNVIDIA and the NVIDIA logo are trademarks or registered trademarks of NVIDIA Corporation in the U.S. and other countries. Other company and product names may be trademarks of the respective companies with which they are associated. Copyright© 2009-2016 NVIDIA Corporation. All rights reserved.。
Atmel CryptoAuthentication AT88CK101 开发套件硬件用户指南说明书
AT88CK101 Atmel CryptoAuthentication Development KitHARDWARE USER GUIDEAtmel CryptoAuthentication AT88CK101 DaughterboardAtmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_112015AT88CK101 Development Kit [HARDWARE USER GUIDE] Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_11201522IntroductionThe Atmel ®CryptoAuthentication™ AT88CK101 is a daughterboard that interfaces with a MCU board via a 10-pin header. The daughterboard has a single 8-pin SOIC socket which can support the AtmelATSHA204A, ATAES132A, ATECC108A, and ATECC508A crypto element devices. The daughter board comes in two different variations with a socket that supports either an 8-lead SOIC or an 8-leadUDFN/XDFN. This kit uses a modular approach, enabling the daughterboard to connect directly to an STKseries Atmel AVR ® or Atmel ARM ®development platform to easily add security to applications. An optional adapter kit is also available when the 10-pin header on the daughterboard is incompatible. The AT88CK101provides a test point header for the I 2C, SWI, and SPI signals. The AT88CK101 is sold with the Atmel AT88Microbase module to form the Atmel AT88CK101-XXX Starter Kit. The AT88Microbase AVR-based base board comes with a USB interface that lets designers learn and experiment on their PCs.Contents∙ Atmel AT88CK101 DaughterboardFeatures∙ 8-lead SOIC and UDFN/XDFN Socket∙ Supports the ATSHA204A, ATAES132A, ATECC108A, and ATECC508A Devices ∙Supports Communication Protocols: – I 2C– SWI (Single-Wire Interface) – SPI ∙ Power LED ∙Test Points HeaderFigure 1.AT88CK101 DaughterboardPin 1 Indicator HeaderStandoff HoleStandoff HoleProtocolTable of ContentsAT88CK101 Starter Kit (4)Development Kit Configuration (5)10-pin Interface Header (5)6-pin Test Header (5)Supports 8-lead SOIC and SPI Interfaces (5)Configurations (6)References and Further Information (7)Revision History (8)AT88CK101 Development Kit [HARDWARE USER GUIDE]Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_1120153 3AT88CK101 Development Kit [HARDWARE USER GUIDE] Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_11201544AT88CK101 Starter KitThe AT88CK101 is sold with the Atmel AT88Microbase module to form the AT88CK101-XXX Starter Kit. For additional information on the AT88Microbase, refer to the Atmel AT88Microbase Hardware User Guide .Figure 2.AT88CK101STK8 Starter KitFigure 3.AT88CK101 Daughterboard with AT88MicrobaseAT88CK101 Development Kit [HARDWARE USER GUIDE]Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_11201555 Development Kit Configuration10-pin Interface HeaderTable 1-1. 10-pin Interface Header (1)(2)Notes: 1. I C Pins:SCL, SDA2. SPI Pins:/CS, SCLK, MOSI, MISO6-pin Test HeaderTable 1-2.6-pin Test HeaderSupports 8-lead SOIC and SPI InterfacesThe AT88CK101 supports 8-lead SOIC and SPI Interfaces with the following pinout configuration.Figure 4.Pinout ConfigurationsNote:Drawings are not to scale.Top View 8-lead SOICNC NC NC NCV CC NC SCL SDA12348765Top View8-lead SOIC/CS SO NC GNDV CC NC SCK SI12348765ConfigurationsThe below table describes the how to configure the AT88CK101 with respect to the AT88Microbase and the STK/EVK development platforms.Table 1. AT88CK101STK8 Starter Kit Configuration GuideNote: X = Don’t CareFigure 5. AT88CK101 Adapter Board Mounted to STK600AT88CK101 Development Kit [HARDWARE USER GUIDE]Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_11201566Figure 6. Atmel AT88CK301ADP Adapter KitTable 2. 10-pin Squid CableReferences and Further InformationSchematics, Gerber files, Bill Of Materials (BOM), development and demonstration software is conveniently downloadable from the Atmel website at /cryptokits.ATMEL EVALUATION BOARD/KIT IMPORTANT NOTICE AND DISCLAIMERThis evaluation board/kit is intended for user's internal development and evaluation purposes only. It is not a finished product and may not comply with technical or legal requirements that are applicable to finished products, including, without limitation, directives or regulations relating to electromagnetic compatibility, recycling (WEEE), FCC, CE or UL. Atmel is providing this evaluation board/kit “AS IS” without any warranties or indemnities. The user assumes all responsibility and liability for handling and use of the evaluation board/kit including, without limitation, the responsibility to take any and all appropriate precautions with regard to electrostatic discharge and other technical issues. User indemnifies Atmel from any claim arising from user's handling or use of this evaluation board/kit. Except for the limited purpose of internal development and evaluation as specified above, no license, express or implied, by estoppel or otherwise, to any Atmel intellectual property right is granted hereunder. ATMEL SHALL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMGES RELATING TO USE OF THIS EVALUATION BOARD/KIT.ATMEL CORPORATION1600 Technology DriveSan Jose, CA 95110USAAT88CK101 Development Kit [HARDWARE USER GUIDE]Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_1120157 7AT88CK101 Development Kit [HARDWARE USER GUIDE] Atmel-8726A-CryptoAuth-AT88CK101-Hardware-UserGuide_11201588Revision History。
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Product Name:
Alisertib CAS No.:
1028486-01-2Cat. No.:
HY-10971
Product Data Sheet
MWt:
518.92Formula:
C27H20ClFN4O4Purity :>98%
Solubility:DMSO ≥
42mg/mL Water
Mechanisms:
Biological Activity:
Alisertib (MLN8237)is a selective Aurora A inhibitor with IC50of 1.2nM;has >200-fold higher
Pathways:Cell Cycle/DNA Damage; Target:Aurora Kinase <1.2mg/mL Ethanol <1.2mg/mL
Alisertib (MLN8237) is a selective Aurora A inhibitor with IC50 of 1.2 nM; has 200fold higher
selectivity for Aurora A than Aurora B.
IC50 Value: 1.2 nM (Aurora A)
Target: Aurora A in vitro: MLN8237 (0.5 μM) treatment inhibits the phosphorylation of Aurora A in MM1.S and OPM1cells, without affecting the Aurora B mediated histone H3 phosphorylation. MLN8237 significantly inhibits cell proliferation in multiple myeloma (MM) cell lines with IC50 values of 0.003-1.71 μM.
MLN8237 displays more potent anti-proliferation activity against primary MM cells and MM cell lines in the presence of BM stroma cells, as well as IL-6 and IGF-1 than against MM cells alone.
References:
[1]. Güllü G?rgün et al A novel Aurora-A kinase inhibitor MLN8237 induces cytotoxicity and cell-cycle
arrest in multiple myeloma Blood June 24, 2010 vol. 115 no. 25 5202-5213[2]Dominic A Sloane?et al Drug-Resistant Aurora A Mutants for Cellular Target Validation of the MLN8237 (0.5 μM) induces 2- to 6-fold increase in G2/M phase in primary MM cells and cell lines,as well as significant apoptosis and senescence, involving the up-regulation of p53, p21 and p27, as well as PARP, ca...
[2]. Dominic A. Sloane? et al Drug Resistant Aurora A Mutants for Cellular Target Validation of the
Small Molecule Kinase Inhibitors MLN8054 and MLN8237 ACS Chem. Biol., 2010, 5 (6), pp 563-576[3]. Matulonis UA, Sharma S, Ghamande S, Gordon MS, Del Prete SA, Ray-Coquard I, Kutarska E,Liu H, Fingert H, Zhou X, Danaee H, Schilder RJ.Phase II study of MLN8237 (alisertib), an
investigational Aurora A kinase inhibitor, in patients with platinum-resistant or -refractory epithelial ovarian, fallopian tube, or primary peritoneal carcinoma.Gynecol Oncol. 2012 Oct;127(1):63-9. Epub
2012 Jul 5.[4]. Manfredi MG, Ecsedy JA, Chakravarty A, Silverman L, Zhang M, Hoar KM, Stroud SG, Chen W,Shind...
Caution: Not fully tested. For research purposes only
Medchemexpress LLC
18W i l k i n s o n W a y , P r i n c e t o n , N J 08540,U S A
E m a i l : i n f o @m e d c h e m e x p r e s s .c o m W e b : w w w .m e d c h e m e x p r e s s .c o m。