R8A66160SP中文资料

QN0
QO0
QP0
qO0
Output lighting
H X ˢ X L H qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 “H”
H ˢ X L L QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QI0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 Output
12 QP
QN 13
QN
PARALLEL DATA OUTPUTS
FUNCTIONAL DESCRIPTION
As R8A66160 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “L”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from QA ~ QP. Outputs QA ~ QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. When reset input R is changed to “L”, QA ~ QP and SQP are reset. In this case, shifting and latching register are reset. If “H” is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation.
8 76 9
CKS R CKL GND
SHIFT DIRECT LATCH CLOCK RESET CLOCK INPUT INPUT INPUT
REJ03F0261-0100 Rev.1.00 Jan.10.2008
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page 1 of 7
元器件交易网
R8A66160DD/SP
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
S S S S S
54
OE A
ENABLE SERIAL INPUT DATA
INPUT
DATA signal OE signal
PARALLEL DATA OUTPUTS QAʙQP
OUTPUT FORMAT
SERIAL DATA OUTPUT SQP
10
3
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
Q
CK DR
APPLICATION
● LED array drive, The various LED display modules ● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipment
BLOCK DIAGRAM
DIRECT RESET INPUT R
7R
QI 18
QI
SHIFT CLOCK INPUT
CKS
8 CKS QJ 17
QJ
GND 9
QK 16
QK
SERIAL DATA OUTPUT SQP 10 SQP QL 15 QL
PARALLEL DATA OUTPUTS
QO
11 QO QM 14
QM
QP
FUNCTION TABLE (Note: 1)
Operation mode
Reset
Shift t1
Shift
Latch t2
Latch
operation Shift t1
Latch t2
Output disable
Input
Parallel data output
Serial data Remarks
t1, t2 ɿt2 is set after t1 is set Z ɿHigh Impedance
REJ03F0261-0100 Rev.1.00 Jan.10.2008
.
page 2 of 7
元器件交易网
R8A66160DD/SP
ABSOLUTE MAXIMUM RATINGS (Ta=-40~+85oC, unless otherwise noted)
PIN CONFIGURATION ( TOP VIEW )
PARALLEL DATA OUTPUTS
QA
1 QA
QC 24
QC
QB
2 QB
QD 23
QD
VCC
3
QE 22
QE
SERIAL DATA INPUT
A
4A
QF 21
QF
ENABLE INPUT
OE
5 OE
QG 20
QG
LATCH CLOCK INPUT CKL 6 CKL QH 19 QH
R CKS CKL
A
OE
QA
QB QC QD
QE QF
QG QH
QI
QJ
QK QL QM
QN QO
QP
output SQP
L XX XX Z Z Z Z Z Z Z Z Z Z Z Z Z ZZ ZL
H ˢX
H
L
QA0
QB0 QC0 QD0
QE0 QF0
QG0 QH0 QI0 QJ0
QK0 QL0 QM0
LOGIC DIAGRAM
PARALLEL DATA OUTPUTS
SERIAL DATA OUTPUT
QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP
1 2 24 23 22 21 20 19 18 17 16 15 14 13 11 12
SQP Vcc
simultaneous lighting available ● Low power dissipation: 100uW/package (max) (Vcc=5.0V, Ta=25oC, quiescent state) ● High noise margin: Schmitt input circuit provides responsiveness to a long line length ● Equipped with direct-coupled reset ● Open drain output: (except serial data output SQP) ● Wide operating temperature range: Ta=-40oC~+85oC ● Pin layout facilitates printed circuit wiring. (This layout facilitates cascade connection and LED connection)