HD74LS273FPEL中文资料 - 360文档中心

用74LS273输出数据

摘要近年来随着计算机在社会领域的渗透和大规模集成电路的发展，单片机的应用正在不断地走向深入，由于它具有功能强，体积小，功耗低，价格便宜，工作可靠，使用方便等特点，因此特别适合于与控制有关的系统，越来越广泛地应用于自动控制，智能化仪器，仪表，数据采集，军工产品以及家用电器等各个领域，单片机往往是作为一个核心部件来使用，在根据具体硬件结构，以及针对具体应用对象特点的软件结合，以作完善。

而51系列单片机是各单片机中最为典型和最有代表性的一种，通过本次课程设计进一步对单片机学习和应用，从而更熟悉单片机的原理和相关设计并提高了开发软、硬件的能力。

本次课设题目是用74LS273输出数据，要求在通用插座上扩展一片74LS273作为输出口，控制八个LED灯，通过此次设计学习在单片机系统中扩展简单I/O接口的方法和数据输出程序的设计方法，了解数据锁存的概念和方法。

关键词：单片机74LS273 LED一、单片机基础知识介绍1.1单片机概述单片机的全称为单片微型计算机，它是在一块硅片上集成微处理器，存储器和各种输入、输出接口，这样一块芯片具有一台计算机的属性。

单片机主要应用于测控领域，用于实现各种测试和控制功能，为了强调其控制属性，在国际上，一般把单片机成为微处理器MCU。

由于单片机应用时通常是处于被控系统的核心地位并嵌入其中，为了强调其“嵌入”的特点，也常常把单片机成为嵌入式控制器EMCU。

单片机按其用途分为通用型和专用型两大类。

通用型单片机具有比较丰富的内部资源，性能全面且适应性强，能覆盖多种应用需求。

用户可以根据需要设计成各种不同应用的控制系统，即通用单片机有一个再设计的过程。

通过用户的进一步设计才能组建成一个以通用单片机芯片为核心再配以其它外围电路的应用控制系统。

单片机的优点是体积小，重量轻，抗干扰能力强，对环境要求不高，价格低廉，可靠性高，灵活性好，开发较容易。

1.2 单片机的应用领域单片机广泛应用于仪器仪表、家用电器、医用设备、航空航天、专用设备的智能化管理及过程控制等领域，大致可分为如下几个范畴：一、在智能仪器仪表的应用单片机具有体积小、功耗低、控制功能强、扩展灵活、微型化和使用方便等优点，广泛应用于仪器仪表中，结合不同类型的传感器，可实现诸如电压、功率、频率、湿度、温度、流量、速度、厚度、角度、长度、硬度、元素、压力等物理量的测量。

MC74ACT273DW中文资料

Octal D FlipĆFlopThe MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip- flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.•Ideal Buffer for MOS Microprocessor or Memory •Eight Edge-Triggered D Flip-Flops •Buffered Common Clock•Buffered, Asynchronous Master Reset•See MC74AC377 for Clock Enable Version•See MC74AC373 for Transparent Latch Version •See MC74AC374 for 3-State Version •Outputs Source/Sink 24 mA•′ACT273 Has TTL Compatible Inputs192018171615142134567V CC 1381291110Q 7D 7D 6Q 6Q 5D 5D 4Q 4CP MRQ 0D 0D 1Q 1Q2D 2D 3Q 3GNDPIN NAMES D 0–D 7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q 7Data Outputsassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.。

HD74LS253FP资料

Hitachi CodeJEDECEIAJWeight (reference value)DP-16 Conforms Conforms 1.07 gHitachi Code JEDEC EIAJWeight (reference value)FP-16DA —Conforms 0.24 g*Dimension including the plating thicknessBase material dimension° – 8°Hitachi CodeJEDECEIAJWeight (reference value)FP-16DNConformsConforms0.15 gUnit: mm*Dimension including the plating thickness Base material dimension° – 8°元器件交易网Cautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.Hitachi Asia Pte. Ltd.16 Collyer Quay #20-00Hitachi TowerSingapore 049318Tel: 535-2100Fax: 535-1533URLNorthAmerica : http:/Europe : /hel/ecg Asia (Singapore): .sg/grp3/sicd/index.htm Asia (Taiwan): /E/Product/SICD_Frame.htm Asia (HongKong): /eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.Taipei Branch Office3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105)Tel: <886> (2) 2718-3666Fax: <886> (2) 2718-8180Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components)7/F., North Tower, World Finance Centre,Harbour City, Canton Road, Tsim Sha Tsui,Kowloon, Hong Kong Tel: <852> (2) 735 9218Fax: <852> (2) 730 0281 Telex: 40815 HITEC HXHitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 778322Hitachi Europe GmbHElectronic components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:。

HD74LS375FPEL中文资料

Hitachi CodeJEDECEIAJWeight (reference value)DP-16 Conforms Conforms 1.07 gHitachi Code JEDEC EIAJWeight (reference value)FP-16DA —Conforms 0.24 g*Dimension including the plating thicknessBase material dimension° – 8°Hitachi CodeJEDECEIAJWeight (reference value)FP-16DNConformsConforms0.15 gUnit: mm*Dimension including the plating thickness Base material dimension° – 8°元器件交易网Cautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.Hitachi Asia Pte. Ltd.16 Collyer Quay #20-00Hitachi TowerSingapore 049318Tel: 535-2100Fax: 535-1533URLNorthAmerica : http:/Europe : /hel/ecg Asia (Singapore): .sg/grp3/sicd/index.htm Asia (Taiwan): /E/Product/SICD_Frame.htm Asia (HongKong): /eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.Taipei Branch Office3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105)Tel: <886> (2) 2718-3666Fax: <886> (2) 2718-8180Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components)7/F., North Tower, World Finance Centre,Harbour City, Canton Road, Tsim Sha Tsui,Kowloon, Hong Kong Tel: <852> (2) 735 9218Fax: <852> (2) 730 0281 Telex: 40815 HITEC HXHitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 778322Hitachi Europe GmbHElectronic components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:。

SN74LS273N中文资料

元器件交易网IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1998, Texas Instruments Incorporated。

74LVQ273MTR中文资料

1/13July 2004sHIGH SPEED:f MAX = 150 MHz (TYP .) at V CC = 3.3 V s COMPATIBLE WITH TTL OUTPUTS sLOW POWER DISSIPATION:I CC = 4 µA (MAX.) at T A =25°C sLOW NOISE:V OLP = 0.4V (TYP .) at V CC = 3.3Vs75Ω TRANSMISSION LINE DRIVING CAPABILITYsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 12mA (MIN) at V CC = 3.0 Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 3.6V (1.2V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273sIMPROVED LATCH-UP IMMUNITYDESCRIPTIONThe 74LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metalwiring C 2MOS technology. It is ideal for low power and low noise 3.3V applications.Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the CLOCK pulse.When the CLEAR input is held low, the Q outputs are held low independently of the other inputs.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74LVQ273OCTAL D-TYPE FLIP FLOP WITH CLEARFigure 1: Pin Connection And IEC Logic SymbolsTable 1: Order CodesPACKAGE T & R SOP 74LVQ273MTR TSSOP74LVQ273TTR74LVQ2732/13Figure 2: Input And Output Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareFigure 3: Logic DiagramThis logic diagram has not be used to estimate propagation delaysPIN No SYMBOL NAME AND FUNCTION 1CLEAR Asynchronous Master Reset (Active LOW)2, 5, 6, 9, 12, 15, 16,19Q0 to Q7Flip-Flop Outputs 3, 4, 7, 8, 13, 14, 17, 18D0 to D7Data Inputs11CLOCK Clock Input (LOW-to-HIGH Edge Triggered)10GND Ground (0V)20V CCPositive Supply Voltage74LVQ2733/13Table 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not impliedTable 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.2V to 3.6V 2) V IN from 0.8V to 2VTable 6: DC Specifications1) Maximum test duration 2ms, one output loaded at time2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75ΩSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current± 400mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage (note 1) 2 to 3.6V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time V CC = 3.0V (note 2)0 to 10ns/VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IH High Level Input Voltage3.0 to 3.62.02.02.0V V IL Low Level Input Voltage0.80.80.8V V OHHigh Level Output Voltage3.0I O =-50 µA2.9 2.992.9 2.9VI O =-12 mA 2.582.48 2.48I O =-24 mA2.22.2V OLLow Level Output Voltage3.0I O =50 µA0.0020.10.10.1V I O =12 mA 00.360.440.44I O =24 mA0.550.55I I Input Leakage Current3.6V I = V CC or GND ± 0.1± 1± 1µA I CC Quiescent Supply Current3.6V I = V CC or GND 44040µA I OLD Dynamic Output Current (note 1, 2)3.6V OLD = 0.8 V max 3636mA I OHDV OHD = 2 V min-25-25mA74LVQ2734/13Table 7: Dynamic Switching Characteristics1) Worst case package.2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ILD ), 0V to threshold (V IHD ), f=1MHz.Table 8: AC Electrical Characteristics (C L = 50 pF, R L = 500 Ω, Input t r = t f = 3ns)1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = |t PLHm - t PLHn |, t OSHL = |t PHLm - t PHLn |)2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V OLP Dynamic Low Voltage Quiet Output (note 1, 2) 3.3C L = 50 pF0.40.8V V OLV -0.8-0.5V IHDDynamic High Voltage Input (note 1, 3) 3.32VV ILDDynamic Low Voltage Input (note 1, 3)3.30.8VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t PLH t PHL Propagation DelayTime CK to Q 2.77.312.014.016.0ns 3.3(*) 6.09.010.512.0t PHL Propagation Delay Time CLR to Q 2.79.815.518.021.0ns 3.3(*)8.612.514.516.5t W CLEAR Pulse Width2.7 5.0 2.5 5.0 5.0ns3.3(*)4.0 2.2 4.0 4.0t W CLOCK Pulse Width2.7 5.0 2.0 5.0 5.0ns3.3(*)4.0 1.6 4.0 4.0t s Setup Time D to CK, HIGH or LOW2.74.0-0.4 4.05.0ns 3.3(*)3.0-0.3 3.04.0t h Hold Time D to CK, HIGH or LOW2.73.00.4 3.0 3.5ns 3.3(*) 2.00.3 2.0 2.5t REM Recovery TimeCLEAR to CLOCK2.7 4.0-0.1 4.0 4.5ns3.3(*)3.00.0 3.0 3.5f MAX Maximum Clock Frequency2.7601505050MHz3.3(*)901907070t OSLH t OSHLOutput To Output Skew Time(note1, 2)2.70.5 1.0 1.0 1.0ns3.3(*)0.51.0 1.01.074LVQ2735/13Table 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per Flip Flop)Figure 4: Test CircuitC L = 50pF or equivalent (includes jig and probe capacitance)R L = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 3.35pF C PDPower Dissipation Capacitance (note 1)3.3f IN= 10MHz30pF74LVQ273Figure 5: Waveform - Propagation Delays, Setup And Hold Times Clock Pulse Width (f=1MHz; 50% duty cycle)Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)6/1374LVQ273 Figure 7: Waveform - Recovery Time, Clear Pulse Width (f=1MHz; 50% duty cycle)7/1374LVQ2738/13DIM.mm.inchMIN.TYP MAX.MIN.TYP.MAX.A 2.35 2.650.0930.104 A10.10.300.0040.012 B0.330.510.0130.020 C0.230.320.0090.013 D12.6013.000.4960.512 E7.47.60.2910.299 e 1.270.050H10.0010.650.3940.419 h0.250.750.0100.030 L0.4 1.270.0160.050 k0°8°0°8°ddd0.1000.004SO-20 MECHANICAL DATA0016022D74LVQ2739/13DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 6.4 6.5 6.60.2520.2560.260E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP20 MECHANICAL DATAcEbA2AE1D1PIN 1 IDENTIFICATIONA1LK e0087225C74LVQ273Tape & Reel SO-20 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T30.4 1.197 Ao10.8110.4250.433 Bo13.213.40.5200.528 Ko 3.1 3.30.1220.130 Po 3.9 4.10.1530.161 P11.912.10.4680.47610/1374LVQ273 Tape & Reel TSSOP20 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T22.40.882Ao 6.870.2680.276Bo 6.97.10.2720.280Ko 1.7 1.90.0670.075Po 3.9 4.10.1530.161P11.912.10.4680.47611/1374LVQ273Table 10: Revision HistoryDate Revision Description of Changes 29-Jul-20045Ordering Codes Revision - pag. 1.12/1374LVQ273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America13/13。

74ABT273CMSA中文资料

© 1999 Fairchild Semiconductor Corporation DS011549January 1993Revised November 199974ABT273 Octal D-Type Flip-Flop74ABT273Octal D-Type Flip-FlopGeneral DescriptionThe ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi-tion, is transferred to the corresponding flip-flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.Featuress Eight edge-triggered D-type flip-flops s Buffered common clocks Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE versions Output sink capability of 64 mA, source capability of 32mA s Guaranteed latchup protections High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capabilitys Disable time less than enable time to avoid bus conten-tionOrdering Code:Device also available in Tape and Reel. Specify by appending suffix letter “X ” to the ordering code.Connection Diagram Pin DescriptionsOrder Number Package NumberPackage Description74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT273CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT273CMSA MSA2020-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide74ABT273CMTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names DescriptionD 0–D 7Data InputsMR Master Reset (Active LOW)CP Clock Pulse Input (Active Rising Edge)Q 0–Q 7Data Outputs 274A B T 273Truth TableH= HIGH Voltage Level steady stateh = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady stateI = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial= LOW-to-HIGH clock transitionLogic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Operating ModeInputs Output MRCP D n Q n Reset (Clear)L XX L Load “1”H h H Load “0”HlL74ABT273Absolute Maximum Ratings (Note 1)Recommended Operating ConditionsNote 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.Note 2: Either voltage limit or current limit is sufficient to protect inputs.DC Electrical CharacteristicsNote 3: Guaranteed but not tested.Note 4: For 8 bits toggling, I CCD < 0.5 mA/MHz.Storage Temperature−65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2)−0.5V to +7.0V Input Current (Note 2)−30 mA to +5.0 mAVoltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +4.75V in the HIGH State −0.5V to V CC Current Applied to Output in LOW State (Max)twice the rated I OL (mA)DC Latchup Source Current −500 mA(Across Comm Operating Range)Over Voltage LatchupV CC + 4.5VFree Air Ambient Temperature −40°C to +85°C Supply Voltage+4.5V to +5.5VMinimum Input Edge Rate (∆V/∆t)Data Input 50 mV/ns Enable Input20 mV/ns Symbol ParameterMin TypMaxUnits V CCConditionsV IH Input HIGH Voltage 2.0V Recognized HIGH Signal V IL Input LOW Voltage 0.8V Recognized LOW Signal V CD Input Clamp Diode Voltage −1.2V Min I IN = −18 mA V OH Output HIGH Voltage 2.5V Min I OH = −3 mA 2.0I OH = −32 mA V OL Output LOW Voltage 0.55V Min I OL = 64 mA I IH Input HIGH Current 1µA Max V IN = 2.7V (Note 3)1V IN = V CC I BVI Input HIGH Current 7µA Max V IN = 7.0V Breakdown Test I IL Input LOW Current −1µA Max V IN = 0.5V (Note 3)−1V IN = 0.0V V ID Input Leakage Test 4.75V 0.0I ID = 1.9 µAAll Other Pins Grounded I OS Output Short-Circuit Current −100−275mA Max V OUT = 0.0V I CEX Output HIGH Leakage Current 50µA Max V OUT = V CC I CCH Power Supply Current 50µA Max All Outputs HIGH I CCL Power Supply Current 30mA Max All Outputs LOW I CCTMaximum I CC /InputOutputs Enabled1.5mAMax V I = V CC − 2.1VData Input V I = V CC − 2.1V All Others at V CC or GNDI CCDDynamic I CCNo Load0.3mA/MaxOutputs Open (Note 4)MHzOne Bit Toggling, 50% Duty Cycle 474A B T 273AC Electrical Characteristics(SSOIC package)AC Operating RequirementsCapacitance(SOIC package)Note 5: C OUT is measured at frequency f = 1 MHz, per MIL-STD-833, Method 3012.SymbolParameterT A = +25°CT A = −55°C to +125°C T A = −40°C to +85°C UnitsV CC = +5.0V V CC = 4.5V to 5.5VV CC = 4.5V to 5.5VC L = 50 pFC L = 50 pF C L = 50 pF MinTyp MaxMin MaxMin Maxf MAX Maximum Clock Frequency 150200150150 MHz t PLH Propagation Delay 2.0 6.0 1.07.0 2.0 6.0ns t PHL CP to O n2.8 6.8 1.07.5 2.8 6.8t PHLPropagation Delay 2.57.4 1.08.2 2.57.4ns MR to O nSymbolParameterT A = +25°CT A = −55°C to +125°C T A = −40°C to +85°C UnitsV CC = +5.0V V CC = 4.5V to 5.5VV CC = 4.5V to 5.5VC L = 50 pF C L = 50 pF C L = 50 pF MinMaxMin MaxMin Maxt S (H)Setup Time, HIGH 2.0 2.0 2.0ns t S (L)or LOW D n to CP 2.5 2.5 2.5t H (H)Hold Time, HIGH 1.2 1.4 1.2ns t H (L)or LOW D n to CP 1.2 1.4 1.2t W (H)Pulse Width, CP , 3.3 3.3 3.3ns t W (L)HIGH or LOW 3.3 3.3 3.3t W (L)Master Reset Pulse 3.3 3.3 3.3ns Width, LOW t RECRecovery Time 2.02.02.0ns MR to CPSymbol ParameterTyp Units Conditions T A = 25°CC INInput Capacitance 5pF V CC = 0V C OUT (Note 5)Output Capacitance9pFV CC = 5.0V 74ABT273AC Loading*Includes jig and probe capacitanceFIGURE 1. Standard AC Test LoadFIGURE 2. V M= 1.5VInput Pulse RequirementsFIGURE 3. Test Input Signal RequirementsAC WaveformsFIGURE 4. Propagation Delay,Pulse Width WaveformsFIGURE 5. 3-STATE Output HIGHand LOW Enable and Disable TimesFIGURE 6. Propagation Delay Waveforms forInverting and Non-Inverting FunctionsFIGURE 7. Setup Time, Hold Timeand Recovery Time WaveformsAmplitude Rep. Rate t W t r t f3.0V 1 MHz500 ns 2.5 ns 2.5 ns 674A B T 273Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide BodyPackage Number M20B 74ABT273Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 874A B T 273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm WidePackage Number MSA20974ABT273 Octal D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

M74HCT273中文资料

元器件交易网
M54HCT273 M74HCT273
OCTAL D TYPE FLIP FLOP WITH CLEAR
. . . . . . .
HIGH SPEED fMAX = 80 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS273
X: Don’t Care
INPUTS CLOCK X
D X L H X
OUTPUS QA L L H Qn
FUNCTION CLEAR
NO CHANGE
LOGIC DIAGRAM
2/10
元器件交易网
M54/M74HCT273
ABSOLUTE MAXIMUM RATINGS
VOL
Low Level Output Voltage
4.5
II ICC ∆ICC
Input Leakage Current Quiescent Supply Current Additional worst case supply current
5.5 5.5 5.5
4/10
元器件交易网

74LS27中文资料

元器件交易网Hitachi CodeJEDECEIAJWeight (reference value)DP-14ConformsConforms0.97 gUnit: mm元器件交易网Hitachi CodeJEDECEIAJWeight (reference value)FP-14DA —Conforms 0.23 g*Dimension including the plating thickness Base material dimension° – 8°Hitachi CodeJEDEC EIAJWeight (reference value)FP-14DN Conforms Conforms 0.13 g° – 8°*Pd platingCautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.Hitachi Asia Pte. Ltd.16 Collyer Quay #20-00Hitachi TowerSingapore 049318Tel: 535-2100Fax: 535-1533URLNorthAmerica : http:/Europe : /hel/ecg Asia (Singapore): .sg/grp3/sicd/index.htm Asia (Taiwan): /E/Product/SICD_Frame.htm Asia (HongKong): /eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.Taipei Branch Office3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105)Tel: <886> (2) 2718-3666Fax: <886> (2) 2718-8180Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components)7/F., North Tower, World Finance Centre,Harbour City, Canton Road, Tsim Sha Tsui,Kowloon, Hong Kong Tel: <852> (2) 735 9218Fax: <852> (2) 730 0281 Telex: 40815 HITEC HXHitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 778322Hitachi Europe GmbHElectronic components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:。

HD74LS32P中文资料

HD74LS32Quadruple 2-input Positive OR GateREJ03D0405–0200Rev.2.00Feb.18.2005 Features• Ordering InformationPart Name Package Type Package Code(Previous Code)PackageAbbreviationTaping Abbreviation(Quantity)HD74LS32P DILP-14pin PRDP0014AB-B(DP-14AV)P —HD74LS32FPEL SOP-14 pin (JEITA) PRSP0014DF-B(FP-14DAV)FP EL (2,000 pcs/reel)Note: Please consult the sales office for the above package availability. Pin ArrangementCircuit Schematic (1/4)Absolute Maximum RatingsUnit Item SymbolRatingsSupply voltage V CC 7 V Input voltage V IN 7 V Power dissipation P T 400mW Storage temperature Tstg –65 to +150 °CNote: Voltage value, unless otherwise noted, are with respect to network ground terminal.Recommended Operating ConditionsUnitMaxItem SymbolMinTypSupply voltage V CC 4.75 5.00 5.25 VI OH — — –400 µAOutput currentI OL — — 8 mA°C7525–20Operating temperature ToprElectrical Characteristics(Ta = –20 to +75 °C)ItemSymbol min. typ.* max. Unit Condition V IH 2.0 — — V Input voltageV IL — — 0.8 V V OH 2.7 — — V V CC = 4.75 V, V IH = 2 V, I OH = –400 µA— — 0.5 I OL = 8 mAOutput voltageV OL— — 0.4 V I OL = 4 mAV CC = 4.75 V, V IL = 0.8 V I IH — — 20 µA V CC = 5.25 V, V I = 2.7 V I IL — — –0.4 mA V CC = 5.25 V, V I = 0.4 VInput current I I — — 0.1 mA V CC = 5.25 V, V I = 7 V Short-circuit outputcurrent I OS –20— –100 mA V CC = 5.25 V I CCH — 3.1 6.2 mA V CC = 5.25 VSupply currentI CCL — 4.9 9.8 mA V CC = 5.25 VInput clamp voltage V IK — — –1.5 V V CC = 4.75 V, I IN = –18 mA Note: * V CC = 5 V, Ta = 25°CSwitching Characteristics(V CC = 5 V, Ta = 25°C)Item Symbol min. typ. max. Unit Conditiont PLH — 14 22 nsPropagation delay time t PHL — 14 22 ns C L = 15 pF, R L = 2 k ΩNote: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D0005-0100)".Package Dimensions RENESAS SALES OFFICESRefer to "/en/network" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900Renesas Technology Hong Kong Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong KongTel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999Renesas Technology (Shanghai) Co., Ltd.Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, ChinaTel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632Tel: <65> 6213-0200, Fax: <65> 6278-8001。

74AC273中文注释资料

动态输出电流 (注意1、2)
低电平输出电压
II Input Leakage Current
ICC Quiescent Supply Current
3.0
VO = 0.1 V or
4.5
VCC - 0.1 V
1.5 0.9
0.9
2.25 1.35
1.35
5.5
2.75 1.65
1.65
3.0
IO=-50 µA 2.9 2.99
2.1 1.5
2.1
4.5
VCC - 0.1 V
3.15 2.25
3.15
输入漏电流
5.5
3.85 2.75
3.85
静供应当前的
VIL Low Level Input Voltage
低电平输入电压
VOH High Level Output Voltage
高水平的输出电压
VOL Low Level Output Voltage
10
GND
20
VCC
符号名称和功能 1明确Asyncronous主重置(活性低) 2、5、6、9、12、15、16日19 个q0 a7触发器Outpus 3、4、7、8、13、14、17、18 D0 D7数据输入 11个时钟时钟输入,由低向高跳变边沿触发) 0接地接地(0 v) 20 VCC积极的电源电压
voltage.
independentely举行的其他
输入。所有的输入和输出
都配备对静电放电保护电
路,使他们2千伏ESD免疫和
瞬态过剩电压。
PIN CONNECTION AND IEC LOGIC SYMBOLS
销连接和IEC逻辑符号

HD74LS240P中文资料

HD74LS240Octal Buffers / Line Drivers / Line Receivers(inverted three-state outputs)REJ03D0459–0200Rev.2.00Feb.18.2005 Features• Ordering InformationPart Name Package Type Package Code(Previous Code)PackageAbbreviationTaping Abbreviation(Quantity)HD74LS240P DILP-20pin PRDP0020AC-B(DP-20NEV)P —HD74LS240FPEL SOP-20 pin (JEITA) PRSP0020DD-B(FP-20DAV)FP EL (2,000 pcs/reel)HD74LS240RPEL SOP-20 pin (JEDEC) PRSP0020DC-A(FP-20DBV)RP EL (1,000 pcs/reel)Note: Please consult the sales office for the above package availability. Pin ArrangementFunction TableInputs OutputG A YH X ZL H LL L HNote: H; high level, L; low level, X; irrelevant, Z; off (high-impedance) state of a 3-state outputBlock Diagram (1/2)Absolute Maximum RatingsUnitRatingsItem SymbolSupply voltage V CC 7 VInput voltage V IN 7 VPower dissipation P T 400 mWStorage temperature Tstg –65 to +150 °CNote: Voltage value, unless otherwise noted, are with respect to network ground terminal.Recommended Operating ConditionsMaxUnitMinItem SymbolTypSupply voltage V CC 4.75 5.00 5.25 VI OH — — –15 mAOutput currentI OL — — 24 mA°C75Operating temperature Topr–2025Electrical Characteristics(Ta = –20 to +75 °C)ItemSymbol min. typ.* max. Unit Condition V IH 2.0 — — VInput voltageV IL — — 0.8 V Hysteresis V T + – V T –0.2 0.4 — V V CC = 4.75 V2.4 — — V IL = 0.8 V, I OH = – 3 mA V OH 2.0 — — VV IL = 0.5 V, I OH = – 15 mA V CC = 4.75V, V IH = 2 V— — 0.4 I OL = 12 mA Output voltageV OL — — 0.5 VI OL = 24 mA V CC = 4.75 V, V IH = 2 V,V IL = 0.8 V I OZH — — 20 µA V O = 2.7 V Off-state output currentI OZL — — –20 µA V O = 0.4 VV CC = 5.25 V, V IH = 2 V, V IL = 0.8 V I IH — — 20 µA V CC = 5.25 V, V I = 2.7 V I IL — — –0.2 mA V CC = 5.25 V, V I = 0.4 VInput current I I —— 0.1 mA V CC = 5.25 V, V I = 7 V Short-circuit outputcurrentI OS –40— –225 mA V CC = 5.25 V Outputs high— 13 23Outputs low— 26 44Supply current**All outputsdisabledI CC— 29 50mA V CC = 5.25 V Input clamp voltage V IK — — –1.5 V V CC = 4.75 V, I IN = –18 mA Notes: * V CC = 5 V, Ta = 25°C ** I CC is measured with all outputs open.Switching Characteristics(V CC = 5 V, Ta = 25°C)Item Symbol min. typ. max. Unit Conditiont PLH — 9 14Propagation delay time t PHL — 12 18nst ZL — 20 30 nsOutput enable timet ZH — 15 23 ns C L = 45 pF, R L = 667 Ωt LZ — 15 25 nsOutput disable time t HZ — 10 18 ns C L = 5 pF, R L = 667 ΩNote: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D0005-0100)".Package Dimensions RENESAS SALES OFFICESRefer to "/en/network" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900Renesas Technology Hong Kong Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong KongTel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999Renesas Technology (Shanghai) Co., Ltd.Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, ChinaTel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632Tel: <65> 6213-0200, Fax: <65> 6278-8001。

74VHC273NX资料

© 2003 Fairchild Semiconductor Corporation DS011670April 1994Revised May 200374VHC273 Octal D-Type Flip-Flop74VHC273Octal D-Type Flip-FlopGeneral DescriptionThe VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technol-ogy. It achieves the high speed operation similar to equiva-lent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is trans-ferred to the corresponding flip-flop’s Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input.An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply volt-age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir-cuit prevents device destruction due to mismatched supply and input voltages.Featuress High Speed: f MAX = 165 MHz (typ) at V CC = 5V s Low power dissipation: I CC = 4 µA (max) at T A = 25°C s High noise immunity: V NIH = V NIL = 28% V CC (min)s Power down protection is provided on all inputs s Low noise: V OLP = 0.9V (max)s Pin and function compatible with 74HC273s Leadless DQFN PackageOrdering Code:Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Order Number Package Number Package Description74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74VHC273BQ (Preliminary)MLP020B (Preliminary)20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm74VHC273MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC273NN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 274V H C 273Logic SymbolsIEEE/IECPin DescriptionsFunction TableH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial= LOW-to-HIGH TransitionConnection DiagramsPin Assignments for PDIP, SOIC, SOP , and TSSOPPad Assignments for DQFN(Top Through View)Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Pin NamesDescriptionD 0–D 7Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q 7Data OutputsOperating Mode InputsOutputsMR CP D n Q n Reset (Clear)L XX L Load '1'H H H Load '0'HLL74VHC273Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 2)Note 1: Absolute Maximum Ratings are values beyond which the devicemay be damaged or have its useful life impaired. The databook specifica-tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari-ables. Fairchild does not recommend operation outside databook specifica-tions.Note 2: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsNoise CharacteristicsNote 3: Parameter guaranteed by design.Supply Voltage (V CC )−0.5V to +7.0V DC Input Voltage (V IN )−0.5V to +7.0V DC Output Voltage (V OUT )−0.5V to V CC + 0.5VInput Diode Current (I IK )−20 mA Output Diode Current (I OK )±20 mA DC Output Current (I OUT )±25 mA DC V CC /GND Current (I CC )±75 mAStorage Temperature (T STG )−65°C to +150°CLead Temperature (T L )(Soldering, 10 seconds)260°CSupply Voltage (V CC ) 2.0V to +5.5V Input Voltage (V IN )0V to +5.5VOutput Voltage (V OUT )0V to V CCOperating Temperature (T OPR )−40°C to +85°C Input Rise and Fall Time (t r , t f )V CC = 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V V CC = 5.0V ± 0.5V0 ns/V ∼ 20 ns/VSymbol ParameterV CC T A = 25°C T A = −40°C to +85°C Units Conditions(V)Min TypMaxMin MaxV IH HIGH Level Input 2.0 1.50 1.50V Voltage3.0 − 5.50.7 V CC0.7 V CCV IL LOW Level Input 2.00.500.50VVoltage3.0 − 5.50.3 V CC0.3 V CC V OHHIGH Level Output 2.0 1.9 2.0 1.9VV IN = V IH I OH = −50 µAVoltage3.0 2.9 3.0 2.9or V IL4.5 4.4 4.54.43.0 2.58 2.48VI OH = −4 mA 4.53.943.80I OH = −8 mAV OLLOW Level Output 2.00.00.10.1V V IN = V IH I OL = 50 µAVoltage3.00.00.10.1or V IL4.50.00.10.13.00.360.44V I OL = 4 mA 4.50.360.44I OL = 8 mAI IN Input Leakage Current 0 − 5.5±0.1±1.0µA V IN = 5.5V or GND I CCQuiescent Supply Current5.54.040.0µAV IN = V CC or GND Symbol ParameterV CC T A = 25°CUnits Conditions (V)Typ Limits V OLP Quiet Output Maximum Dynamic V OL 5.00.60.9V C L = 50 pF (Note 3)V OLV Quiet Output Minimum Dynamic V OL5.0−0.6−0.9V C L = 50 pF (Note 3)V IHD Minimum HIGH Level Dynamic Input Voltage 5.0 3.5V C L = 50 pF (Note 3)V ILD Maximum LOW Level Dynamic Input Voltage5.01.5VC L = 50 pF(Note 3) 474V H C 273AC Electrical CharacteristicsNote 4: Parameter guaranteed by design t OSLH = |t PLH max − t PLH min|; t OSHL = |t PHL max − t PHL min|.Note 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: I CC (opr.) = C PD * V CC * f IN + I CC /8 (per F/F). The total C PD when n pieces of the Flip-Flop operates can be calculated by the equation: C PD (total) = 22 + 9n.AC Operating RequirementsNote 6: V CC is 3.3 ± 0.3V or 5.0 ± 0.5VSymbol ParameterV CC T A = 25°C T A = −40°C to +85°C Units Conditions(V)Min Typ MaxMin Maxf MAXMaximum Clock 3.3 ± 0.37512065MHz C L = 15 pF Frequency507545C L = 50 pF 5.0 ± 0.5120165100MHz C L = 15 pF 8011070C L = 50 pF t PLH Propagation Delay 3.3 ± 0.38.713.6 1.016.0ns C L = 15 pF t PHLTime (CK - Q)11.217.1 1.019.5C L = 50 pF 5.0 ± 0.55.89.0 1.010.5ns C L = 15 pF 7.311.0 1.012.5C L = 50 pF t PHLPropagation Delay 3.3 ± 0.38.913.6 1.016.0ns C L = 15 pF Time (MR - Q)11.417.1 1.019.5C L = 50 pF 5.0 ± 0.55.28.5 1.010.0ns C L = 15 pF6.710.5 1.012.0C L = 50 pFt OSLH Output to 3.3 ± 0.3 1.5 1.5ns (Note 4)C L = 50 pF t OSHL Output Skew 5.0 ± 0.51.01.0C L = 50 pFC IN Input Capacitance 4.010.010.0pF V CC = Open C PDPower Dissipation 31pF(Note 5)CapacitanceSymbol ParameterV CC (V)(Note 6)T A = 25°C T A = −40°C to +85°CUnitsTypGuaranteed Minimum t W (L)Minimum Pulse Width (CK)3.3 5.5 6.5nst W (H) 5.0 5.0 5.0t W (L)Minimum Pulse Width (MR) 3.3 5.0 6.0ns 5.0 5.0 5.0t S Minimum Setup Time 3.3 5.5 6.5ns 5.0 4.5 4.5t H Minimum Hold Time3.3 1.0 1.0ns5.01.0 1.0t RECMinimum Removal Time (MR)3.3 2.5 2.5ns5.02.02.074VHC273Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 674V H C 273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D74VHC273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mmPackage Number MLP020B(Preliminary) 874V H C 273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20974VHC273 Octal D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

HD74LV273A中文资料

0
—
—
5
current
µA
VI or VO = 0 V to 5.5 V
Input
CIN
3.3
—
2
—
pF
VI = VCC or GND
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Setup time
Symbol fmax
tPHL
tPLH / tPHL tPHL tPLH / tPHL tSU
Min Typ 120 205
80 160 — 4.7
— 4.8 — 6.0 — 6.2 4.5 —
Max Min — 100
— 70 8.5 1.0
9.0 1.0 10.5 1.0 11.0 1.0 — 4.5
CL = 50 pF ns
ns ns
FROM (Iபைடு நூலகம்put)
TO (Output)
CLR
Q
CLK
Q
CLR
Q
CLK
Q
Data
CLR inactive
CLR L CLK H or L
6
HD74LV273A
Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Function Table
Inputs
CLR
CLK
D
Output Q
L
X
X
L
H
↑

74ACT273TTR中文资料

1/11April 2001sHIGH SPEED:f MAX = 190MHz (TYP.) at V CC = 5V sLOW POWER DISSIPATION:I CC = 4 µA (MAX.) at T A =25°CsCOMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN.), V IL = 0.8V (MAX.)s50Ω TRANSMISSION LINE DRIVING CAPABILITYsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 4.5V to 5.5VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273sIMPROVED LATCH-UP IMMUNITYDESCRIPTIONThe 74ACT273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. Information signals applied to D inputs are transfered to the Q output on the positive-going edge of the clock pulse.When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74ACT273OCTAL D-TYPE FLIP FLOP WITH CLEARPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & R DIP 74ACT273B SOP 74ACT273M74ACT273MTR TSSOP74ACT273TTR74ACT2732/11INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLELOGIC DIAGRAMThis logic diagram has not be used to estimate propagation delaysPIN No SYMBOL NAME AND FUNCTION 1CLEAR Asyncronous Master Reset (Active LOW)2, 5, 6, 9, 12, 15, 16,19Q0 to Q7Flip-Flop Outputs 3, 4, 7, 8, 13, 14, 17, 18D0 to D7Data Inputs11CLOCK Clock Input (LOW-to-HIGH Edge Triggered)10GND Ground (0V)20V CCPositive Supply Voltage74ACT2733/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.RECOMMENDED OPERATING CONDITIONS1) V IN from 0.8V to 2.0VSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current± 400mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 4.5 to 5.5V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time V CC = 4.5 to 5.5V (note 1)8ns/V74ACT2734/11DC SPECIFICATIONS1) Maximum test duration 2ms, one output loaded at time2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50ΩAC ELECTRICAL CHARACTERISTICS (C L = 50 pF, R L = 500 Ω, Input t r = t f = 3ns)(*) Voltage range is 5.0V ± 0.5VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IH High Level Input Voltage4.5V O = 0.1 V or V CC -0.1V 2.0 1.5 2.0 2.0V5.5 2.01.52.02.0V IL Low Level Input Voltage4.5V O = 0.1 V or V CC -0.1V 1.50.80.80.85.5 1.50.80.80.8VV OHHigh Level Output Voltage4.5I O =-50 µA 4.4 4.49 4.4 4.45.5I O =-50 µA 5.4 5.495.4 5.44.5I O =-24 mA 3.86 3.76 3.7V5.5I O =-24 mA 4.864.764.7V OLLow Level Output Voltage4.5I O =50 µA 0.0010.10.10.15.5I O =50 µA 0.0010.10.10.14.5I O =24 mA 0.360.440.55.5I O =24 mA 0.360.440.5I I Input Leakage Cur-rent5.5V I = V CC or GND ± 0.1± 1± 1µA I CCT Max I CC /Input 5.5V I = V CC - 2.1V 0.61.5 1.6mA I CC Quiescent Supply Current5.5V I = V CC or GND 44080µA I OLD Dynamic Output Current (note 1, 2)5.5V OLD = 1.65 V max 7550mA I OHDV OHD = 3.85 V min-75-50mA SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t PLH t PHL Propagation DelayTime CLOCK to Y5.0(*) 1.5 4.08.5 1.59.0 1.59.0ns t PHL Propagation DelayTime CLEAR to Y5.0(*) 1.54.59.0 1.59.5 1.59.5ns t WL CLEAR PulseWidth5.0(*) 2.3 4.0 4.0 4.0ns t W CLOCK PulseWidth5.0(*) 1.8 4.0 4.0 4.0ns t s Setup Time D toCLOCK, HIGH or LOW5.0(*) 1.03.53.53.5ns t h Hold Time D toCLOCK, HIGH or LOW5.0(*)-0.5 1.5 1.5 1.5ns t REMRecovery Time CLEAR to CLOCK5.0(*)0.5 3.03.03.0ns f MAX Maximum CLOCKFrequency5.0(*)125190110110MHz74ACT2735/11CAPACITIVE CHARACTERISTICSPD load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /n (per circuit)TEST CIRCUITC L = 50pF or equivalent (includes jig and probe capacitance)R L = R 1 = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 5.04pF C PDPower Dissipation Capacitance (note 1)5.0f IN = 10MHz32pF74ACT2736/11WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)WAVEFORM 2: PROPAGATION DELAYS(f=1MHz; 50% duty cycle)74ACT2737/11WAVEFORM 3: RECOVERY TIME(f=1MHz; 50% duty cycle)元器件交易网74ACT273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 11/11。

74LVX273MTC中文资料

© 2005 Fairchild Semiconductor Corporation DS011614June 1993Revised April 200574LVX273 Low Voltage Octal D-Type Flip-Flop74LVX273Low Voltage Octal D-Type Flip-FlopGeneral DescriptionThe LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi-tion, is transferred to the corresponding flip-flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.Featuress Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applicationss Guaranteed simultaneous switching noise level and dynamic threshold performanceOrdering Code:Devices also available in T ape and Reel. Specify by appending letter suffix “X ” to the ordering code.Pb-Free package per JEDEC J-STD-020B.Logic Symbols IEEE/IECPin DescriptionsConnection DiagramTruth TableH HIGH Voltage Level X ImmaterialL LOW Voltage LevelLOW-to-HIGH TransitionOrder Number Package NumberPackage Description74LVX273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVX273MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names DescriptionD 0–D 7Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q 7Data OutputsOperating ModeInputs Outputs MR CP D n Q n Reset (Clear)L XX L Load '1'H H H Load '0'HLL 274L V X 273Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.74LVX273Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 2)Note 1: The “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions ” table will define the conditions for actual device operation.Note 2: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsNoise Characteristics (Note 3)Note 3: Input t r t f 3nsSupply Voltage (V CC ) 0.5V to 7.0VDC Input Diode Current (I IK )V I 0.5V 20 mA DC Input Voltage (V I )0.5V to 7VDC Output Diode Current (I OK )V O 0.5V 20 mA V O V CC 0.5V 20 mADC Output Voltage (V O ) 0.5V to V CC 0.5VDC Output Source or Sink Current (I O )r 25 mA DC V CC or Ground Current (I CC or I GND )r 75 mAStorage Temperature (T STG ) 65q C to 150q CPower Dissipation180 mWSupply Voltage (V CC ) 2.0V to 3.6V Input Voltage (V I )0V to 5.5V Output Voltage (V O )0V to V CCOperating Temperature (T A ) 40q C to 85q C Input Rise and Fall Time ('t/'V)0 ns/V to 100 ns/VSymbol ParameterV CC T A 25q CT A 40q C to 85q C UnitsConditionsMin TypMaxMin MaxV IHHIGH Level 2.0 1.5 1.5Input Voltage3.0 2.0 2.0V3.6 2.42.4V ILLOW Level 2.00.50.5Input Voltage3.00.80.8V 3.60.80.8V OHHIGH Level 2.0 1.9 2.0 1.9V IN V IH or V IL I OH 50 P AOutput Voltage3.0 2.9 3.0 2.9VI OH 50 P A3.0 2.582.48I OH 4 mAV OLLOW Level 2.00.00.10.1V IN V IH or V IL I OL 50 P AOutput Voltage3.00.00.10.1V I OL 50 P A 3.00.360.44I OL 4 mAI OZ 3-STATE Output 3.6r 0.25r 2.5P AV IN V IH or V IL Off-State Current V OUT V CC or GND I IN Input Leakage Current 3.6r 0.1r 1.0P A V IN 5.5V or GND I CCQuiescent Supply Current3.64.040.0P AV IN V CC or GNDSymbol ParameterV CC T A 25q C Units C L (pF)(V)Typ Limit V OLP Quiet Output Maximum Dynamic V OL 3.30.50.8V 50V OLV Quiet Output Minimum Dynamic V OL3.3 0.50.8V 50V IHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0V 50V ILDMaximum LOW Level Dynamic Input Voltage3.30.8V50 474L V X 273AC Electrical CharacteristicsNote 4: Parameter guaranteed by design. t OSLH |t PLHm t PLHn |, t OSHL |t PHLm t PHLn |CapacitanceNote 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Symbol ParameterV CC T A 25q CT A 40q C to 85q C UnitsC L (pF)(V)MinTyp Max Min Max t PLH Propagation 2.79.016.9 1.020.5ns 15t PHLDelay Time 11.520.0 1.024.050CP to Q n3.3 r 0.37.111.0 1.013.0159.614.5 1.016.550t PHLPropagation Delay 2.79.317.8 1.020.5ns 15MR to Q n11.821.1 1.024.0503.3 r 0.37.311.5 1.013.5159.815.01.017.050t S Setup Time 2.78.09.5ns D n to CP 3.3 r 0.3 5.5 6.5t H Hold Time 2.7 1.0 1.0ns D n to CP 3.3 r 0.3 1.0 1.0t REC Removal Time 2.7 4.0 4.0ns MR to CP 3.3 r 0.3 2.5 2.5t W Clock Pulse 2.78.09.5ns Width 3.3 r 0.3 5.5 6.5t W MR Pulse 2.77.58.5nsWidth 3.3 r 0.3 5.0 6.0f MAXMaximum 2.75511045MHz15Clock 45604050Frequency3.3 r 0.395150801560905050t OSLH Output to Output 2.7 1.5 1.5ns 50t OSHLSkew (Note 4)3.3 1.51.5Symbol ParameterT A 25q CT A 40q C to 85q C Units MinTyp Max MinMax C IN Input Capacitance 41010pF C OUT Output Capacitance 6pF C PDPower Dissipation 31pFCapacitance (Note 5) 74LVX273Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 674L V X 273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D74LVX273 Low Voltage Octal D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.。

HD74LS273P中文资料

HD74LS273Octal D-type Positive-edge-triggered Flip-Flops (with Clear)REJ03D0473–0300Rev.3.00 Jul.15.2005The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a direct clear input.Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.When the clock input is at either the high or low level, the D input signal has no effect at the output.Features• Ordering InformationPart NamePackage TypePackage Code (Previous Code) PackageAbbreviationTaping Abbreviation (Quantity)HD74LS273P DILP-20 pin PRDP0020AC-B (DP-20NEV) P — HD74LS273FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV)FPEL (2,000 pcs/reel) HD74LS273RPEL SOP-20 pin (JEDEC)PRSP0020DC-A(FP-20DBV)RPEL (1,000 pcs/reel)Note: Please consult the sales office for the above package availability.Pin ArrangementFunction TableInputs Output Clear Clock D QL X X LH ↑ H HH ↑ L LH L X Q0Notes: H; high level, L; low level, X; irrelevant↑; transition from low to high levelQ0; level of Q before the indicated steady-state input conditions were established.Block DiagramAbsolute Maximum RatingsUnitRatingsItem SymbolSupply voltage V CC 7 VInput voltage V IN 7 VPower dissipation P T 400 mWStorage temperature Tstg –65 to +150 °CNote: Voltage value, unless otherwise noted, are with respect to network ground terminal.Recommended Operating ConditionsMaxTypUnitMinItem SymbolSupply voltage V CC 4.75 5.00 5.25 VI OH — — –400 µAOutput currentI OL — — 8 mA°C75Operating temperature Topr25–20Clock frequency ƒclock 0 — 30 MHzClock pulse width t w (clock) 20 — — nsClear pulse width t w (clear) 20 — — nsData setup time t su (data) 20↑ — — nsClear (inactive-state) setup time t su (clear) 25↑ — — nsData hold time t h (data)5↑ — — nsElectrical Characteristics(Ta = –20 to +75 °C)Item Symbol min. typ.* max. UnitConditionV IH 2.0 — — VInput voltageV IL — — 0.8 VV OH 2.7 — — VV CC = 4.75 V, V IH = 2 V, V IL = 0.8 V,I OH = –400 µA— — 0.5 I OL = 8 mA Output voltageV OL — — 0.4 VI OL = 4 mA V CC = 4.75 V, V IH = 2 V,V IL = 0.8 VI IH — 20 µA V CC = 5.25 V, V I = 2.7 V I IL — –0.4 mA V CC = 5.25 V, V I = 0.4 VInput currentI I —0.1 mA V CC = 5.25 V, V I = 7 V Short-circuit output currentI OS –20 — –100 mA V CC = 5.25 V Supply currentI CC ** — 17 27 mA V CC = 5.25 V Input clamp voltage VIK — — –1.5 V V CC = 4.75 V, I IN = –18 mANotes: * V CC = 5 V, Ta = 25°C ** With all outputs open and 4.5 V applied to all data and clear inputs, I CC is measured after a momentaryground, then 4.5 V is applied to clock.Switching Characteristics(V CC = 5 V, Ta = 25°C)Item Symbol Inputs min. typ. max. Unit ConditionMaximum clock frequency ƒmax Clock 30 40 — MHzt PHL Clear — 18 27t PLH — 17 27Propagation delay time t PHL Clock— 18 27 ns C L = 15 pF, R L = 2 k ΩTesting MethodTest CircuitWaveforms 1Waveforms 2Package Dimensions RENESAS SALES OFFICESRefer to "/en/network" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900Renesas Technology Hong Kong Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong KongTel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999Renesas Technology (Shanghai) Co., Ltd.Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, ChinaTel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632Tel: <65> 6213-0200, Fax: <65> 6278-8001Renesas Technology Korea Co., Ltd.Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, KoreaTel: <82> 2-796-3115, Fax: <82> 2-796-2145Renesas Technology Malaysia Sdn. Bhd.Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, MalaysiaTel: <603> 7955-9390, Fax: <603> 7955-9510。

74VHC273_07资料

74VHC273 Octal D-Type Flip-Flop元器件交易网74VHC273 Octal D-Type Flip-FlopConnection DiagramsPin Assignments for PDIP, SOIC, SOP, and TSSOPPad Assignments for DQFN(Top Through View)Pin DescriptionsLogic SymbolsIEEE/IECFunction TableH = HIGH Voltage LevelL = LOW Voltage Level X = Immaterial= LOW-to-HIGH TransitionPin NamesDescriptionD 0 –D 7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0 –Q 7Data OutputsOperating ModeInputs OutputsMRCPD nQ nReset (Clear)L XX L Load ‘1’H H H Load ‘0’HLL元器件交易网74VHC273 Octal D-Type Flip-FlopLogic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Figure 1.元器件交易网74VHC273 Octal D-Type Flip-FlopAbsolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.Recommended Operating Conditions (1)The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Note:1.Unused inputs must be held HIGH or LOW. They may not float.Symbol ParameterRatingV CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5VI IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±75mAT STG Storage Temperature–65°C to +150°CT LLead Temperature (Soldering, 10 seconds)260°CSymbol ParameterRatingV CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CCT OPR Operating Temperature –40°C to +85°C t r , t fInput Rise and Fall Time, V CC = 3.3V ± 0.3VV CC =5.0V ± 0.5V0ns/V ∼ 100ns/V 0ns/V ∼20ns/V元器件交易网74VHC273 Octal D-Type Flip-FlopDC Electrical CharacteristicsNoise CharacteristicsNote:2.Parameter guaranteed by design.SymbolParameterV CC (V)Conditions T A =Units25°C–40°C to +85°CMin.Typ.Max.Min.Max. V IH HIGH Level Input Voltage2.0 1.50 1.50V3.0–5.50.7 x V CC0.7 x V CCV IL LOW Level Input Voltage2.00.500.50V3.0–5.50.3 x V CC0.3 x V CCV OHHIGH Level Output Voltage2.0V IN = V IH or V ILI OH = –50µA 1.9 2.0 1.9V 3.0 2.9 3.0 2.94.5 4.4 4.54.43.0I OH = –4mA 2.58 2.484.5I OH = –8mA3.943.80V OLLOW Level Output Voltage2.0V IN = V IH or V ILI OL = 50µA 0.00.10.1V3.00.00.10.14.50.00.10.13.0I OL = 4mA 0.360.444.5I OL = 8mA0.360.44I IN Input Leakage Current 0–5.5V IN = 5.5V or GND ±0.1±1.0µA I CCQuiescent Supply Current5.5V IN = V CC or GND4.040.0µASymbolParameterV CC (V)ConditionsT A = 25°CUnitsTyp.LimitsV OLP (2) Quiet Output Maximum Dynamic V OL5.0C L = 50pF 0.60.9V V OLV (2) Quiet Output Minimum Dynamic V OL5.0C L = 50pF –0.6–0.9V V IHD (2) Minimum HIGH Level Dynamic Input Voltage 5.0C L = 50pF 3.5V VILD (2)Maximum LOW Level Dynamic Input Voltage5.0C L = 50pF1.5V元器件交易网74VHC273 Octal D-Type Flip-FlopAC Electrical CharacteristicsNotes:3.Parameter guaranteed by design t OSLH = |t PLH max – t PLH min|; t OSHL = |t PHL max – t PHL min|.4.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation:I CC (opr.) = C PD • V CC • f IN + I CC / 8 (per F/F). The total C PD when n pieces of the Flip-Flop operates can be calculated by the equation: C PD (total) = 22 + 9n.AC Operating RequirementsNote:5.V CC is 3.3 ± 0.3V or 5.0 ± 0.5VSymbolParameterV CC (V)ConditionsT A = 25°CT A = –40°C to +85°C UnitsMin.Typ.Max.Min.Max.f MAXMaximum Clock Frequency3.3 ± 0.3C L = 15pF 7512065MHzC L = 50pF 5075455.0 ± 0.5C L = 15pF 120165100MHzC L = 50pF 8011070t PLH , t PHLPropagation Delay Time (CK – Q)3.3 ± 0.3C L = 15pF 8.713.6 1.016.0ns C L = 50pF 11.217.1 1.019.55.0 ± 0.5C L = 15pF 5.89.0 1.010.5ns C L = 50pF 7.311.0 1.012.5t PHLPropagation Delay Time (MR – Q)3.3 ± 0.3C L = 15pF 8.913.6 1.016.0ns C L = 50pF 11.417.1 1.019.55.0 ± 0.5C L = 15pF 5.28.5 1.010.0ns C L = 50pF6.710.5 1.012.0t OSLH , t OSHL Output to Output Skew3.3 ± 0.3(3)C L = 50pF 1.5 1.5ns 5.0 ± 0.5C L = 50pF1.01.0C IN Input Capacitance V CC = Open4.010.010.0pF C PDPower Dissipation Capacitance(4)31pF SymbolParameterV CC (V)(5)T A = 25°CT A = –40°C to +85°CUnitsTyp.Guaranteed Minimumt W (L), t W (H)Minimum Pulse Width (CK) 3.3 5.5 6.5ns 5.0 5.0 5.0t W (L)Minimum Pulse Width (MR) 3.3 5.0 6.0ns 5.0 5.0 5.0t S Minimum Setup Time 3.3 5.5 6.5ns 5.0 4.5 4.5t H Minimum Hold Time3.3 1.0 1.0ns 5.0 1.0 1.0t RECMinimum Removal Time (MR)3.3 2.5 2.5ns5.02.02.0Figure 2.Tape Size A B C D N W1W212mm13.0(330)0.059(1.50)0.512(13.00)0.795(20.20)7.008(178)0.488(12.4)0.724(18.4)Figure 3.Figure 4. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20BFigure 6. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mmPackage Number MLP020B (Preliminary)74VHC273 Octal D-Type Flip-Flop The Power Franchise™TinyBoost。

74LS系列芯片引脚图资料大全

74系列芯片引脚图资料大全作者:佚名来源:本站原创点击数:57276 更新时间：2007年07月26日【字体：大中小】为了方便大家我收集了下列74系列芯片的引脚图资料，如还有需要请上电子论坛/b bs/反相器驱动器LS04 LS05 LS06 LS07 LS125 LS240 LS244 LS245与门与非门LS00 LS08 LS10 LS11 LS20 LS21 LS27 LS30 LS38或门或非门与或非门LS02 LS32 LS51 LS64 LS65异或门比较器LS86译码器LS138 LS139寄存器LS74 LS175 LS373反相器:Vcc 6A 6Y 5A 5Y 4A 4Y 六非门 74LS04┌┴—┴—┴—┴—┴—┴—┴┐六非门(OC门) 74LS05_ │14 13 12 11 10 9 8│六非门(OC高压输出) 74LS06 Y = A ）││ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1Y 2A 2Y 3A 3Y GND驱动器:Vcc 6A 6Y 5A 5Y 4A 4Y┌┴—┴—┴—┴—┴—┴—┴┐│14 13 12 11 10 9 8│Y = A ）│六驱动器(OC高压输出) 74LS07 │ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1Y 2A 2Y 3A 3Y GNDVcc -4C 4A 4Y -3C 3A 3Y┌┴—┴—┴—┴—┴—┴—┴┐_ │14 13 12 11 10 9 8│Y =A+C ）│四总线三态门74LS125 │ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘-1C 1A 1Y -2C 2A 2Y GNDVcc -G B1 B2 B3 B4 B8 B6 B7 B8┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8位总线驱动器74LS245│20 19 18 17 16 15 14 13 12 11│）│ DIR=1 A=>B│ 1 2 3 4 5 6 7 8 9 10│ DIR=0 B=>A└┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘DIR A1 A2 A3 A4 A5 A6 A7 A8 GND页首非门,驱动器与门,与非门或门,或非门异或门,比较器译码器寄存器正逻辑与门,与非门:Vcc 4B 4A 4Y 3B 3A 3Y┌┴—┴—┴—┴—┴—┴—┴┐│14 13 12 11 10 9 8│Y = AB ）│ 2输入四正与门74LS08│1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1B 1Y 2A 2B 2Y GNDVcc 4B 4A 4Y 3B 3A 3Y┌┴—┴—┴—┴—┴—┴—┴┐__ │14 13 12 11 10 9 8│Y = AB ）│ 2输入四正与非门74LS00│ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1B 1Y 2A 2B 2Y GNDVcc 1C 1Y 3C 3B 3A 3Y┌┴—┴—┴—┴—┴—┴—┴┐___ │14 13 12 11 10 9 8│Y = ABC ）│ 3输入三正与非门74LS10│ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1B 2A 2B 2C 2Y GNDVcc H G Y┌┴—┴—┴—┴—┴—┴—┴┐│14 13 12 11 10 9 8│）│ 8输入与非门74LS30│ 1 2 3 4 5 6 7│ ________└┬—┬—┬—┬—┬—┬—┬┘ Y = ABCDEFGHA B C D E F GND页首非门,驱动器与门,与非门或门,或非门异或门,比较器译码器寄存器正逻辑或门,或非门:Vcc 4B 4A 4Y 3B 3A 3Y┌┴—┴—┴—┴—┴—┴—┴┐ 2输入四或门74LS32│14 13 12 11 10 9 8│）│ Y = A+B│ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1A 1B 1Y 2A 2B 2Y GNDVcc 4Y 4B 4A 3Y 3B 3A┌┴—┴—┴—┴—┴—┴—┴┐ 2输入四或非门74LS02│14 13 12 11 10 9 8│___）│Y = A+B│ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1Y 1A 1B 2Y 2A 2B GNDVcc 2Y 2B 2A 2D 2E 1F┌┴—┴—┴—┴—┴—┴—┴┐双与或非门74S51│14 13 12 11 10 9 8│_____）│ 2Y = AB+DE│ 1 2 3 4 5 6 7│_______└┬—┬—┬—┬—┬—┬—┬┘ 1Y = ABC+DEF1Y 1A 1B 1C 1D 1E GNDVcc D C B K J Y┌┴—┴—┴—┴—┴—┴—┴┐ 4-2-3-2与或非门74S64 74S65(OC门)│14 13 12 11 10 9 8│ ______________）│ Y = ABCD+EF+GHI+JK│ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘A E F G H I GND页首非门,驱动器与门,与非门或门,或非门异或门,比较器译码器寄存器2输入四异或门74LS86Vcc 4B 4A 4Y 3Y 3B 3A┌┴—┴—┴—┴—┴—┴—┴┐│14 13 12 11 10 9 8│）│ _ _│ 1 2 3 4 5 6 7│ Y=AB+AB└┬—┬—┬—┬—┬—┬—┬┘1A 1B 1Y 2Y 2A 2B GND8*2输入比较器74LS688_Vcc Y B8 A8 B7 A7 B6 A6 B5 A5┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8*2输入比较器74LS688│20 19 18 17 16 15 14 13 12 11│）││ 1 2 3 4 5 6 7 8 9 10│└┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘CE A1 B1 A2 B2 A3 B3 A4 B4 GND_Y=A1⊙B1+A2⊙B2+A3⊙B3+A4⊙B4+A5⊙B5+A6⊙B6+A7⊙B7+A8⊙B8页首非门,驱动器与门,与非门或门,或非门异或门,比较器译码器寄存器3-8译码器74LS138Vcc -Y0 -Y1 -Y2 -Y3 -Y4 -Y5 -Y6 __ _ _ _ __ _ _ __ _ _ __ _┌┴—┴—┴—┴—┴—┴—┴—┴┐ Y0=A B C Y1=A B B Y2=A B C Y3=A B C │16 15 14 13 12 11 10 9 │）│ __ _ _ __ _ __ _ __│ 1 2 3 4 5 6 7 8│ Y4=A B C Y5=A B C Y6=A B C Y7=A B C └┬—┬—┬—┬—┬—┬—┬—┬┘A B C -CS0 -CS1 CS2 -Y7 GND双2-4译码器74LS139Vcc -2G 2A 2B -Y0 -Y1 -Y2 -Y3 __ __ __ __ __ __ __ __┌┴—┴—┴—┴—┴—┴—┴—┴┐ Y0=2A 2B Y1=2A 2B Y2=2A 2B Y3=2A 2B │16 15 14 13 12 11 10 9 │）│ __ __ __ __ __ __ __ __│ 1 2 3 4 5 6 7 8│ Y0=1A 1B Y1=1A 1B Y2=1A 1B Y3=1A 1B └┬—┬—┬—┬—┬—┬—┬—┬┘-1G 1A 1B -Y0 -Y1 -Y2 -Y3 GND8*2输入比较器74LS688_Vcc Y B8 A8 B7 A7 B6 A6 B5 A5┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8*2输入比较器74LS688│20 19 18 17 16 15 14 13 12 11│）││ 1 2 3 4 5 6 7 8 9 10│└┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘CE A1 B1 A2 B2 A3 B3 A4 B4 GND_Y=A1⊙B1+A2⊙B2+A3⊙B3+A4⊙B4+A5⊙B5+A6⊙B6+A7⊙B7+A8⊙B8寄存器:Vcc 2CR 2D 2Ck 2St 2Q -2Q┌┴—┴—┴—┴—┴—┴—┴┐双D触发器74LS74│14 13 12 11 10 9 8 │）││ 1 2 3 4 5 6 7│└┬—┬—┬—┬—┬—┬—┬┘1Cr 1D 1Ck 1St 1Q -1Q GNDVcc 8Q 8D 7D 7Q 6Q 6D 5D 5Q ALE┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8位锁存器74LS373 │20 19 18 17 16 15 14 13 12 11│）││ 1 2 3 4 5 6 7 8 9 10│└┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘-OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND等.下面介绍一下常用的74芯片，以便大家在电路中遇到了查询----------------------------------------------------型号内容----------------------------------------------------74ls00 2输入四与非门74ls01 2输入四与非门(oc)74ls02 2输入四或非门74ls03 2输入四与非门(oc)74ls04 六倒相器74ls05 六倒相器(oc)74ls06 六高压输出反相缓冲器/驱动器(oc,30v) 74ls07 六高压输出缓冲器/驱动器(oc,30v)74ls08 2输入四与门74ls09 2输入四与门(oc)74ls10 3输入三与非门74ls11 3输入三与门74ls12 3输入三与非门(oc)74ls13 4输入双与非门(斯密特触发)74ls14 六倒相器(斯密特触发)74ls15 3输入三与门(oc)74ls16 六高压输出反相缓冲器/驱动器(oc,15v) 74ls17 六高压输出缓冲器/驱动器(oc,15v)74ls18 4输入双与非门(斯密特触发)74ls19 六倒相器(斯密特触发)74ls20 4输入双与非门74ls21 4输入双与门74ls22 4输入双与非门(oc)74ls23 双可扩展的输入或非门74ls24 2输入四与非门(斯密特触发)74ls25 4输入双或非门(有选通)74ls26 2输入四高电平接口与非缓冲器(oc,15v) 74ls27 3输入三或非门74ls28 2输入四或非缓冲器74ls30 8输入与非门74ls31 延迟电路74ls32 2输入四或门74ls33 2输入四或非缓冲器(集电极开路输出) 74ls34 六缓冲器74ls35 六缓冲器(oc)74ls36 2输入四或非门(有选通)74ls37 2输入四与非缓冲器74ls38 2输入四或非缓冲器(集电极开路输出) 74ls39 2输入四或非缓冲器(集电极开路输出) 74ls40 4输入双与非缓冲器74ls41 bcd-十进制计数器74ls42 4线-10线译码器(bcd输入)74ls43 4线-10线译码器(余3码输入)74ls44 4线-10线译码器(余3葛莱码输入)74ls45 bcd-十进制译码器/驱动器74ls46 bcd-七段译码器/驱动器74ls47 bcd-七段译码器/驱动器74ls48 bcd-七段译码器/驱动器74ls49 bcd-七段译码器/驱动器(oc)74ls50 双二路2-2输入与或非门(一门可扩展) 74ls51 双二路2-2输入与或非门74ls51 二路3-3输入,二路2-2输入与或非门74ls52 四路2-3-2-2输入与或门(可扩展)74ls53 四路2-2-2-2输入与或非门(可扩展) 74ls53 四路2-2-3-2输入与或非门(可扩展) 74ls54 四路2-2-2-2输入与或非门74ls54 四路2-3-3-2输入与或非门74ls54 四路2-2-3-2输入与或非门74ls55 二路4-4输入与或非门(可扩展)74ls60 双四输入与扩展74ls61 三3输入与扩展74ls62 四路2-3-3-2输入与或扩展器74ls63 六电流读出接口门74ls64 四路4-2-3-2输入与或非门74ls65 四路4-2-3-2输入与或非门(oc)74ls70 与门输入上升沿jk触发器74ls71 与输入r-s主从触发器74ls72 与门输入主从jk触发器74ls73 双j-k触发器(带清除端)74ls74 正沿触发双d型触发器(带预置端和清除端)74ls75 4位双稳锁存器74ls76 双j-k触发器(带预置端和清除端)74ls77 4位双稳态锁存器74ls78 双j-k触发器(带预置端,公共清除端和公共时钟端) 74ls80 门控全加器74ls81 16位随机存取存储器74ls82 2位二进制全加器(快速进位)74ls83 4位二进制全加器(快速进位)74ls84 16位随机存取存储器74ls85 4位数字比较器74ls86 2输入四异或门74ls87 四位二进制原码/反码/oi单元74ls89 64位读/写存储器74ls90 十进制计数器74ls91 八位移位寄存器74ls92 12分频计数器(2分频和6分频)74ls93 4位二进制计数器74ls94 4位移位寄存器(异步)74ls95 4位移位寄存器(并行io)74ls96 5位移位寄存器74ls97 六位同步二进制比率乘法器74ls100 八位双稳锁存器74ls103 负沿触发双j-k主从触发器(带清除端)74ls106 负沿触发双j-k主从触发器(带预置,清除,时钟) 74ls107 双j-k主从触发器(带清除端)74ls108 双j-k主从触发器(带预置,清除,时钟)74ls109 双j-k触发器(带置位,清除,正触发)74ls110 与门输入j-k主从触发器(带锁定)74ls111 双j-k主从触发器(带数据锁定)74ls112 负沿触发双j-k触发器(带预置端和清除端)74ls113 负沿触发双j-k触发器(带预置端)74ls114 双j-k触发器(带预置端,共清除端和时钟端) 74ls116 双四位锁存器74ls120 双脉冲同步器/驱动器74ls121 单稳态触发器(施密特触发)74ls122 可再触发单稳态多谐振荡器(带清除端)74ls123 可再触发双单稳多谐振荡器74ls125 四总线缓冲门(三态输出)74ls126 四总线缓冲门(三态输出)74ls128 2输入四或非线驱动器74ls131 3-8译码器74ls132 2输入四与非门(斯密特触发)74ls133 13输入端与非门74ls134 12输入端与门(三态输出)74ls135 四异或/异或非门74ls136 2输入四异或门(oc)74ls137 八选1锁存译码器/多路转换器74ls138 3-8线译码器/多路转换器74ls139 双2-4线译码器/多路转换器74ls140 双4输入与非线驱动器74ls141 bcd-十进制译码器/驱动器74ls142 计数器/锁存器/译码器/驱动器74ls145 4-10译码器/驱动器74ls147 10线-4线优先编码器74ls148 8线-3线八进制优先编码器74ls150 16选1数据选择器(反补输出)74ls151 8选1数据选择器(互补输出)74ls152 8选1数据选择器多路开关74ls153 双4选1数据选择器/多路选择器74ls154 4线-16线译码器74ls155 双2-4译码器/分配器(图腾柱输出)74ls156 双2-4译码器/分配器(集电极开路输出) 74ls157 四2选1数据选择器/多路选择器74ls158 四2选1数据选择器(反相输出)74ls160 可预置bcd计数器(异步清除)74ls161 可预置四位二进制计数器(并清除异步) 74ls162 可预置bcd计数器(异步清除)74ls163 可预置四位二进制计数器(并清除异步) 74ls164 8位并行输出串行移位寄存器74ls165 并行输入8位移位寄存器(补码输出)74ls166 8位移位寄存器74ls167 同步十进制比率乘法器74ls168 4位加/减同步计数器(十进制)74ls169 同步二进制可逆计数器74ls170 4*4寄存器堆74ls171 四d触发器(带清除端)74ls172 16位寄存器堆74ls173 4位d型寄存器(带清除端)74ls174 六d触发器74ls175 四d触发器74ls176 十进制可预置计数器74ls177 2-8-16进制可预置计数器74ls178 四位通用移位寄存器74ls179 四位通用移位寄存器74ls180 九位奇偶产生/校验器74ls181 算术逻辑单元/功能发生器74ls182 先行进位发生器74ls183 双保留进位全加器74ls184 bcd-二进制转换器74ls185 二进制-bcd转换器74ls190 同步可逆计数器(bcd,二进制) 74ls191 同步可逆计数器(bcd,二进制) 74ls192 同步可逆计数器(bcd,二进制) 74ls193 同步可逆计数器(bcd,二进制) 74ls194 四位双向通用移位寄存器74ls195 四位通用移位寄存器74ls196 可预置计数器/锁存器74ls197 可预置计数器/锁存器(二进制) 74ls198 八位双向移位寄存器74ls199 八位移位寄存器74ls210 2-5-10进制计数器74ls213 2-n-10可变进制计数器74ls221 双单稳触发器74ls230 八3态总线驱动器74ls231 八3态总线反向驱动器74ls240 八缓冲器/线驱动器/线接收器(反码三态输出) 74ls241 八缓冲器/线驱动器/线接收器(原码三态输出) 74ls242 八缓冲器/线驱动器/线接收器74ls243 4同相三态总线收发器74ls244 八缓冲器/线驱动器/线接收器74ls245 八双向总线收发器74ls246 4线-七段译码/驱动器(30v)74ls247 4线-七段译码/驱动器(15v)74ls248 4线-七段译码/驱动器74ls249 4线-七段译码/驱动器74ls251 8选1数据选择器(三态输出)74ls253 双四选1数据选择器(三态输出)74ls256 双四位可寻址锁存器74ls257 四2选1数据选择器(三态输出)74ls258 四2选1数据选择器(反码三态输出)74ls259 8为可寻址锁存器74ls260 双5输入或非门74ls261 4*2并行二进制乘法器74ls265 四互补输出元件74ls266 2输入四异或非门(oc)74ls270 2048位rom (512位四字节,oc)74ls271 2048位rom (256位八字节,oc)74ls273 八d触发器74ls274 4*4并行二进制乘法器74ls275 七位片式华莱士树乘法器74ls276 四jk触发器74ls278 四位可级联优先寄存器74ls279 四s-r锁存器74ls280 9位奇数/偶数奇偶发生器/较验器74ls28174ls283 4位二进制全加器74ls290 十进制计数器74ls291 32位可编程模74ls293 4位二进制计数器74ls294 16位可编程模74ls295 四位双向通用移位寄存器74ls298 四-2输入多路转换器(带选通)74ls299 八位通用移位寄存器(三态输出)74ls348 8-3线优先编码器(三态输出)74ls352 双四选1数据选择器/多路转换器74ls353 双4-1线数据选择器(三态输出)74ls354 8输入端多路转换器/数据选择器/寄存器,三态补码输出74ls355 8输入端多路转换器/数据选择器/寄存器,三态补码输出74ls356 8输入端多路转换器/数据选择器/寄存器,三态补码输出74ls357 8输入端多路转换器/数据选择器/寄存器,三态补码输出74ls365 6总线驱动器74ls366 六反向三态缓冲器/线驱动器74ls367 六同向三态缓冲器/线驱动器74ls368 六反向三态缓冲器/线驱动器74ls373 八d锁存器74ls374 八d触发器(三态同相)74ls375 4位双稳态锁存器74ls377 带使能的八d触发器74ls378 六d触发器74ls379 四d触发器74ls381 算术逻辑单元/函数发生器74ls382 算术逻辑单元/函数发生器74ls384 8位*1位补码乘法器74ls385 四串行加法器/乘法器74ls386 2输入四异或门74ls390 双十进制计数器74ls391 双四位二进制计数器74ls395 4位通用移位寄存器74ls396 八位存储寄存器74ls398 四2输入端多路开关(双路输出) 74ls399 四-2输入多路转换器(带选通)74ls422 单稳态触发器74ls423 双单稳态触发器74ls440 四3方向总线收发器,集电极开路74ls441 四3方向总线收发器,集电极开路74ls442 四3方向总线收发器,三态输出74ls443 四3方向总线收发器,三态输出74ls444 四3方向总线收发器,三态输出74ls445 bcd-十进制译码器/驱动器,三态输出74ls446 有方向控制的双总线收发器74ls448 四3方向总线收发器,三态输出74ls449 有方向控制的双总线收发器74ls465 八三态线缓冲器74ls466 八三态线反向缓冲器74ls467 八三态线缓冲器74ls468 八三态线反向缓冲器74ls490 双十进制计数器74ls540 八位三态总线缓冲器(反向)74ls541 八位三态总线缓冲器74ls589 有输入锁存的并入串出移位寄存器74ls590 带输出寄存器的8位二进制计数器74ls591 带输出寄存器的8位二进制计数器74ls592 带输出寄存器的8位二进制计数器74ls593 带输出寄存器的8位二进制计数器74ls594 带输出锁存的8位串入并出移位寄存器74ls595 8位输出锁存移位寄存器74ls596 带输出锁存的8位串入并出移位寄存器74ls597 8位输出锁存移位寄存器74ls598 带输入锁存的并入串出移位寄存器74ls599 带输出锁存的8位串入并出移位寄存器74ls604 双8位锁存器74ls605 双8位锁存器74ls606 双8位锁存器74ls607 双8位锁存器74ls620 8位三态总线发送接收器(反相)74ls621 8位总线收发器74ls622 8位总线收发器74ls623 8位总线收发器74ls640 反相总线收发器(三态输出)74ls641 同相8总线收发器,集电极开路74ls642 同相8总线收发器,集电极开路74ls643 8位三态总线发送接收器74ls644 真值反相8总线收发器,集电极开路74ls645 三态同相8总线收发器74ls646 八位总线收发器,寄存器74ls647 八位总线收发器,寄存器74ls648 八位总线收发器,寄存器74ls649 八位总线收发器,寄存器74ls651 三态反相8总线收发器74ls652 三态反相8总线收发器74ls653 反相8总线收发器,集电极开路74ls654 同相8总线收发器,集电极开路74ls668 4位同步加/减十进制计数器74ls669 带先行进位的4位同步二进制可逆计数器74ls670 4*4寄存器堆(三态)74ls671 带输出寄存的四位并入并出移位寄存器74ls672 带输出寄存的四位并入并出移位寄存器74ls673 16位并行输出存储器,16位串入串出移位寄存器74ls674 16位并行输入串行输出移位寄存器74ls681 4位并行二进制累加器74ls682 8位数值比较器(图腾柱输出)74ls683 8位数值比较器(集电极开路)74ls684 8位数值比较器(图腾柱输出)74ls685 8位数值比较器(集电极开路)74ls686 8位数值比较器(图腾柱输出)74ls687 8位数值比较器(集电极开路)74ls688 8位数字比较器(oc输出)74ls689 8位数字比较器74ls690 同步十进制计数器/寄存器(带数选,三态输出,直接清除)74ls691 计数器/寄存器(带多转换,三态输出)74ls692 同步十进制计数器(带预置输入,同步清除)74ls693 计数器/寄存器(带多转换,三态输出)74ls696 同步加/减十进制计数器/寄存器(带数选,三态输出,直接清除) 74ls697 计数器/寄存器(带多转换,三态输出)74ls698 计数器/寄存器(带多转换,三态输出)74ls699 计数器/寄存器(带多转换,三态输出)74ls716 可编程模n十进制计数器74ls718 可编程模n十进制计数器【发表评论】【告诉好友】【收藏此文】【关闭窗口】上一篇：74LS74引脚图(双D触发器)下一篇：DAC0832引脚图及接口电路。