TC4044 datasheet
AT24c04 的datasheet
1Features•Medium-voltage and Standard-voltage Operation –5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•100 kHz (2.7V) and 400 kHz (5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes are Allowed •Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•8-lead PDIP and 8-lead JEDEC SOIC PackagesDescriptionThe AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-trically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential.The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NCNo Connect2AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.Absolute Maximum RatingsOperating Temperature ......................................−55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature .........................................−65°C to +150°C Voltage on Any Pinwith Respect to Ground ........................................−1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08/163256F–SEEPR–10/04The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.The AT24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects.WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown see Table 2.Table 2. Write ProtectNotes:1.This device is not recommended for new designs. Please refer to A T24C08A.2.This device is not recommended for new designs. Please refer to A T24C16A.Memory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,the 8K requires a 10-bit data word address for random word addressing.AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin StatusPart of the Array Protected24C01A 24C0224C0424C08(1)24C16(2)At V CCFull (1K) ArrayFull (2K) ArrayFull (4K) ArrayNormal Read/Write OperationUpper Half (8K) ArrayAt GND Normal Read/Write Operations4AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This parameter is characterized and is not 100% tested.Notes:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T A = −40°C to +125°C, V CC = +2.7V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 2.7 5.5V V CC2Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB2Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)−0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08/163256F–SEEPR–10/04Notes:1.The A T24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on thetopside of the package), guarantees 400 kHz (2.5V , 2.7V).2.This parameter is characterized and is not 100% tested (T A = 25°C).3.This parameter is characterized and is not 100% tested.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 7).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.Table 5. AC CharacteristicsApplicable over recommended operating range from T A = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).Symbol ParameterAT24C01A/02/04/08,2.7VAT24C16, 2.7V AT24C01A/02/04/08/16,5.0V Units Min Max MinMax MinMax f SCL Clock Frequency, SCL 400(1)400400kHz t LOW Clock Pulse Width Low 1.2 1.2 1.2µs t HIGH Clock Pulse Width High 0.60.60.6µst I Noise Suppression Time (2)505050ns t AA Clock Low to Data Out Valid 0.10.90.10.90.10.9µs t BUF Time the bus must be free before a new transmission can start (3) 1.2 1.2 1.2µs t HD.STA Start Hold Time 0.60.60.6µs t SU.STA Start Set-up Time 0.60.60.6µs t HD.DAT Data In Hold Time 000µs t SU.DA T Data In Set-up Time 100100100nst R Inputs Rise Time (3)300300300ns t F Inputs Fall Time (3)300300300ns t SU.STO Stop Set-up Time 0.60.60.6µs t DH Data Out Hold Time 505050nst WRWrite Cycle Time 555ms Endurance5.0V , 25°C1M1M1MWrite Cycles6AT24C01A/02/04/08/163256F–SEEPR–10/04STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.7AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 4. Data ValidityFigure 5. Start and Stop DefinitionFigure 6.Output Acknowledge8AT24C01A/02/04/08/163256F–SEEPR–10/04Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7on page 9).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-9AT24C01A/02/04/08/163256F–SEEPR–10/04ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 10).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 11).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condi-tion (see Figure 12 on page 11).Figure 7.Device Address10AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)Figure 10.Current Address Read11AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read12AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C01A Ordering InformationOrdering Code Package Operation Range A T24C01A-10P A-5.0C A T24C01A-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C01A-10P A-2.7C A T24C01A-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)13AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C02 Ordering InformationOrdering Code Package Operation Range A T24C02-10P A-5.0C A T24C02N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C02-10P A-2.7C A T24C02N-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)14AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C04 Ordering InformationOrdering Code Package Operation Range A T24C04-10P A-5.0C A T24C04N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C04-10P A-2.7C A T24C04N-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)15AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This device is not recommended for new designs. Please refer to A T24C08A.AT24C08(1) Ordering InformationOrdering Code Package Operation Range A T24C08-10P A-5.0C A T24C08N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C08-10P A-2.7C A T24C08N-10SA-2.7C 8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)16AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This device is not recommended for new designs. Please refer to A T24C16A.AT24C16(1) Ordering InformationOrdering Code Package Operation Range A T24C16-10P A-5.0C A T24C16N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C16-10P A-2.7C A T24C16N-10SA-2.7C 8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)17AT24C01A/02/04/08/163256F–SEEPR–10/04Packaging Information8P3 – PDIP18AT24C01A/02/04/08/163256F–SEEPR–10/048S1 – JEDEC SOIC3256F–SEEPR–10/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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TC4405COA;TC4404COA;TC4405CPA;TC4405EOA;TC4404EOA;中文规格书,Datasheet资料
TC4404/TC4405Features:•Independently Programmable Rise and Fall Times•Low Output Impedance – 7Ω Typ.•High Speed t R, t F –<30 nsec with 1000 pF Load •Short Delay Times – <30 nsec•Wide Operating Range:- 4.5V to 18V•Latch-Up Protected: Will Withstand > 500 mA Reverse Current (Either Polarity)•Input Withstands Negative Swings Up to -5VApplications:•Motor Controls•Driving Bipolar Transistors•Driver for Non-overlapping Totem Poles •Reach-Up/Reach-Down DriverDevice Selection Table General Description:The TC4404/TC4405 are CMOS buffer-drivers constructed with complementary MOS outputs, where the drains of the totem-pole output have been left separated so that individual connections can be made to the pull-up and pull-down sections of the output. This allows the insertion of drain-current-limiting resistors in the pull-up and/or pull-down sections, allowing the user to define the rates of rise and fall for a capacitive load; or a reduced output swing, if driving a resistive load, or to limit base current, when driving a bipolar transistor. Minimum rise and fall times, with no resistors, will be less than 30 nsec for a 1000 pF load.For driving MOSFETs in motor-control applications, where slow-ON/fast-OFF operation is desired, these devices are superior to the previously used technique of adding a diode-resistor combination between the driver output and the MOSFET, because they allow accurate control of turn-ON, while maintaining fast turn-OFF and maximum noise immunity for an OFF device. When used to drive bipolar transistors, these drivers maintain the high speeds common to other Microchip drivers. They allow insertion of a base current-limiting resistor, while providing a separate half-output for fast turn-OFF. By proper positioning of the resistor, either npn or pnp transistors can be driven.For driving many loads in low-power regimes, these drivers, because they eliminate shoot-through currents in the output stage, require significantly less power at higher frequencies, and can be helpful in meeting low-power budgets.Part Number Package Temp. RangeTC4404COA8-Pin SOIC0°C to +70°CTC4404CPA8-Pin PDIP0°C to +70°CTC4404EOA8-Pin SOIC-40°C to +85°CTC4404EPA8-Pin PDIP-40°C to +85°CTC4404MJA8-Pin CERDIP-55°C to +125°CTC4405COA8-Pin SOIC0°C to +70°CTC4405CPA8-Pin PDIP0°C to +70°CTC4405EOA8-Pin SOIC-40°C to +85°CTC4405EPA8-Pin PDIP-40°C to +85°CTC4405MJA8-Pin CERDIP-55°C to +125°C1.5A Dual Open-Drain MOSFET Drivers© 2006 Microchip Technology Inc.DS21418C-page 1TC4404/TC4405DS21418C-page 2© 2006 Microchip Technology Inc.Because neither drain in an output is dependent on the other, these devices can also be used as open-drain buffer/drivers where both drains are available in one device, thus minimizing chip count. Unused open drains should be returned to the supply rail that their device sources are connected to (pull-downs to ground, pull-ups to V DD ), to prevent static damage. In addition, in situations where timing resistors or other means of limiting crossover currents are used, like drains may be paralleled for greater current carrying capacity.These devices are built to operate in the most demand-ing electrical environments. They will not latch-up under any conditions within their power and voltage ratings; they are not subject to damage when up to 5V of noise spiking of either polarity occurs on their ground pin; and they can accept, without damage or logic upset, up to 1/2 amp of reverse current (of either polarity) being forced back into their outputs. All terminals are fully protected against up to 2 kV of electrostatic discharge.TC4404/TC44051.0ELECTRICALCHARACTERISTICSAbsolute Maximum Ratings*Supply Voltage.....................................................+22V Power Dissipation (T A≤ 70°C)PDIP........................................................730 mW CERDIP..................................................800 mW SOIC.......................................................470 mW Package Thermal ResistancePDIP RθJ-A.............................................125°C/W PDIP RθJ-C...............................................45°C/W CERDIP RθJ-A........................................150°C/W CERDIP RθJ-C..........................................55°C/W SOIC RθJ-A.............................................155°C/W SOIC RθJ-C...............................................45°C/W Operating Temperature RangeC Version........................................0°C to +70°C E Version......................................-40°C to +85°C M Version...................................-55°C to +125°C Storage Temperature Range..............-65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.TC4404/TC4405 ELECTRICAL SPECIFICATIONSElectrical Characteristics: T A = +25°C, with 4.5V ≤ V DD ≤ 18V, unless otherwise noted.Symbol Parameter Min Typ Max Units Test ConditionsInputV IH Logic 1, High Input Voltage 2.4——VV IL Logic 0, Low Input Voltage——0.8VI IN Input Current-1—1μA0V ≤ V IN ≤ V DDOutputV OH High Output Voltage V DD – 0.025——VV OL Low Output Voltage——0.025VR O Output Resistance—710ΩI OUT = 10 mA, V DD = 18V; Any Drain I PK Peak Output Current (Any Drain)— 1.5—A Duty cycle ≤ 2%, t ≤ 300 μsecI DC Continuous Output Current (Any Drain)——100mAI R Latch-Up Protection (Any Drain)Withstand Reverse Current—>500—mA Duty cycle ≤ 2%, t ≤ 300 μsec Switching Time (Note 1)t R Rise Time—2530nsec Figure3-1, C L = 1000 pFt F Fall Time—2530nsec Figure3-1, C L = 1000 pFt D1Delay Time—1530nsec Figure3-1, C L = 1000 pFt D2Delay Time—3250nsec Figure3-1, C L = 1000 pFPower SupplyI S Power Supply Current————4.50.4mA V IN = 3V (Both Inputs)V IN = 0V (Both Inputs)Note1:Switching times ensured by design.© 2006 Microchip Technology Inc.DS21418C-page 3TC4404/TC4405DS21418C-page 4© 2006 Microchip Technology Inc.TC4404/TC4405 ELECTRICAL SPECIFICATIONS (CONTINUED)Electrical Characteristics: Over operating temperature range with 4.5V ≤ V DD ≤ 18V, unless otherwise noted.Symbol ParameterMin Typ Max Units Test ConditionsV IH Logic 1, High Input Voltage 2.4——V V IL Logic 0, Low Input Voltage ——0.8V I IN Input Current-10—10μA0V ≤ V IN ≤ V DDOutput V OH High Output Voltage V DD – 0.025——V V OL Low Output Voltage ——0.025V R O Output Resistance—912ΩI OUT = 10 mA, V DD = 18V; Any Drain I PK Peak Output Current (Any Drain)— 1.5—A Duty cycle ≤ 2%, t ≤ 300 μsecI DC Continuous Output Current (Any Drain)——100mA I RLatch-Up Protection (Any Drain)Withstand Reverse Current —>500—mADuty cycle ≤ 2%, t ≤ 300 μsec Switching Time (Note 1)t R Rise Time ——40nsec Figure 3-1, C L = 1000 pF t F Fall Time ——40nsec Figure 3-1, C L = 1000 pF t D1Delay Time ——40nsec Figure 3-1, C L = 1000 pF t D2Delay Time——60nsec Figure 3-1, C L = 1000 pF Power SupplyI SPower Supply Current————80.6mAV IN = 3V (Both Inputs)V IN = 0V (Both Inputs)Note 1:Switching times ensured by design.TC4404/TC44052.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table2-1.TABLE 2-1:PIN FUNCTION TABLEPin No.Symbol Description(8-Pin PDIP,SOIC, CERDIP)1V DD Supply input, 4.5V to 18V.2IN A Control input A, TTL/CMOS compatible input.3IN B Control input A, TTL/CMOS compatible input.4GND Ground.5 B BOTTOM Output B, pull-down.6 B TOP Output B, pull-up.7 A BOTTOM Output A, pull-down.8 A TOP Output A, pull-up.© 2006 Microchip Technology Inc.DS21418C-page 5TC4404/TC4405DS21418C-page 6© 2006 Microchip Technology Inc.3.0APPLICATIONS INFORMATION3.1Circuit Layout GuidelinesAvoid long power supply and ground traces (added inductance causes unwanted voltage transients). Use power and ground planes wherever possible.In addition, it is advisable that low ESR bypass capac-itors (4.7 μF or 10 μF tantalum) be placed as close to the driver as possible. The driver should be physically located as close to the device it is driving as possible to minimize the length of the output trace.FIGURE 3-1:Switching Time Test Circuit3.2Typical ApplicationsFIGURE 3-2:Zero Crossover Current Totem-Pole SwitchFIGURE 3-3:Driving Bipolar TransistorsTC4404/TC4405FIGURE 3-4:Servo Motor ControlFIGURE 3-5:Reach-Up and Reach-Down Driving© 2006 Microchip Technology Inc.DS21418C-page 7TC4404/TC44054.0TYPICAL CHARACTERISTICSNote:The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.DS21418C-page 8© 2006 Microchip Technology Inc.TC4404/TC4405 TYPICAL CHARACTERISTICS (CONTINUED)© 2006 Microchip Technology Inc.DS21418C-page 9TC4404/TC44055.0PACKAGING INFORMATION5.1Package Marking InformationPackage marking data not available at this time.DS21418C-page 10© 2006 Microchip Technology Inc.分销商库存信息:MICROCHIPTC4405COA TC4404COA TC4405CPA TC4405EOA TC4404EOA TC4404EPA TC4405COA713TC4404COA713TC4404EOA713 TC4405EOA713TC4405EPA TC4404CPA TC4404MJA TC4405MJA。
TC4423 datasheet
- With Logic ‘1’ Input – 3.5 mA (Max) - With Logic ‘0’ Input – 350 µA (Max) • Low Output Impedance: 3.5Ω (typ) • Latch-Up Protected: Will Withstand 1.5A Reverse Current • Logic Input Will Withstand Negative Swing Up To 5V • ESD Protected: 4 kV • Pin compatible with the TC1426/TC1427/TC1428, TC4426/TC4427/TC4428 and TC4426A/ TC4427A/TC4428A devices. • Space-saving 8-Pin 6x5 DFN Package
(Each Input)
GND
Non-inverting
4.7V TC4423 Dual Inverting TC4424 Dual Non-inverting TC4425 One Inverting, One Non-inverting
Note 1: Unused inputs should be grounded.
16-Pin SOIC (Wide) TC4423 TC4424 TC4425
NC 1 IN A 2 NC 3 GND 4 GND 5 NC 6 IN B 7 NC 8
TC4423 TC4424 TC4425
TP4054中文手册_替代LTC4054
0.8
1.8
4
ms
IPROG
PROG 引脚上拉电流
2.5
μA
3
南京拓微集成电路有限公司
典型性能特征
恒定电流模式下 PROG 引脚 电压与电源电压的关系曲线
PROG 引脚电压与温度的 关系曲线
充电电流与 PROG 引脚电 压的关系曲线
PROG 引脚上拉电流与温度 和电源电压的关系曲线
PROG 引脚电流与 PROG 引脚 电压的关系曲线（上拉电流）
1000V
1000V
R=
PROG
I
, ICHG = R
CHG
PROG
从 BAT 引 脚 输 出 的 充 电 电 流 可 通 过 监 视 PROG 引脚电压随时确定，公式如下：
V
I BAT
=
PROG
R
• 1000
PROG
至设定值的 1/10 时，充电循环被终止。该条
件是通过采用一个内部滤波比较器对 PROG
在电池的充电过程中，由一个内部 N 沟道
MOSFET 将 CHRG 引脚拉至低电平。当充
电循环结束时，一个约 20μA 的弱下拉电流
源被连接至 CHRG 引脚，指示一个“AC 存
在”状态。当 TP4054 检测到一个欠压闭锁
条件时，CHRG 引脚被强制为高阻抗状态。
GND（引脚 2）：地 BAT（引脚 3）：充电电流输出。该引脚向电 池提供充电电流并将最终浮充电压调节至 4.2V。该、引脚的一个精准内部电阻分压器 设定浮充电压，在停机模式中，该内部电阻 分压器断开。 VCC（引脚 4）：正输入电源电压。该引脚向 充电器供电。VCC 的变化范围在 4.25V 至 6.5V 之间，并应通过至少一个 1μF 电容器 进行旁路。当 VCC 降至 BAT 引脚电压的 30mV 以内，TP4054 进入停机模式，从而使
OPA404KU,OPA404KP,OPA404KU 1K,OPA404KU 1KE4,OPA404KUG4,OPA404AG,OPA404BG, 规格书,Datasheet 资料
KP, KU Operating
KP, KU Storage
KP, KU θ Junction-Ambient
KP, KU
IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature
© 1986 Burr-Brown Corporation
PDS-677F
Printed in U.S.A. August 1995
芯天下--/
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted.
®
OPA404
2
芯天下--/
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.
OPA404AG, KP, KU
8
0.5
12
1013 || 1 1014 || 3
±10.5 88 84
+13, –11 100 100
88
100
4
6.4
570
24
35
0.6
1.5
±11.5 +13.2, –13.8
±5
±10
80
1000
±10
±27
±40
±15
±5
±18
9
10
–25
PT4243A;PT4244C;PT4242C;PT4243N;PT4244A;中文规格书,Datasheet资料
Standard Application
Ordering Information
Mechanical Shock
Mechanical Vibration
Weight Flammability
Io
Vin Vo tol Regtemp Regline Regload ∆Votot η
Vr
ttr ∆Vtr Vadj Ilim ƒs UVLO VIH VIL IIL Iin standby Cin Cout
PT Series Suffix (PT1234 x )
Case/Pin Configuration
Order Suffix
Package Code
Vertical Horizontal SMD
N
(EPE)
A
(EPF)
C
(EPG)
(Reference the applicable package code drawing for the dimensions and PC board layout)
Vo ≤ 5.0V Vo = 12V
Vo ≥2.5V
Vin =18V, ∆Vo = –1%
Over Vin range
Referenced to –Vin (pin 3)
pins 1 & 3 connected
Vo ≤ 5.0V Vo = 12V Input–output/input–case Input to output Input to output Over Vin range — Per Bellcore TR-332 50% stress, Ta =40°C, ground benign Per Mil-Std-883D, method 2002.3, 1mS, half-sine, mounted to a fixture Mil-Std-883D, Method 2007.2 20-2000Hz, all case styles soldered to PC — Materials meet UL 94V-0
真空计VGC402403
产品型号 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
参数模式 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 选用 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 参数组 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 基本操作 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
使用说明书
附质量保证书
VGC402
双通道测量和控制仪器
VGC403
三通道测量和控制仪器
tinb07c1-c 2007-11
ch
para
ch
para
1
目录
1
1.1 1.1.1 1.1.2 1.1.3
1.2 1.2.1
1.3
1.4 1.4.1 1.4.2 1.4.3
前言
有效性 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 件号 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 固件版号 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 型号标签 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CD4044
Applications
Y Y Y Y
Multiple bus storage Strobed register Four bits of independent storage with output enable General digital logic
Connection Diagrams
CD4043BM CD4043BC Dual-In-Line and Flat Packages CD4044BM CD4044BC Dual-In-Line and Flat Packages
b 0 64 b1 6 b4 2
VOH
High Level Output Voltage
4 95 9 95 14 95 15 30 40
4 95 9 95 14 95
50 10 15 2 25 45 6 75 15 30 40
4 95 9 95 14 95 15 30 40 35 70 11 0 36 09 24
VOL
lIOl s 1 mA VIL e 0V VIH e VDD VDD e 5 0V VDD e 10V VDD e 15V lIOl s 1 mA VIL e 0V VIH e VDD VDD e 5 0V VDD e 10V VDD e 15V
2 4 95 9 95 14 95
VOH
High Level Output Voltage
b 0 36 b0 9 b2 4 b0 1 b1 0
VIL
Low Level Input Voltage
V V V V V V mA mA mA mA mA mA
VIH
High Level Input Voltage
35 70 11 0 51 13 34
LTC4054datasheet
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.12LTC4054L-4.24054l42i(Note 1)Input Supply Voltage (V CC )....................... –0.3V to 10V PROG............................................. –0.3V to V CC + 0.3V CHRG........................................................ –0.3V to 10V BAT............................................................. –0.3V to 7V BAT Short-Circuit Duration.......................... Continuous BAT Pin Current................................................. 200mA PROG Pin Current................................................1.5mA Maximum Junction Temperature..........................125°C Operating Temperature Range (Note 2)..–40°C to 85°C Storage Temperature Range.................–65°C to 125°C Lead Temperature (Soldering, 10 sec)..................300°CT JMAX = 125°C, θJA = 100°C/W TO 150°C/W DEPENDING ON PC BOARD LAYOUT (NOTE 4)ORDER PART NUMBER S5 PART MARKINGLTC4054LES5-4.2LTAFASYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Supply Voltage q 4.256.5V I CCSupply CurrentCharge Mode (Note 3), R PROG = 1k q 12002000µA Standby Mode (Charge Terminated)q 200500µA Shutdown Mode (R PROG Not Connected,q2550µA V CC < V BAT , or V CC < V UV )V FLOAT Regulated Output (Float) Voltage 0°C ≤ T A ≤ 85°C, I BAT = 40mA 4.158 4.2 4.242V I BATBAT Pin CurrentV CC = 5V, R PROG = 15k, Current Mode q 9.31010.7mA V CC = 5V, R PROG = 1k, Current Mode q 142.5150157.5mA Standby Mode, V BAT = 4.2Vq–2.5–6µA Shutdown Mode (R PROG Not Connected)±1±2µA Sleep Mode, V CC = 0V±1±2µA I TRIKL Trickle Charge Current V BAT < 2.9V, R PROG = 1k (I BAT = 150mA)q 51525mA V TRIKL Trickle Charge Threshold Voltage R PROG = 15k, V BAT Rising 2.8 2.93V V TRHYS Trickle Charge Hysteresis VoltageR PROG = 15k 6080110mV V UV V CC Undervoltage Lockout Threshold Voltage From V CC Low to High q 3.7 3.8 3.92V V UVHYS V CC Undervoltage Lockout Hysteresis Voltage q 150200300mV V MSD Manual Shutdown Threshold Voltage PROG Pin Rising q 1.15 1.21 1.30V PROG Pin Falling q 0.9 1.0 1.1V V ASD V CC – V BAT Lockout Threshold Voltage V CC from Low to High 70100140mV V CC from High to Low53050mV I TERM C/10 Termination Current Threshold R PROG = 15k (I BAT = 10mA) (Note 5)q 0.0850.100.115mA/mA R PROG = 1k (I BAT = 150mA) (Note 5)q 0.0880.100.112mA/mAV PROG PROG Pin VoltageR PROG = 1k, Current Mode q 0.931 1.07V I CHRG CHRG Pin Weak Pull-Down Current V CHRG = 5V 82035µA V CHRG CHRG Pin Output Low Voltage I CHRG = 5mA 0.350.6V ∆V RECHRGRecharge Battery Hysteresis VoltageV FLOAT – V RECHRG100150200mVThe q denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, unless otherwise noted.ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOU U WELECTRICAL CHARACTERISTICSConsult LTC Marketing for parts specified with wider operating temperature ranges.CHRG 1GND 2TOP VIEWS5 PACKAGE5-LEAD PLASTIC TSOT-23BAT 35 PROG4 V CC3LTC4054L-4.24054l42iU U UPI FU CTIO SThe q denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, unless otherwise noted.ELECTRICAL CHARACTERISTICSCHRG (Pin 1): Open-Drain Charge Status Output. When the battery is charging, the CHRG pin is pulled low by an internal N-channel MOSFET. When the charge cycle is completed, a weak pull-down of approximately 20µA is connected to the CHRG pin, indicating an “AC present”condition. When the LTC4054L detects an undervoltage lockout condition, CHRG is forced to a high impedance state.GND (Pin 2): Ground.BAT (Pin 3): Charge Current Output. Provides charge current to the battery and regulates the final float voltage to 4.2V. An internal precision resistor divider from this pin sets this float voltage and is disconnected in shutdown mode.V CC (Pin 4): Positive Input Supply Voltage. Provides power to the charger. V CC can range from 4.25V to 6.5V and should be bypassed with at least a 1µF capacitor.When V CC drops to within 30mV of the BAT pin voltage, theLTC4054L enters shutdown mode, dropping I BAT to less than 2µA.PROG (Pin 5): Charge Current Program, Charge Current Monitor and Shutdown Pin. The charge current is pro-grammed by connecting a 1% resistor, R PROG , to ground.When charging in constant-current mode, this pin servos to 1V. In all modes, the voltage on this pin can be used to measure the charge current using the following formula:I BAT = (V PROG /R PROG ) • 150The PROG pin is also used to shut down the charger.Disconnecting the program resistor from ground allows a 3µA current to pull the PROG pin high. When it reaches the 1.21V shutdown threshold voltage, the charger enters shutdown mode, charging stops and the input supply current drops to 25µA. This pin is also clamped to approximately 2.4V. Driving this pin to voltages beyond the clamp voltage will draw currents as high as 1.5mA.Reconnecting R PROG to ground will return the charger to normal operation.SYMBOL PARAMETERCONDITIONSMINTYP MAXUNITST LIM Junction Temperature in Constant 120°C Temperature Mode R ON Power FET “ON” Resistance 1.5Ω(Between V CC and BAT)t SS Soft-Start TimeI BAT = 0 to I BAT =150V/R PROG 100µs t RECHARGE Recharge Comparator Filter Time V BAT High to Low 0.752 4.5ms t TERM Termination Comparator Filter Time I BAT Falling40010002500µs I PROGPROG Pin Pull-Up Current1.535µANote 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.Note 2: The LTC4054LE-4.2 is guaranteed to meet performance specifica-tions from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 3: Supply current includes PROG pin current (≈1mA) but does not include any current delivered to the battery through the BAT pin.Note 4: See Thermal Considerations.Note 5: I TERM is expressed as a fraction of measured full charge current with indicated PROG resistor.LTC4054L-4.245LTC4054L-4.24054l42iOPERATIOU1Any external sources that hold the PROG pin above 100mV will prevent the LTC4054L fromterminating a charge cycle.The LTC4054L is a single cell lithium-ion battery charger using a constant-current/constant-voltage algorithm. Its ability to control charge currents as low as 10mA make it well-suited for charging low capacity lithium-ion coin cell batteries. The LTC4054L includes an internal P-channel power MOSFET and thermal regulation circuitry. No block-ing diode or external sense resistor is required; thus, the basic charger circuit requires only three external compo-nents. Furthermore, the LTC4054L is capable of operating from a USB power source.Normal Charge CycleThe charge cycle begins when the voltage at the V CC pin rises above the UVLO level and a 1% program resistor is connected from the PROG pin to ground. If the BAT pin is less than 2.9V, the charger enters trickle charge mode. In this mode, the LTC4054L supplies approximately 1/10 the programmed charge current in order to bring the battery voltage up to a safe level for full current charging.When the BAT pin voltage rises above 2.9V, the charger enters constant-current mode, where the programmed charge current is supplied to the battery. When the BAT pin approaches the final float voltage (4.2V), the LTC4054L enters constant-voltage mode and the charge current begins to decrease. When the charge current drops to 1/10 of the programmed value, the charge cycle ends.Programming Charge CurrentThe charge current is programmed using a single resistor from the PROG pin to ground. The battery charge current is 150 times the current out of the PROG pin. The program resistor and the charge current are calculated using the following equations:R V I I VR PROG CHG CHG PROG==150150,The charge current out of the BAT pin can be determinedat any time by monitoring the PROG pin voltage using the following equation:I V R BAT PROGPROG=•150Charge TerminationThe charge cycle is terminated when the charge current falls to 1/10th the programmed value. This condition is detected by using an internal, filtered comparator to monitor the PROG pin. When the PROG pin voltage falls below 100mV 1 for longer than t TERM (typically 1ms),charging is terminated. The charge current is latched off and the LTC4054L enters standby mode, where the input supply current drops to 200µA.While charging, transient loads on the BAT pin can cause the PROG pin to fall below 100mV for short periods of time, even before the DC charge current has dropped to 1/10th the programmed value. The 1ms filter time (t TERM )on the termination comparator ensures that transient loads of this nature do not result in premature charge cycle termination. Once the charge current drops below 1/10th the programmed value for longer than t TERM , the LTC4054L terminates the charge cycle and ceases to provide any current through the BAT pin. In this state, all loads on the BAT pin must be supplied by the battery.The LTC4054L constantly monitors the BAT pin voltage in standby mode. When this voltage drops below the 4.05V recharge threshold (V RECHRG ), another charge cycle be-gins and current is once again supplied to the battery. To manually restart a charge cycle when in standby mode, the input voltage must be removed and reapplied, or the charger must be shut down and restarted by momentarily floating the PROG pin. Figure 1 shows the state diagram of a typical charge cycle.Charge Status Indicator (CHRG)The charge status output has three different states: strong pull-down (~10mA), weak pull-down (~20uA), and high impedance. The strong pull-down state indicates that the LTC4054L is in a charge cycle. Once the charge cycle has terminated, the pin state is determined by undervoltage lockout conditions. A weak pull-down indicates that V CC meets the UVLO conditions and the LTC4054L is ready to charge. High impedance indicates that LTC4054L is in undervoltage lock-out mode: either V CC is within 100mV of the BAT pin voltage or insufficient voltage is applied to6LTC4054L-4.24054l42iOPERATIOUthe V CC pin. A microprocessor can be used to distinguish between these three states—this method is discussed in the Applications Information section.Thermal LimitingAn internal thermal feedback loop reduces the programmed charge current if the die temperature attempts to rise above a preset value of approximately 120°C. This feature protects the LTC4054L from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the LTC4054L. The charge current can be set according to typical (not worst-case) ambient temperature with the assurance that the charger will automatically reduce the current in worst-case conditions. ThinSOT power consid-erations are discussed further in the Applications Informa-tion section.Undervoltage Lockout (UVLO)An internal undervoltage lockout circuit monitors the input voltage and keeps the charger in shutdown mode until V CC rises above the undervoltage lockout threshold. The UVLO circuit has a built-in hysteresis of 200mV. Furthermore, to protect against reverse current in the power MOSFET, theUVLO circuit keeps the charger in shutdown mode if V CC falls to within 30mV of the battery voltage. If the UVLO comparator is tripped, the charger will not come out of shutdown mode until V CC rises 100mV above the battery voltage.Manual ShutdownAt any point in the charge cycle, the LTC4054L can be put into shutdown mode by removing R PROG thus floating the PROG pin. This reduces the battery drain current to less than 2µA and the supply current to less than 50µA. A new charge cycle can be initiated by reconnecting the program resistor.Automatic RechargeOnce the charge cycle is terminated, the LTC4054L con-tinuously monitors the voltage on the BAT pin. A charge cycle restarts when the battery voltage falls below 4.05V (which corresponds to approximately 80% to 90% battery capacity). This ensures that the battery is kept at or near a fully charged condition and eliminates the need for periodic charge cycle initiations. CHRG output enters a strong pull-down state during recharge cycles.7LTC4054L-4.289LTC4054L-4.24054l42iAPPLICATIO S I FOR ATIOW UUU Power DissipationThe conditions that cause the LTC4054L to reduce charge current through thermal feedback can be approximated by considering the power dissipated in the IC. Nearly all of this power dissipation is generated from the internal MOSFET—this is calculated to be approximately:P D = (V CC – V BAT ) • I BATwhere P D is the power dissipated, V CC is the input supply voltage, V BAT is the battery voltage and I BAT is the charge current. The approximate ambient temperature at which the thermal feedback begins to protect the IC is:T A = 120°C – P D θJAT A = 120°C – (V CC – V BAT ) • I BAT • θJAExample: An LTC4054L operating from a 6V wall adapter is programmed to supply 150mA full-scale current to a discharged Li-Ion battery with a voltage of 3.75V. Assum-ing θJA is 200°C/W, the ambient temperature at which the LTC4054L will begin to reduce the charge current is approximately:T A = 120°C – (6V – 3.75V) • (150mA) • 200°C/W T A = 120°C – 0.3375W • 200°C/W = 120°C – 67.5°C T A = 52.5°CThe LTC4054L can be used above 52.5°C, but the charge current will be reduced from 150mA. The approximate current at a given ambient temperature can be approxi-mated by:I C T V V BAT A CC BAT JA=°()120––•θUsing the previous example with an ambient tempera-ture of 60°C, the charge current will be reduced to approximately:I C C V V C W CC AI mABAT BAT =°°()°=°°=12060637520060450133––.•//Moreover, when thermal feedback reduces the charge current, the voltage at the PROG pin is also reduced proportionally as discussed in the Operation section.It is important to remember that LTC4054L applications do not need to be designed for worst-case thermal condi-tions since the IC will automatically reduce power dissipa-tion when the junction temperature reaches approximately 120°C.Thermal ConsiderationsBecause of the small size of the ThinSOT package, it is very important to use a good thermal PC board layout to maximize the available charge current. The thermal path for the heat generated by the IC is from the die to the copper lead frame, through the package leads, (especially the ground lead) to the PC board copper. The PC board copper is the heat sink. The footprint copper pads should be as wide as possible and expand out to larger copper areas to spread and dissipate the heat to the surrounding ambient. Feedthrough vias to inner or backside copper layers are also useful in improving the overall thermal performance of the charger. Other heat sources on the board, not related to the charger, must also be considered when designing a PC board layout because they will affect overall temperature rise and the maximum charge current.LTC4054L-4.2101112LTC4054L-4.2LT/TP 0503 1K • PRINTED IN USA© LINEAR TECHNOLOGY CORPORA TION 20031630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 q FAX: (408) 434-0507 q 。
HCF4046BEY;HCF4046M013TR;中文规格书,Datasheet资料
1/12September 2001sQUIESCENT CURRENT SPECIFIED UP TO 20VsVERY LOW POWER CONSUMPTION : 70µW (TYP .) AT VCO f o = 10kHz, V DD = 5VsOPERATING FREQUENCY RANGE : UP TO 1.4MHz (TYP .) AT V DD = 10VsLOW FREQUENCY DRIFT : 0.04%/°C (typ.) AT V DD = 10VsCHOICE OF TWO PHASE COMPARATORS :1) EXCLUSIVE - OR NETWORK 2) EDGE-CONTROLLED MEMORYNETWORK WITH PHASE-PULSE OUTPUT FOR LOCK INDICATIONs HIGH VCO LINEARITY: <1% (TYP.)sVCO INHIBIT CONTROL FOR ON-OFF KEYING AND ULTRA-LOW STANDBY POWER CONSUMPTIONsSOURCE-FOLLOWER OUTPUT OF VCO CONTROL INPUT (demod. output)sZENER DIODE TO ASSIST SUPPLY REGULATIONs 5V, 10V AND 15V PARAMETRIC RATINGS sINPUT LEAKAGE CURRENTI I = 100nA (MAX) AT V DD = 18V T A = 25°C s 100% TESTED FOR QUIESCENT CURRENT sMEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"DESCRIPTIONThe HCF4046B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor Technology, available in 16-lead dual in-line plastic or ceramic package. The HCF4046B CMOS Micropower Phase-Locked Loop (PLL)consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary.HCF4046BMICROPOWER PHASE-LOCKED LOOPORDER CODESPACKAGE TUBE T & R DIP HCF4046BEY SOPHCF4046BM1HCF4046M013TRHCF4046B2/12VCO SectionThe VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2).Resistor R1 and capacitor C1 determine the frequency range of the VCO and resistor R2enables the VCO to have a frequency offset if required. The high input impedance (1012Ω) of the VCO simplifiers the design of low-pass filters by permitting the designer a wide choice of resistor-to-capacitor ratios. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at terminal 10(DEMODULATED OUTPUT). If this terminal is used, a load resistor (R S ) of 10 K Ω or more should be connected from this terminal to V SS . If unused this terminal should be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. A full CMOS logic swing is available at the output of the VCO and allows direct coupling to CMOS frequency dividers such as the HCF4024B, HCF4018B, HCF4020B, HCF4022B,HCF4029B and HBF4059A. One or more HCF4018B (Presettable Divide-by-N Counter) or HCF4029B (Presettable Up/Down Counter), or HBF4059A (Programmable Divide-by-"N"Counter), together with the HCF4046B (Phase-Locked Loop) can be used to build a micropower low-frequency synthesizer. A logic 0on the INHIBIT input "enables" the VCO and the source follower, while a logic 1 "turns off" both to minimize stand-by power consumption.Phase ComparatorsThe phase-comparator signal input (terminal 14)can be direct-coupled provided the signal swing is within CMOS logic levels [logic "0" ≤ 30% of (V DD -V SS ), logic "1" ≥ 70% of (V DD -V SS )]. For smaller swings the signal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase comparator I is an exclusive-OR network; it operates analagously to an over-driven balanced mixer. To maximize the lock range, the signal-and comparator-input frequencies must have a 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to V DD /2. The low-pass filter connected to the output of phase comparator I supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range ofinput signals on which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2 f C ). The frequency range of input signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (2 f L ). The capture range is ≤ the lock range.With phase comparator I the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the low-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator I enables a PLL system to remain in lock in spite of high amounts of noise in the input signal. One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between 0°and 180°, and is 90° at the center frequency. Fig.1shows the typical, triangular, phase-to-output response characteristic of phase-comparator I.Typical waveforms for a CMOS phase-locked-loop employing phase comparator I in locked condition of fo is shown in fig.2.Phase-comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a three-stage output-circuit comprising p- and n-type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to V DD or down to V SS , respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLL system utilizing this type of comparator. If the signal-input frequency is higher than the comparator-input frequency, the p-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal-input frequency is lower than the comparator-input frequency, the n-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal and comparator-input frequencies are the same, but the signal input lags the comparator input in phase, the n-type output driver is maintained ON for a time corresponding to the phase difference. If the signal and comparator-input frequencies are the same, but the comparator input lags the signal in phase, theHCF4046B3/12p-type output driver is maintained ON for a time corresponding to the phase difference.Subsequently, the capacitor voltage of the low-pass filter connected to this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this stable point both p- and n-type output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Moreover the signal at the "phase pulses" output is a high level which can be used for indicating a locked condition. Thus, for phase comparator II, no phase difference exists betweensignal and comparator input over the full VCO frequency range. Moreover, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the p-and n-type output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator II. Fig.3 shows typical waveforms for a CMOS PLL employing phase comparator II in a locked condition.Figure 1 : Phase-Comparator I Characteristics at Low-Pass Filter Output.Figure 2 : Typical Waveforms for CMOS Phase Locked-Loop Employing Phase Comparator I in Locked Condition of f oHCF4046B4/12Figure 3 : Typical Waveforms for CMOS Phase-locked Loop Employing Phase Comparator II In Locked ConditionINPUT EQUIVALENT CIRCUITPIN DESCRIPTIONPIN No SYMBOL NAME AND FUNCTION1PHASE PULSESPhase Comparator Pulse Output2PHASE COMP I OUT Phase Comparator 1Output3COMPARATOR IN Comparator Input4VCO OUT VCO Output 5INHIBIT Inhibit Input 6, 7C1Capacitors 9VCO IN VCO Input10DEMODULATOR OUTDemodulator Output11R 1 TO V SSResistor R1 Connection 12R 2 TO V SS Resistor R2Connection 13PHASE COMP IIOUT Phase Comparator 2 Output14SIGNAL IN Signal Input 15ZENER Diode Zener8V SSNegative Supply Voltage16V DDPositive Supply VoltageHCF4046B5/12FUNCTIONAL DIAGRAMABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.All voltage values are referred to V SS pin voltage.RECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V DD Supply Voltage -0.5 to +22V V I DC Input Voltage -0.5 to V DD + 0.5V I I DC Input Current± 10mA P D Power Dissipation per Package200mW Power Dissipation per Output Transistor 100mW T op Operating Temperature -55 to +125°C T stgStorage Temperature-65 to +150°CSymbol ParameterValue Unit V DD Supply Voltage 3 to 20V V I Input Voltage0 to V DD V T opOperating Temperature-55 to 125°CHCF4046B6/12DC SPECIFICATIONSThe Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15VSymbolParameterTest ConditionValue UnitV I (V)V O (V)|I O |(µA)V DD (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.VCO SECTION V OH High Level OutputVoltage 0/5<15 4.95 4.95 4.95V0/10<1109.959.959.950/15<11514.9514.9514.95V OLLow Level Output Voltage 5/0<150.050.050.05V10/0<1100.050.050.0515/0<1150.050.050.05I OHOutput Drive Current0/5 2.5<15-1.36-3.2-1.15-1.1mA0/5 4.6<15-0.44-1-0.36-0.360/109.5<110-1.1-2.6-0.9-0.90/1513.5<115-3.0-6.8-2.4-2.4I OLOutput Sink Current0/50.4<150.4410.360.36mA 0/100.5<110 1.1 2.60.90.90/151.5<115 3.06.8 2.42.4I I Input LeakageCurrent0/18Any Input18±10-5±0.1±1±1µAPHASE COMPARATOR SECTIONI DDTotal Device Current Pin 14= OpenPin 5= V DD0/550.050.10.10.1mA0/10100.250.50.50.50/15150.75 1.5 1.5 1.50/20202444Total DeviceCurrent Pin 14= V SS or V DDPin 5= V DD0/550.045150150µA0/10100.0410*******/15150.04206006000/20200.081003000I OHOutput Drive Current 0/5 2.5<15-1.36-3.2-1.15-1.1mA0/54.6<15-0.44-1-0.36-0.360/109.5<110-1.1-2.6-0.9-0.90/1513.5<115-3.0-6.8-2.4-2.4I OLOutput Sink Current 0/50.4<150.4410.360.36mA0/100.5<110 1.1 2.60.90.90/151.5<115 3.0 6.82.4 2.4V IHHigh Level Input Voltage0.5/4.5<15 3.5 3.5 3.5V1/9<1107771.5/13.5<115111111V ILLow Level Input Voltage4.5/0.5<15 1.5 1.5 1.5V 9/1<11033313.5/1.5<115444I I Input Leakage Current0/18Any Input 18±10-5±0.1±1±1µA I OUT High Impedance Leakage Current 0/18Any Input 18±10-4±0.4±12±12µA C IInput CapacitanceAny Input57.5pFHCF4046B7/12ELECTRICAL CHARACTERISTICS (T amb = 25°C)SymbolParameterTest ConditionValue (*)UnitV DD (V)Min.Typ.Max.VCO SECTIONP DOperating Power Dissipation 5f O = 10KHz R1 = 10M ΩR2 = ∞V COIN = V DD /270140µW1080016001530006000f MAXMaximum frequency5R 1 = 10K ΩC1 = 50pF R2 = ∞V COIN = V DD0.30.6ns100.6 1.2150.8 1.65R 1 = 5K Ω C1 = 50pFR2 = ∞V COIN = V DD0.50.8ns101 1.4151.42.4Center Frequency (f O ) and frequency Range f max - f min Programable with external components R 1, R 2, and C 1See Design InformationLinearity5V COIN =2.5V ±0.3R 1 = 10K Ω 1.7%10V COIN =5V ±1R 1 = 100K Ω0.510V COIN =5V ±2.5R 1 = 400K Ω415V COIN =7.5V ±1.5R 1 = 100K Ω0.515V COIN =7.5V ±5R 1 = 1M Ω7TemperatureFrequency Stability (no frequency offset) f min = 05±0.12%/°C 10±0.0415±0.015TemperatureFrequency Stability (frequency offset) f min = 05±0.0910±0.0715±0.03VCO Output Duty Cycle 5, 10, 1550%t TLH t THL VCO OutputTransition Time5100200ns 1050100154080Source Follower Out-put (Demodulated Output): Offset Volt-age V COIN -V DEM 5, 10, 15R S > 10K Ω1.82.5V Source FollowerOutput (Demodulated Output): Linearity 5R S = 100K ΩV COIN =2.5V ±0.30.3%10R S = 300K ΩV COIN =5V ±2.50.715R S = 500K ΩV COIN =7.5V ±50.9V Z Zener Diode Volt-ageI Z = 50 µA 4.455.57.5V R ZZener Dynamic ResistanceI Z = 1 mA40ΩHCF4046B8/12(*) For sine Wave the frequency must be greater than 10KHz for Phase Comparator IIPHASE COMPARATOR SECTION R14Pin 14 (signal in) Input Resistance 512M Ω100.20.4150.10.2AC Coupled Signal Input Sensivity (*) (peak to peak)5f IN = 100KHz sine wave180360mV10330660159001800t PLHPropagation Delay Time High to Low Level Pins 14 to 15225450ns101002001565130t PLHPropagation Delay Time Low to High Level5350700ns1015030015100200t PHZDisable Time High Level to High ImpedancePins 14 to 135225450ns101002001565130t PLZ Disable Time Low Level to High Impedance5285570ns101302601595190t r t fInput Rise or Fall Time Comparator Pin 3550µs101150.3Signal Pin 145500µs102015 2.5t TLH t THL Transition Time5100200ns1050100154080SymbolParameterTest ConditionValue (*)UnitV DD (V)Min.Typ.Max.HCF4046B9/12DESIGN INFORMATION This information is a guide for approximating the value of external components in a Phase-Locked-Loop system. The selected external components must be within the following ranges:5K Ω ≤ R 1, R 2, R S ≤ 1M Ω C 1 ≥ 100pF at V DD ≥ 5V C 1 ≥ 50pF at V DD ≥ 10VFor further information, see(1) F. Gardner, "Phase-Lock Techniques" John Wiley and Sons, New York, 1966(2) G.S. Mosckytz "miniaturized RC filters using phase Lockedloop" BSTJ May 1965分销商库存信息:STMHCF4046BEY HCF4046M013TR。
GC4014资料
微讯VSC8484数据手册：四通道WAN LAN 背板XAUI到SFP+ KR接收器说明书
VSC8484 Datasheet Quad Channel WAN/LAN/Backplane XAUI to SFP+/KRTransceiverMicrosemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email: *************************** ©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.About MicrosemiMicrosemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs andmidspans; as well as custom design capabilities and services. Learn more at .Contents1Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1Revision4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2Revision4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Revision4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4Revision4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6Revision2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32.1Major Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.1Transmit Operation for XAUI to SFI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.2Receive Operation for SFI to XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.3PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.3.1Supported Data Rates and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3.2Rate Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3.3Receiver (Rx) Subsection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3.4Variable Gain Amplifier Input Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3.5Rx Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.6Rx Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.7Rx Data Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3.8Rx Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.9External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.10VScope Input Signal Monitoring Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.11Unity Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.12Link Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.13Transmitter (Tx) Subsection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.14Tx Data Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3.15Tx Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.1610BASE-KR Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.17PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.3.18PMA Linetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.3.19External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3.20Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3.21Reference Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.3.22Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.3.23Synchronous Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.3.24 1.25Gbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.3.25Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3.26Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3.27Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4WAN Interface Sublayer (WIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.4.1Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.4.2Section Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.4.3A1, A2 (Frame Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.4.4Loss of Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.5Loss of Optical Carrier (LOPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.6Severely Errored Frame (SEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.4.7Loss of Frame (LOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.4.9Z0 (Reserved for Section Growth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.10Scrambling/Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.11B1 (Section Error Monitoring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.12E1 (Section Orderwire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.13F1 (Section User Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.14DCC-S (Section Data Communication Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.15Reserved, National, and Unused Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.16Line Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.4.17B2 (Line Error Monitoring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.4.18K1, K2 (APS Channel and Line Remote Defect Identifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.4.19D4 to D12 (Line Data Communications Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.20M0 and M1 (STS-1/N Line Remote Error Indication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.21S1 (Synchronization Messaging) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.22Z1 and Z2 (Reserved for Line Growth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.23E2 (Orderwire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.24SPE Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.25Bit Designations within Payload Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.4.26Pointer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.4.27Pointer Adjustment Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.4.28Pointer Increment/Decrement Majority Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.4.29Pointer Interpretation States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.4.30Valid Pointer Definition for Interpreter State Diagram Transitions . . . . . . . . . . . . . . . . . . . . . . 403.4.31Path Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.4.32J1 (Overhead Octet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.4.33B3 (STS Path Error Monitoring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.4.34C2 (STS Path Signal Label and Path Label Mismatch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.4.35G1 (Remote Path Error Indication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.4.36G1 (Path Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.4.37F2 (Path User Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.38H4 (Multiframe Indicator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.39Z3-Z4 (Reserved for Path Growth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.40N1 (Tandem Connection Maintenance/Path Data Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.41Loss of Code Group Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.42Reading Statistical Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.4.43Defects and Anomalies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.4.44Interrupt Pins and Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.4.45Overhead Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.4.46Transmit Overhead Serial Interface (TOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.4.47Receive Overhead Serial Interface (ROSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.4.48Pattern Generator and Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5Physical Coding Sublayer (64B/66B PCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.5.1Control Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.5.2Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.5.3Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.5.4PCS Standard Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.5.5PCS XGMII BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6Client/Host Interface (XAUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.6.1XGMII Extender Sublayer (PHY XS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.6.2XAUI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.6.3XAUI Receiver Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.6.4XAUI Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.6.5XAUI Code Group Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.6.6XAUI Lane Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.6.710B/8B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.88b/10b Encoder and Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.9XAUI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.10XAUI Transmitter Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.12XAUI Failover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.710GBASE-KR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.7.1Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.7.2Technology Ability Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.7.3Transmitted Nonce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.7.4Role of Firmware during Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.7.5Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.7.6Advertised Ability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.7.7Link Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.7.8Next Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.7.9Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.7.10Coefficient Update Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.7.11Status Report Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.7.12Training Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.7.13Role of Hardware and Firmware during Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.7.14Training Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733.7.15Coefficient Update and Status Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743.7.16BER Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753.7.17Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753.8Loopback and Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.8.1Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.8.2Loopback A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.8.3Loopback B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.8.4Loopback F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.8.5Loopback G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773.8.6Loopback J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773.8.7Loopback K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773.9Low-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783.9.1MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793.9.2Two-Wire Serial (Master) for Loading Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813.9.3Two-Wire Serial Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823.9.4UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833.9.5JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833.10Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843.10.1Firmware Load Mode, EEPROM Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843.10.2Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853.11Loading Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853.11.1EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853.11.2MDIO and Two-Wire Serial Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863.12Microcontroller Activity Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873.13Interrupt Pending Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873.14Multipurpose GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883.15PCS Activity Monitor LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913.16Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .944.1Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944.1.1GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974.2Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724.3EDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2864.3.1Hardware DC Offset Correction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3035.1DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3035.1.1Low-Speed Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3035.1.3MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045.2AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045.2.1Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045.2.2Transmitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3085.2.3Timing and Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3145.2.4Two-Wire Serial (Slave) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3145.2.5MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155.3Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3165.4Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3186Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3206.1Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3206.2Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3206.2.1General Purpose Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216.2.2JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216.2.3Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3226.2.4Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3236.2.5Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3236.2.6Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3246.2.7Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3246.2.8Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3256.2.9Test and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3256.2.10Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3266.2.11XAUI Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3266.2.12Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3297Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3307.1Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3307.2Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3317.3Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3328Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3338.1Sync-E in LAN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3338.2Sync-E in WAN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 9Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335。
VFT4045BP-M34W;中文规格书,Datasheet资料
0.600 (15.24) 0.580 (14.73)
7° REF. 0.350 (8.89) 0.330 (8.38)
1
2 0.191 (4.85) 0.171 (4.35) 7° REF.
0.560 (14.22) 0.530 (13.46)
0.057 (1.45) 0.045 (1.14)
0.110 (2.79) 0.100 (2.54)
0.025 (0.64) 0.015 (0.38)
0.035 (0.89) 0.025 (0.64) 0.205 (5.21) 0.195 (4.95) 0.028 (0.71) 0.020 (0.51)
Document Number: 89456 3 For technical questions within your region: DiodesAmericas@, DiodesAsia@, DiodesEurope@ THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000 /
Case Temperature (°C)
Fig. 1 - Maximum Forward Current Derating Curve
Instantaneous Forward Voltage (V) Fig. 2 - Typical Instantaneous Forward Characteristics
Reverse Voltage (V) Fig. 4 - Typical Junction Capacitance
74HC40104中文资料
Product specification
74HC/HCT40104
FEATURES
• Synchronous parallel or serial operating • 3-state outputs • Output capability: bus driver • ICC category: MSI
74HC/HCT40104 4-bit bidirectional universal shift register; 3-state
Product specification File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the shift-right (DSR) and shift-left (DSL) serial inputs, respectively.
74HC/HCT40104
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver ICC category: MSI
TC4044BP_07中文资料
ns
15
⎯
20
40
CIN
⎯
⎯
5
7.5
pF
4
2007-10-01
元器件交易网
Waveforms for Measurement of Dynamic Characteristics
Waveform 1
TC4044BP/BF/BFN
Waveform 2
5
2007-10-01
Min pulse width (SET, RESET) Input capacitance
Symbol
Test Condition
Min Typ. Max Unit
VDD (V)
5
⎯
70 200
tTLH
⎯
10
⎯
35 100 ns
15
⎯
30
80
5
⎯
70 200
tTHL
⎯
10
⎯
35 100 ns
15
⎯
Operating Ranges (VSS = 0 V) (Note)
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
DC supply voltage Input voltage
VDD VIN
⎯
3
⎯
18
V
⎯
0
⎯
VDD
V
Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VDD or VSS.
TC4426MJA;TC4427MJA;TC4428MJA;中文规格书,Datasheet资料
• Switch-mode Power Supplies • Line Drivers • Pulse Transformer Drive
General Description
The TC4426M/TC4427M/TC4428M are improved versions of the earlier TC426M/TC427M/TC428M family of MOSFET drivers. The TC4426M/TC4427M/ TC4428M devices have matched rise and fall times when charging and discharging the gate of a MOSFET.
Package Types
8-Pin CERDIP TC4426M TC4427M TC4428M
NC 1 IN A 2 GND 3 IN B 4
8 NC 7 OUT A 6 VDD 5 OUT B
NC
OUT A VDD OUT B
NC
OUT A VDD OUT B
TC4426M TC4427M TC4428M
1.5A Dual High-Speed Power MOSFET Drivers
Featuresቤተ መጻሕፍቲ ባይዱ
• High Peak Output Current – 1.5A • Wide Input Supply Voltage Operating Range:
- 4.5V to 18V • High Capacitive Load Drive Capability – 1000 pF
© 2005 Microchip Technology Inc.
IEC TC34标准目录
IEC60682-国际电工委员会IEC(TC34)TC34制定灯及其相关设备的国际标准。
它成立于1948年。
电灯、灯头和灯座、灯的控制装置和灯具是照明装置的所有组成部件，当他们共同工作时，照明装置即能完成它们的照明功能。
T 由TC34和其分委会所进行的标准化工作的目的是确保上述这些部件的安全性、性能可靠性及其互换性。
IEC TC34标准目录TC34灯及其相关设备范围:制定关于下列部件有关技术要求的国际标准:a)灯的启辉器，b)灯头和灯座，c)灯的控制装置，d)灯具，e) 其他技术委员会的项目中没有包括的各种相关设备。
TC34有四个分委会:34A，34B，34C和34D，它们轮流为维护组和工作组进行评价和完善 对新的或现行的标准、建立项目组或根据需要成SC 34A:灯制定关于灯的启辉器技术要求的国际标准。
SC 34B:灯头和灯座灯头的灯座及保证与其接触的互换性和安全性的标准化。
SC 34C:灯的附件制定关于灯的控制装置的技术要求的国际标准。
SC 34D:灯具制定关于灯具的技术规范的国际标准。
全国电光源标准化中心成立于1982年,是全国电光源及其附件标准化制定的 专门机构，为了更好的与国际接轨，1997年成立了全国照明电器标准化技术委员会，秘书处设在我所。
中心和标委会的业务工作直接受国家质量监督检验检疫总局和中国轻工业联合会的领导和管理。
作为国际电工委员会IEC（TC34）的国内技术归口单位，全国照明电器标准化委员会的任务是：1.制定照明电器行业的国家标准、行业标准。
2.制、修订标准的计划并负责组织落实及管理工作。
3.研究和提出本行业的IEC标准草案、修改意见和参加表决。
4.承担本专业国家标准、行业标准的宣讲、解释及技术咨询。
目前中心和标委会归口管理的IEC标准、国家标准和行业标准近300项，涉及灯、灯头、灯座、镇流器、启动器、灯具等照明电器的各个方面。
中心和标委会 竭诚为国内外用户提供优质的标准服务。