OPA121KP4中文资料

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OPA2604运放_参数_数据手册

Printed in U.S.A.®OPA2604/databook/OPA2604.htmlDual FET-Input, Low DistortionOPERATIONAL AMPLIFIERFEATURESq LOW DISTORTION: 0.0003% at 1kHz q LOW NOISE: 10nV/ Hz q HIGH SLEW RATE: 25V/∝sq WIDE GAIN-BANDWIDTH: 20MHz q UNITY-GAIN STABLEq WIDE SUPPLY RANGE: V S = ±4.5 to ±24V q DRIVES 600& LOADSDESCRIPTIONThe OPA2604 is a dual, FET-input operational ampli- fier designed for enhanced AC performance. Very low distortion, low noise and wide bandwidth provide superior performance in high quality audio and other applications requiring excellent dynamic performance.APPLICATIONSq PROFESSIONAL AUDIO EQUIPMENT q PCM DAC I/V CONVERTERq SPECTRAL ANALYSIS EQUIPMENT q ACTIVE FILTERS q TRANSDUCER AMPLIFIER q DATA ACQUISITION(+)(3, 5)(8) V+New circuit techniques and special laser trimming of dynamic circuit performance yield very low harmonic distortion. The result is an op amp with exceptional (–) (2, 6)Distortion Rejection Circuitry*Output Stage*(1, 7)V Osound quality. The low-noise FET input of the OPA2604 provides wide dynamic range, even with high source impedance. Offset voltage is laser-trimmed to minimize the need for interstage coupling capacitors. The OPA2604 is available in 8-pin plastic mini-DIP and SO-8 surface-mount packages, specified for the –25︒C to +85︒C temperature range.(4) V –* Patents Granted: #5053718, 5019789®© 1991 Burr-Brown CorporationPDS-1069ESBOS006SPECIFICATIONSELECTRICALAt T A=+25︒C,V S=±15V,unless otherwise noted.NOTES:(1)Typical performance,measured fully warmed-up.(2)Soldered to circuit board—see text.The information provided herein is believed to be reliable;however,BURR-BROWN assumes no responsibility for inaccuracies or omissions.BURR-BROWN assumes no responsibility for the use of this information,and all use of such information shall be entirely at the user’s own risk.Prices and specifications are subject to change without notice.No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.OPA26042PIN CONFIGURATIONTop ViewDIP/SOICABSOLUTEMAXIMUM RATINGS (1)Power Supply Voltage .......................................................................±25VInput Voltage ............................................................. (V –)–1V to (V+)+1V Output A–In A+In AV –12348765V+Output B–In B+In BOutput Short Circuit to Ground ...............................................ContinuousOperating Temperature ................................................. –40︒C to +100︒C Storage Temperature.....................................................–40︒C to +125︒CJunction Temperature .................................................................... +150︒C Lead Temperature (soldering, 10s) AP ......................................... +300︒C Lead Temperature (soldering, 3s) AU ..........................................+260︒CNOTE: (1) Stresses above these ratings may cause permanent damage.ORDERING INFORMATIONELECTROSTATICDISCHARGE SENSITIVITYAny integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with ap- propriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric PACKAGING INFORMATION NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.changes could cause the device not to meet published speci- fications.®3OPA2604T H D +N (%)T H D +N (%)P h a s e S h i f t (D e g r e e s )I n p u t O f f s e t C u r r e n t (p A )I n p u t B i a s C u r r e n t (p A )I n p u t B i a s C u r r e n t (p A )I n p u t O f f s e t C u r r e n t (p A )C u r r e n t N o i s e (f A /H z )V o l t a g e G a i n (d B )V o l t a g e N o i s e (n V /H z )TYPICAL PERFORMANCE CURVESAt T A = +25︒C, V S = ±15V, unless otherwise noted.TOTAL HARMONIC DISTORTION + NOISEvs FREQUENCYTOTAL HARMONIC DISTORTION + NOISEvs OUTPUT VOLTAGE10.10.1See “Distortion Measurements”for description of test method.V O1k &0.01f = 1kHz0.01 0.0010.001Measurement BW = 80kHz0.0001 201001k 10k 20k Frequency (Hz)OPEN-LOOP GAIN/PHASE vs FREQUENCY0.00010.11 10 100Output Voltage (Vp-p)INPUT VOLTAGE AND CURRENT NOISESPECTRAL DENSITY vs FREQUENCY120 01k1k100 –45 80 60 40–90 10010020 0 –20 1101001k 10k 100k 1M 10M Frequency (Hz) –135–180 101 110110100 1k 10k 100k 1MFrequency (Hz)100nAINPUT BIAS AND INPUT OFFSET CURRENT10nAINPUT BIAS AND INPUT OFFSET CURRENTvs INPUT COMMON-MODE VOLTAGE1nA10nAInput1nA1nA Bias Current100100 10100Input10Offset Current1–75 –50–250255075100125Ambient Temperature (°C)10–151–10–5 0 5 10 15Common-Mode Voltage (V)®OPA2604 4C o m m o n -M o d e R e j e c t i o n (d B )I n p u t B i a s C u r r e n t (p A )A O L ,P S R ,C M R (dB )P S R ,C M R (d B )G a i n -B a n d w i d t h (M H z )G a i n -B a n d w i d t h (M H z )S l e w R a t e (V /µs )S l e w R a t e (V /µs )–252575TYPICAL PERFORMANCE CURVES (CONT)At T A = +25︒C, V S = ±15V, unless otherwise noted.1nAINPUTBIAS CURRENTvs TIME FROM POWER TURN-ON120COMMON-MODE REJECTION vs COMMON-MODE VOLTAGE110100 1001090180012345Time After Power Turn-On (min)–15–10–5 0 5 10 15Common-Mode Voltage (V)POWER SUPPLY AND COMMON-MODE120100REJECTION vs FREQUENCY120110A OL , PSR, AND CMR vs SUPPLY VOLTAGE80100609040200 80 702824 20 16 12 101001k 10k 100k 1M 10MFrequency (Hz)GAIN-BANDWIDTH AND SLEW RATEvs SUPPLY VOLTAGE282420 16 12510152025Supply Voltage (±V S ) GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE510152025–75–50050100125Supply Voltage (±V S )Temperature (°C)5 OPA2604®C h a n n e l S e p a r a t i o n (d B )S e t t l i n g T i m e (µs )O u t p u t V o l t a g e (V p -p )S u p p l y C u r r e n t (m A )O u t p u t V o l t a g e (V )O u t p u t V o l t a g e (m V )S l e w R a t e (V /µs )TYPICAL PERFORMANCE CURVES (CONT)At T A = +25︒C, V S = ±15V, unless otherwise noted.5SETTLING TIME vs CLOSED-LOOP GAIN160CHANNEL SEPARATION vs FREQUENCY4140 31202110080 –1–10–100–1000101001k 10k 100k30Closed-Loop Gain (V/V)MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY14 Frequency (Hz)SUPPLY CURRENT vs TEMPERATURE1220 10 10 8 0 6 10k 100k1M 10M –75–50–250255075100125+10Frequency (Hz)LARGE-SIGNAL TRANSIENT RESPONSE+100Ambient Temperature (°C)SMALL-SIGNAL TRANSIENT RESPONSE30FPOBleed to edge25201510–105 10Time (µs)–1001∝s 2∝sTime (µs)25®OPA2604 6S h o r t -C i r c u i t C u r r e n t (m A )P o w e r D i s s i p a t i o n (W )T o t a l P o w e r D i s s i p a t i o n (W )TYPICAL PERFORMANCE CURVES (CONT)At T A = +25︒C, V S = ±15V, unless otherwise noted.6050SHORT-CIRCUIT CURRENT vs TEMPERATURE10.9 0.8POWER DISSIPATION vs SUPPLY VOLTAGE0.7 0.6 400.5 0.4 30200.3 0.2 0.1 –75–50–250255075100125Ambient Temperature (°C)681012141618202224Supply Voltage, ±V S (V)MAXIMUM POWER DISSIPATION vs TEMPERATURE1.41.21.00.80.60.40.2255075100125150Ambient Temperature (°C)7 OPA2604®APPLICATIONS INFORMATIONThe OPA2604is unity-gain stable,making it easy to use in a wide range of circuitry.Applications with noisy or high impedance power supply lines may require decoupling ca-pacitors close to the device pins.In most cases1∝F tantalum capacitors are adequate.DISTORTION MEASUREMENTSThe distortion produced by the OPA2604is below the mea-surement limit of virtually all commercially available equip-ment.A special test circuit,however,can be used to extend the measurement capabilities.Op amp distortion can be considered an internal error source which can be referred to the input.Figure1shows a circuit which causes the op amp distortion to be101times greater than normally produced by the op amp.The addition of R3to the otherwise standard non-inverting amplifier configuration alters the feedback factor or noise gain of the circuit.The closed-loop gain is unchanged,but the feedback available for error correction is reduced by a factor of101.This extends the measurement limit,including the effects of the signal-source purity,by a factor of101.Note that the input signal and load applied to the op amp are the same as with conventional feedback without R3.Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency where the distortion is within the measurement capability of the test equipment.Measurements for this data sheet were made with the Audio Precision System One which greatly simplifies such repetitive measurements.The measurement technique can,however,be performed with manual distortion measure-ment instruments.CAPACITIVE LOADSThe dynamic characteristics of the OPA2604have been optimized for commonly encountered gains,loads and oper-ating conditions.The combination of low closed-loop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations.Load capacitance reacts with the op amp’s open-loop output resistance to form an additional pole in the feedback loop.Figure2shows various circuits which preserve phase margin with capacitive load. Request Application Bulletin AB-028for details of analysis techniques and applications circuits.For the unity-gain buffer,Figure2a,stability is preserved by adding a phase-lead network,R C and C C.Voltage drop across R C will reduce output voltage swing with heavy loads.An alternate circuit,Figure2b,does not limit the output with low load impedance.It provides a small amount of positive feed-back to reduce the net feedback factor.Input impedance of this circuit falls at high frequency as op amp gain rolloff reduces the bootstrap action on the compensation network. Figures2c and2d show compensation techniques for noninverting amplifiers.Like the follower circuits,the circuit in Figure2d eliminates voltage drop due to load current,but at the penalty of somewhat reduced input impedance at high frequency.Figures2e and2f show input lead compensation networks for inverting and difference amplifier configurations.NOISE PERFORMANCEOp amp noise is described by two parameters—noise voltage and noise current.The voltage noise determines the noise performance with low source impedance.Low noise bipolar-input op amps such as the OPA27and OPA37provide very low voltage noise.But if source impedance is greater than a few thousand ohms,the current noise of bipolar-input op amps react with the source impedance and will dominate.At a few thousand ohms source impedance and above,the OPA2604 will generally provide lower noise.FIGURE1.Distortion Test Circuit.®OPA2604*Measurement BW=80kHz8R 2 C L(a)C C(b)820pF1 21 2R COPA2604e o e iOPA2604750&e oC CC LC L0.47µF 5000pF5000pFR 2R CC C =120 X 10–12 C Le i2k &R C =10&R 24C L X 1010 – 1C C =C L X 10C(c)(d)R 110k &R 210k & C C24pFR 12k &R C20&R 22k &e i1 2OPA2604R C25&e oe iC C 0.22µF 1 2OPA2604e oC C = 50C L5000pFR C =R 22C L X 1010 – (1 + R 2/R 1)C L5000pFC CC L X 103C(e)(f)R 22k &e 1R 12k &R 22k &e iR 12k &R C20& C C 0.22µF1 2OPA2604e oC L5000pFe 2R C 20&C C 0.22µF R 31 2OPA2604R 4e oC L5000pFR C =R 22C L X 1010 – (1 + R 2/R 1)C C =C L X 103C2k & 2k &R C =R 22C L X 1010 – (1 + R 2/R 1)C CC L X 10CNOTE: Design equations and component values are approximate. User adjustment is required for optimum performance.FIGURE 2. Driving Large Capacitive Loads.®9 OPA2604POWER DISSIPATIONThe OPA2604is capable of driving600&loads with power supply voltages up to±24V.Internal power dissipation is increased when operating at high power supply voltage.The typical performance curve,Power Dissipation vs Power Sup-ply Voltage,shows quiescent dissipation(no signal or no load)as well as dissipation with a worst case continuous sine wave.Continuous high-level music signals typically produce dissipation significantly less than worst case sine waves.Copper leadframe construction used in the OPA2604im-proves heat dissipation compared to conventional plastic packages.To achieve best heat dissipation,solder the device directly to the circuit board and use wide circuit board traces. OUTPUT CURRENT LIMITOutput current is limited by internal circuitry to approxi-mately±40mA at25︒C.The limit current decreases with increasing temperature as shown in the typical curves.f p=20kHzFIGURE3.Three-Pole Low-Pass Filter.12R1R5OPA2604V O V IN6.04k&R24.02k&2k&C31000pF12 OPA2604R24.02k&C112OPA2604Low-pass3-pole Butterworthf–3dB=40kHz 1000pFR45.36k&See Application Bulletin AB-026 C2for information on GIC filters. 1000pFFIGURE4.Three-Pole Generalized Immittance Converter(GIC)Low-Pass Filter.®OPA260410C1*I-Out DAC R1C22k&2200pF12C OUT12OPA2604*C1=~R22.94k&C OUT2 R1f cR321k&OPA2604C3470pFLow-pass2-pole Butterworthf–3dB=20kHzV OR1=Feedback resistance=2k&f c=Crossover frequency=8MHzFIGURE5.DAC I/V Amplifier and Low-Pass Filter.FIGURE6.Differential Amplifier with Low-Pass Filter.®11OPA2604* Provides input bias current return path.FIGURE 7. High Impedance Amplifier.filter.FIGURE 8. Digital Audio DAC I-V Amplifier.FIGURE 9. Using the Dual OPA2604 Op Amp to Double the Output Current to a Load.®OPA2604 12PACKAGE OPTION ADDENDUM 6-Dec-2006 PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins Package Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)QtyOPA2604AP ACTIVE PDIP P850Green(RoHS&no Sb/Br) OPA2604APG4ACTIVE PDIP P850Green(RoHS&no Sb/Br) OPA2604AU ACTIVE SOIC D8100Green(RoHS&no Sb/Br) OPA2604AU/2K5ACTIVE SOIC D82500Pb-Free(RoHS) OPA2604AU/2K5E4ACTIVE SOIC D82500Pb-Free(RoHS) OPA2604AUE4ACTIVE SOIC D8100Green(RoHS&no Sb/Br) OPA2604AUG4ACTIVE SOIC D8100Green(RoHS&CU NIPDAU N/A for Pkg Type CU NIPDAU N/A for Pkg Type CU NIPDAU Level-3-260C-168HR CU NIPDAU Level-3-260C-168HR CU NIPDAU Level-3-260C-168HR CU NIPDAU Level-3-260C-168HR CU NIPDAU Level-3-260C-168HRno Sb/Br)(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirementsfor all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.Addendum-Page1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications, enhancements,improvements,and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.T o minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right, copyright,mask work right,or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityLow Power Wireless /lpw Telephony /telephonyVideo&Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box655303Dallas,Texas75265Copyright 2006,T exas Instruments Incorporated万联芯城-电子元器件采购网，提供一站式电子元器件配套服务，为客户解决物料烦恼，万联芯城产品线包括IC集成电路，电阻电容，二三极管，客户只需提交BOM物料清单，即可进行一站式报价，所售产品均为原装现货，价格有明显优势，为客户节省采购成本，为客户解决采购烦恼。

上海维宏四气缸单变频器参数设置

文章标题：深度解析：上海维宏四气缸单变频器参数设置一、引言在工业自动化领域，上海维宏四气缸单变频器参数设置是一个至关重要的主题。

它直接关系到生产线的稳定性、效率和安全性。

而针对这一主题，我将从简到繁、由浅入深地进行全面评估，为您撰写一篇有价值的文章。

二、基础概念我们先来了解一下上海维宏四气缸单变频器的基本概念。

四气缸单变频器是一种用于控制气缸运动的设备，通过调节气缸的运行速度和力度，实现对工件的精准处理。

而在设置参数时，需要考虑到气缸的速度、加速度、减速度、力度等多个因素，以确保其在工作过程中的稳定性和精准度。

三、深度评估接下来，我们将从深度和广度的角度对上海维宏四气缸单变频器参数设置进行全面评估。

1. 参数设置方法在进行参数设置时，首先需要了解每个参数的作用和影响。

速度参数会直接影响气缸的运行速度，而加速度和减速度则关系到气缸的启动和停止过程。

在设置这些参数时，需要综合考虑它们之间的关联性，以及对整体工作流程的影响。

2. 调试过程在参数设置完成后，需要进行一定的调试过程。

通过观察气缸的运行状态和工件的加工效果，及时调整参数，以达到最佳的工作效果。

此过程需要不断地实践和总结经验，以提升调试的效率和准确度。

3. 稳定性和安全性在设置参数时，稳定性和安全性是至关重要的考量因素。

稳定性可以保证生产线的连续工作，而安全性则关系到工人的人身安全。

在参数设置过程中，需要严格把控每个参数的范围和极限，以保证工作的稳定和安全。

四、总结与回顾通过以上的深度评估，我们可以发现上海维宏四气缸单变频器参数设置是一个需要综合考量和实际调试的复杂工作。

只有在充分了解每个参数的作用和影响后，才能够做出准确的设置和调试。

而在长期的实践中，我们也可以不断地积累经验，以提升参数设置的准确度和稳定性。

五、个人观点与理解对于上海维宏四气缸单变频器参数设置，我个人认为需要在了解其基础概念的基础上，注重实际操作和实践经验的积累。

只有将理论知识与实际操作相结合，才能够做出更加准确和稳定的参数设置。

OPA842_中文资料

宽带、低失真,单位增益稳定,电压反馈运算放大器
单位增益带宽:400 mhz
增益贷款
低输入电压噪声:2.6 nv /√赫兹
极低的失真:-93 dbc(5 mhz)
高开环增益:110分贝
快12位结算:22 ns(0.01%)
低直流电压偏移量:300 mv典型
专业水平差异获得/相位误差:0.003% / 0.008°
DC和DAC缓冲驱动程序
低失真中频放大器
积极滤波器配置
低噪声差动接收器
高分辨率成像
测试仪器
专业音响
OPA64升级
展示了增益+2的高频应用电路图
单运算放大器微分放大器
三个运算放大器差分
pa842--宽带低失真单位增益稳定的电压反馈运算放大器
DAC 互阻抗放大器
高频数模转换器(DACs) 需要一个失真的输出放大器保留SFDR性能到真实的负载。

单端输
出驱动器实现如图Figure 41.所示。

在这个电路中，只有一侧的互补输出驱动信号被使用。

图表显示了输出电流信号连接到虚拟。

ADC121S101_06中文资料

ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D ConverterGeneral DescriptionThe ADC121S101is a low-power,single channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface.Unlike the conventional practice of specifying per-formance at a single sample rate only,the ADC121S101is fully specified over a sample rate range of 500ksps to 1Msps.The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit.The output serial data is straight binary,and is compatible with several standards,such as SPI ™,QSPI ™,MICROWIRE,and many common DSP serial interfaces.The ADC121S101operates with a single supply that can range from +2.7V to +5.25V.Normal power consumption using a +3V or +5V supply is 2.0mW and 10mW,respec-tively.The power-down feature reduces the power consump-tion to as low as 2.6µW using a +5V supply.The ADC121S101is packaged in 6-lead LLP and SOT-23packages.Operation over the industrial temperature range of −40˚C to +125˚C is guaranteed.Featuresn Specified over a range of sample rates.n 6-lead LLP and SOT-23packages n Variable power managementn Single power supply with 2.7V -5.25V range nSPI ™/QSPI ™/MICROWIRE/DSP compatibleKey Specificationsn DNL +0.5/−0.3LSB (typ)n INL ±0.40LSB (typ)n SNR72.5dB (typ)nPower Consumption —3V Supply 2.0mW (typ)—5V Supply10mW (typ)Applicationsn Portable Systemsn Remote Data Acquisitionn Instrumentation and Control SystemsPin-Compatible Alternatives by Resolution and SpeedAll devices are fully pin and function compatible.ResolutionSpecified for Sample Rate Range of:50to 200ksps200to 500ksps 500ksps to 1Msps12-bit ADC121S021ADC121S051ADC121S10110-bit ADC101S021ADC101S051ADC101S1018-bitADC081S021ADC081S051ADC081S101Connection Diagram20145005Ordering InformationOrder Code Temperature Range Description Top Mark ADC121S101CISD −40˚C to +125˚C 6-Lead LLP PackageX1C ADC121S101CISDX −40˚C to +125˚C 6-Lead LLP Package,Tape &ReelX1C ADC121S101CIMF −40˚C to +125˚C 6-Lead SOT-23PackageX01C ADC121S101CIMF −40˚C to +125˚C6-Lead SOT-23Package,Tape &ReelX01CADC121S101EVALEvaluation BoardTRI-STATE ®is a trademark of National Semiconductor Corporation QSPI ™and SPI ™are trademarks of Motorola,Inc.April 2006ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D Converter©2006National Semiconductor Corporation Block Diagram20145007Pin Descriptions and Equivalent CircuitsPin No.SymbolDescriptionANALOG I/O3V INAnalog input.This signal can range from 0V to V A .DIGITAL I/O4SCLK Digital clock input.This clock directly controls the conversion and readout processes.5SDATA Digital data output.The output samples are clocked out of this pin on falling edges of the SCLK pin.6CSChip select.On the falling edge of CS,a conversion process begins.POWER SUPPLY1V A Positive supply pin.This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1µF capacitor and a 0.1µF monolithic capacitor located within 1cm of the power pin.2GND The ground return for the supply and signals.PADGNDFor package suffix CISD(X)only,it is recommended that the center pad should be connected to ground.A D C 121S 101 2Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Analog Supply Voltage V A−0.3V to6.5V Voltage on Any Digital Pin to GND−0.3V to6.5V Voltage on Any Analog Pin to GND−0.3V to(V A+0.3V) Input Current at Any Pin(Note3)±10mA Package Input Current(Note3)±20mA Power Consumption at T A=25˚C See(Note4) ESD Susceptibility(Note5)Human Body Model Machine Model 3500V 300VJunction Temperature+150˚C Storage Temperature−65˚C to+150˚C Operating Ratings(Notes1,2)Operating Temperature Range−40˚C≤T A≤+125˚C V A Supply Voltage+2.7V to+5.25V Digital Input Pins Voltage Range(regardless of supply voltage)−0.3V to5.25V Analog Input Pins Voltage Range0V to V A Clock Frequency1MHz to20MHz Sample Rate up to1Msps Package Thermal ResistancePackageθJA6-lead LLP94˚C/W6-lead SOT-23265˚C/WSoldering process must comply with National Semiconduc-tor’s Reflow Temperature Profile specifications.Refer to /packaging.(Note6)ADC121S101Converter Electrical Characteristics(Notes7,9)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsSTATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes V A=+2.7v to+3.6V−40˚C≤T A≤125˚C12BitsINL Integral Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6VSOT-23+0.4±1.0LSB(max)-0.4LSB(min)LLP+0.4+1.0LSB(max)-0.4-1.2LSB(min)T A=125˚CV A=+2.7v to+3.6VSOT-23+1.0LSB(max)-1.1LSB(min)LLP+1.0LSB(max)-1.3LSB(min)DNL Differential Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6V+0.5+1.0LSB(max)−0.3-0.9LSB(min) T A=125˚CV A=+2.7v to+3.6V±1.0LSB(max)V OFF Offset Error −40˚C≤T A≤125˚CV A=+2.7v to+3.6V±0.1±1.2LSB(max)LSB(min)GE Gain Error −40˚C≤T A≤125˚CV A=+2.7to+3.6VSOT-23±0.20±1.2LSB(max)LLP±0.20±1.5LSB(max)DYNAMIC CONVERTER CHARACTERISTICSSINAD Signal-to-Noise Plus Distortion Ratio V A=+2.7to5.25V−40˚C≤T A≤125˚Cf IN=100kHz,−0.02dBFS7270dB(min)SNR Signal-to-Noise Ratio V A=+2.7to5.25V−40˚C≤T A≤+85˚Cf IN=100kHz,−0.02dBFS72.570.8dB(min)V A=+2.7to5.25VT A=+125˚Cf IN=100kHz,−0.02dBFS70.6ADC121S101 3ADC121S101Converter Electrical Characteristics (Notes 7,9)(Continued)The following specifications apply for V A =+2.7V to 5.25V,GND =0V,f SCLK =10MHz to 20MHz,C L =15pF,f SAMPLE =500ksps to 1Msps,unless otherwise noted.Boldface limits apply for T A =-40˚C to +85˚C :all other limits T A =25˚C unless otherwise noted.SymbolParameterConditionsTypicalLimits (Note 9)UnitsDYNAMIC CONVERTER CHARACTERISTICS THD Total Harmonic Distortion V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS −80dB (max)SFDR Spurious-Free Dynamic Range V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 82dB (min)ENOBEffective Number of BitsV A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 11.611.3Bits (min)IMDIntermodulation Distortion,Second Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB Intermodulation Distortion,Third Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB FPBW-3dB Full Power BandwidthV A =+5V 11MHz V A =+3V8MHz ANALOG INPUT CHARACTERISTICS V IN Input Range 0to V AVI DCL DC Leakage Current ±1µA (max)C INAInput CapacitanceTrack Mode 30pF Hold Mode 4pF DIGITAL INPUT CHARACTERISTICS V IH Input High Voltage V A =+5.25V 2.4V (min)V A =+3.6V 2.1V (min)V IL Input Low Voltage V A =+5V 0.8V (max)V A =+3V 0.4V (max)I IN Input CurrentV IN =0V or V A±0.1±1µA (max)C INDDigital Input Capacitance24pF (max)DIGITAL OUTPUT CHARACTERISTICS V OH Output High Voltage I SOURCE =200µA V A −0.07V A −0.2V (min)I SOURCE =1mA V A −0.1V V OL Output Low VoltageI SINK =200µA 0.030.4V (max)I SINK =1mA0.1VI OZH ,I OZL TRI-STATE ®Leakage Current ±0.1±10µA (max)C OUTTRI-STATE ®Output Capacitance 24pF (max)Output CodingStraight (Natural)BinaryPOWER SUPPLY CHARACTERISTICS V ASupply Voltage2.7V (min)5.25V (max)I ASupply Current,Normal Mode (Operational,CS low)V A =+5.25V,f SAMPLE =1Msps 2.0 3.2mA (max)V A =+3.6V,f SAMPLE =1Msps 0.6 1.5mA (max)Supply Current,Shutdown (CS high)f SCLK =0MHz,V A =+5V,f SAMPLE =0ksps500nA f SCLK =20MHz,V A =+5V,f SAMPLE =0ksps60µAA D C 121S 101 4ADC121S101Converter Electrical Characteristics(Notes7,9)(Continued)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsPOWER SUPPLY CHARACTERISTICSP D Power Consumption,Normal Mode(Operational,CS low)V A=+5V1016mW(max)V A=+3V 2.0 4.5mW(max)Power Consumption,Shutdown(CShigh)f SCLK=0MHz,V A=+5Vf SAMPLE=0ksps2.5µWf SCLK=20MHz,V A=+5V,f SAMPLE=0ksps300µWAC ELECTRICAL CHARACTERISTICSf SCLK Clock Frequency(Note8)10MHz(min) 20MHz(max)f S Sample Rate(Note8)500ksps(min) 1Msps(max)t CONV Conversion Time16SCLK cyclesDC SCLK Duty Cycle f SCLK=20MHz5040%(min) 60%(max)t ACQ Track/Hold Acquisition Time400ns(max) Throughput Time Acquisition Time+Conversion Time20SCLK cycles t QUIET(Note10)50ns(min) t AD Aperture Delay3nst AJ Aperture Jitter30ps ADC121S101Timing SpecificationsThe following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10.0MHz to20.0MHz,C L=25pF,f SAMPLE=500ksps to1Msps,Boldface limits apply for T A=-40˚C to+85˚C;all other limits T A=25˚C.Symbol Parameter Conditions Typical Limits Units t CS Minimum CS Pulse Width10ns(min) t SU CS to SCLK Setup Time10ns(min)t EN Delay from CS Until SDATA TRI-STATE®Disabled(Note11)20ns(max)t ACC Data Access Time after SCLK Falling Edge(Note12)V A=+2.7to+3.640ns(max)V A=+4.75to+5.2520ns(max)t CL SCLK Low Pulse Width 0.4xt SCLKns(min)t CH SCLK High Pulse Width 0.4xt SCLKns(min)t H SCLK to Data Valid Hold Time V A=+2.7V to+3.6V7ns(min) V A=+4.75V to+5.25V5ns(min)t DIS SCLK Falling Edge to SDATA HighImpedance(Note13)V A=+2.7V to+3.6V25ns(max)6ns(min)V A=+4.75V to+5.25V25ns(max)5ns(min)t POWER-UP Power-Up Time from Full Power-Down1µs Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note2:All voltages are measured with respect to GND=0V,unless otherwise specified.ADC121S1015ADC121S101Timing Specifications(Continued)Note 3:When the input voltage at any pin exceeds the power supply (that is,V IN <GND or V IN >V A ),the current at that pin should be limited to 10mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10mA to two.The Absolute Maximum Rating specification does not apply to the V A pin.The current into the V A pin is limited by the Analog Supply Voltage specification.Note 4:The absolute maximum junction temperature (T J max)for this device is 150˚C.The maximum allowable power dissipation is dictated by T J max,the junction-to-ambient thermal resistance (θJA ),and the ambient temperature (T A ),and can be calculated using the formula P D max =(T J max −T A )/θJA .The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g.when input or output pins are driven beyond the power supply voltages,or the power supply polarity is reversed).Obviously,such conditions should always be avoided.Note 5:Human body model is 100pF capacitor discharged through a 1.5k Ωresistor.Machine model is 220pF discharged through zero ohms.Note 6:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 7:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 8:This is the frequency range over which the electrical performance is guaranteed.The device is functional over a wider range which is specified under Operating Ratings.Note 9:Data sheet min/max specification limits are guaranteed by design,test,or statistical analysis.Note 10:Minimum Quiet Time required by bus relinquish and the start of the next conversion.Note 11:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V.Note 12:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V or 2.0V.Note 13:t DIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1.The measured number is then adjusted to remove the effects of charging or discharging the output capacitance.This means that t DIS is the true bus relinquish time,independent of the bus loading.A D C 121S 101 6Timing Diagrams20145008FIGURE 1.Timing Test Circuit20145006FIGURE 2.ADC121S101Serial Timing DiagramADC121S1017Specification DefinitionsACQUISITION TIME is the time required to acquire the input voltage.That is,it is time required for the hold capacitor to charge up to the input voltage.APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.APERTURE JITTER (APERTURE UNCERTAINTY)is the variation in aperture delay from sample to sample.Aperture jitter manifests itself as noise in the output.CONVERSION TIME is the time required,after the input voltage is acquired,for the ADC to convert the input voltage to a digital word.DIFFERENTIAL NON-LINEARITY (DNL)is the measure of the maximum deviation from the ideal step size of 1LSB.DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.The speci-fication here refers to the SCLK.EFFECTIVE NUMBER OF BITS (ENOB,or EFFECTIVE BITS)is another method of specifying Signal-to-Noise and Distortion or SINAD.ENOB is defined as (SINAD −1.76)/6.02and says that the converter is equiva-lent to a perfect ADC of this (ENOB)number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3dB below its low frequency value for a full scale input.GAIN ERROR is the deviation of the last code transition (111...110)to (111...111)from the ideal (V REF −1.5LSB),after adjusting for offset error.INTEGRAL NON-LINEARITY (INL)is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2LSB below the first code transition)through positive full scale (1⁄2LSB above the last code transition).The deviation of any given code from this straight line is measured from the center of that code value.INTERMODULATION DISTORTION (IMD)is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the sum of the power in both of the original frequencies.IMD is usually expressed in dB.MISSING CODES are those output codes that will never appear at the ADC outputs.The ADC121S101is guaranteed not to have any missing codes.OFFSET ERROR is the deviation of the first code transition (000...000)to (000...001)from the ideal (i.e.GND +0.5LSB).SIGNAL TO NOISE RATIO (SNR)is the ratio,expressed in dB,of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency,not including harmonics or d.c.SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)Is the ratio,expressed in dB,of the rms value of the input signal to the rms value of all of the other spectral compo-nents below half the clock frequency,including harmonics but excluding d.c.SPURIOUS FREE DYNAMIC RANGE (SFDR)is the differ-ence,expressed in dB,between the desired signal ampli-tude to the amplitude of the peak spurious spectral compo-nent,where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.TOTAL HARMONIC DISTORTION (THD)is the ratio,ex-pressed in dB or dBc,of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output.THD is calcu-lated aswhere A f1is the RMS power of the input frequency at the output and A f2through A f6are the RMS power in the first 5harmonic frequencies.THROUGHPUT TIME is the minimum time required between the start of two successive conversion.It is the acquisition time plus the conversion time.A D C 121S 101 8Typical Performance CharacteristicsT A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN=100kHz unless otherwise stated.DNLf SCLK =10MHzINLf SCLK=10MHz2014502020145021DNLf SCLK =20MHz INLf SCLK =20MHz2014506020145061DNL vs.Clock Frequency INL vs.Clock Frequency2014506520145066ADC121S1019Typical Performance Characteristics T A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN =100kHz unless otherwise stated.(Continued)SNR vs.Clock FrequencySINAD vs.Clock Frequency2014506320145064SFDR vs.Clock Frequency THD vs.Clock Frequency2014506720145068Spectral Response,V A =5.25Vf SCLK =10MHz Spectral Response,V A =5.25Vf SCLK =20MHz2014506920145070A D C 121S 101 10ADC121S101Typical Performance Characteristics T=+25˚C,f SAMPLE=500ksps to1Msps,Af SCLK=10MHz to20MHz,f IN=100kHz unless otherwise stated.(Continued)Power Consumption vs.Throughput,f SCLK=20MHz Array 2014505511Applications Information1.0ADC121S101OPERATIONThe ADC121S101is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter core.Simplified schematics of the ADC121S101in both track and hold modes are shown in Figure 3and Figure 4,respectively.In Figure 3,the device is in track mode:switch SW1connects the sampling capacitor to the input,and SW2balances the comparator inputs.The device is in this state until CS is brought low,at which point the device moves to hold mode.Figure 4shows the device in hold mode:switch SW1con-nects the sampling capacitor to ground,maintaining the sampled voltage,and switch SW2unbalances the compara-tor.The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced.When the comparator is balanced,the digital word supplied to the DAC is the digital representation of the analog input voltage.The device moves from hold mode to track mode on the 13th rising edge of SCLK.2.0USING THE ADC121S101The serial interface timing diagram for the ADC121S101is shown in Figure 2.CS is chip select,which initiates conver-sions on the ADC121S101and frames the serial data trans-fers.SCLK (serial clock)controls both the conversion pro-cess and the timing of serial data.SDATA is the serial data out pin,where a conversion result is found as a serial data stream.Basic operation of the ADC121S101begins with CS going low,which initiates a conversion process and data transfer.Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS;for example,"the third falling edge of SCLK"shall refer to the third falling edge of SCLK after CS goes low.At the fall of CS,the SDATA pin comes out of TRI-STATE,and the converter moves from track mode to hold mode.The input signal is sampled and held for conversion on the fallingedge of CS.The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2).The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK,or at the rising edge of CS,whichever occurs first.After a conversion is completed,the quiet time t QUIET must be satisfied before bringing CS low again to begin another conversion.Sixteen SCLK cycles are required to read a complete sample from the ADC121S101.The sample bits (including leading zeroes)are clocked out on falling edges of SCLK,and are intended to be clocked in by a receiver on subse-quent falling edges of SCLK.The ADC121S101will produce three leading zero bits on SDATA,followed by twelve data bits,most significant first.If CS goes low before the rising edge of SCLK,an additional (fourth)zero bit may be captured by the next falling edge of SCLK.20145009FIGURE 3.ADC121S101in Track Mode20145010FIGURE 4.ADC121S101in Hold ModeA D C 121S 101 12Applications Information(Continued)3.0ADC121S101TRANSFER FUNCTIONThe output format of the ADC121S101is straight binary.Code transitions occur midway between successive integer LSB values.The LSB width for the ADC121S101is V A /4096.The ideal transfer characteristic is shown in Figure 5.The transition from an output code of 000000000000to a code of 000000000001is at 1/2LSB,or a voltage of V A /8192.Other code transitions occur at steps of one LSB.4.0TYPICAL APPLICATION CIRCUITA typical application of the ADC121S101is shown in Figure 6.Power is provided in this example by the National Semiconductor LP2950low-dropout voltage regulator,avail-able in a variety of fixed and adjustable output voltages.The power supply pin is bypassed with a capacitor network lo-cated close to the ADC121S101.Because the reference for the ADC121S101is the supply voltage,any noise on the supply will degrade device noise performance.To keep noise off the supply,use a dedicated linear regulator for this de-vice,or provide sufficient decoupling from other circuitry to keep noise off the ADC121S101supply pin.Because of the ADC121S101’s low power requirements,it is also possible to use a precision reference as a power supply to maximize performance.The three-wire interface is shown connected to a microprocessor or DSP .5.0ANALOG INPUTSAn equivalent circuit for the ADC121S101’s input is shown in Figure 7.Diodes D1and D2provide ESD protection for the analog inputs.At no time should the analog input go beyond (V A +300mV)or (GND −300mV),as these ESD diodes will begin conducting,which could result in erratic operation.The capacitor C1in Figure 7has a typical value of 4pF,and is mainly the package pin capacitance.Resistor R1is the on resistance of the track /hold switch,and is typically 500ohms.Capacitor C2is the ADC121S101sampling capacitor and is typically 26pF.The ADC121S101will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.This is especially important when using the ADC121S101to sample AC signals.Also important when sampling dynamic signals is an anti-aliasing filter.6.0DIGITAL INPUTS AND OUTPUTSThe ADC121S101digital inputs (SCLK and CS)are not limited by the same maximum ratings as the analog inputs.The digital input pins are instead limited to +5.25V with respect to GND,regardless of V A ,the supply voltage.This allows the ADC121S101to be interfaced with a wide range of logic levels,independent of the supply voltage.7.0MODES OF OPERATIONThe ADC121S101has two possible modes of operation:normal mode,and shutdown mode.The ADC121S101en-ters normal mode (and a conversion process is begun)when CS is pulled low.The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low,or will stay in normal mode if CS remains low.Once in shutdown mode,the device will stay there until CS is brought low again.By varying the ratio of time spent in the normal and shutdown modes,a system may trade-off throughput for power consumption,with a sample rate as low as zero.7.1Normal ModeThe fastest possible throughput is obtained by leaving the ADC121S101in normal mode at all times,so there are no power-up delays.To keep the device in normal mode con-tinuously,CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).If CS is brought high after the 10th falling edge,but before the 16th falling edge,the device will remain in normal mode,but the current conversion will be aborted,and SDATA will return to TRI-STATE (truncating the output word).Sixteen SCLK cycles are required to read all of a conversion word from the device.After sixteen SCLK cycles have20145011FIGURE 5.Ideal Transfer Characteristic20145013FIGURE 6.Typical Application Circuit20145014FIGURE 7.Equivalent Input CircuitADC121S10113Applications Information(Continued)elapsed,CS may be idled either high or low until the next conversion.If CS is idled low,it must be brought high again before the start of the next conversion,which begins when CS is again brought low.After sixteen SCLK cycles,SDATA returns to TRI-STATE.Another conversion may be started,after t QUIET has elapsed,by bringing CS low again.7.2Shutdown ModeShutdown mode is appropriate for applications that either do not sample continuously,or it is acceptable to trade through-put for power consumption.When the ADC121S101is in shutdown mode,all of the analog circuitry is turned off.To enter shutdown mode,a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK,as shown in Figure 8.Once CS has been brought high in this manner,the device will enter shutdown mode;the current conversion will be aborted and SDATA will enter TRI-STATE.If CS is brought high before the second falling edge of SCLK,the device will not change mode;this is to avoid accidentally changing mode as a result of noise on the CS line.To exit shutdown mode,bring CS back low.Upon bringing CS low,the ADC121S101will begin powering up (power-up time is specified in the Timing Specifications table).This power-up delay results in the first conversion result being unusable.The second conversion performed after power-up,however,is valid,as shown in Figure 9.If CS is brought back high before the 10th falling edge of SCLK,the device will return to shutdown mode.This is done to avoid accidentally entering normal mode as a result of noise on the CS line.To exit shutdown mode and remain in normal mode,CS must be kept low until after the 10th falling edge of SCLK.The ADC121S101will be fully powered-up after 16SCLK cycles.8.0POWER MANAGEMENTThe ADC121S101takes time to power-up,either after first applying V A ,or after returning to normal mode from shut-down mode.This corresponds to one "dummy"conversion for any SCLK frequency within the specifications in this document.After this first dummy conversion,the ADC121S101will perform conversions properly.Note that the t QUIET time must still be included between the first dummy conversion and the second valid conversion.When the V A supply is first applied,the ADC121S101may power up in either of the two modes:normal or shutdown.As such,one dummy conversion should be performed after start-up,as described in the previous paragraph.The part may then be placed into either normal mode or the shutdown mode,as described in Sections 7.1and 7.2.When the ADC121S101is operated continuously in normal mode,the maximum throughput is f SCLK /20.Throughput may be traded for power consumption by running f SCLK at its maximum specified rate and performing fewer conversions per unit time,raising the ADC121S101CS line after the 10th and before the 15th fall of SCLK of each conversion.A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section.To calculate the power consumption for a given throughput,multiply the frac-tion of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption.Note that the curve of power consumption vs.throughput is essentially linear.This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.20145016FIGURE 8.Entering Shutdown Mode20145017FIGURE 9.Entering Normal ModeA D C 121S 10114。

OPA404KU,OPA404KP,OPA404KU 1K,OPA404KU 1KE4,OPA404KUG4,OPA404AG,OPA404BG, 规格书,Datasheet 资料

TEMPERATURE RANGE Specification
KP, KU Operating
KP, KU Storage
KP, KU θ Junction-Ambient
KP, KU
IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature
© 1986 Burr-Brown Corporation
PDS-677F
Printed in U.S.A. August 1995
芯天下--/
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted.
®
OPA404
2
芯天下--/
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.
OPA404AG, KP, KU
8
0.5
12
1013 || 1 1014 || 3
±10.5 88 84
+13, –11 100 100
88
100
4
6.4
570
24
35
0.6
1.5
±11.5 +13.2, –13.8
±5
±10
80
1000
±10
±27
±40
±15
±5
±18
9
10
–25

OPA4234PA中文资料

OPA234 OPA2234 OPA4234
Low Power, Precision SINGLE-SUPPLY OPERATIONAL AMPLIFIERS
FEATURES
q WIDE SUPPLY RANGE: Single Supply: VS = +2.7V to +36V Dual Supply: VS = ±1.35V to ±18V
IO = 0
+5
T
V
+2.7
+36
T
T
V
250
300
T
T
µA
–40
+85
T
T
°C
–40
+125
T
T
°C
–55
+125
T
T
°C
100
T
°C/W
150
T
°C/W
220
T
°C/W
80
T
°C/W
110
T
°C/W
T Specifications same as OPA234P,U,E.
NOTES: (1) Guaranteed by wafer-level test to 95% confidence level. (2) Positive conventional current flows into the input terminals. (3) See “Small-Signal Overshoot vs Load Capacitance” typical curve.
±40 ±100 ±0.5
3 0.2 0.3
±100 ±150

海利普变频器说明书

定额
100%连续
最大过载电流
150% 1分钟，180% 0.2 秒
电源额定输入电压
AC 380V: 340~460V
AVR功能有效时，在输入电压变动的情况下，输出电输出电压自动调整压基本不变，保持恒定V/f 值
控制方式
SPWM
频率控制范围
0~400HZ
频率精度
数字式：0 . 01% (-10 ~ 4 0 ℃)；模拟式：0 .1% (2 5± 10℃)
→000.00
PROG
CD000
FOR HZ 进入编程状态
↓
¢ ¤ 显示功能CD000
ENYER
000.0 0
FOR HZ 显示CD000中内容 ¢ ¤
▲↓← ENTER
5 0.00
FOR HZ 修改CD000中内容
END→50.00 ¢ ¤ 确定修改数值
↓
CD001
3、安装空间与方向 ● 为了冷却及维护方便起见，变频器周围需留有足够的空间。如图所示； ● 为使冷却效果良好，必须将变频器垂直放置，并保证空气流通顺畅。 ● 安装如果有不牢固的情形，在变频器底座下置一平板后再安装，安装在松脱的平面上，应力可能会造成主回路零件损坏，因而损坏变频器；
·3·
海利普变频器
（1）良
（2）良 ·7·
（3）不良
海利普变频器
三、产品标准规格
项目
规格
额定输出电压
三相 380V
变频器功率（KW） 11 15 18.5 22 30 37 45 55 75
输出
适用电机（KW）额定输出电流(A)
11 15 18.5 22 30 37 45 55 75 24 33 40 47 65 80 91 110 152

OPA541中文资料

2®OPA541SPECIFICATIONSELECTRICALAt T C = +25°C and V S = ±35VDC, unless otherwise noted.OPA541AM/APOPA541BM/SM PARAMETERCONDITIONSMINTYP MAX MINTYP MAX UNITS INPUT OFFSET VOLTAGE V OS±2±10±0.1±1mV vs Temperature Specified Temperature Range±20±40±15±30µV/°C vs Supply Voltage V S = ±10V to ±V MAX±2.5±10T T µV/V vs Power±20±60T T µV/W INPUT BIAS CURRENT I B450T T pA INPUT OFFSET CURRENT I OS±1±30T TpA Specified Temperature Range5T nA INPUT CHARACTERISTICS Common-Mode Voltage Range Specified Temperature Range±(|V S | – 6)±(|V S | – 3)T T V Common-Mode Rejection V CM = (|±V S | – 6V)95113TT dB Input Capacitance 5T pF Input Impedance, DC 1T T ΩGAIN CHARACTERISTICS Open Loop Gain at 10Hz R L = 6Ω9097TT dB Gain-Bandwidth Product 1.6T MHz OUTPUTVoltage SwingI O = 5A, Continuous±(|V S | – 5.5)±(|V S | – 4.5)T T V I O = 2A ±(|V S | – 4.5)±(|V S | – 3.6)T T V I O = 0.5A±(|V S | – 4)±(|V S | – 3.2)T T V Current, Peak 910T T A AC PERFORMANCE Slew Rate610T T V/µs Power Bandwidth R L = 8Ω, V O = 20Vrms4555TT kHz Settling Time to 0.1%2V Step2Tµs Capacitive Load Specified Temperature Range, G = 1 3.3T nF Specified Temperature Range, G >10SOA (1)T Phase MarginSpecified Temperature Range, R L = 8Ω40T Degrees POWER SUPPLYPower Supply Voltage, ±V S Specified Temperature Range±10±30±35T±35±40V Current, Quiescent 2025TTmA THERMAL RESISTANCE θJC (Junction-to-Case)(2)AC Output f > 60Hz2.5°C/W θJC (2)DC Output 3°C/W θJA (Junction-to-Ambient)No Heat Sink40°C/W OPA541AP (Plastic)40°C/W TEMPERATURE RANGE T CASEAM, BM, AP–25+85T T °C SM–55+125°CT Specification same as OPA541AM/AP.NOTE: (1) SOA is the Safe Operating Area shown in Figure 1. (2) Plastic package may require insulator which typically adds 1°C/W.The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.3®OPA541CONNECTION DIAGRAMSORDERING INFORMATIONTEMPERATURECONTINUOUS PRODUCT PACKAGE RANGE CURRENT OPA541AP Power Plastic–25°C to +85°C 5A at 25°C OPA541AM TO-3–25°C to +85°C 5A at 25°C OPA541BM TO-3–25°C to +85°C 5A at 25°C OPA541SMTO-3–55°C to +125°C5A at 25°CABSOLUTE MAXIMUM RATINGSSupply Voltage, +V S to –V S ...............................................................80V Output Current.............................................................................see SOA Power Dissipation, Internal (1)...........................................................125W Input Voltage: Differential ....................................................................±V SCommon-mode.............................................................±V STemperature: Pin solder, 10s........................................................+300°CJunction (1)...............................................................+150°CTemperature Range:AM, BM SMStorage ....................................................................–65°C to +150°C Operating (case)......................................................–55°C to +125°C APStorage ......................................................................–40°C to +85°C Operating (case)........................................................–25°C to +85°C NOTE: (1) Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF.PACKAGE INFORMATIONPACKAGE DRAWINGPRODUCT PACKAGE NUMBER (1)OPA541AP Power Plastic242OPA541AM TO-3030OPA541BM TO-3030OPA541SMTO-3030NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.4®OPA5411010.10.010.001101001k 10k100kFrequency (Hz)T H D + N o i s e (%)TOTAL HARMONIC DISTORTION + NOISEvs FREQUENCY1k10010V o l t a g e N o i s e D e n s i t y (n V /√Hz )VOLTAGE NOISE DENSITYvs FREQUENCY1101001k10k100kFrequency (Hz)6543210012345678910I (A)OUT|±V | – |V | (V )OU T S OUTPUT VOLTAGE SWING vs OUTPUT CURRENT1.31.21.110.90.80.70.62030405060708090+V + |–V | (V)S SN o r m a l i z ed I NORMALIZED QUIESCENT CURRENT vs TOTAL POWER SUPPLY VOLTAGEQ1109070503010–101101001k 10k 100k 1M 10MFrequency (Hz)V o l t a g e G a i n (d B )OPEN-LOOP GAIN AND PHASEvs FREQUENCY–45–90–135–180P h a s e (D e g r e e s )–2502550751001251001010.10.010.001I n p u t B i as C u r r e n t (n A )Temperature (°C)INPUT BIAS CURRENT vs TEMPERATURETYPICAL PERFORMANCE CURVESAt T A = +25°C, V S = ±35VDC, unless otherwise noted.5®OPA5411201101009080706050101001k10k100k1MFrequency (Hz)C M R R (d B )COMMON-MODE REJECTIONvs FREQUENCY1010.10.010.1110R ( )ΩCL I (A )L I M I TCURRENT LIMIT vs RESISTANCE LIMITTYPICAL PERFORMANCE CURVES (CONT)At T A = +25°C, V S = ±35VDC, unless otherwise noted.Time (1µs/division)DYNAMIC RESPONSEV o l t a g e (2V /d i v i s i o n)1010.10.010.1110R ( )ΩCL I (A )L I M I TCURRENT LIMIT vs RESISTANCE LIMITvs TEMPERATURE6®OPA541θHS =T CASE – T AMBIENTP D (max)INSTALLATION INSTRUCTIONSPOWER SUPPLIESThe OPA541 is specified for operation from power supplies up to ±40V. It can also be operated from unbalanced power supplies or a single power supply, as long as the total power supply voltage does not exceed 80V. The power supplies should be bypassed with low series impedance capacitors such as ceramic or tantalum. These should be located as near as practical to the amplifier’s power supply pins. Good power amplifier circuit layout is, in general, like good high frequency layout. Consider the path of large power supply and output currents. Avoid routing these connections near low-level input circuitry to avoid waveform distortion and oscillations.CURRENT LIMITInternal current limit circuitry is controlled by a single external resistor, R CL . Output load current flows through this external resistor. The current limit is activated when the voltage across this resistor is approximately a base-emitter turn-on voltage. The value of the current limit resistor is approximately:(AM, BM, SM)R CL =– 0.057(AP)R CL =– 0.020.809|I LIM |0.813|I LIM |Because of the internal structure of the OPA541, the actual current limit depends on whether current is positive or negative. The above R CL gives an average value. For a given R CL , +I OUT will actually be limited at about 10% below the expected level, while –I OUT will be limited about 10% above the expected level.The current limit value decreases with increasing tempera-ture due to the temperature coefficient of a base-emitter junction voltage. Similarly, the current limit value increases at low temperatures. Current limit versus resistor value and temperature effects are shown in the Typical Performance Curves. Approximate values for R CL at other temperatures may be calculated by adjusting R CL as follows:The adjustable current limit can be set to provide protection from short circuits. The safe short-circuit current depends on power supply voltage. See the discussion on Safe Operating Area to determine the proper current limit value.Since the full load current flows through R CL , it must be selected for sufficient power dissipation. For a 5A current limit on the TO-3 package, the formula yields an R CL of 0.105Ω (0.143Ω on the power plastic package due to differ-ent internal resistances). A continuous 5A through 0.105Ωwould require an R CL that can dissipate 2.625W.∆R CL =x (T – 25)–2mV|I LIM |Sinusoidal outputs create dissipation according to rms load current. For the same R CL , AC peaks would still be limited to 5A, but rms current would be 3.5A, and a current limiting resistor with a lower power rating could be used. Some applications (such as voice amplification) are assured of signals with much lower duty cycles, allowing a current resistor with a low power rating. Wire-wound resistors may be used for R CL . Some wire-wound resistors, however, have excessive inductance and may cause loop-stability prob-lems. Be sure to evaluate circuit performance with resistor type planned for production to assure proper circuit opera-tion.HEAT SINKINGPower amplifiers are rated by case temperature, not ambient temperature as with signal op amps. Sufficient heat sinking must be provided to keep the case temperature within rated limits for the maximum ambient temperature and power dissipation. The thermal resistance of the heat sink required may be calculated by:Commercially available heat sinks often specify their ther-mal resistance. These ratings are often suspect, however,since they depend greatly on the mounting environment and air flow conditions. Actual thermal performance should be verified by measurement of case temperature under the required load and environmental conditions.No insulating hardware is required when using the TO-3package. Since mica and other similar insulators typically add approximately 0.7°C/W thermal resistance, their elimi-nation significantly improves thermal performance. See Burr-Brown Application Bulletin AB-038 for further details on heat sinking. On the power plastic package, the metal tab is connected to –V S , and appropriate actions should be taken when mounting on a heat sink or chassis.SAFE OPERATING AREAThe safe operating area (SOA) plot provides comprehensive information on the power handling abilities of the OPA541.It shows the allowable output current as a function of the voltage across the conducting output transistor (see Figure 1). This voltage is equal to the power supply voltage minus the output voltage. For example, as the amplifier output swings near the positive power supply voltage, the voltage across the output transistor decreases and the device can safely provide large output currents demanded by the load.7®OPA541FIGURE 1. Safe Operating Area.Short circuit protection requires evaluation of SOA. Whenthe amplifier output is shorted to ground, the full power supply voltage is impressed across the conducting output transistor. The current limit must be set to a value which is safe for the power supply voltage used. For instance, with V S ±35V, a short to ground would force 35V across the conduc-ting power transistor. A current limit of 1.8A would be safe.Reactive, or EMF-generating, loads such as DC motors can present difficult SOA requirements. With a purely reactive load, output voltage and load current are 90° out of phase.Thus, peak output current occurs when the output voltage is zero and the voltage across the conducting transistor is equal to the full power supply voltage. See Burr-Brown Applica-tion Bulletin AB-039 for further information on evaluating SOA.REPLACING HYBRID POWER AMPLIFIERSThe OPA541 can be used in applications currently using various hybrid power amplifiers, including the OPA501,OPA511, OPA512, and 3573. Of course, the application must be evaluated to assure that the output capability and other performance attributes of the OPA541 meet the neces-sary requirement. These hybrid power amplifiers use two current limit resistors to independently set the positive and negative current limit value. Since the OPA541 uses only one current limit resistor to set both the positive and negative current limit, only one resistor (see Figure 4) need be installed. If installed, the resistor connected to pin 2 (TO-3package) is superfluous, but it does no harm.Because one resistor carries the current previously carried by two, the resistor may require a higher power rating.Minor adjustments may be required in the resistor value to achieve the same current limit value. Often, however, the change in current limit value when changing models is small compared to its variation over temperature. Many applica-tions can use the same current limit resistor.FIGURE 3. Isolating Capacitive Loads.APPLICATIONS CIRCUITSFIGURE 2. Clamping Output for EMF-Generating Loads.FIGURE 4. Replacing OPA501 with OPA541.8®OPA541FIGURE 5. Paralleled Operation, Extended SOA.FIGURE 6. Programmable Voltage Source.FIGURE 7. 16-Bit Programmable Voltage Source.。

MKP3384X2中文资料

• 15 to 55 mm lead pitch • Supplied loose in box • Consists of a low-inductive wound cell of metallized polypropylene film, potted in a flame-retardant case • Fixed and insulated leads.
BCcomponents
DATA SHEET
MKP 338 4 X2 Interference suppression film capacitors
Product Specification NEW File under BCcomponents, BC05 2001 Jun 22
BCcomponents
MKP 338 4 X2
MULTIPLIER (nF) 1 10 100 1000 3 4 5 6
X2
Example: 104 = 10 x 10 = 100 nF
2222
338
4.
XX X
TYPE 338 4
PACKAGING loose in box taped
LEAD CONFIGURATION lead length 3.5 mm lead length 5.0 mm lead length 25.0 mm 15.0 mm bent back to 7.5 mm insulated leads stranded Cu-wire 0.5 mm2 for 37.5 and 55 mm pitch lead length 3.5 mm
• For X2 electromagnetic interference suppression • Specially designed to meet the requirements of the “IEC 60384-14 2nd edition and EN 132400”, requiring a 2.5 kV peak pulse voltage test, and the UL1283 specifications.

Pyle Pro PTA4 2x120W 立体声放大器用户手册说明书

PTA42x120W Max Stereo Power Amplifierwith AUX CD/MP3 Input and MIC PAGER1 - Pyle Pro PTA4 ManualYour new Pyle Pro PTA4 Stereo Power Amplifiergives you the power and versatility you need in a professional sound system.Its wide frequency response make it suitable for amplifying music or vocalprogram material.The front located 3.5mm jack allows you to connect the input of various ofMP3 devices conveniently and the MIC PAGER/MIXING function offers theflexibility of using it at paging or musical events. It can be used formeeting halls, house, restaurant, school, stores, live bands, or office.FEATURES AND CONTROLSPyle Pro PTA4 Manual - 2FEATURES AND CONTROLS(1) Blue LED Output Level Display(2) Power On/Off and LED IndicatorMain power switch, the indicator lights when the amplifier is turned on.(3) CD/MP3 3.5mm AUX Input Jack (FRONT)Lets you easily connect the computerized MP3 Device (player) sources,such as PC (CD ROM), Laptop, Walkman, iPod, and Cell Phone.(4) 1/4" PHONE JackAccepts headphones with 1/4" plug.(5) MIC Volume ControlLets you adjust the volume of connected MIC to the proper setting.(6) MASTER Volume ControlLets you control the overall volume level. It doesn't affect the volume of MIC.(7) BALANCE ControlLets you adjust the sound balance between the left and right of amplifier outputs.(8) BASS and TREBLE ControlsAllows you to boost or attenuate bass and treble for the desired sound.(9) AUX 1/AUX 2/CD Input SelectorLets you select the desired input music source.(10) Switchable MIC PAGER and MIXING ModesSet to PAGER, the signal from AUX 1/AUX 2/CD will be attenuated BY -12dB and the signal from MIC will override to page (Auto Talkover), it is good for paging system. Set to MIXING, the signals fromAUX 1/AUX 2/CD and MIC will be existed at the same time, it acts like playing at KARAOKE event. (11) 1/4" MIC Input JackLets you connect a microphone with a 1/4" plug.(12) AUX 1/AUX 2/CD RCA InputsLets you connect most high level audio sources such as CD player, tape deck, tuner, camcorder, or VCR.(13) REC RCA OutputLets you connect the amplifier to a tape deck for recording.(14) Push Type Speaker TerminalLets you easily connect speaker wires directly to the amplifier. The speaker impedance can be ranged from 4 to 8 Ohms for the general stereo output. The total speaker impedance must be at least 4-Ohm per channel at stereo mode.(15) 110/220 Voltage SelectorThis amplifier has selectable input voltage from 110V/60Hz (the standard in USA and CANADA) to220V/50Hz (for EUROPEAN operation). Please make sure the switch is in the proper position before operating, otherwise, the severe damage will be incurred and not covered by the warranty.(16) Replaceable Power FuseThe amplifier uses a fuse for protection against surges and short circuit. If the amplifier suddenly turns off and will not turn on, check the fuse and if necessary replace it with a 1.5-amp, 250-volt, fast-acting,5x20mm fuse (not supplied).3 - Pyle Pro PTA4 ManualCONNECTION DIAGRAMPyle Pro PTA4 Manual - 4SpecificationsOutput Power, 2 channels driven4-Ohm, 1 kHz, 1% THD .............................................................................. 20Wx2 4-Ohm, 1 kHz, 10% THD ............................................................................. 32Wx2 Max Power .................................................................................................120Wx2T otal Harmonic Distortion, 1 kHz Rated Power ................................................ 0.3%Input Sensitivity, 1 kHz, 4-Ohm Rated PowerAUX 1 .......................................................................................................... 250mV AUX 2 .......................................................................................................... 250mV CD ............................................................................................................... 250mV MIC .............................................................................................................. 2.5mVFrequency Response ........................................................................... 20Hz-40kHzSignal to Noise Ratio, 1 kHz, 4-Ohm Rated PowerAUX 1 ............................................................................................................ 80dB AUX 2 ............................................................................................................ 80dB CD ................................................................................................................. 80dB MIC ................................................................................................................ 70dBT one ControlsBASS ............................................................................................. +/-12dB, 100Hz TREBLE ......................................................................................... +/-12dB, 10kHzPower Requirement ................................................. 120V AC 60Hz/230V AC 50Hz Power Fuse ......................................................... 1.5 A, 250V fast-acting, 5x20mm Dimensions, inches (mm) WxHxD ..................... 8.27 x 2.72 x 5.39 (210 x 69 x 137) Weight, lbs (kg) ........................................................................................ 5.68(2.58)Specifications are typical; individual units might vary.Specifications are subject to change and improvement without notice.5 - Pyle Pro PTA4 ManualPyle Pro PTA4 Manual - 6Your Pyle Pro Amplifier is an example of superior design and craftsmanship. The following suggestions will help you care for your amplifier so you can enjoy years of use:Keep the amplifier dry. If it gets wet, wipe immediately.Use the amplifier only in well-ventilated installations.Handle the amplifier gently and carefully - do nto drop!Keep the amplifier away from dust adn dirt.Wipe occasionally with a damp cloth to keep it looking new.Do not use harsh chemicals, solvents or detergents!7 - Pyle Pro PTA4 Manual。

几种运算放大器的简单介绍

几种运算放大器的简单介绍学号：2120110996 姓名：肖辅荣学院：自动化学院一，通用型运算放大器μA741通用型运放是现在运用最多的运放，常用的通用型运放有μA741（单运放）、LM358（双运放）、LM324（四运放）等，下面介绍μA741的原理和功能。

如图1所示为其引脚定义图，其中，V CC+和V CC-分别为其正电源和负电源，IN+为其同相输入端，IN-为其反向输入端，OUT为其输出端，OFFSET N1和OFFEST N2为调零端。

主要参数及优点：（1）：电源电压范围宽：单电源（3～30 V），双电源（±1.5～±15 V）。

（2）：输出电压摆幅大（V CC-+1.5 V至V CC+—1.5 V）。

（3）：短路保护；（4）：芯片运行温度根据型号的不同而不同，如μA741C工作温度为0～70 °C，而μA741M 工作温度则为—55～125 °C。

=±15 V、工作温度是25 °C时，输入电压偏移为1 mV，最大为6 mV；输入（5）：V CC±电阻为2 MΩ；输出电阻为7 Ω；无负载时功率损失为50 mW；共模抑制比为90 dB；共模输入电压范围为±13 V；短路输出电流为±25 mA；上升时间为0.3 µs。

二，高阻型运算放大器CA3130是一种集合了CMOS管和双极性晶体管的双重优势的运算放大器。

其输入端为PMOS晶体管，这种结构可以提供非常高的输入阻抗，非常低的输入电流以及非常优越的速度性能；并且可以有效地降低输入端的共模电压的影响。

其输出采用得是一对CMOS管来提供输出电流，并且能保证输出电压相对每一个电源提供端的电压偏差都在10mv之内。

而且CA3130既可以用单电源也可以双电源来供电，单电源供电范围为5v到8V，双电源供电范围为正负2.5V到正负5V之间。

该运放的引脚图如右图所示：引脚1,5为偏置输入，3,2为同相反相输入，7,4为电源输入引脚，8为输出滤波，6输出。

KE04子系列数据手册说明书

MKE04P24M48SF0 KE04子系列数据手册支持以下产品：MKE04Z8VTG4(R)、MKE04Z8VWJ4(R)和MKE04Z8VFK4(R)主要功能•工作范围–电压范围：2.7至5.5 V–Flash编程电压范围：2.7至5.5 V–温度范围（环境）：-40至105°C•性能–最高48 MHz的ARM® Cortex-M0+内核–单周期32位 x 32位乘法器–单周期I/O访问端口•存储器和存储器接口–最高8 KB的Flash–最高1 KB的RAM•时钟–振荡器(OSC) - 支持32.768 kHz晶振或4 MHz至24 MHz晶振或陶瓷谐振器；可选择低功耗或高增益振荡器–内部时钟源(ICS) - 内部FLL，集成内部或外部基准时钟源、37.5 kHz预校准内部基准时钟源，可用于48 MHz系统时钟–内部1 kHz低功耗振荡器(LPO)•系统外设–电源管理模块(PMC)有三个功率模式：运行、待机和停止–可复位、中断并带可选跳变点的低压检测(LVD)–带独立时钟源的看门狗(WDOG)–可配置循环冗余校验(CRC)模块–串行线调试(SWD)接口–SRAM位操作映射区域(BIT-BAND)–位处理引擎(BME)•安全性和完整性模块–每个芯片拥有80位唯一标识(ID)号•人机接口–最多22个通用输入/输出(GPIO)–两个8位键盘中断(KBI)模块–外部中断(IRQ)模块•模拟模块–一个12通道，12位SAR ADC，可工作在停止模式，可选硬件触发源(ADC)–两个包含6位DAC和可配置参考输入的模拟比较器(ACMP)•定时器–一个6通道FlexTimer/PWM (FTM)–一个2通道FlexTimer/PWM (FTM)–一个2通道周期性中断定时器(PIT)–一个脉宽计数器(PWT)–一个实时时钟(RTC)•通信接口–一个SPI模块(SPI)–一个UART模块(UART)–一个I2C模块(I2C)•封装选项–24引脚QFN–20引脚SOIC–16引脚TSSOPFreescale Semiconductor数据手册: 技术数据Rev 3, 3/2014 Freescale reserves the right to change the detail specifications as may berequired to permit improvements in the design of its products.© 2013 Freescale Semiconductor, Inc.目录1订购器件 (3)1.1确定有效的可订购器件 (3)2器件标识 (3)2.1说明 (3)2.2格式 (3)2.3字段 (3)2.4示例 (4)3参数分类 (4)4额定值 (4)4.1热学操作极限 (4)4.2湿度操作极限 (5)4.3ESD操作额定值 (5)4.4电压和电流操作额定值 (5)5通用 (6)5.1静态电气规格 (6)5.1.1DC特性 (6)5.1.2电源电流特性 (12)5.1.3EMC性能 (13)5.2动态规格 (14)5.2.1控制时序 (14)5.2.2FTM模块时序 (15)5.3热规格 (16)5.3.1热特性 (16)6模块工作要求和行为 (17)6.1内核模块 (17)6.1.1SWD电气规格 (17)6.2外部振荡器(OSC)和ICS特性 (18)6.3NVM规格 (20)6.4模拟 (21)6.4.1ADC特性 (21)6.4.2模拟比较器(ACMP)电气规格 (23)6.5通信接口 (24)6.5.1SPI开关规格 (24)7尺寸 (27)7.1获取封装尺寸 (27)8引脚分配 (27)8.1信号多路复用和引脚分配 (27)8.2器件引脚分配 (29)9修订历史 (30)订购器件1.1确定有效的可订购器件有效可订购器件编号已发布在网络上。

FLUKE示波表的使用手册

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低噪声OPA4134_datasheet

PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
AUDIO PERFORMANCE Total Harmonic Distortion + Noise
Intermodulation Distortion Headroom(1) FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate(2) Full Power Bandwidth Settling Time 0.1%
TEMPERATURE RANGE Specified Range Operating Range Storage Thermal Resistance, θJA
8-Pin DIP SO-8 Surface-Mount 14-Pin DIP SO-14 Surface-Mount
IO = 0
±15
±2.5
vs Temperature vs Power Supply (PSRR) Channel Separation (Dual, Quad)
INPUT BIAS CURRENT Input Bias Current(4)
vs Temperature(3) Input Offset Current(4) INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection
APPLICATIONS
q PROFESSIONAL AUDIO AND MUSIC q LINE DRIVERS q LINE RECEIVERS q MULTIMEDIA AUDIO q ACTIVE FILTERS q PREAMPLIFIERS q INTEGRATORS q CROSSOVER NETWORKS

OPA121资料

V
82
100
dB
106
114
dB
2
MHz
32Leabharlann kHz2V/µs
6
µs
10
µs
5
µs
±11
±12
V
±5.5
±10
mA
100
Ω
1000
pF
10
40
mA
±15
VDC
±5
±18
VDC
2.5
4.5
mA
0
+70
°C
–25
+85
°C
–55
+125
°C
150(4)
°C/W
NOTES: (1) Sample tested. (2) Offset voltage, offset current, and bias current are specified with the units fully warmed up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) 100°C/W for KU grade.
Standard 741 pin configuration allows upgrading of existing designs to higher performance levels.
APPLICATIONS
q OPTOELECTRONICS q DATA ACQUISITION q TEST EQUIPMENT q MEDICAL EQUIPMENT q RADIATION HARD EQUIPMENT

MPR121中文数据手册

Device Name MPR121QR2
Temperature Range -40°C to +85°C
ORDERING INFORMATION
Case Number
Touch Pads
2059 (20-Pin QFN)
12-pads
MPR121 Rev 0, 9/2009
MPR121
Capacitive Touch Sensor Controller
© Freescale Semiconductor, Inc., 2009. All rights reserved.
简图和实施
VDD 1.71 V至2.75 V
VDD 1.71 V至2.75 V
0.1 μF GND
20 VDD 6 VSS 5 VREG 1 IRQ 2 SCL 3 SDA 4 ADDR 7 REXT
接近传感
一项新功能的MPR121接近感应系统,使系统的电极,可缩短使用
一起内部,创建一个大的电极.这种电极的电容是较大的和预计的电容可以
被测量.当启用时,这个“13
th“电极将被包含在一个正常的检测周期的末尾,将有自己的
独立设置的配置寄存器.此系统被描述在应用笔记AN3893.
LED驱动器
MPR121包括8个共享的LED驱动销.当这些引脚不作为电极的配置,它们可以被用于驱动LED.该系统可以为上拉和下拉LED配置,以及作为通用GPIO推/拉功能. 应用笔记AN3894中描述的结构的LED驱动器系统.
Freescale Semiconductor Technical Data
Advanced Information Proximity Capacitive Touch Sensor Controller

11种运放的听音主观对比

11种运放的听音主观对比测试平台：误差矫正功放软件平台：超过30张进口发烧CD。

有铝碟、金碟、HDCD金碟、JVC公司出品的XR2代的CD、KKV公司产品的FXCD，如《许茹云茹此精彩金碟》、《齐秦10年精选双CD金碟》、《悲情城市》、《迈克尔.杰克逊危险之旅》、《蓝雨衣》、《雨果发烧碟9 HDCD版》、《许美静静听精彩13首》等。

型号有: JRC4558DST LF353NNS LM833NTI/BB OPA2132PA, OPA2604AP, OPA2111KP大S NE5532NPhilips NE5532ANTI NE5532PAD AD827JN, OP285GLT LT1057ACN8经过一天的主观听音对比，终于有了结果。

结论是：任何一个牌子的5532都是值得的，尤其是尾缀带A的，for audio，其性能专为音频应用而优化。

更值得称赞的是，可以超出双22V的极限工作电压，在双28V正常工作5、6个小时，其表面温度达到五六十度。

其他型号的运放只能在其规格书上所讲的最大工作电压，一般是20V，在22V能工作的没几个。

LT1057超过20V就会立即保护，其他IC的音质就劣化，输出端出现很大直流漂移电压，甚至损坏。

JRC4558D作为最普通、最廉价的音频运放，在低成本音频产品上大量应用。

主观听音上，低音几乎没有，在中音上，可以让普通的耳朵接受，高音发飘，受转换速率的限制，细微之处是听不到了。

先天性不足，只能到这个份上了，几毛钱的东西，只能是发声级的要求。

ST LF353N曾经作为四大运放，现在已经让人淡忘了。

从参数上看，指标也不算差了。

只能在一些高速伺服电源电路上还能见到。

实际听音的结果，让人大感超值，还算对得起过去的称号。

低音量够，就是有点混，中高音都很清晰，典型的美国声。

NS LM833N在NS的宣传资料上，说跟NE5532在指标和听感上最接近的音频IC。

实际听感上，低音比NE5532的好，是这11个IC里低音量最足的，中高音稍微逊色些。