VHDL程序设计数字电子表2收集资料

-- 子文件定义代码
ARCHITECTURE a OF COUNTER24 IS
ENB (0)
NUM(4)
CYH
BCD 选择
BCD (7-4)
BCD (3-0)
24
进CYM制计源自器DBH60进
CYS
制
计数器
DBM
60 进 制 计数器
DBS
BCD(8)BIN(6)
BIN ( 6 )
CLR
38
6 个七段数码管
译
码
SEG (8)
时钟显示 电路方框图
CP 分频器Q SEC
BCD 七段译码电路
ELSIF CP'event AND CP = '1' THEN DLY <= Q(5); IF EC = '1' THEN Q <= Q+1; END IF;
END IF; END PROCESS;
END a;
CY60 <= NOT Q(5) AND DLY; RST <= '1' WHEN Q=60 OR CLR='1' ELSE
-- 子文件定义代码 --*************************************************** LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --*************************************************** ENTITY COUNTER60 IS PORT(
END PROCESS;
Free_Counter : Block Signal Q Signal DLY
Begin
: STD_LOGIC_VECTOR(24 DOWNTO 0); : STD_LOGIC;
PROCESS (CP) Begin
IF CP'Event AND CP='1' then DLY <= Q(21); Q <= Q+1;
CP : IN STD_LOGIC; BIN : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); S : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY60 : OUT STD_LOGIC ); END COUNTER60;
CP : IN STD_LOGIC; BIN : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); S : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY24 : OUT STD_LOGIC ); END COUNTER24;
BIN <=
DBS WHEN ENB = "001" ELSE DBM WHEN ENB = "010" ELSE DBH WHEN ENB = "100" ELSE "000000";
End Block Free_Counter;
--主文件声明代码
COMPONENT COUNTER60 PORT(
-- 子文件定义代码
ARCHITECTURE a OF COUNTER60 IS SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC;
BEGIN
PROCESS (CP,RST) BEGIN
IF RST = '1' THEN Q <= "000000";
CP : IN STD_LOGIC; BIN : OUTSTD_LOGIC_VECTOR (5 DOWNTO 0); S : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY60 : OUT STD_LOGIC ); END COMPONENT;
END IF; END PROCESS;
SEC <= Q(21) AND NOT DLY; S <= Q(15 DOWNTO 13);
--about 1Hz --about 250 Hz
ENB <=
"001" WHEN (S=0 OR S=1) ELSE "010" WHEN (S=2 OR S=3) ELSE "100" WHEN (S=4 OR S=5) ELSE "000";
-- 子文件定义代码 --*************************************************** LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --*************************************************** ENTITY COUNTER24 IS PORT(
第六章 VHDL综合应用
数字电子时钟显示电路
6 个七段数码管 SEGOUT ( 8 )
时钟显示 电路方框图
SELOUT ( 6 )
FPGA
CLR
CP
38
6 个七段数码管
译
码
SEG (8)
时钟显示 电路方框图
CP 分频器Q SEC
BCD 七段译码电路
ENB (2)
扫描电路 S(3)
ENB (1)
'0'; BIN <= Q WHEN S = '1' ELSE
"000000";
--主文件声明代码
COMPONENT COUNTER24 PORT(
CP : IN STD_LOGIC; BIN : OUTSTD_LOGIC_VECTOR (5 DOWNTO 0); S : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY60 : OUT STD_LOGIC ); END COMPONENT;
ENB (2)
扫描电路 S(3)
ENB (1)
ENB (0)
NUM(4)
CYH
BCD 选择
BCD (7-4)
BCD (3-0)
24
进
CYM
制
计数器
DBH
60
进
CYS
制
计数器
DBM
60 进 制 计数器
DBS
BCD(8)BIN(6)
BIN ( 6 )
CLR
PROCESS (CP) Begin IF CP'Event AND CP='1' then DLY <= Q(21); Q <= Q+1; END IF;