实验五_ALU的VHDL设计

实验五ALU的VHDL设计完成如表所示ALU的VHDL设计
控制信号S 运算
000
算术运算A+B；A+B+1
001 A-B ；A-B-1 010 A；A+1 011 A；A-1
100
逻辑运算AB
101 A+B
110 A⊕B
111
A
library ieee; ------库程序包调用
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu4 is ------实体：电路外观配置port
( a:in unsigned(3 downto 0);
b:in unsigned(3 downto 0);
cin:in std_logic;
s:in std_logic_vector(2 downto 0);
bcdout:out std_logic_vector(3 downto 0);
cout: out std_logic
);
end alu4;
architecture arch of alu4 is ------结构体：电路功能描述signal c:std_logic_vector(3 downto 0);
signal q:unsigned(3 downto 0);
begin
process(s)
begin
case s is
when "000"=> ------加法：A+B ;A+B+1
q(0)<=a(0)xor b(0)xor cin;
c(0)<=(a(0) and b(0))or (b(0)and cin)or (a(0)and cin);
gen1:for i in 1 to 3 loop
q(i)<=a(i)xor b(i)xor c(i-1);
c(i)<=( a(i) and b(i))or (b(i)and c(i-1))or (a(i)and c(i-1));
end loop;
bcdout<=q(3)&q(2)&q(1)&q(0);
cout<=c(3);
when "001"=> ------减法：A-B ;A-B-1
q(0)<=a(0)xor b(0)xor cin;
c(0)<=(not a(0) and b(0))or (b(0)and cin)or (not a(0)and cin);
gen2:for i in 1 to 3 loop
q(i)<=a(i)xor b(i)xor c(i-1);
c(i)<=(not a(i) and b(i))or (b(i)and c(i-1))or (not a(i)and c(i-1));
end loop;
bcdout<=q(3)&q(2)&q(1)&q(0);
cout<=c(3);
when "010"=>
if cin='0'then
bcdout<=a(3)&a(2)&a(1)&a(0); --传递进位Cin=0 else
bcdout<=a+1; --执行a+1
end if;
cout<='0';
when "011"=>
if cin='0'then
bcdout<=a(3)&a(2)&a(1)&a(0);--传递借位Cin=0 else
bcdout<=a-1; --执行a-1
end if;
cout<='0';
when "100"=> --逻辑与：AB
q(3)<=a(3)and b(3);
q(2)<=a(2)and b(2);
q(1)<=a(1)and b(1);
q(0)<=a(0)and b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when "101"=> --逻辑或：A+B
q(3)<=a(3)or b(3);
q(2)<=a(2)or b(2);
q(1)<=a(1)or b(1);
q(0)<=a(0)or b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when "110"=> --异或：A⊕B
q(3)<=a(3)xor b(3);
q(2)<=a(2)xor b(2);
q(1)<=a(1)xor b(1);
q(0)<=a(0)xor b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when others=> --逻辑非：A
bcdout<=not a(3)& not a(2)& not a(1)& not a(0);
cout<='0';
end case;
end process;
end arch;
1、波形仿真分析
时间控制信号S 进位C 运算(A=6,B=B) 结果bcdout 0—30ns 000 0 A+B（算术加）0001即1 30—60ns 001 1 A-B-1 1010 即A 60—90ns 010 0 A 0110 即6 90—120ns 011 1 A-1 0101 即5 120—150ns 100 x AB 0010 即2 150—180ns 101 x A+B（逻辑或）1111 即F 180—210ns 110 x A⊕B 1101 即D 210—240ns 111 x
A1001 即9 2、延时仿真分析
每对连接的节点输入信号(source)和输出信号(destination)之间最小/最大传播延迟。

实验五报告格式要求：
实验名：ALU的VHDL设计一、实验目的：
ALU的VHDL设计
二、实验要求
Max+Plus II开发环境
三、源程序代码
ALU的VHDL设计：
……………
…………….
…………………
四、波形仿真
（1）波形仿真图
（2）波形仿真分析
五、延时仿真
（1）延时仿真图
（2）延时仿真分析
六、实验总结
控制信号S 运算
000
算术运算A+Badd
001 A-Bsub 010 b
a⨯mul 011 b
a÷div
100
逻辑运算ABand
101 A+Bor
110 A⊕Bxor
111
A not
when "100"=> --逻辑与：AB
q(3)<=a(3)and b(3);
q(2)<=a(2)and b(2);
q(1)<=a(1)and b(1);
q(0)<=a(0)and b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when "101"=> --逻辑或：A+B
q(3)<=a(3)or b(3);
q(2)<=a(2)or b(2);
q(1)<=a(1)or b(1);
q(0)<=a(0)or b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when "110"=> --异或：A⊕B
q(3)<=a(3)xor b(3);
q(2)<=a(2)xor b(2);
q(1)<=a(1)xor b(1);
q(0)<=a(0)xor b(0);
bcdout<=q(3)&q(2)&q(1)&q(0);
when others=> --逻辑非：A
bcdout<=not a(3)& not a(2)& not a(1)& not a(0);
cout<='0';。