LM3S9B96SAFERTOS介绍
LM3S9B95开发板核心板原理图0
Stellaris® LM3S9B96 Development Kit User’s ManualCopyrightCopyright © 2009 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Texas Instruments108 Wild Basin, Suite 350Austin, TX 78746Main: +1-512-279-8800Fax: +1-512-279-8879Stellaris® LM3S9B96 Development Kit User’s ManualTable of ContentsChapter 1: Stellaris® LM3S9B96 Development Board Overview (7)Features (7)Development Kit Contents (10)Block Diagram (11)Development Board Specifications (11)Chapter 2: Stellaris® LM3S9B96 Development Board Hardware Description (13)LM3S9B96 Microcontroller Overview (13)Jumpers and GPIO Assignments (13)Clocking (14)Reset (15)Power Supplies (15)USB (15)Debugging (16)Color QVGA LCD Touch Panel (17)I2S Audio (19)User Switch and LED (19)Chapter 3: Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI) (21)SDRAM Expansion Board (21)Flash and SRAM Memory Expansion Board (21)Chapter 4: Using the In-Circuit Debugger Interface (23)Appendix A: Stellaris® LM3S9B96 Development Board Schematics (25)Appendix B: Stellaris® LM3S9B96 Development Board Component Locations (33)Appendix C: Stellaris® LM3S9B96 Development Board Connection Details (35)DC Power Jack (35)ARM Target Pinout (35)Appendix D: Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments (37)Appendix E: Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board (41)Installation (41)Features (42)Hardware Description (43)Functional Description (43)Memory Map (45)Component Locations (46)Schematics (46)Appendix F: References (49)List of FiguresFigure1-1.DK-LM3S9B96 Development Board (9)Figure1-2.DK-LM3S9B96 Development Board Block Diagram (11)Figure2-1.Factory Default Jumper Settings (14)Figure4-1.ICD Interface Mode (23)Figure ponent Placement Plot for Top (34)Figure E-1.DK-LM3S9B96-EXP-FS8 Board Image (41)Figure E-2.DK-LM3S9B96 Development Board (42)Figure E-3.DK-LM3S9B96-EXP-FS8 Flash/SRAM/LCD IF Expansion Board Block Diagram (43)Figure ponent Placement Plot for Top and Bottom (46)Stellaris® LM3S9B96 Development Kit User’s ManualList of TablesTable2-1.Board Features and Peripherals that are Disconnected in Factory Default Configuration (13)B-Related Signals (15)Table2-3.Hardware Debugging Configurations (16)Table2-4.Debug-Related Signals (17)Table2-5.LCD-Related Signals (18)Table2-6.I2S Audio-Related Signals (19)Table2-7.Navigation Switch-Related Signals (19)Table C-1.Debug Interface Pin Assignments (35)Table D-1.Microcontroller GPIO Assignments (37)Table E-1.Flash and SRAM Memory Expansion Board Memory Map (45)Table E-2.LCD Latch Register (45)C H A P T E R1Stellaris® LM3S9B96 Development Board Overview The Stellaris® LM3S9B96 Development Board provides a platform for developing systems aroundthe advanced capabilities of the LM3S9B96 ARM® Cortex™-M3-based microcontroller.The LM3S9B96 is a member of the Stellaris Tempest-class microcontroller family. Tempest-classdevices include capabilities such as 80MHz clock speeds, an External Peripheral Interface (EPI)and Audio I2S interfaces. In addition to new hardware to support these features, theDK-LM3S9B96 board includes a rich set of peripherals found on other Stellaris boards.The development board includes an on-board in-circuit debug interface (ICDI) that supports bothJTAG and SWD debugging. A standard ARM 20-pin debug header supports an array of debuggingsolutions.The Stellaris® LM3S9B96 Development Kit accelerates development of Tempest-classmicrocontrollers. The kit also includes extensive example applications and complete source code. FeaturesThe Stellaris® LM3S9B96 Development Board includes the following features.Simple set-up—USB cable provides debugging, communication, and powerFlexible development platform with a wide range of peripheralsColor LCD graphics display–TFT LCD module with 320 x 240 resolution–Resistive touch interface80 MHz LM3S9B96 microcontroller with 256 K Flash, 96 K SRAM, and integrated EthernetMAC+PHY, USB OTG, and CAN communications–– 8 MB SDRAM (plug-in EPI option board)–– EPI break-out board (plug-in option board)1MB serial Flash memoryPrecision 3.00V voltage referenceSAFE RTOS™ operating system in microcontroller ROMI2S stereo audio codec–Line In/Out–Headphone Out–Microphone InController Area Network (CAN) Interface10/100 BaseT EthernetUSB On-The-Go (OTG) Connector–Device, Host, and OTG modesUser LED and push buttonThumbwheel potentiometer (can be used for menu navigation)MicroSD card slotSupports a range of debugging options–Integrated In-circuit Debug Interface (ICDI)–JTAG, SWD, and SWO all supported–Standard ARM® 20-pin JTAG debug connectorUSB Virtual COM PortJumper shunts to conveniently reallocate I/O resourcesDevelop using tools supporting the DK-LM3S9B96 from Keil, IAR, Code Sourcery, and Code RedSupported by StellarisWare® software including the graphics library, the USB library, and the peripheral driver libraryAn optional Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) is also available for use with the DK-LM3S9B96 development board–Works with the External Peripheral Interface (EPI) of the Stellaris microcontroller–Provides Flash memory, SRAM, and an improved performance LCD interfaceFor more information on the DK-LM3S9B96-EXP-FS8 memory expansion board, seeAppendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.The DK-LM3S9B96-EXP-FS8 memory expansion board is available for purchase separately.Stellaris® LM3S9B96 Development Kit User’s Manual Figure1-1.DK-LM3S9B96 Development BoardAudio Line Output1MB Serial Flash Memory3.5" LCD Touch PanelDevelopment Kit ContentsThe Stellaris® LM3S9B96 Development Kit contains everything needed to develop and run arange of applications using Stellaris microcontrollers:LM3S9B96 development board8MB SDRAM expansion boardEPI signal breakout boardRetractable Ethernet cableUSB Mini-B cable for debugger useUSB Micro-B cable for OTG-to-PC connectionUSB Micro-A to USB A adapter for USB HostUSB Flash memory stickmicroSD Card20-position ribbon cableCDs containing evaluation versions of the following tools:–StellarisWare with example code for this board–ARM RealView® Microcontroller Development Kit (MDK)–IAR Embedded Workbench® Kickstart Edition–Code Red Technologies Red Suite™–CodeSourcery Sourcery G++™ GNU tools.Stellaris® LM3S9B96 Development Kit User’s Manual Block DiagramFigure1-2.DK-LM3S9B96 Development Board Block DiagramDevelopment Board SpecificationsBoard supply voltage: 4.75–5.25 Vdc from one of the following sources:–Debugger (ICDI) USB cable (connected to a PC)–USB Micro-B cable (connected to a PC)–DC power jack (2.1x5.5mm from external power supply)Break-out power output: 3.3 Vdc (100 mA max)Dimensions (excluding LCD panel):– 4.50” x 4.25” x 0.60” (LxWxH) with SDRAM board– 4.50” x 4.25” x 0.75” (LxWxH) with EPI breakout boardAnalog Reference: 3.0V +/-0.2%RoHS status: CompliantNOTE:When the LM3S9B96 Development Board is used in USB Host mode, the host connector is capable of supplying power to the connected USB device. The available supply current is limited to ~200mA unless the development board is powered from an external 5Vsupply with a =600mA rating.C H A P T E R2Stellaris® LM3S9B96 Development Board Hardware DescriptionIn addition to an LM3S9B96 microcontroller, the development board includes a range of usefulperipheral features and an integrated in-circuit debug interface (ICDI). This chapter describes howthese peripherals operate and interface to the microcontrollerLM3S9B96 Microcontroller OverviewThe Stellaris LM3S9B96 is an ARM Cortex-M3-based microcontroller with 256-KB flash memory,80-MHz operation, Ethernet, USB, EPI, SAFE RTOS™ in ROM, and a wide range of peripherals.See the LM3S9B96 Microcontroller Data Sheet (order number DS-LM3S9B96) for completemicrocontroller details.The LM3S9B96 microcontroller is factory-programmed with a quickstart demo program. Thequickstart program resides in on-chip flash memory and runs each time power is applied, unlessthe quickstart has been replaced with a user program.Jumpers and GPIO AssignmentsEach peripheral circuit on the development board is interfaced to the LM3S9B96 microcontrollerthrough a 0.1” pitch jumper/shunt. Figure2-1 on page 14 shows the factory default positions of thejumpers. The jumpers must be in these positions for the quickstart demo program to functioncorrectly.The development board offers capabilities that the LM3S9B96 cannot support simultaneously dueto pin count and GPIO multiplexing limitations. For example, as configured, the board does notsupport SDRAM and I2S receive (microphone or line input) functions at the same time. Thejumpers associated with I2S receive are omitted in the default configuration.Table2-1 lists all features and peripherals that are disconnected in the factory defaultconfiguration. Using these peripherals requires that other peripherals be disconnected.Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,” onpage 37 lists alternative jumper configurations used in conjunction with some of theStellarisWare™ example applications for this board.Table2-1.Board Features and Peripherals that are Disconnected in Factory DefaultConfigurationPeripheral JumpersI2S Receive (Audio Input)JP44, 45, 47, 49Controller Area Network (CAN) JP14, 15Ethernet Yellow Status LED (LED2)JP2Analog 3.0V Reference JP33See Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,”on page 37, for a complete list of GPIO assignments. The table lists all default and alternateassignments that are supported by the 0.1”jumpers and PCB routing. The LM3S9B96 hasadditional internal multiplexing that enables additional configurations which may require discretewiring between peripherals and GPIO pins.The ICDI section of the board has a GND-GND jumper that serves no function other than toprovide a convenient place to ‘park’ a spare jumper. This jumper may be reused as required.ClockingThe development board uses a 16.0-MHz (Y2) crystal to complete the LM3S9B96microcontroller's main internal clock circuit. An internal PLL, configured in software, multiples thisclock to higher frequencies for core and peripheral timing.A 25.0-MHz (Y1) crystal provides an accurate timebase for the Ethernet PHY.Stellaris® LM3S9B96 Development Kit User’s ManualResetThe RESETn signal into the LM3S9B96 microcontroller connects to the reset switch (SW2) and tothe ICDI circuit for a debugger-controlled reset.External reset is asserted (active low) under any one of the three following conditions:Power-on reset (filtered by an R-C network)Reset push switch SW2 held downBy the ICDI circuit (U12 FT2232, U13D 74LVC125A) when instructed by the debugger (this capability is optional, and may not be supported by all debuggers)The LCD module has special Reset timing requirements requiring a dedicated control line from themicrocontroller.Power SuppliesThe development board requires a regulated 5.0V power source. Jumpers JP34-36 select thepower source, with the default source being the ICDI USB connector. Only one +5V source shouldbe selected at any time to avoid conflict between the power sources.When using USB in Host mode, the power source should be set to either ICDI or to EXT if a +5Vpower supply (not included in the kit) is available.The development board has two main power rails. A +3.3V supply powers the microcontroller andmost other circuitry. +5V is used by the OTG USB port and In-circuit Debug Interface (ICDI) USBcontroller. A low drop-out (LDO) regulator (U5) converts the +5V power rail to +3.3V. Both railsare routed to test loops for easy access.USBThe LM3S9B96’s full-speed USB controller supports On-the-Go, Host, and Device configurations.See Table2-2 for USB-related signals. The 5-pin microAB OTG connector supports all threeinterfaces in conjunction with the cables included in the kit.The USB port has additional ESD protection diode arrays (D1, D2,D5) for up to 15kV of ESDprotection.B-Related SignalsMicrocontroller Pin Board Function Jumper NamePin 70 USB0DM USB Data--Pin 71 USB0DP USB Data+-Pin 73 USB0RBIAS USB bias resistor-Pin 66 USB0ID OTG ID signal (input to microcontroller)OTG IDPin 67 USB0VBUS Vbus Level monitoring+VBUSPin 34 USB0EPE Host power enable (active high)EPENPin 35 USB0PFLT Host power fault signal (active low)PFLTU6, a fault-protected switch, controls and monitors power to the USB host port. USB0EPEN, thecontrol signal from the microcontroller, has a pull-down resistor to ensure host-port power remainsoff during reset. The power switch will immediately cut power if the attached USB device drawsmore than 1Amp, or if the switches’ thermal limits are exceeded by a device drawing more than 500mA. USB0PFLT indicates the over-current status back to the microcontroller.The development board can be either a bus-powered USB device or self-powered USB device depending on the power-supply configuration jumpers.When using the development board in USB-host mode, power to the EVB should be supplied by the In-circuit Debugger (ICDI) USB cable or by a +5V source connected to the DC power jack. Note that the LM3S9B96’s USB capabilities are completely independent from the In-Circuit Debug Interface USB functionality.DebuggingStellaris microcontrollers support programming and debugging using either JTAG or SWD. JTAG uses the TCK, TMS, TDI, and TDO signals. SWD requires fewer signals (SWCLK, SWDIO, and, optionally, SWO for trace). The debugger determines which debug protocol is used.Debugging ModesThe LM3S9B96 development board supports a range of hardware debugging configurations. Table 2-3 summarizes these configurations.Debug In ConsiderationsDebug Mode 3 supports board debugging using an external debug interface such as a Segger J-Link or Keil ULINK. Most debuggers use Pin 1 of the Debug connector to sense the target voltage and, in some cases, power the output logic circuit. Installing the VDD/PIN1 jumper will apply 3.3V power to this pin in order to support external debuggers.Debug USB OverviewAn FT2232 device from Future Technology Devices International Ltd implements USB-to-serial conversion. The FT2232 is factory-configured to implement a JTAG/SWD port (synchronous serial) on channel A and a Virtual COM Port (VCP) on channel B. This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable. Separate Windows drivers for each function are provided on the Documentation and Software CD.The In-Circuit Debug Interface USB capabilities are completely independent from the LM3S9B96’s on-chip USB functionality.Table 2-3.Hardware Debugging ConfigurationsMode Debug Function UseSelected by (1)Internal ICDIDebug on-board LM3S9B96 microcontroller over Debug USB interface.Default mode2ICDI out to JTAG/ SWD headerThe development board is used as a USB to SWD/ JTAG interface to an external target.Connecting to an external target and starting debug software.3 In from JTAG/SWD headerFor users who prefer an external debug interface (ULINK, JLINK, etc.) with the EVB.Connecting an externaldebugger to the JTAG/SWD headerStellaris® LM3S9B96 Development Kit User’s ManualA small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible bythe LM3S9B96 microcontroller. For full details on FT2232 operation, go to . USB to JTAG/SWDThe FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger.A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode,provides direction control for the bidirectional data line.Virtual COM PortThe Virtual COM Port (VCP) allows Windows applications (such as HyperTerminal) tocommunicate with UART0 on the LM3S9B96 over USB. Once the FT2232 VCP driver is installed,Windows assigns a COM port number to the VCP channel. Table2-4 shows the debug-relatedsignals.Table2-4.Debug-Related SignalsMicrocontroller Pin Board Function Jumper NamePin 77 TDO/SWO JTAG data out or trace data out TDOPin 78 TDI JTAG data in TDIPin 79 TMS/SWDIO JTAG TMS or SWD data in/out TMSPin 80 TCK/SWCLK JTAG Clock or SWD clock TCKPin 26 PA0/U0RX Virtual Com port data to LM3S9B96VCPRXPin 27 PA1/U0TX Virtual Com port data from LM3S9B96VCPTXPin 64 RSTn System Reset RSTnSerial Wire Out (SWO)The development board supports the Cortex-M3 Serial-Wire Output (SWO) trace capabilities.Under debugger control, on-board logic can route the SWO datastream to the VCP transmitchannel. The debugger software can then decode and interpret the trace information receivedfrom the Virtual Com Port. The normal VCP connection to UART0 is interrupted when using SWO.Not all debuggers support SWO.See the Stellaris LM3S9B96 Microcontroller Data Sheet for additional information on the TracePort Interface Unit (TPIU).Color QVGA LCD Touch PanelThe development board features a TFT Liquid Crystal graphics display with 320 x 240 pixelresolution. The display is protected during shipping by a thin, protective plastic film which shouldbe removed before use.FeaturesFeatures of the LCD module include:Kitronix K350QVG-V1-F display320 x RGB x 240 dots3.5” 262K colorsWide temperature range White LED backlight Integrated RAMResistive touch panelControl InterfaceThe Color LCD module has a built-in controller IC with a multi-mode parallel interface. The development board uses an 8-bit 8080 type interface with GPIO Port D providing the data bus. Table 2-4 shows the LCD-related signals.BacklightThe white LED backlight must be powered for the display to be clearly visible. U7 (FAN5331B) implements a 20mA constant-current LED power source to the backlight. The backlight is not normally controlled by the microcontroller, however, the control signal is available on a header. A jumper may be installed to disable the backlight by connecting it to GND. Alternatively, a wire may be used to control this signal from a spare microcontroller GPIO line.Because the FAN5331B operates in a constant current mode, its output voltage will jump up if the LCD should become disconnected. To prevent over-voltage failure of the IC or diode D3, a zener (D4) clamps the voltage. The current will limit to 20mA, but the total board current will be higher than when the LCD panel is connected. To avoid over-heating the backlighting circuit, install the BLON jumper to completely shut-down the backlighting circuit.PowerThe LCD module has internal bias voltage generators and requires only a single 3.3V dc supply.Resistive Touch PanelThe 4-wire resistive touch panel interfaces directly to the microcontroller, using 2 ADC channels and 2 GPIO signals. See the StellarisWare™ source code for additional information on touch panel implementation.Table 2-5.LCD-Related SignalsMicrocontroller Pin Board Function Jumper Name PE6/ADC1Touch X+X+PE3Touch Y-Y-PE2Touch X-X-PE7/ADC0Touch Y+Y+PB7 LCD Reset LRSTn PD0..7LCD Data Bus 0..7LD0..7PH7LCD Data/Control Select LDC PB5LCD Read Strobe LRDn PH6LCD Write Strobe LWRn -Backlight controlBLONStellaris® LM3S9B96 Development Kit User’s ManualI2S AudioThe LM3S9B96 development board has advanced audio capabilities using an I2S-connectedAudio TLV320AIC23 CODEC. The factory default configuration has Audio output (Line Out and/orHeadphone output) enabled. Four additional I2S signals are required for Audio input (Line Inputand/or Microphone). All four audio interfaces are through 1/8” (3.5mm) stereo jacks. Table2-6shows the I2S audio-related signals.Table2-6.I2S Audio-Related SignalsMicrocontroller Pin Board Function Jumper NameI2C0SDA CODEC Configuration Data SDAI2C0SCL CODEC Configuration Clock SCLI2STXSD Audio Out Serial Data TXSDI2STXWS Audio Out Framing signal TXWSI2STXSCK Audio Out Bit Clock BCLK aI2STXMCLK Audio Out System Clock MCLKI2SRXSD Audio In Serial Data RXSD bI2SRXWS Audio In Framing signal RXWS bI2SRXSCK Audio In Bit Clock BCLK bI2SRXMCLK Audio In System Clock MCLK ba.Shares GPIO line with Analog voltage reference. Jumper installed by default.b.Shares GPIO line with LCD data bus – Port D. Jumper omitted by default.The Audio CODEC has a number of control registers which are configured using the I2C bussignals. CODEC settings can only be written, but not read, using I2C. See the StellarisWare™example applications for programming information and the TLV320AIX23B data sheet forcomplete register details.The Headphone output can be connected directly to any standard headphones. The Line Output issuitable for connection to an external amplifier, including PC desktop speaker sets.User Switch and LEDThe development board provides a user push-switch and LED (see Table2-7).Table2-7.Navigation Switch-Related SignalsMicrocontroller Pin Board Function Jumper NamePJ7User Switch SWITCHPF3User LED LED aa.Shared with Ethernet Jack Yellow LED. This jumper is installed by default.C H A P T E R3Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI)The External Peripheral Interface (EPI) is a high-speed 8/16/32-bit parallel bus for connectingexternal peripherals or memory without glue logic. Supported modes include SDRAM, SRAM, andFlash memories, as well as Host-bus and FIFO modes.The LM3S9B96 development kit includes an 8MB SDRAM board in addition to an EPI break-outboard. Other EPI expansion boards may be available.SDRAM Expansion BoardThe SDRAM board provides 8MB of memory (4M x 16) which, once configured, becomes part ofthe LM3S9B96’s memory map at either 0x6000.0000 or 0x8000.0000. The SDRAM interfacemultiplexes DQ00..14 and AD/BA0..14 without requiring external latches or buffers. Of the 32 EPIsignals, only 24 are used in SDRAM mode, with the remaining signals used for non-EPI functionson the board.Flash and SRAM Memory Expansion BoardThe optional Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) is a plug-in forthe DK-LM3S9B96 development board. This expansion board works with the External PeripheralInterface (EPI) of the Stellaris microcontroller and provides Flash memory, SRAM, and animproved performance LCD interface.For more information on the DK-LM3S9B96-EXP-FS8 memory expansion board (sold separately),see Appendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.C H A P T E R4Using the In-Circuit Debugger InterfaceThe Stellaris® LM3S9B96 Development Kit can operate as an In-Circuit Debugger Interface(ICDI). ICDI acts as a USB to the JTAG/SWD adaptor, allowing debugging of any external targetboard that uses a Stellaris microcontroller. See “Debugging Modes” on page16 for a description ofhow to enter Debug Out mode.Figure4-1.ICD Interface Mode`The debug interface operates in either serial-wire debug (SWD) or JTAG mode, depending on theconfiguration in the debugger IDE.The IDE/debugger does not distinguish between the on-board Stellaris microcontroller and anexternal Stellaris microcontroller. The only requirement is that the correct Stellaris device isselected in the project configuration.The Stellaris target board should have a 2x10 0.1” pin header with signals as indicated inTable C-1 on page35. This applies to both an external Stellaris microcontroller target (DebugOutput mode) and to external JTAG/SWD debuggers (Debug Input mode).ICDI does not control RST (device reset) or TRST (test reset) signals. Both reset functions areimplemented as commands over JTAG/SWD, so these signals are usually not necessary.It is recommended that connections be made to all GND pins; however, both targets and externaldebug interfaces must connect pin 5 and at least one other GND pin to GND. Some externaldebug interfaces may require a voltage on Pin 1 to set line driver thresholds. The developmentboard ICDI circuit automatically sets Pin 1 high if an external debugger is connected. In othermodes this pin is unused.A P P E N D I X AStellaris® LM3S9B96 Development Board SchematicsThis section contains the schematics for the DK-LM3S9B96 development board.Micro, EPI connector, USB, and Ethernet on page26LCD CAN, Serial Memory, and User I/O on page27Power Supplies on page28I2S Audio Expansion Board on page29EPI and SDRAM Expansion Boards on page30In-circuit Debug Interface (ICDI) on page3132October 3, 2009A P P E N D I X BStellaris® LM3S9B96 Development Board Component LocationsThis appendix contains details on component locations, including:Component placement plot for top (Figure B-1)October 3, 20093334October 3, 2009October 3, 200935Stellaris® LM3S9B96 Development Board Connection DetailsThis appendix contains the following sections: DC Power Jack (see page 35)ARM Target Pinout (see page 35)DC Power JackThe EVB provides a DC power jack for connecting an external +5V regulated (+/-5%) power source.The socket is 5.5 mm dia with a 2.1 mm pin.ARM Target PinoutIn ICDI input and output mode, the Stellaris® LM3S9B96 Development Kit supports ARM’sstandard 20-pin JTAG/SWD configuration. The same pin configuration can be used for debugging over serial-wire debug (SWD) and JTAG interfaces.Insert Jumper VDD/PIN1 Jumper (JP57) only when using the development board with an external debug interface such as a ULINK or JLINK.Table C-1.Debug Interface Pin AssignmentsFunction Pin Number TDI 5TDO/SWO 13TMS/SWDIO 7TCK/SWCLK 9System Reset 15VDD 1GND 4, 6, 8, 10, 12, 14, 16, 18, 20No Connect2, 3, 11, 17, 19A P P E N D I XC36October 3, 2009A P P E N D I X DStellaris® LM3S9B96 Development Board Microcontroller GPIO AssignmentsTable D-1 shows the pin assignments for the LM3S9B96 microcontroller.Table D-1.Microcontroller GPIO AssignmentsLM3S9B96 GPIO Pin Development Board UseNumber Description Default Function Default Use Alt. Function Alternate Use 26PA0U0Rx Virtual Com Port27PA1U0Tx Virtual Com Port28PA2SSI0Clk SPI29PA3SSI0Fss SD Card CSn30PA4SSI0Rx SPI31PA5SSI0Tx SPI34PA6USB0EPEN USB Pwr Enable CAN0RX35PA7USB0PFLT USB Pwr Fault CAN0TX66PB0USB0ID USB OTG ID67PB1USB0VBUS USB Vbus72PB2I2C0SCL Audio I2C65PB3I2C0SDA Audio I2C92PB4ADC10Potentiometer EPI0S23EPI Breakout91PB5PB5LCD RDn EPI0S22EPI Breakout90PB6PB6I2STXSCK AVREF Ext Volt Ref89PB7PB7LCD RST80PC0TCK/SWCLK JTAG79PC1TMS/SWDIO JTAG78PC2TDI JTAG77PC3TDO/SWO JTAG25PC4EPI0S2SDRAM D02EPI0S0224PC5EPI0S3SDRAM D03EPI0S0323PC6EPI0S4SDRAM D04EPI0S0422PC7EPI0S5SDRAM D05EPI0S05October 3, 200937。
三环控制锂电池充电器的设计
PROCESS AUTOMATION INSTRUMENTATION Vol.34No.8August 2013国家863计划基金资助项目(编号:2011AA05AA103);上海市教育发展基金资助项目(编号:LM201135);上海市科技发展基金资助项目(编号:11195802100)㊂修改稿收到日期:2012-08-20㊂第一作者徐颖晟(1984-),男,现为上海交通大学电机与电器专业在读硕士研究生;主要从事锂电池充电器方面的研究㊂三环控制锂电池充电器的设计Design of the 3⁃closed⁃loop Controlled Lithium Battery Charger徐颖晟1 王志新1 余俊宏1 邹建龙2(上海交通大学电子信息与电气工程学院1,上海 200240;嘉兴清源电气科技有限公司2,浙江嘉兴 314031)摘 要:针对现有充电器存在的不足,设计了基于DK⁃LM3S9B96嵌入式处理器的锂电池充电器,阐述了充电器的硬件电路结构㊁工作原理及软件程序设计㊂该充电器增加了温度环,根据锂电池取样电流㊁电压值及电池温度等信息,由DK⁃LM3S9B96输出PWM 信号用以控制DC /DC 变换器工作和锂电池充电过程,从而实现锂电池充电器的数字化和智能化㊂试验结果表明,所设计的锂电池充电器具有三段式充电功能,能够满足锂电池高效充电的要求,同时也避免了使用集成芯片控制容易引起的温升㊁控制精度不高等问题㊂关键词:嵌入式处理器 整流电路 通信系统 智能控制 数字化中图分类号:TP368 文献标志码:AAbstract :Aiming at the shortcomings of the existing charger ,the lithium battery charger based on DK⁃LM3S9B96embedded process has been designed.The structure of hardware circuitry ,principle and software program design of the charger are described.In accordance with the sampled information including current ,voltage and temperature of the battery ,the DC /DC converter and the charging procedures of the battery are controlled by PWM signal output by DK⁃LM3S9B96,thus the digitized and intelligent battery charger is implemented.The test results show that this charger features 3sectional charging function ,and meets high efficient charging requirement for lithium battery ,in addition ,it avoids the demerits of IC control ,e.g.,easily leads to temperature rise and low control accuracy.Keywords :Embedded processor Rectification circuit Communication system Intelligent control Digitalization0 引言目前,锂电池因其电压高㊁循环性能好和无记忆效应等特点,被用作移动便携式仪器的核心储能装置,而与之相匹配的锂电池充电器也越来越被人们所重视㊂充电器的好坏不仅对仪器设备的性能有影响,而且对电池的寿命和设备工作效率也有影响㊂现在市面上较为典型的一种充电器是用一个专用集成芯片来控制充电电流㊁电压的变化,这种充电方式的充电器虽然芯片体积小,但是也存在一些不足,如充电效率低㊁易发热而降低电池寿命㊁控制精度低[1-2]等㊂针对集成芯片的发热问题[3],通常采用加入温度保护模块予以解决㊂本文针对锂电池的充放电特性及实际使用中的需求,选用新型的嵌入式处理器LM3S9B96为主控制器,克服了采用集成IC 带来的易发热的问题㊂同时,在锂电池充电过程中进行智能控制,严格控制充电电流㊁电压㊁温度等参数,从而提高了充电效率,实现了充电过程的数字化和智能化㊂1 充电器的硬件设计锂电池充电器的硬件设计主要包括整流电路和充电器主电路(包括电源变换电路㊁采样电路及保护电路等部分)㊂1.1 PFC 电路由于电力电子装置和非线性负载的广泛使用,电力系统电压及波形容易产生畸变,从而产生大量的谐波,导致电源输入功率因数降低,电网环境严重污染,用电设备所处环境恶化等问题㊂同时,也给周围的通信系统和公共电网以外的设备带来了危害[4]㊂为了克服以上问题,设计的锂电池充电器采用功率因数补偿(power factor compensation,PFC)电路进行交直流转换,如图1所示㊂图1 功率因数补偿电路Fig.1 PFC circuit图1中:S 1为双向开关管㊂当开关管导通时,输47三环控制锂电池充电器的设计 徐颖晟,等‘自动化仪表“第34卷第8期 2013年8月入电流先后流经电感和开关管,对电感进行储能,同时直流侧滤波电容给负载供电;当开关管断开时,输入电流经过电感和整流二极管到达负载端,电感储能和交流电源同时给负载和电容供电㊂该电路使用平均电流控制模式[5],可以消除许多严重问题,诸如较差抗噪声能力㊁斜坡补偿以及峰值平均电流误差等[6]㊂1.2 充电器主电路1.2.1 DC /DC 电源变换电路在给锂电池充电的过程中,充电器通过改变充电电压和电流来实现不同的充电策略[7]㊂DC /DC 双管正激电路如图2所示㊂在考虑电压㊁电流影响的同时,也将温度控制放入了充电策略中㊂正激电路的优点是可以提高效率㊁降低设计的复杂性[8-9]㊂图2 双管正激电路Fig.2 Double⁃tube positive excited circuit图2中:U in 为输入电压;D 1㊁D 2㊁D 3㊁D 4为续流二极管㊂DC /DC 双管正激变换器的工作原理是:当PWM输出高电平时,MOSFET 管导通,电流流经晶体管和电感到达电池㊂在这一阶段,电感吸收能量,电容被充电;当PWM 输出低电平时,MOSFET 关断,电流经续流二极管续流,电感电压反向,电感㊁电容作为滤波器输出电压电流[10]㊂1.2.2 采样电路采样及保护电路如图3所示㊂图3 采样及保护电路Fig.3 Sampling and protection circuit图3中:R 3=10kΩ,为精密电阻;R 4为NTC⁃10KPX3⁃42H⁃S1热敏电阻㊂采样包括对充电电流㊁充电电池端电压和电池温度的采样㊂采样的电压㊁电流和温度经过ADC 模块发送到LM3S9B96控制芯片中,由LM3S9B96对数据进行分析与处理㊂①电压采样电路锂电池充电电压检测采用电阻分压原理㊂电压采样电路通过1个10kΩ和1个2kΩ的滑动变阻器分压,将检测电压转换为0~3V 的电压㊂保护电路由RC 电路和嵌位二极管组成,采集的电压信号经过保护电路后导入A IN 0口,以保证A /D 口不会因为流经电压太大而致使芯片被烧毁㊂②电流采样电路电流采样不外加传感器,通过1个传感电阻把流过电池的电流转换为电压后,再经ADC 转换取样㊂根据功率计算公式P =I 2R 可知,若传感电阻R 越大,消耗的功率也就越大,从而导致传感电阻本身发热严重㊂因此,传感电阻取值设计为0.1Ω,经MCP6031运算放大器电压放大到3V 左右,再通过保护电路,最终传送到A IN 1管脚㊂③温度采样电路温度控制对于锂电池充电器而言非常重要,这是因为充电过程中电池温度过高,可能导致锂电池发生永久性损坏,甚至发生爆炸现象㊂基于以上因素的考虑,设计的锂电池充电器加入了温度控制环路,并采用运放AD823进行电压跟随,运放输出后经过RC 滤波及钳位保护电路接入A IN 2口,进行数模转换㊂温度传感器使用热敏电阻,选用的热敏电阻型号为NTC⁃10KPX3⁃42H⁃S1㊂该热敏电阻为负温度系数直插类型,25℃时电阻为10kΩ,精度为1%㊂2 充电器的软件设计2.1 DK⁃LM3S9B96简介本文采用LM3S9B96芯片作为中央处理器㊂该芯片包括1个低压降的稳压器,集成掉电复位和上电复位功能以及16bit 的ADC㊁DMA㊁GPIO 等各种丰富的外设功能,可直接通向GPIO 管脚㊂LM3S9B96芯片有2路ADC,即ADC 0和ADC 1㊂ADC 0和ADC 1都有16位输入,即A IN 0~A IN 15,这十分适合所设计的锂电池充电器㊂从采样电路处实时采集到的充电电压㊁电流及温度信息,通过A IN 0㊁A IN 1和A IN 2口送入处理器,再通过计算决定下阶段的充电电流,并利用PWM 信号控制充电电流㊂57三环控制锂电池充电器的设计 徐颖晟,等PROCESS AUTOMATION INSTRUMENTATION Vol.34No.8August 20132.2 软件程序设计本次设计的锂电池充电器主要采用分时处理模式,由电池电压采集模块㊁电池电流采集模块和温度采集模块组成㊂充电器流程图如图2所示㊂图4 充电器流程图Fig.4 The flowchart of charge 系统启动时先检测电压端电压值,如果符合充电要求,则继续充电,否则终止充电㊂充电器的充电控制单元LM3S9B96通过检测电池端电压值来选择进行哪一阶段的充电模式㊂由于锂电池在温度高时工作效率和寿命都受很大影响,并且可能发生爆炸,因此,本次设计的锂电池充电器着重在恒定电流充电㊁恒定电压充电两个充电状态检测电池的本身温度,再选择充电模式㊂当温度超过给定的温度值时,就停止工作;当温度低于给定值时,则继续进行充电㊂3 试验结果及分析对基于微处理器DK⁃LM3S9B96控制的锂电池充电器的关键参数电压和电流进行测试,并针对24V /40Ah 锂电池进行试验,采用的电压表㊁电流表型号为VICTOR⁃VC890D,示波器型号为TDS2024C㊂实际测得的锂电池充电过程测试数据如表1所示㊂由表1可知,在充电初期,锂电池组处在深度放电状态,需要进行预充电,由DK⁃LM3S9B96控制的PWM 波产生小电流进行充电,这段时间锂电池电压缓缓上升,时间间隔取20min㊂随后,在各节电池电压达到最低充电门限电压后,进入6A 电流值恒流充电模式,此过程中的数据记录间隔为30min㊂当单节锂电池电压达到最高充电门限电流时,锂电池两端电池已经基本稳定,但是锂电池的电流还没减小到设定值,当电流减小到接近600mA 时,充电结束㊂表1 锂电池的充电记录Tab.1 The charging records of the lithium battery开始时刻电压/V 电流/A 开始时刻电压/V 电流/A 8∶5024.6 6.0214∶5028.2 2.6710∶5026.0 6.0015∶3028.5 2.2711∶5026.5 6.0116∶0028.7 1.3813∶5027.9 4.2017∶2029.10.6214∶0028.03.804 结束语本文采用DK⁃LM3S9B96作为核心处理器,以锂电池为应用对象,设计了三环控制的锂电池充电器,并制造搭建了样机㊂试验表明,本次设计的充电器具有以下优点:硬件电路和软件相结合,采用数字控制技术,大大提升了系(下转第80页)67三环控制锂电池充电器的设计 徐颖晟,等。
隔离电源模块常用芯片
隔离电源模块常用芯片
隔离电源模块是电子设备电路中常用的一种电源模块。
它能够有效地隔离输入输出之间的电气信号,防止电路中出现潜在的接地故障和电压干扰。
在隔离电源模块中,常用的芯片有以下几种:
1. LT8300:这是一种高效率隔离型DC/DC转换器芯片,能够在输入电压范围内实现高达92%的转换效率。
它支持多种输入电压和输出电压,并具有过热保护和短路保护功能。
2. ADuM3190:这是一种高速隔离型数字隔离器芯片,能够在高达1 Mbps的数据速率下实现高精度的信号隔离。
它支持多种输入电压和输出电压,并具有电磁干扰和电压浪涌保护功能。
3. CS8122:这是一种高精度隔离型电流传感器芯片,能够实现高达±200A的电流测量范围。
它支持多种输入电压和输出电压,并具有过载保护和短路保护功能。
4. ISO1540:这是一种高速隔离型数字隔离器芯片,能够在高达100 Mbps的数据速率下实现高精度的信号隔离。
它支持多种输入电压和输出电压,并具有电磁干扰和电压浪涌保护功能。
以上是隔离电源模块中常见的芯片,它们能够为电子设备提供高效、精确、可靠的隔离电源解决方案。
- 1 -。
LM3S9B92概述
LM3S9B92概述概述德州仪器(TI)公司Stellaris?所提供一系列的微控制器是首款基于ARM? CortexTM-M3的控制器,它们为对成本尤其敏感的嵌入式微控制器应用方案带来了高性能的32位运算能力。
这些具备领先技术的芯片使用户能够以传统的8位和16位器件的价位来享受32位的性能,而且所有型号都是以小占位面积的封装形式提供。
LM3S9B92微控制器的优势还在于能够方便的运用多种ARM的开发工具和片上系统(SoC)的底层IP应用方案,以及广大的用户群体。
另外,该微控制器使用了兼容ARM Thumb?的Thumb2指令集来减少存储容量的需求,并以此达到降低成本的目的。
最后,LM3S9B92微控制器与Stellaris?系列的所有成员是代码兼容的,这为用户提供了灵活性,能够适应各种精确的需求。
为了能够帮助用户产品快速的上市,德州仪器(TI)公司提供了一整套的解决方案,包括评估和开发板、白皮书和应用笔记、方便使用的外设驱动程序库、以及强大的支持、销售和分销商网络。
特性LM3S9B92包含了下列特性:ARM Cortex-M3处理器内核-80MHz主频,100DMIPS性能-ARM Cortex系统定时器-嵌套向量中断控制器片上存储器-256KB单周期Flash-96KB单周期SRAM-片上ROM StellarisWare 软件Stellaris外设驱动库Stellaris BootLoader高级加密标准(AES)密钥表格循环冗余校验 (CRC) 错误检测功能外围设备接口(EPI)-8/16/32位独立外设并行总线-支持SDRAM、SRAM/Flash、FPGA、CPLD先进的连续性-10/100以太网 MAC/PHY-两路CAN2.0 A/B控制器-USB2.0 OTG/Host/Device-三路支持IrDA和ISO7816的UART(其中一路具有调制解调控制功能)-两个I2C模块-两个SSI模块-I2S模块系统综合性能-DMA控制器-系统控制与时钟(包括片上16MHz高精度振荡器)-4个32位通用定时器-8路CCP管脚-实时时钟-两个看门狗定时器一个定时器时钟源为主振荡器另一个定时器时钟源为片内高精度振荡器-通过配置多达65个GPIO口灵活配置为GPIO或者其他一种外设功能驱动电流可独立配置为2、4或者8mA多达4个GPIO口有18 mA驱动能力先进的运动控制-8路PWM输出,应用于运动控制场合-4种硬件故障处理输入操作,实现低延时关闭-两个QEI模块模拟功能-两个10位共16路采样通道AD转换器,采样率为1Msps -三个模拟比较器-16个数字比较器-一个片上基准源JTAG和SWDLQFP100封装工业级温度范围(-40℃~85℃ )。
IAR编译错误
IAR编译错误清单Warning[Pe1665]: concatenation with "PDOR" in macro "PT" does not create a valid token E:\All learning files\IAR files\四轴\电调\VCANBLDC\Board\src\VCAN_NRF24L0.c 317警告:“PDDR”宏“PT”不创建有效的TOK级联未解1,错误:Error[Li005]: no definition for "__VECTOR_TABLE" [referenced from F:\k60 example\ E04 WOTCHDOG\Watdog\Debug\Obj\vectors.o]Error[Li005]: no definition for "__VECTOR_RAM" [referenced from F:\k60 example\E 04 WOTCHDOG\Watdog\Debug\Obj\vectors.o]Error[Li005]: no definition for "__BOOT_STACK_ADDRESS" [referenced from F:\k60 example\E04 WOTCHDOG\Watdog\Debug\Obj\vectors.o]错误原因(见下图):在linker里没有设置icf文件的路径。
说2,错误:Warning[Pe223]: function "LCD_Init" declared implicitly D:\All learning files\IA R files\exercise\Project\files\main.c 30files\exercise\Project\files\main.c 31Warning[Pe223]: function "LCD_P8x16Str" declared implicitly D:\All learning files\IAR files\exercise\Project\files\main.c 40Warning[Pe223]: function "LCD_P6x8Str" declared implicitly D:\All learning files\IAR f iles\exercise\Project\files\main.c 41Warning[Pe223]: function "LCD_CLS" declared implicitly D:\All learning files\IAR files\ exercise\Project\files\main.c 44Error[Pe020]: identifier "longqiu96x64" is undefined D:\All learning files\IAR files\exer cise\Project\files\main.c 45或者:Error[Pe101]: "uint8" has already been declared in the current scope (at line 72 of "D:\All learning files\IAR files\exercise\ D:\All learning files\IAR files\exercise\LI B\drivers\LQ12864\LQ12864.h 10Project\iar\..\..\LIB\cpu\arm_cm4.h")Error[Pe070]: incomplete type is not allowed D:\All learning files\IAR files\exercise\LI B\drivers\LQ12864\LQ12864.h 10Error[Pe065]: expected a ";" D:\All learning files\IAR files\exercise\LIB\drivers\LQ1286 4\LQ12864.h 10Error while running C/C++ Compilermain.cError[Pe101]: "uint8" has already been declared in the current scope (at line 72 of "D:\All learning files\IAR files\exercise\ D:\All learning files\IAR files\exercise\LIB\drive rs\LQ12864\LQ12864.h 10Project\iar\..\..\LIB\cpu\arm_cm4.h")Error[Pe070]: incomplete type is not allowed D:\All learning files\IAR files\exercise\LI B\drivers\LQ12864\LQ12864.h 10Error[Pe065]: expected a ";" D:\All learning files\IAR files\exercise\LIB\drivers\LQ1286 4\LQ12864.h 10Warning[Pe223]: function "LCD_Init" declared implicitly D:\All learning files\IAR files\e xercise\Project\files\main.c 30Warning[Pe223]: function "Draw_LibLogo" declared implicitly D:\All learning files\IAR files\exercise\Project\files\main.c 31files\exercise\Project\files\main.c 40Warning[Pe223]: function "LCD_P6x8Str" declared implicitly D:\All learning files\IAR f iles\exercise\Project\files\main.c 41Warning[Pe223]: function "LCD_CLS" declared implicitly D:\All learning files\IAR files\ exercise\Project\files\main.c 44Error[Pe020]: identifier "longqiu96x64" is undefined D:\All learning files\IAR files\exer cise\Project\files\main.c 45Error while running C/C++ Compiler注意:我这是把LQ12864.h中的void byte longqiu96x64[768];//void LCD_Init(void);//void LCD_CLS(void);//void LCD_P6x8Str(byte x,byte y,byte ch[]);//void LCD_P8x16Str(byte x,byte y,byte ch[]);//void LCD_P14x16Str(byte x,byte y,byte ch[]);void LCD_Print(byte x, byte y, byte ch[]);// void LCD_PutPixel(byte x,byte y);//void LCD_Rectangle(byte x1,byte y1,byte x2,byte y2,byte gif);//void Draw_LQLogo(void);//void Draw_LibLogo(void);看到没我都给注释了,然后出现这么多错误,最后又把本来是extern byte longqiu96x64[7 68];改成void byte longqiu96x64[768];于是出现了:Error[Pe101]: "uint8" has already been declared in the current scope (at line 72 of "D:\All learning files\IAR files\exercise\ D:\All learning files\IAR files\exercise\LIB\drive rs\LQ12864\LQ12864.h 10Project\iar\..\..\LIB\cpu\arm_cm4.h")Error[Pe070]: incomplete type is not allowed D:\All learning files\IAR files\exercise\LI B\drivers\LQ12864\LQ12864.h 10Error[Pe065]: expected a ";" D:\All learning files\IAR files\exercise\LIB\drivers\LQ1286 4\LQ12864.h 10Error while running C/C++ CompilerIAR 6.20编译错误清单1、①错误描述:Tool Internal Error:Internal Error: [CoreUtil/General]: Access violation (0xc0000005) at 007588A5 (reading from address 0x0)Internal Error: [CoreUtil/General]: Access violation (0xc0000005) at 007588A5 (reading from address 0x0)Error while running C/C++ Compiler②错误原因:High配置设置为Size,应该为Low2、①错误描述:Fatal Error[Pe1696]: cannot open source file "inc/hw_types.h" E:\StellarisWareM3_9D92\boards\dk-lm3s9b96\boot_demo2\boot_demo2.c 25②错误原因:C/C++ Complier(Assember)->Preprocessor->Additional include directories:$PROJ_DIR$\.$PROJ_DIR$\..$PROJ_DIR$\..\..\..3、①错误描述:Fatal Error[Pe1696]: cannot open source file "lwip/opt.h" E:\StellarisWareM3_9D92\utils\lwiplib.h 44②错误原因:C/C++ Complier-(Assember)>Preprocessor->Additional include directories:$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\apps$PROJ_DIR$\..\..\..\third_party\bget$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\ports\stellaris\include$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\src\include$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\src\include\ipv4$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\src\include\lwip$PROJ_DIR$\..\..\..\third_party4、①错误描述:Fatal Error[Pe035]: #error directive: Unrecognized COMPILER! E:\StellarisWareM3_9D92\boards\dk-lm3s9b96\drivers\set_pinout.h 59Error while running C/C++ Compiler②错误原因:C/C++ Complier-(Assember)>Preprocessor->Defined symbols: ewarm5、①错误描述:Error[Pe020]: identifier "ROM_pvAESTable" is undefined E:\StellarisWareM3_9D92\third_party\aes\aes.c 319②错误原因:6、①错误描述:Error[Li005]: no definition for "main" [referenced from cmain.o(rt7M_tl.a)]Error while running Linker②错误原因:定义函数:int main(void) { return (0); }7、①错误描述:Error[Li005]: no definition for "main" [referenced from cmain.o(rt7M_tl.a)]Error while running Linker②错误原因:如果是库是库函数,在:General Options->Output->Output file:选择:Library项4、①错误描述:Fatal Error[Pe1696]: cannot open source file "uip.h" E:\StellarisWareM3_9D92\third_party\uip-1.0\apps\dhcpc\dhcpc.c 37②错误原因:5、①错误描述:②错误原因:$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\apps$PROJ_DIR$\..\..\..\third_party\bget$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\ports\stellaris\include$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\src\include$PROJ_DIR$\..\..\..\third_party\lwip-1.3.2\src\include\ipv4$PROJ_DIR$\..\..\..\third_party$PROJ_DIR$\..\..\..\third_party\uip-1.0$PROJ_DIR$\..\..\..\third_party\uip-1.0\uip$PROJ_DIR$\..\..\..\third_party\uip-1.0\apps$PROJ_DIR$\..\..\..\third_party\\speex-1.2rc1\include$PROJ_DIR$\..\..\..\third_party\\speex-1.2rc1\include\speex$PROJ_DIR$\..\..\..\third_party\\speex-1.2rc1\stellaris6、①错误描述:Fatal Error[Pe035]: #error directive: You now need to define either FIXED_POINT or FLOATING_POINT E:\StellarisWareM3_9D92\third_party\speex-1.2rc1\libspeex\arch.h 65②错误原因:7、①错误描述:Fatal Error[Pe035]: #error directive: "Unrecognized/undefined driver for DISK0!" E:\StellarisWareM3_9D92\third_party\fatfs\port\dual-disk-driver.c 62Error while running C/C++ Compiler②错误原因:UART_BUFFEREDDISK0_DK_LM3S9B96DISK1_USB_MSCINCLUDE_BGET_STATS8、①错误描述:Error[Pe020]: identifier "ROM_pvAESTable" is undefined E:\SWM3_9D92(6.20)\third_party\aes\aes.c 359Error while running C/C++ Compiler②错误原因:10、①错误描述:Fatal Error[Pe035]: #error directive: You now need to define either FIXED_POINT or FLOATING_POINT E:\SWM3_9D92(6.20)\third_party\speex-1.2rc1\libspeex\arch.h 65Error while running C/C++ Compiler②错误原因:11、①错误描述:Error[Li005]: no definition for "ROM_SysCtlClockSet" [referenced from E:\SWM3_9D92(6.20)\boards\dk-lm3s9b96\safertos_demo\Debug\Obj\safertos_demo.o] Error[Li005]: no definition for "ROM_FlashUserGet" [referenced from E:\SWM3_9D92(6.20)\boards\dk-lm3s9b96\safertos_demo\Debug\Obj\lwip_task.o] Error[Li005]: no definition for "ROM_IntPrioritySet" [referenced from E:\SWM3_9D92(6.20)\boards\dk-lm3s9b96\safertos_demo\Debug\Obj\lwip_task.o] Error[Li005]: no definition for "ROM_GPIOPinTypeGPIOOutput" [referenced from E:\SWM3_9D92(6.20)\boards\dk-lm3s9b96\safertos_demo\Debug\Obj\led_task.o]Error[Li005]: no definition for "ROM_GPIOPinWrite" [referenced from E:\SWM3_9D92(6.20)\boards\dk-lm3s9b96\safertos_demo\Debug\Obj\led_task.o]Error[Lp011]: section placement failed: unable to allocate space for sections/blocks with a total estimated minimum size of 0x11e54 bytes in<[0x20000000-0x2000ffff]> (total uncommitted space 0x10000).Error while running Linker②错误原因:12、①错误描述:Error[Lp011]: section placement failed: unable to allocate space for sections/blocks with a total estimated minimum size of 0x11e54 bytes in <[0x20000000-0x2000ffff]> (total uncommitted space 0x10000).Error while running Linker。
LM3S9B96开发板主要特性
TheLM3S9B96isamemberoftheStellarisTem pest-classmicrocontrollerfamily.Tempest-c lassdevicesincludecapabilitiessuchas80MHz clockspeeds,anExternalPeripheralInterface (EPI)andAudioI2Sinterfaces.Inadditiontone whardwaretosupportthesefeatures,theDK-LM3 S9B96boardincludesarichsetofperipheralsfo undonotherStellarisboards.
道送德芙巧克力的意思,特别是对于自己更是有特殊的意义。可是木子又害怕
TheStellaris?LM3S9B96DevelopmentKitae
leratesdevelopmentofTempest-classmicrocon
trollers.Thekitalsoincludesextensiveexamp leapplicationsandpletesourcecode.LM3S9B96
LM3S9TheStellaris?LM3S9B96DevelopmentKitcon
tainseverythingneededtodevelopandrunarang eofapplicationsusingStellarismicrocontrol
lers:
LM3S9B96developmentboard
■Motioncontrol ■Medicalinstrumentation
道送德芙巧克力的意思,特别是对于自己更是有特殊的意义。可是木子又害怕
德州仪器,LM3S9B90-I系列, 规格书,Datasheet 资料
Texas Instruments •108 Wild Basin, Suite 350•Austin, TX 78746/stellarisCopyright © 2009–2011 Texas Instruments, Inc. All rights reserved. Stellaris andStellarisWare are registered trademarks of Texas Instruments. ARM and Thumb areregistered trademarks, and Cortex is a trademark of ARM Limited. Other names andbrands may be claimed as the property of others.PB-LM3S9B90EK-05June 29, 2011The Stellaris® LM3S9B90 Ethernet+USB-OTG Evaluation Kit provides a low-cost evaluation platform for the LM3S9B90 ARM® Cortex™-M3-based microcontroller. The kit includes two boards: the EK-LM3S9B90 evaluation board, and the BD-ICDI In-Circuit Debug Interface board.The evaluation board design highlights the LM3S9B90 microcontroller’s10/100 Mbit Ethernet port, full-speed USB-OTG port, In-Circuit Debug Interface (ICDI) board, and easy connection to the GPIO ports.Features The evaluation board uses the LM3S9B90 microcontroller which features a Hibernation module toefficiently power down the device to a low-power state during extended periods of inactivity.The LM3S9B90 microcontroller also features an external 16MHz crystal that provides the main oscillator clock which can directly drive the ARM core clock or an internalPLL to increase the core clock up to 80MHz. A 25MHz crystal is used for the Ethernet clock and a 4.194304MHz crystal is used for the real-time clock. The LM3S9B90 microcontroller also has an internal LDO voltage regulator that supplies power for internal use.The Stellaris LM3S9B90 evaluation board includes the following features: Stellaris LM3S9B90 high-performance microcontroller with large memory –32-bit ARM® Cortex™-M3 core –256KB main Flash memory, 96KB SRAM Ethernet 10/100 port with two LED indicators USB 2.0 Full-Speed OTG port Virtual serial communications port capability Oversized board pads for GPIO access Reset pushbutton and power LED User pushbutton and LEDDetachable In-Circuit Debug Interface (ICDI) board can be used for programming and debugging other Stellaris® boardsKit ContentsThe EK-LM3S9B90 evaluation kit comes with the following:EK-LM3S9B90 Evaluation Board (EVB)BD-ICDI In-Circuit Debug Interface BoardCables–USB cable–10-pin ribbon cable for JTAG–8-pin ribbon cable for power/UART connectionEvaluation Kit CD containing:–Complete documentation–StellarisWare® Peripheral Driver Library andexample source code– A supported evaluation version of one of thefollowing:–Keil™ RealView® MicrocontrollerDevelopment Kit (MDK-ARM)–IAR Embedded Workbench® developmenttools–Sourcery CodeBench development tools –Code Red Technologies Red Suite –Texas Instruments’ Code Composer Studio™ IDEOrdering InformationProductNumber Description EKK-LM3S9B90Stellaris® LM3S9B90 Low-Cost Evaluation Kit for Keil™ RealView® MDK-ARM (32 KB code-size limited)EKI-LM3S9B90Stellaris® LM3S9B90 Low-Cost Evaluation Kit for IAR Systems Embedded Workbench® (32 KB code-size limited)EKC-LM3S9B90Stellaris® LM3S9B90 Low-Cost Evaluation Kit for Sourcery CodeBench(30-day limited)EKT-LM3S9B90Stellaris® LM3S9B90 Low-Cost Evaluation Kit for Code Red Technologies Red Suite (90-day limited)EKS-LM3S9B90Stellaris® LM3S9B90 Low-Cost Evaluation Kit for Code ComposerStudio™ IDE (board-locked)Stellaris®LM3S9B90Ethernet+USB-OTG Evaluation Kit 芯天下--/IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAudio /audio Communications and Telecom /communicationsAmplifiers Computers and Peripherals /computersData Converters Consumer Electronics /consumer-appsDLP®Products Energy and Lighting /energyDSP Industrial /industrialClocks and Timers /clocks Medical /medicalInterface Security /securityLogic Space,Avionics and Defense /space-avionics-defense Power Mgmt Transportation and /automotiveAutomotiveMicrocontrollers Video and Imaging /videoRFID Wireless /wireless-appsRF/IF and ZigBee®Solutions /lprfTI E2E Community Home Page Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2011,Texas Instruments Incorporated芯天下--/。
嵌入式系统实验指导书
第1部分DK-LM3S9B92 教学实验平台简介1.1 Stellaris® LM3S9B92开发板本书中旳所有实验都是基于DK-LM3S9B92开发平台,LM3S9B92开发板提供了一种平台给基于ARM Cortex-M3旳高性能旳LM3S9B92微控制器开发系统。
LM3S9B92是Stellaris® Tempest-class微控制器家族旳成员之一。
Tempest-class系列设备拥有性能为80MHz旳时钟速率,一种外围设备接口(EPI)和Audio I2S接口。
除了支持这些功能旳新硬件外,DK-LM3S9B92还涉及了一系列丰富旳基于其她Stellaris® 板旳外设。
开发板涉及一种板载线上调试接口(on-board in-circuit debug interface,ICDI),该接口支持JTAG和SWD调试。
一种原则旳ARM 20针脚旳调试头支持大量旳调试解决方案。
Stellaris® LM3S9B92开发套件加快了Tempest-class微控制器旳开发。
该套件还涉及了完整旳实验源代码。
Stellaris® LM3S9B92开发板涉及如下特性:⏹ 设立简朴旳USB线提供调试、通讯和供电功能⏹ 拥有众多外设旳灵活开发平台⏹ 彩色LCD图形显示– 320×240辨别率旳TFT LCD模块–电阻式触摸接口⏹ 拥有256K闪存,96K SDRAM以及整合以太网、MAC+PHY、USB OTG和CAN通讯功能旳80 MHz LM3S9B92 微控制器⏹ 8MB SDRAM扩展(通过EPI接口)⏹ 1MB串行闪存⏹ 精确3.00V电压参照⏹ 微解决器ROM中内建SAFERTOS™操作系统⏹ I2S立体声音频编解码器–输入输出–耳机输出–麦克风输入⏹ 控制器区域网络(CAN)接口⏹ 10/100 BaseT 以太网⏹ USB On-The-Go(OTG)连接器– Device、Host、以及OTG模式⏹ 顾客LED和按钮⏹ 指轮电位器(可以用于菜单导航)⏹ MicroSD 卡插槽⏹ 支持一系列调试选项–集成在线调试接口(ICDI)–全面支持JTAG、SWD和SWO–原则旳ARM 20 针脚JTAG 调试连接器⏹ USB 虚拟COM 端口⏹ 跳线分流以便重新分派I/O 资源⏹ 为StellarisWare 软件所支持,涉及图形库、USB 库和外围驱动库图1-1 DK-LM3S9B92开发板1.1.1 开发工具清单Stellaris® LM3S9B92 开发工具涉及开发和运营使用Stellaris®微解决器旳应用程序所需旳所有东西:⏹ LM3S9B92 开发板⏹ 网线⏹ 用于调试旳USB Mini-B 线缆⏹ 用于OTG 连接PC 旳USB Micro-B 线缆⏹ 用于USB 主机旳连接USB A 适配器旳USB Micro-A 线缆⏹ USB 闪存记忆棒⏹ microSD 卡⏹ 20 位带状电缆线⏹ 光盘涉及如下工具旳评估版本:– StellarisWare 及用于本开发板旳实验代码–IAR Embedded Workbench Kickstart Edition1.1.2 系统框图图1-2 DK-LM3S9B92开发板框图1.1.3 开发板阐明⏹ 开发板旳供电电压:4.75—5.25 VDC,从如下旳输入源中旳一种得到:–调试器(ICDI)USB 线缆(连接至PC)–USB Micro-B 线缆(连接至PC)–直流电源插孔(2.1x5.5mm 由外部电源供应)⏹ 尺寸:-107mmx 114mm⏹ 模拟参照电压:3.0V +/-0.2%⏹ RoHS 状态:符合注:当LM3S9B92开发板工作在USB主机模式时,主机旳连接器供电给已连接旳USB 设备。
基于LM3S9B96的心电监护系统
基于LM3S9B96的心电监护系统一功能介绍心血管疾病是威胁人类健康的主要疾病之一。
随着人们生活节奏的加快和工作压力的加大,越来越多的人不幸患有甚至死于心血管疾病。
由于心血管疾病具有发病突然、死亡率高等特点,因此,很有必要研制一种能够对心血管疾病患者及潜在患者进行实时监测并迅速报警的便携式心电监控设备。
现阶段市场中常见心电图仪在便携性与实时分析报警的结合方面仍有待改进,例如,当病人独自在家时,监测装置大多只能进行心电监测与记录,若有突发异常状况不能及时报警,很可能导致无法挽回的后果。
因此,本方案以价格低廉,携带方便,实时分析心电数据并及时对异常情况进行报警为研究出发点,提出了一种基于LM3S9B96的心电监护系统,针对LM3S9B96微处理器的特点提出了心电监护系统设计方案,能够实现对心电信号的实时分析处理,对异常情况的及时报警以及对病人的准确定位。
二方案描述硬件框图:基于LM3S9B96的心电监护系统由心电信号采集放大模块、LCD触摸屏号码输入与波形显示模块、GPS模块与EM310短信报警模块组成。
(1)将心电电极贴片贴到人体皮肤表面的固定位置,采集峰峰值为2mV左右的微弱心电信号,并通过导联线输入到心电信号采集放大模块进行放大,其输出电压范围应与LM3S9B96中ADC10模块的参考电压相匹配;(2)心电信号采集放大模块通过GPIO口与LM3S9B96相连,LM3S9B96内部的ADC10模块对心电信号采集放大模块的输出模拟信号进行模数转换,以便LM3S9B96对数字化的心电信号进行后续处理;(3)LM3S9B96内部的μDMA(Micro Direct Memory Access,微型直接存储器访问)控制器将模数转换后的心电信号传送到SRAM进行处理,设置μDMA通道在乒乓模式下工作,这样便可以在无需CPU 进行过多干预的条件下完成心电信号从ADC10到SRAM的连续传输;(4)LM3S9B96对传输到SRAM中的数据进行处理,包括小波分解与重构、动态R波阈值计算、病理逻辑诊断分类等步骤;(5)实时心电波形和心率由Kitronix公司的K350QVG-V1-F TFT LCD触摸显示屏显示,同时LCD显示屏还作为报警所需短信报警的电话号码的输入端,电话号码存储在Flash存储器中,确保掉电后不需要重新输入,便于使用;(6)LM3S9B96微控制器内部的两个UART模块分别与GPS模块和EM310模块相连,GPS模块用来采集观测对象的GPS地理位置信息,当检测到心电信号出现异常时,通过EM310模块将诊断信息和GPS地理位置信息以短信形式发送给指定号码进行报警。
ZH-LM3S9B96DB用户指南
ZH ZH--LM3S9B96DB Cortex M3应用应用开发用户指南开发用户指南南京智鹤电子南京智鹤电子科技有限公司科技有限公司尊敬的用户:您好!感谢您选购南京智鹤电子科技有限公司(原志和科技)物联网应用开发系统系列产品。
南京智鹤电子科技有限公司作为无线传感器网络解决方案的专业提供商,为ZigBee技术、RFID技术以及物联网技术在国内的推广与应用做出了不懈的努力,为广大初学者和用户提供从学习开发套件、RFID射频模块、ZigBee典型应用方案演示模型到产品解决方案和商业应用一条龙服务。
我们有资深的射频工程师及嵌入式软件工程师,在无线技术领域应用开发方面积累了大量的经验。
为了使广大电子工程师在物联网技术应用开发方面迅速入门和深入开发,南京智鹤电子科技有限公司经过全体研发人员的共同努力,在CC2530、LM3S9B96以及TRF7960等应用方案的基础上,成功研制了ZH-LM3S9B96DB物联网应用开发系统套件。
本手册是ZH-LM3S9B96DB Cortex M3开发系统(以下简称为ZH-LM3S9B96DB)的用户指南,主要目的是向用户描述ZH-LM3S9B96DB的软硬件开发平台以及在使用ZH-LM3S9B96DB进行学习和深入开发前所要做的准备工作。
无论您是初学者还是资深的电子工程师,我们都强烈建议您在进行学习和开发前认真阅读本手册,不要盲目下手做我们所提供的各类实验。
在您熟悉本手册后,您可按照我们配套提供的《ZH-LM3S9B96DB实验指导书》上的各类实验指导进行相关实验。
在实验过程中,您可能会遇到各种各样的问题,但请务必耐心,仔细检查实验的具体步骤是否与我们所描述的一致,若还是无法解决您的问题,您可使用如下方式联系我们以获取帮助:�技术支持邮箱:service@最后,衷心祝愿您早日掌握Cortex M3技术。
目录1.ZH-LM3S9B96DB软硬件开发平台 (4)1.1ZH-LM3S9B96DB的硬件平台 (4)1.1.1ZH-LM3S9B96DB综合网关 (6)1.1.2ZH-LM3S9B96-SDRAM扩展板 (15)1.1.3ZH-LM LINK(LM3S系列在线仿真器) (15)1.2ZH-LM3S9B96DB的软件平台 (17)1.2.1IAR Embedded Workbench (18)1.2.2LM Flash Programmer (18)1.2.3串口调试助手 (19)1.2.4TCP&UDP测试工具 (20)1.2.5StellarisWare (20)2.开发前的准备工作 (21)2.1硬件平台方面的准备工作 (21)2.2软件平台方面的准备工作 (21)2.2.1软件开发环境IAR Embedded Workbench for ARM v5.50.5的安装(必需)222.2.2StellarisWare软件的安装(必需) (22)2.2.3ZH-LM LINK仿真器的驱动程序安装(必需) (23)3.出厂演示实验 (30)3.1演示前的准备工作 (30)3.1.1ZH-LM3S9B96DB综合网关跳线设置 (30)3.1.2安装ZH-LM3S9B96-SDRAM扩展板 (30)3.1.3ZH-LM3S9B96DB综合网关外围连接 (31)3.2实验演示过程 (32)3.2.1ZH-LM3S9B96DB综合网关状态演示实验 (32)3.2.2ZH-LM3S9B96DB综合网关I/O控制演示实验 (32)3.2.3ZH-LM3S9B96DB综合网关ADC演示实验 (33)3.2.4ZH-LM3S9B96DB综合网关USB演示实验 (33)3.2.5ZH-LM3S9B96DB综合网关网络演示实验 (34)3.2.6ZH-LM3S9B96DB综合网关触摸屏演示实验 (35)3.2.7ZH-LM3S9B96DB综合网关图形库演示实验 (36)3.2.8ZH-LM3S9B96DB综合网关音频播放演示实验 (36)3.2.9ZH-LM3S9B96DB综合网关JTAG解码演示实验 (37)4.附录I—常见问题解答 (38)4.1LM3S9B96芯片和程序常见问题 (38)5.附录II—电路原理图 (39)5.1ZH-LM3S9B96DB综合网关原理图 (39)5.2ZH-LCMILI9320液晶模块原理图 (39)5.3ZH-LM3S9B96-SDRAM8MB扩展模块原理图 (39)5.4ZH-LM LINK仿真器原理图 (39)。
DK-LM3S9B96-FPGA;中文规格书,Datasheet资料
K-LM3S9B96-FPGA) provides an easy way to ral Interface (EPI) using the highly elopment platform.RequirementsM3S9B96 development platformoftware CD oaded an SD Card in the DK-LM3S9B96’s SD card slot. This is only necessary opment board via the eral Interface connector and the LCD connection header. Before installing the GA LCD A expansion jumper POT/PB4 at be removed. See Figure 1. DK-LM3S9B96Development Board.With the jumpers removed, you must then remove any expansion board that is currently fitted to the expansion connector. Boards that may be installed in this location are the SDRAM daughter board, the EPI Signal Breakout board or the Flash/SRAM/LCD daughter board. Figure 1. DK-LM3S9B96 Development Board Stellaris ® FPGA Expansion BoardThe Stellaris ® FPGA expansion board (D evaluate the capabilities of the Stellaris External Periphe integrated DK-LM3S9B96 dev FPGA Expansion BoardYou have a DK-L You have the Stellaris LM3S9B96 Development Kit Documentation and S RecommendationsYou have l for the “Save Image” function.A JTAG Programming cable that supports Xilinx® Spartan3 devices.Board Set-UpThe FPGA expansion board interfaces to the h DK-LM3S9B96 devel Extended Perip the bottom left of the board must also FPGA expansion board, you must remove the jumpers from JP16-31 in the QV section of the development board. If you do not remove the jumpers, the FPG board cannot be installed on the DK-LM3S9B96 development board. TheOnce the jumpers and expansion boards have been removed, fit the FPGA expansion board onto the DK-LM3S9B96 development board. There is a male EPI expansion connector on the bottom side of the FPGA expansion board that connects to the female EPI expansion5V Powerough the PCB. included tely above the JTAG port on the daughter upper pins immediately below and to the right of the “EXT +5V” ith the FPGA and is elopment kit. The ion PROM comes pre-loaded with the binary image required by the videocap application, so no FPGA-specific tools are required.find the videocap supported he LM Flash cation, it automatically connects to the FPGA and begins displaying the camera image on the LCD.d the videocap application in version 5879 or later of the StellarisWareellaris web site at /mcu/docs/mcuorphan.tsp?contentId=87903gle d view and full screen view.Save Image to DiskIf an SD Card is installed, click the “Freeze” and then “Save” buttons to save the camera image as a .bmp file.Image Quality ControlsThe Controls panel allows for real-time adjustment of the brightness, saturation, and contrast of the image.connector of the DK-LM3S9B96 development board (J2). Since the FPGA expansion board also interfaces to the LCD, there are holes to fit the LCD header pins thrOnce the expansion board is connected to the EPI and LCD interfaces, use the jumper wire to provide 5 V power to J5 (immedia board) from any of the three connector on the development board (as shown in Figure 1).VideoCap ApplicationThe “videocap” example application illustrates communication w provided in the StellarisWare® software release for the DK-LM3S9B96 dev FPGA expansion board’s configurat If you installed StellarisWare in the default installation directory, you can application source in the following location:C:\StellarisWare\boards\dk-lm39b96\Lower level subdirectories contain binaries for the application built with each toolchain. These binaries can be downloaded to the dk-lm3s9b96 board using t Programmer tool. When you run the videocap appli You can fin distribution. Download the latest version of StellarisWare from the /stThe application has the following functions:Pan / ZoomTouch and Drag on the touchscreen to pan the image. Click the “Scale” button to tog between 2x scaleCopyright © 2010 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.Texas Instruments108 Wild Basin Rd., Suite 350Austin, TX 78746/stellarisRev. 1.0 4/19/2010s are included on the Stellaris LM3S9B96 Development Kit Documentation and Software CD and are also available for download at theReferencesThe following reference /stellaris web site:Stellaris LM3S9B96 Development Kit User's Manual (publication num DK-LM3S9B96)bertion number K-LM3S9B96) Stellaris ® Peripheral Driver Library User’s Guide (publication number SW-DRL-UG) Stellaris LM3S9B96 Microcontroller Data Sheet (publication number DS-LM3S9B96)DK-LM3S9B96 Firmware Development Package User’s Guide (publica SW-DK-LM3S9B96-UG)DK-LM3S9B96 Firmware Development Package (order number SW-DIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDLP®Products Communications and /communicationsTelecomDSP Computers and /computersPeripheralsClocks and Timers /clocks Consumer Electronics /consumer-appsInterface Energy /energyLogic Industrial /industrialPower Mgmt Medical /medicalMicrocontrollers Security /securityRFID Space,Avionics&/space-avionics-defenseDefenseRF/IF and ZigBee®Solutions /lprf Video and Imaging /videoWireless /wireless-appsMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2010,Texas Instruments Incorporated分销商库存信息: TIDK-LM3S9B96-FPGA。
NRSEC3000在电压监测仪安全防护中的应用
NRSEC3000在电压监测仪安全防护中的应用郭晶;季爱明【摘要】Introduces the features, read and write operation of encryption chip NRSEC3000, as well as the hardware interface circuit and drivers between microprocessor and NRSEC3000. The software design process of key agreement when accessing to condition acquisition controller (CAC) is explained in detail. The mixed cryptosystem security protocols based on SM1 and SM2 algorithms is successfully implemented and effectively improves encryption-system's speed and safety. Finally the application of encryption chip NRSEC3000 in voltage monitor security protection is discussed.%介绍了加密芯片NRSEC3000的特点、读写工作原理以及微处理器对NRSEC3000进行操作时的硬件接口电路和底层驱动。
详细阐述了芯片与状态接入控制器(CAC)之间的秘钥协商软件设计流程,成功实现了以SM1、SM2算法为核心的混合加密协议,有效提高了加密系统的效率与安全。
最后讨论了该芯片在电压监测仪安全防护中的应用。
【期刊名称】《电子设计工程》【年(卷),期】2015(000)017【总页数】4页(P39-42)【关键词】电压监测仪;安全防护;NRSEC3000;秘钥协商;混合加密【作者】郭晶;季爱明【作者单位】苏州大学城市轨道交通学院,江苏苏州 215137;苏州大学城市轨道交通学院,江苏苏州 215137【正文语种】中文【中图分类】TN918随着智能电网技术的发展,配电自动化系统规模日益扩大,多种通信方式并存及所有报文均采用明文传输的通信方式导致系统受到各种网络攻击的风险较大[1]。
基于ARM Cortex-M3的电源监控系统
基于ARM Cortex-M3的电源监控系统
郭宇荃;于卫华
【期刊名称】《电子制作》
【年(卷),期】2014(0)7
【摘要】本文提出了一种智能化的电源监控系统,该系统可监视电源各供电支路
的电压和电流。
当某供电支路发生欠压、过压、过流等异常状态时,该系统可迅速自动响应,对该支路实施相应安全保护措施。
在正常工作状态下,上位机用户可通过显控软件实时查看各供电支路的电压和电流值,并可通过显控软件下发控制指令,控制相应的供电支路开通或关断。
本设计采用TI公司的Luminary Cortex-M3系列ARM中的LM3S9B96芯片,集嵌入式技术、电路控制、网络传输、计算机等
技术于一体,实现了一种小型化、高可靠性、可远程监控的智能电源系统。
【总页数】2页(P25-26)
【作者】郭宇荃;于卫华
【作者单位】中国电波传播研究所青岛分所 266000;中国联合网络通信有限公司
青岛市分公司 266000
【正文语种】中文
【中图分类】TP23
【相关文献】
1.基于ARM的UPS电源网络监控系统的研究 [J], 夏西泉
2.基于ARM的UPS电源网络监控系统的研究 [J], 赵鑫
3.基于ARM的通信电源监控系统的设计 [J], 邓海丽;刘泽军;刘敏
4.基于ARM嵌入式Web服务器的电梯应急电源远程监控系统设计 [J], 林建一;叶永武;嵇毅君
5.基于ARM的UPS电源网络监控系统的研究 [J], 侯玉芬
因版权原因,仅展示原文概要,查看原文内容请购买。
技术干货:MCU专用RTOS种类盘点
技术干货:MCU专用RTOS种类盘点微控制器(MCU)广泛应用在各行各业,如各式家电、工业自动化,即时控制、资料采集等领域,为因应工控所需的即时(Realtime)控制、快速回应等需求,因此MCU大多搭载RTOS(即时作业系统)运作。
随着物联网的兴起,软体业也为RTOS加入物联网的成分,以提早卡位物联网的核心软体市场…各种处理器专用之OS在一般功能(General-purpose)的处理器市场分类中,若以功能与执行速度来说,大致分为CPU > MPU > MCU。
CPU的功能最强,主要应用在电脑产品;MPU功能次之,其应用多元,主要应用在嵌入式系统与精简型电脑等多种;而MCU则是以单一应用为主,应用在各式家电、电子产品、嵌入式产品、可穿戴设备、物联网(IoT)应用产品等控制应用。
MCU内部整合了KHz~MHz级的CPU、KB~MB级的记忆体单元(RAM与ROM/EEPROM/Flash)、时脉产生器(Oscillator;Clock Generator)、与I/O扩充单元等,可视为一种速度较慢的系统单芯片(SoC)。
由于内部存储容量小,因此大型作业系统如Windows、Linux等是不可能塞入MCU去执行的,且MCU大多被应用在即时控制的环境,因此许多容量小的RTOS(Real-Time Operating System;即时作业系统),便成为开发MCU软体的主要平台。
----------------------------电子发烧友最新一期《智能硬件特刊》即将上线,敬请期待!主打嵌入式应用的中高阶RTOSRTOS的种类繁多,主要设计给基于MPU或MCU的嵌入式系统所使用。
例如MPU等级专用的有Integrity、QNX、VxWorks等功能强大之RTOS;至于体积较小巧,主要支援MCU等级为主的RTOS,则有Nucleus、ThreadX、Unison OS、ucOS II/III等等。
LM3S系列单片机休眠与深度休眠应用笔记
LM3S 系列单片机休眠与深度休眠应用笔记(一)LM3S 系列单片机休眠与深度休眠应用笔记1处理器的3 种模式Contex-M3 处理器除支持正常运行模式外,还支持睡眠模式和深度睡眠模式,用来实现低功耗。
处理器在运行模式中控制器积极执行代码;睡眠模式中器件的时钟不变,但控制器不再执行代码(并且也不再需要时钟);在深度睡眠模式中,器件的时钟可以改变,并且控制器不再执行代码(也不需要时钟)。
z 运行模式运行模式下,处理器和所有当前被RCGCn 寄存器使能的外设均可以正常运行。
系统时钟可以由包括PLL 在内的所有可用时钟源提供。
z 睡眠模式睡眠模式下,Cortex-M3 处理器内核和存储器子系统都不使用时钟。
外设仅在相应的时钟门控在SCGCn 寄存器中使能且Auto Clock Gating (见RCC 寄存器)使能时,或者在相应的时钟门控在RCGCn 寄存器中使能且Auto Clock Gating 被禁能时,才使用时钟。
睡眠模式下,系统时钟源和频率均与运行模式下相同。
z 深度睡眠模式深度睡眠模式下,Cortex-M3 处理器内核和存储器子系统都不使用时钟。
外设仅在相应的时钟门控在DCGCn 寄存器中使能且Auto Clock Gating (见RCC 寄存器)使能时,或者在相应的时钟门控在RCGCn 寄存器中使能且Auto Clock Gating 被禁能时,才使用时钟。
在睡眠模式下,系统时钟源默认为主振荡器。
但如果DSLPCLKCFG 寄存器中的IOSC 位被置位,那么系统时钟源也可以是内部振荡器。
在使用DSLPCLKCFG 寄存器时,如有必要,可以让内部振荡器上电,同时让主振荡器开始断电。
如果PLL 在执行WFI 指令时工作,硬件将会让主振荡器断电,并将激活的RCC 寄存器中的SYSDIV 字段变为1/16 。
当发生深度睡眠退出事件时,在使能深度睡眠期间被停止的时钟前,硬件先将系统时钟的时钟源和频率变回到开始进入深度睡眠模式时的值。
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SAFE RTOS™User’s ManualCopyrightCopyright © 2009 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. SAFE RTOS is a trademark of Wittenstein Aerospace and Simulation Ltd. Other names and brands may be claimed as the property of others.Texas Instruments108 Wild Basin, Suite 350Austin, TX 78746Main: +1-512-279-8800Fax: +1-512-279-8879SAFERTOS™ is a robust, specialized Real-time Operating System which has been independently certified by the TÜV ashaving been developed in compliance with IEC61508 up to Safety Integrity Level (SIL) 3.WITTENSTEIN high integrity systems is a trading name of WITTENSTEIN Aerospace and Simulation Ltd.SafeRTOS™ User’s ManualTable of ContentsPreface: About this Manual (11)Identification (11)Use in Safety-Related Systems (11)Document Overview (12)Scope (12)Contents (12)Chapter 1: System Overview (13)Summary of the SAFE RTOS Scheduler (13)Differences between SAFE RTOS and OPEN RTOS (13)Design Goals (13)Coding Conventions (14)Project Definitions (14)Naming Conventions (15)System Components (15)Tasks (15)Task Priorities (18)The Scheduler (18)Communication between Tasks and Interrupts (25)Interrupts (25)Chapter 2: Installation (27)Source Code and Libraries (27)Hook Functions (27)Configuration (28)Chapter 3: API Reference (29)Task Functions (29)vTaskInitializeScheduler() (30)xTaskCreate() (32)xTaskDelete() (35)xTaskDelay() (37)xTaskDelayUntil() (39)xTaskPriorityGet() (41)xTaskPrioritySet() (43)xTaskSuspend() (45)xTaskResume() (47)Scheduler Control Functions (49)xTaskStartScheduler() (50)vTaskSuspendScheduler() (51)xTaskResumeScheduler() (53)xTaskGetTickCount() (54)taskYIELD() (55)taskYIELD_FROM_ISR() (56)taskENTER_CRITICAL() (57)Table of ContentstaskEXIT_CRITICAL() (59)Queue Functions (61)xQueueCreate() (62)xQueueSend() (64)xQueueReceive() (66)xQueueMessagesWaiting() (68)xQueueSendFromISR() (69)xQueueReceiveFromISR() (71)Chapter 4: Stellaris® ARM® Cortex™-M3 Processor Core Port-Specific Information (73)Installation (73)C Startup Code (73)Vector Table (73)Execution Context (73)Interrupts (75)Interrupt Entry and Exit (75)Interrupt Priorities and Nesting (75)Interrupt Vectors (75)System Tick Timer (SysTick) (75)RAM Usage (76)SafeRTOS™ User’s ManualList of Code ExamplesCode Example1-1.pdTASK_CODE definition (16)Code Example1-2.Typical structure of a task (16)Code Example1-3. A task deleting itself prior to the function terminating (16)Code ing queues to implement binary semaphores (23)Code ing a gatekeeper task to control access to a resource (23)Code Example1-6.Deferring interrupt processing to the task level (25)Code Example2-1.vApplicationErrorHook() Function Prototype (27)Code Example2-2.vApplicationTaskDeleteHook() function prototype (28)Code Example2-3.vApplicationIdleHook() function prototype (28)Code ing the vTaskInitializeScheduler() API function (30)Code ing the xTaskCreate() API function (33)Code ing the xTaskDelete() API function (35)Code ing the xTaskDelay() API function (37)Code ing the xTaskDelayUntil() API function (40)Code ing the xTaskPriorityGet() API function (41)Code ing the xTaskPrioritySet() API function (44)Code ing the xTaskSuspend() API function (45)Code ing the xTaskResume() API function (48)Code ing the vTaskSuspendScheduler() and xTaskResumeScheduler() API functions (51)Code ing the xTaskGetTickCount() API function (54)Code ing the taskYIELD() API function (55)Code ing the taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros (58)Code ing the xQueueCreate() API function (63)Code ing the xQueueSend() API function (65)Code ing the xQueueReceive() API function (67)Code ing the xQueueMessagesWaiting() API function (68)Code ing the xQueueSendFromISR() API function (70)Code ing the xQueueReceiveFromISR() API function (72)Code Example4-1.Definition of the xPORT_INIT_PARAMETERS Structure (73)Code Example4-2.The ISR (75)List of Code ExamplesSafeRTOS™ User’s ManualList of FiguresFigure1-1.Valid Task State Transitions (17)Figure1-2.Valid Scheduler State Transitions (20)List of FiguresSafeRTOS™ User’s ManualList of TablesTable1-1.Project Definitions (14)Table1-2.Port-Dependent Definitions (14)Table1-3.Naming Conventions (15)Table1-4.Task States (17)Table1-5.Scheduler States (19)Table4-1.Example xPORT_INIT_PARAMETERS Initialization Values (74)List of TablesP R E F A C EAbout this ManualIdentificationThis is the user’s manual for SAFE RTOS™ - a low over head, mini, pre-emptive real timescheduler. SAFE RTOS is pre-programmed into the processor ROM, providing a uniqueway to develop high integrity applications quickly and safely.I ncorporating SAFE RTOS in to an embedded software application permits that applicationto be structured as a set of autonomous tasks. The scheduler selects which task toexecute at any point in time in accordance with the state and relative priority of each task.Chapter1, “System Overview”, elaborates on the states in which a task can exist.This SAFE RTOS User’s Manual contains detailed reference information related to usingSAFE RTOS from ROM.SAFE RTOS is based on the FREE RTOS™ and OPEN RTOS™ code base and can beused either as a general purpose real-time operating system or in a mission criticalenvironment.Use in Safety-Related SystemsSAFE RTOS was developed using a formal and rigorous process. The process wascertified by TÜV SÜD to confirm that it was in compliance with that mandated by IEC61508 [Reference 3] parts 1 and 3 for Safety Integrity Level (SIL) 3 projects. The sameprocesses have been used throughout the SAFE RTOS development.Simply using SAFERTOS in an application does not mean developers can make a claimrelated to the conformance of SAFE RTOS to any requirements or process specification(including IEC 61508 [Reference 3]) without first following a recognized system wideconformance verification process. Conformance evidence must then be presented,audited and accepted by a recognized and relevant independent assessmentorganization. Without undergoing this process of due diligence, no claim can be made asto the suitability of SAFE RTOS to be used in any safety or otherwise commercially criticalapplication.In order to facilitate low risk certification, WITTENSTEIN have developed a DesignAssurance Pack which contains full conformance evidence for SAFE RTOS. The DesignAssurance Pack facilitates certification and speeds and de-risks the use of SAFE RTOS inindustrial, medical and other similar critical applications.In order to obtain the Design Assurance Packs for either IEC61508 (SIL3) or FDA510(k)certification, please contact your local WITTENSTEIN sales representative. Informationcan be found at / or by sending an email toinfo@.Preface - About this ManualDocument OverviewScopeEngineers holding a position of responsibility within a safety or commercially criticaldevelopment team must be adequately trained or have adequate prior experience to fulfilltheir responsibilities competently. It is therefore assumed that readers are alreadyfamiliar with the concepts and development of multitasking embedded systems and thesefundamental concepts are omitted from this manual. The eBook “Using the FreeRTOSReal Time Kernel – A Practical Guide” provides a more introductory text that can bereferenced if required.The ‘’ symbol is used to emphasize instruction or information to which compliance isdeemed to be essential for the correct and safe integration of SAFE RTOS into anapplication.ContentsThe SAFE RTOS User’s Manual is organized into the following chapters:Chapter1, “System Overview,” provides an overview of SAFE RTOS and the description of the SAFE RTOS task, queue, semaphore and scheduling mechanisms.Chapter2, “Installation,” describes the installation and setup required to use SAFE RTOS in your application.Chapter3, “API Reference,” provides the SAFE RTOS API reference.Chapter4, “Stellaris® ARM® Cortex™-M3 Processor Core Port-Specific Information,”provides information on using Stellaris® ARM® Cortex™-M3 Processor Core productvariants.E SSENTIAL C OMPLIANCE I NFORMATIONSAFE RTOS users must not call functions within the SAFE RTOS code base that are not documentedin Chapter3, “API Reference.”C H A P T E R1System OverviewThis chapter provides an overview of SAFE RTOS.Summary of the SAFERTOS SchedulerThe SAFE RTOS pre-emptive real time scheduler has the following characteristics:Any number of tasks can be created – the availability of RAM being the only limiting factor.Each task is assigned a priority between zero and ten, zero being the lowest priority. Source code versions of SAFE RTOS (as opposed to ROMed versions) do not impose restrictions onthe number of priorities available.Any number of tasks can share the same priority – allowing for maximum application design flexibility.The highest priority task that is able to execute (that is, not blocked or suspended) will be the task selected by the scheduler to execute.Tasks of equal priority will each get a share of the processing time available to tasks of that priority. A time sliced round robin policy is used (see “The Scheduling Policy” on page18).Tasks can block for a fixed period.Tasks can block to wait for an absolutespecified time.Tasks can block with a specified time-out period to wait for queue events (either data being written to or read from the queue).Queues can be used to send data between tasks, and to send data between tasks and interrupt service routines (ISR).Semaphores can be used to synchronize tasks with other tasks and to synchronize tasks with interrupt service routines.Semaphores can be used to ensure mutually exclusive access to shared resources. Differences between SAFERTOS and OPENRTOS While SAFE RTOS and OPEN RTOS share many attributes, the development process hasnecessitated some notable differences. In partular SAFE RTOS does not perform anydynamic memory allocation, and SAFE RTOS performs numerious parameter and internaldata validity checks.SAFE RTOS is a statically declared subset of OPEN RTOS. OPEN RTOS to SAFE RTOSconversion instructions are provided in a separate technical note.Design GoalsThe design goal of SAFE RTOS is to achieve its stated functionality using a small, simple,and (most importantly) robust implementation.Chapter 1 - System OverviewCoding ConventionsThis section defines the coding conventions used for the SAFE RTOS API.Project DefinitionsEach C file that utilizes the SAFE RTOS API must include the SAFERTOS.h header. TheSAFERTOS.h header file itslef includes the ProjDefs.h header file which contains the definitions shown in Table 1-1 and Table 1-2.Table 1-1.Project Definitions DefinitionValue pdTRUE aa.The ‘pd’ prefix denotes that the constant is defined within the ProjDefs.hheader file. The ProjDefs.h header file also contains error code definitionsthat begin with the ‘err’ prefix.1pdFALSE0pdPASS1pdFAIL 0Table 1-2.Port-Dependent DefinitionsDefinitionValue portCHARchar (type)portLONGlong (type)portSHORTshort (type)portBASE_TYPEPort-dependent a – defined to be the most efficient data type for the architecture a.Port-dependent values are described in Chapter 4, “Stellaris® ARM® Cortex™-M3 Processor Core Port-SpecificInformation” on page 73.portMAX_DELAYPort-dependent portTickType Port-dependentSafeRTOS™ User’s ManualNaming ConventionsThe following conventions are used throughout the code:Parameter names are prefixed with their type as follows:Historically function names were also prefixed with their return type using the sameconvention. The additional validity checking performed by SAFE RTOS has resulted in nearly all API functions returning a value, and for reasons of portability this value is always of type portBASE_TYPE (prefix ‘x’). It is simpler therefore to consider any function that is prefixed ‘x’ as returning either a status code or a value, and any function that is prefixed ‘v’ (void) as returning no value.API functions are also prefixed with the feature to which they relate, either Task or Queue. For example, the prototype for the API function xTaskGetTickCount(), or xQueueSend().Macro names are written in all uppercase other than a lowercase prefix that indicates in whichheader file the macro is defined. The exception to this rule are the error codes which are prefixed with ‘err’ but contained in the ProjDefs.h header file.System ComponentsTasksIncluding SAFERTOS in your application allows the application to be structured as a set ofautonomous tasks. Each task executes within its own context with no coincidental dependency on other tasks within the system or the scheduler itself.Task FunctionsFunctions that implement a task must be of pdTASK_CODE type, where pdTASK_CODE is defined as shown in Code Example 1-1 with an example of such a function shown inCode Example 1-2.Table 1-3.Naming Conventions Parameter NameType Prefix Variables portCHARc portSHORTs portLONGl portBASE_TYPEx structures, and so onx voidv a a.For example, pointers to void and void functions.Pointers—p b b.For example, a pointer to a short will have the prefix ps, apointer to void will have the prefix pv, and so on.Unsigned variables —u cc.For example, an unsigned short will have the prefix us.Chapter 1 - System OverviewA task will typically execute indefinitely and as such be written as an infinite loop, also shown inCode Example1-2.Code Example1-1pdTASK_CODE definitiontypedef void (*pdTASK_CODE)( void * pvParameters );Code Example1-2Typical structure of a taskvoid vATaskFunction( void *pvParameters ){/* The function executes indefinitely so enter an infinite loop. */for( ;; ){/* -- Task application code goes here. -- */}}A task is created using the xTaskCreate() API function.A task is deleted using the xTaskDelete() API function.E SSENTIAL C OMPLIANCE I NFORMATIONA task function must never terminate by attempting to return to its caller (or by calling exit()) as doingso will result in undefined behavior. If required, a task can delete itself prior to reaching the functionend as shown in Code Example1-3.Code Example1-3A task deleting itself prior to the function terminatingvoid vATaskFunction( void *pvParameters ){for( ;; ){/* -- Task application code here. -- */}/* The task deletes itself (indicated by the NULL parameter) before reaching the end of the task function. */xTaskDelete( NULL );}The void* function parameter permits a reference to any type to be passed into the task when thetask is created. Where more than one parameter is required, a pointer to a structure can be used.See the API documentation for the xTaskCreate() function on page32 for further information. Task StatesOnly one task can be executing at a time. The scheduler is responsible for selecting the task toexecute in accordance with each task’s relative priority and state. A task can exist in one of thestates described by Table1-4, with valid transitions between states shown in Figure1-1 on page17.SafeRTOS™ User’s ManualFigure 1-1.Valid Task State TransitionsTable 1-4.Task States Task StateDescription Running When a task is actually executing it is said to be in the Running state. It is the taskselected by the scheduler to execute and is currently utilizing the processor.Only one task can be in the Running state at any given time.Blocked A task is in the Blocked state if it is waiting for an event. The task cannot continue untilthe event occurs and until that time, it cannot be selected by the scheduler as the task toenter the Running state.Tasks in the Blocked state always have a time-out period, after which the task becomesunblocked.Suspended A task enters the Suspended state when it is the subject of a call to the xTaskSuspend() API function, and remains in the Suspended state untilunsuspended by a call to the xTaskResume() API function. A time-out periodcannot be specified.A Suspended state task cannot be selected by the scheduler as the task to enter theRunning state.Ready A task is in the Ready state if it is able to enter the Running state (it is not in the Blockedor Suspended state), but is not currently the task that is selected to execute.The only tasks that are available to the scheduler for selection as the task to enter theRunning state are those that are in the Ready state.Ready is the initial state when a task is created.Chapter 1 - System OverviewEach task executes within its own context. The process of transitioning one task out of theRunning state while transitioning another task into the Running state is called context switching.A call to the xTaskSuspend() API function can cause a task in the Running state, Blockedstate, or Ready state to enter the Suspended state.Calls to the xTaskDelay() and xTaskDelayUntil() API functions can cause a task in theRunning state to enter the Blocked state to wait for a temporal event – the event being theexpiration of the requested delay period.Calls to the xQueueSend() and xQueueReceive() API functions can cause a task in theRunning state to enter the Blocked state to wait for a queue event – the event being either databeing added to or removed from a queue. “Intertask Communication” on page21 provides moreinformation on using queues.Task PrioritiesA priority is assigned to each task when the task is created.The priority of a task can be queried using the xTaskPriorityGet() API function andchanged by using the xTaskPrioritySet() API function.Low numeric values denote low priority tasks. The lowest priority value that can be assigned to atask is 0.High numeric values denote high priority tasks. The maximum priority that can be assigned to atask is 10 (this restriction applies only when executing SafeRTOS out of ROM).The SchedulerThe scheduler has responsibility for:Deciding which task to select to enter the Running statePerforming the applicable context switchingMeasuring the passage of timeTransitioning tasks from the Blocked state into the Ready state upon the expiration of a time-out periodMeasuring TimeA periodic (tick) timer interrupt is used to measure time. The time between two consecutive timerinterrupts is defined as one tick. All times are measured and specified in tick units.The number of milliseconds between each tick is set using the ulTickRateHz member of thestructure passed to the vTaskInitializeScheduler() API function.The core SysTick timer is used to generate the tick interrupt.The Scheduling PolicyThe scheduler selects as the task to be in the Running state the highest priority task that wouldotherwise be in the Ready state. In other words, the task chosen to execute is the highest prioritytask that is able to execute. Tasks in the Blocked or Suspended state are not able to execute.Different tasks can be assigned the same priority. When this is the case, the tasks of equal priorityare selected to enter the Running state in turn. Each task executes for a maximum of one tickperiod before the scheduler selects another task of equal priority to enter the Running state.SafeRTOS™ User’s ManualNOTE:While the scheduler ensures that tasks of equal priority are selected to enter the Running state in turn, it is not guaranteed that each such task will get an equalshare of processing time.Starting the SchedulerThe scheduler is started using the xTaskStartScheduler() API function. SeeCode Example1-5on page23 for an example usage scenario.At least one task must be created prior to the xTaskStartScheduler() function beingcalled.Calling the xTaskStartScheduler() function causes the creation of the Idle task. The Idletask never enters the Blocked or Suspended state. It is created to ensure there is always at leastone task that is able to enter the Running state. The idle task hook (callback) function can be usedto execute application-specific code within the Idle task.YieldingYielding is where a task volunteers to leave the Running state by re-entering the Ready state.When a task yields, the schedule re-evaluates which task should be in the Running state. If notasks of higher or equal priority to the yielding task are in the Ready state, then the yielding taskwill again be selected as the task to enter the Running state.A task can yield by explicitly calling the taskYIELD() macro, or by calling an API function thatchanges the state or priority of another task within the application.Scheduler StatesThe scheduler can exist in one of the states Table1-5, with valid transitions betweenstates shown in Figure1-2 on page 20.Table1-5.Scheduler StatesScheduler State DescriptionInitialization This is the initial state, prior to the scheduler being started.While in the Initialization state the scheduler has no control over theapplication execution.Tasks and queues can be created while the scheduler is in theInitialization state.Active While in the Active state the scheduler controls the applicationexecution by selecting the task that is in the Running state at anygiven time..Suspended The Scheduler does not perform any context switching while in theSuspended state. The task that was in the Running state when thescheduler entered the Suspended state will remain in the Runningstate until the scheduler returns to the Active state.Chapter 1 - System OverviewFigure1-2.Valid Scheduler State TransitionsThe scheduler enters the Suspended state following a call to thexTaskSuspendScheduler() function, and returns to the Active state following a call to thexTaskResumeScheduler() function.A code section that must be executed atomically (without interruption from other tasks orinterrupts) to guarantee data integrity is called a critical region. The traditional method ofimplementing a critical region of code is to disable and then re-enable interrupts as the criticalregion is entered and then exited respectively. The taskENTER_CRITICAL() andtaskEXIT_CRITICAL() macros are provided for this purpose. Critical sections will only disableinterrupts that have a priority up to and including interrupt priority 5 (a basepri value of 191). Theexecution of interrupts with a higher priority (those with priority 4 to 0) will not be effected by criticalsections.Implementing a critical section through the use of the taskENTER_CRITICAL() andtaskEXIT_CRITICAL() macros has the disadvantage of the application being unresponsiveto interrupts of priority 5 and below for the duration of the critical region. The scheduler suspensionmechanism provides an alternative approach that permits interrupts to remain enabled during thecritical region itself.The xTaskSuspendScheduler() API function places the scheduler into the Suspended state. Whilein the Suspended state a switch to another task will never occur. The task executing the criticalregion is guaranteed to remain as the task in the Running state until the xTaskResumeScheduler()function is called.SafeRTOS™ User’s ManualE SSENTIAL C OMPLIANCE I NFORMATION•Interrupts remain enabled while the scheduler is in the Suspended state. Critical regionsimplemented using the scheduler suspension mechanism therefore protect the critical data from access by other tasks, but not by interrupts. It is safe for an interrupt to access a queue or semaphore while the scheduler is in the Suspended state.•The xTaskSuspendScheduler() API function places the scheduler into the Suspended state. While in the Suspended state a switch to another task will never occur. The task executing the critical region is guaranteed to remain as the task in the Running state until the xTaskResumeScheduler() function is called. It is still desirable for the scheduler not to be held in the Suspended state for an extended period as doing so will reduce the responsiveness of high-priority tasks.Intertask CommunicationSAFE RTOS provides a queue implementation that permits data to be transferred safely between tasks. The queue mechanism removes the need for data that is shared between tasks to be declared globally, or for the application writer to concern themselves with mutual exclusion primitives when accessing the data.The queue implementation is flexible and can be used to achieve a number of objectives, including simple data transfer, synchronization, and semaphore-type behavior.Queue CharacteristicsThe queue is implemented as follows:At any time a queue can contain zero or more items.The size of each item and the maximum number of items that the queue can hold are configured when the queue is created.Items are sent to a queue using the xQueueSend() and xQueueSendFromISR() API functions.Items are received from a queue using the xQueueReceive() and xQueueReceiveFromISR() API functions. Queues are FIFO buffers – that is, the first item sent to a queue using the xQueueSend()(or xQueueSendFromISR()) function is the first item retrieved from the queue when using the xQueueReceive() (or xQueueReceiveFromISR()) function.Data transferred through a queue is done so by copy – the data is copied byte for byte into the queue when the data is sent, and then copied byte for byte out of the queue when the data is subsequently received.Queue EventsData being sent to or received from a queue is called a queue event.When calling the xQueueSend() function, a task can specify a period during which it should be held in the Blocked state to wait for space to become available on the queue if the queue is already full. The task is blocking on a queue event and leaves the Blocked state automatically when another task or interrupt removes an item from the queue.When calling the xQueueReceive() function, a task can specify a period during which it should be held in the Blocked state to wait for data to become available from the queue if thequeue is already empty. Again, the task is blocking on a queue event and leaves the Blocked state automatically when another task or interrupt writes data to the queue.Chapter 1 - System OverviewIf more than one task is blocked waiting for the same event, then the task unblocked upon theoccurrence of the event is the task that has the highest priority. Where more than one task of thesame priority are blocked waiting for the same event, then the task unblocked upon the occurrenceof the event will be the task that has been in the Blocked state for the longest time.Data FormattingThe queue sender and receiver must agree on the meaning of the data placed in the queue. Thiscould be a simple data type, such as a char or long, or a compound data type, such as a structurecontaining a number of complex data items. For example, a structure can be used to hold both adata value and the identity of the task sending the data.If the amount of data requiring transfer in each item is large, then it may be preferable to queue apointer to the data rather than the data itself. This is more efficient as only the pointer value needsto be copied rather than each byte of the data itself.E SSENTIAL C OMPLIANCE I NFORMATIONWhen data is sent to a queue by copy, then the queue implementation ensures access is consistentand mutual exclusion primitives are not required when accessing the data. When data is queued byreference (that is, a pointer to the data is queued rather than the data itself), then each task withaccess to the referenced data must agree how consistent and exclusive access is to be achieved.Using Queues as Binary SemaphoresSemaphores can be used for task to task synchronization, interrupt to task synchronization, and asa means for a task to signal that it wants to have exclusive access to data or other resources. Inthe latter case, while the task has the semaphore, other tasks know they are excluded fromaccessing the protected resource.To be permitted access to the resource, the task must first take the semaphore, and when it hasfinished with the resourc, it must give the semaphore back. If it cannot take the semaphore, itknows the resource is already in use by another task and it must wait for the semaphore tobecome available. If a task chooses to enter the Blocked state to wait for a semaphore, it willautomatically be moved back to the Ready state as soon as the semaphore is available.A binary semaphore can be considered to be a queue that can contain, as a maximum, one item.For efficiency, the item size can be zero, thus preventing any data from actually being copied intoand out of the queue. The important information is whether or not the queue is empty or full (theonly two available states as it can only contain one item), not the value of the data it contains.When the resource is available, the queue (representing the semaphore) is full. To take thesemaphore, the task simply receives from the queue which results in the queue being empty. Togive the semaphore, the task simply sends to the queue which results in the queue again beingfull. If, when attempting to receive from the queue, it finds the queue is already empty, a taskknows it cannot access the resource and can choose whether or not it wishes to enter the Blockedstate to wait for the resource to become available again.Code Example1-4 provides an example semaphore function that creates, takes, andgives that uses the SAFE RTOS queue implementation. See Chapter3, “API Reference”on page 29 for more information on the API functions used (xQueueCreate(),xQueueReceive(), and xQueueSend()). Macros are also provided to hide theunderlying mechanism.。