MOSFET3400
AO3400A SOT-23-3L NMOS Vds30V 规格书AO推荐
10µs 100µs 1ms
10ms
0.1
TJ(Max)=150°C
TA=25°C
10s DC
0.0
0.01
0.1
1
10
100
VDS (Volts)
Figure 9: Maximum Forward Biased Safe Operating Area (Note F)
Power (W)
1000 100
ID
Pulsed Drain Current C
IDM
TA=25°C Power Dissipation B TA=70°C
PD
Junction and Storage Temperature Range
TJ, TSTG
G S
Maximum 30 ±12 5.7 4.7 30 1.4 0.9
-55 to 150
In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
AO3400A
30V N-Channel MOSFET
General Description
Product Summary
The AO3400A combines advanced trench MOSFET technology with a low resistance package to provide extremely low RDS(ON). This device is suitable for use as a load switch or in PWM applications.
B. The power dissipation PD is based on TJ(MAX)=150°C, using ≤ 10s junction-to-ambient thermal resistance. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initialTJ=25°C. D. The RθJA is the sum of the thermal impedence from junction to lead RθJL and lead to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-ambient thermal impedence which is measured with the device mounted on 1in2 FR-4 board with
AO3400 规格书 AOS
VGS=10V
1.8
VGS=4.5V Id=5A 1.6
1.4
17
VGS=105V
1.2
Id=5.8A2
10
1
10
0
5
10
15
20
ID (A)
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note E)
0.8 0
25 50 75 100 125 150 175
In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
ZθJA Normalized Transient Thermal Resistance
ID(A)
15
VDS=5V 12
9
6
125°C 3
25°C
0
0
0.5
1
1.5
2
2.5
3
VGS(Volts) Figure 2: Transfer Characteristics (Note E)
Normalized On-Resistance
RDS(ON) (mΩ)
30
25 VGS=4.5V
20
15
AO3400
30V N-Channel MOSFET
General Description
Product Summary
The AO3400 combines advanced trench MOSFET technology with a low resistance package to provide extremely low RDS(ON). This device is suitable for use as a load switch or in PWM applications.
MOS管3400
1
2
3
引脚序号 SOT-23-6
1 2 3
4 5 6
引脚名称
作用
SW GND FB
EN VOUT VIN
开关引脚 电源地，信号地
反馈 逻辑控制停机输
入 输出 输入
SHIWEI SEMICONDUCTOR Co.,LTD. 深圳市世微半导体有限公司
ｗｗｗ．ｓｈｉｗｅｉｄｚ．ｃｏｍ
0755-86248636/29977358
负载电流
VIN=1.2V VIN=1.5V VIN=2.4V VIN=2.7V
负载与效率的关系曲线图
90 80 70 60 率50
效40 30 20 10 0
1
10
100
1000
负载电流
负载与效率的关系曲线图
VIN=1.2V VIN=1.5V
100
90 80 70
率 60
效 50
40 30 20 10
AP3400
绝对最大额定值
VIN电压…………………………………………………………………………………- 0.3 V ～ + 6 V VOUT电压……………………………………………...…………………………………- 0.3 V ～ + 6 V VSW电压 …….…………………………………………………………………………- 0.3 V ～ + 6 V VEN, VOUT电压…………………………………………………………………………- 0.3 V ～ + 6 V 工作温度范围…………………………………………………..………………………- 30℃ ～ + 85℃ 引脚温度(焊接时间 10 秒) ..……………………………………………………………………+ 300℃ 贮存温度范围 ………………………………………….…………………………..- 65℃ ～ + 125℃
AO3400
D
SOT-23-3L
G S
REF. A B C D E F
Millimeter Min. Max. 2.70 3.10 2.65 2.95 1.50 1.70 0.35 0.50 0 0.10 0.45 0.55
REF. G H K J L M
Millimeter Min. Max. 1.90 REF. 1.00 1.30 0.10 0.20 0.40 0.85 1.15 0° 10°
Parameter Static Drain-Source Breakdown Voltage Drain-Source On-State Resistance Drain-Source On-State Resistance Drain-Source On-State Resistance Gate Threshold Voltage Zero Gate Voltage Drain Current Gate Body Leakage Forward Transconductance Gate Resistance Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Source-Drain Diode Max. Diode Forward Current Diode Forward Voltage IS VSD IS = 1.6A, VGS = 0V 1.6 1.2 A V Qg VDS = 15V, ID = 5.8A Qgs VGS = 4.5V Qgd td(on) VDD = 15V, RL=2.7Ω tr ID = 1A, VGEN = 10V td(off) RG = 3Ω tf Ciss VDS = 10V, VGS = 0V Coss f = 1.0 MHz Crss 33 115 pF 3 340 10 38 50 15 20 ns 2.8 7 11 1.6 nC 11 14 BVDSS RDS(on) RDS(on) RDS(on) VGS(th) IDSS IGSS gfs Rg VGS = 0V, ID = 250uA VGS = 10V, ID = 5.8A VGS = 4.5V, ID =5A VGS = 2.5V, ID =4A VDS =VGS, ID = 250uA VDS = 24V, VGS = 0V VGS = ± 12V, VDS = 0V VDS = 5V, ID = 5A F=1.0MHz 10 6 15 7 7.5 0.7 30 22.0 27.0 43.0 28.0 33.0 52.0 1.4 1 ±100 V uA nA S Ω mΩ V
HT3400_Chinese spec_V1.0
Ver1.0
2
HT3400
电器特性（测试条件：Ta=25℃, Vin=1.2V , Vout = 3.3V,特别说明的除外）
参数
条件
最小 典型
输出电压范围 (可调.) 最小启动电压 最小工作电压 开关频率 最大占空比
限流滞后（相当于 Vout） 反馈电压
反馈吸收电流 NMOS 开关漏电流 PMOS 开关漏电流 NMOS 开关导通电阻 PMOS 开关导通电阻
SW
1
和电路板上的功率损耗。
GND
2
接地端.
反馈引脚.输出与地之间接两个电阻分压，再将分压接到此脚。输出电压的值根
FB
3
据公式 VOUT = 1.203V * [1 + (R1/R2)]可算出，调节范围在 2.5V 到 5.0V 之间。
逻辑使能开关. EN 为逻辑高电平时：芯片处于正常工作模式， 1.5MHz 的典型工
HT3400 变换器采用 SOT-23-6 引脚封装。
特点
高效率：高达 96% 低压启动：0.9V 输入电压范围：0.9V 至 5V 输出电压范围：2.5V 至 5V 1.5MHz 恒定频率操作 低接通电阻 RDS(ON) 内部开关:0.35Ω 短路保护 高开关电流: 1A 无需肖特基二极管（VOUT<4.3V） 超低停机电流:IQ＜1uA 小外型 SOT-23-6 封装 (无铅封装)
2.5 1.2 80 1.165
700 1
0.9 0.6 1.5 87 40 1.203 1 0.1 0.1 0.35 0.45 950 300 0.1
使能端吸收电流
VEN = 5.5V
0.01
最大 5
0.75 1.7
场效应管参数
1W(TO-92)
TO-92
MJE13003/KSE13003/
TO-12 20WTO-126
量
3DD13003/CS13003/
__
HM13003 NPN 400V 600V 9V 0.5A 3A
)
6
产 JCS13003/SIF13003/JD
TO-22
13003
0
40W(TO-22
0)
4A
HM13005 NPN 400V 700V 9V
O8810
21mΩ 21mΩ
SOT2 量 3-6 产
TSSO 量
AO8205/CEM8205/ APM8205 /AP8205/AO8205 AO8205A/CEM8205
道
HM4606
N+P 沟 30V/- 20V/
道
1.4V 30V -20V
HM50N03K N 沟道 30V 20V 1.6V
N 沟道 20V 12V 0.7V 3A
9A
RDS(o
n)
封装
(Max)
状 直接替代型号
态
Si2301/AP2301/SI23
SOT2 量 05/XP152A/
65mΩ 3
产 IRLML6401/IRML6
402/AO3423
Si2301/AP2301/SI23
SOT2 量 05/XP152A
74mΩ 3
极
型号
性
Ve Ic Vceo Vces
Ib
Icp
Ibp
Pc
bo
__
1W
HM13001 NPN 400V 600V 9V 0.5A 1A
状 封装 态
mosfet固态继电器型号
mosfet固态继电器型号Mosfet固态继电器（MOSFET Solid State Relay）是一种具有优异电气特性和可靠性的电子开关装置。
它由固态电子器件MOSFET和触发电路组成，能够实现电气信号的放大、开关和隔离等功能。
受到其低功耗、快速开关速度和长寿命等优点的驱动，Mosfet固态继电器被广泛应用于各种领域，包括自动化控制、家电、电力系统以及工业设备。
一、Mosfet固态继电器原理介绍Mosfet固态继电器是基于金属氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，缩写为MOSFET）的原理工作。
MOSFET是一种三端器件，包括门极（G），漏极（D）和源极（S）。
通过改变门极电压，可以实现对漏极-源极电流的控制。
当门极电压超过阈值电压时，MOSFET导通，漏极-源极间出现低电阻状态，形成通路。
相比传统继电器，Mosfet固态继电器具有更低的电阻和电压降。
二、Mosfet固态继电器的型号及特性1.型号一：G3MC系列G3MC系列是一系列具有高可靠性和高精度驱动电路的Mosfet固态继电器。
它采用了欧姆隔离技术，能够在较小的体积中实现大电流传导。
G3MC系列广泛应用于自动化设备、测量仪器以及家电等领域。
其特点包括：- 高继电器寿命：具有高达100万次的机械继电器寿命，可满足长时间运行的需求。
- 快速开关速度：能够在微秒级别内实现开关的快速响应，适用于高频率和精确控制的应用。
- 低功耗：相比传统继电器，G3MC系列的功耗更低，能够节省能源和降低系统成本。
2.型号二：AQV系列AQV系列是另一种常见的Mosfet固态继电器型号，采用了碳化硅功率MOSFET作为核心器件，具有更高的开关电压和电流能力。
AQV系列适用于需要高电流和高电压开关的应用场景，如电力系统和工业控制等。
其特性包括：- 高开关能力：AQV系列能够承受高达100A的电流和600V的电压，适用于大功率负载的控制。
ao3400中文资料
O3400a数据手册规格AO3401A中文信息PDF）MOS晶体管-MOS管测试步骤：5：MOS晶体管的Gate AOS公司MOS管7407导线的连接使栅极电荷释放，内部电场消失，导电沟道消失，因此漏极和源极之间的电阻变得无限大。
此时，用一根导线连接被测管的栅极和源，万用表的指针将立即返回无穷大，如图5-6所示。
6：MOS晶体管源AOS半导体MOS晶体管74117：VDMOS，MOSFET，osmos晶体管MOS 7413（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管8：MESFET如何工作AOS模拟开关MOS 74159：双栅极MOSFET AOSTVS二极管MOS晶体管7417如果去除了电阻，则探针将逐渐恢复为高电阻甚至无限大，因此应考虑被测管的栅极泄漏。
此时处于图5-4的状态；然后将连接的电阻移开，然后万用表的指针仍应为MOS晶体管导通指数保持不变，如图5-5所示。
尽管去除了电阻，但是由于由电阻充电至栅极的电荷不会消失，因此栅极电场继续保持，内部导电沟道保持不变，这是绝缘栅MOS晶体管的特性。
10：功率MOSFET有源模块MOS管740111：电子零件MOS管7405（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管12：AOS公司的MOS FET参数MOS 780013：用于MOS FET的AOS半导体MOS晶体管7801此时，使用100k-200k电阻连接栅极和漏极，如图5-4所示。
此时，欧姆越小越好。
通常，它可以指示0欧姆。
此时，正电荷通过100k电阻为高功率MOS晶体管的栅极充电，以产生栅极电场。
随着电场的产生，导电通道导致漏极和源极连接，因此万用表指针会偏转并偏转角度。
高度（小欧姆指数）表示良好的放电性能。
14：MOSFET AOS代理MOS晶体管340015：什么是场效应管MOS晶体管3400a（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管16：什么是MOS晶体管MOS晶体管340217：MOSFET的基础知识MOS晶体管3404将红色探针连接到MOS晶体管的源极，将黑色探针连接到MOS晶体管的漏极D。
ao3400中文资料
ao3400中文资料场效应管（Field Effect Transistor，缩写FET）是场效应晶体管的简称，是利用控制输入回路的电场效应来控制输出回路电流的一种半导体器件。
它主要有两种类型：结型场效应管和金属- 氧化物半导体场效应管，具有输入电阻高（107～1015Ω）、噪声小、功耗低、动态范围大、易于集成、没有二次击穿现象等优点。
与双极型晶体管相比，场效应管具有如下特点。
（1）场效应管是电压控制器件，它通过VGS(栅源电压)来控制ID（漏极电流）；（2）场效应管的控制输入端电流极小，因此它的输入电阻（107～1012Ω）很大。
（3）它是利用多数载流子导电，因此它的温度稳定性较好；（4）它组成的放大电路的电压放大系数要小于三极管组成放大电路的电压放大系数；（5）场效应管的抗辐射能力强；（6）由于它不存在杂乱运动的电子扩散引起的散粒噪声，所以噪声低。
场效应管工作原理用一句话说，就是“漏极-源极间流经沟道的ID，用以栅极与沟道间的pn结形成的反偏的栅极电压控制ID”。
更正确地说，ID流经通路的宽度，即沟道截面积，它是由pn结反偏的变化，产生耗尽层扩展变化控制的缘故。
在VGS=0的非饱和区域，表示的过渡层的扩展因为不很大，根据漏极-源极间所加VDS的电场，源极区域的某些电子被漏极拉去，即从漏极向源极有电流ID流动。
从门极向漏极扩展的过度层将沟道的一部分构成堵塞型，ID饱和。
将这种状态称为夹断。
这意味着过渡层将沟道的一部分阻挡，并不是电流被切断。
在过渡层由于没有电子、空穴的自由移动，在理想状态下几乎具有绝缘特性，通常电流也难流动。
但是此时漏极-源极间的电场，实际上是两个过渡层接触漏极与门极下部附近，由于漂移电场拉去的高速电子通过过渡层。
因漂移电场的强度几乎不变产生ID的饱和现象。
其次，VGS向负的方向变化，让VGS=VGS(off)，此时过渡层大致成为覆盖全区域的状态。
而且VDS的电场大部分加到过渡层上，将电子拉向漂移方向的电场，只有靠近源极的很短部分，这更使电流不能流通。
SI3400中文资料
Rev. 0.9 8/07Copyright © 2007 by Silicon LaboratoriesSi3400/Si3401This information applies to a product under development. Its characteristics and specifications are subject to change without notice.Si3400Si3401F U L L Y -I N T EG R A T E D 802.3-C O M P L I A N T PD I N T E R F A C E A N D S W I T CHI N G R E G U L A T O RFeaturesApplicationsDescriptionThe Si3400 and Si3401 integrate all power management and control functions required in a Power-over-Ethernet (PoE) powered device (PD)application. The Si3400 and Si3401 convert the high voltage supplied over the 10/100/1000BASE-T Ethernet connection into a regulated, low-voltage output supply. The optimized architectures of the Si3400 and Si3401minimize the solution footprint, reduce external BOM cost, and enable the use of low-cost external components while maintaining high performance.The Si3400 and Si3401 integrate the required diode bridges and transient surge suppressors, thus enabling direct connection of ICs to the Ethernet RJ-45 connector. The switching power FET and all associated functions are also integrated. The integrated switching regulator supports isolated (flyback) and non-isolated (buck) converter topologies. The Si3400 and Si3401 support IEEE STD™ 802.3-2005 (future instances are referred to as 802.3) compliant solutions as well as pre-standard products, all in a single IC. Standard external resistors connected to the Si3400 and Si3401 provide the proper 802.3 signatures for the detection function and programming of the classification mode. Startup circuits ensure well-controlled initial operation of both the hotswap switch and the voltage regulator. The Si3400and Si3401 are available in low-profile, 20-pin, 5x 5mm QFN packages.While the Si3400 is designed for applications up to 10W, the Si3401 is optimized for higher power applications (up to approximately 15W). See also “AN313: Using the Si3400/01 in High Power Applications” for more information.IEEE 802.3 standard-compliant solution, including pre-standard (legacy) PoE supportHighly-integrated IC enables compact solution footprintsMinimal external components Integrated diode bridges and transient surge suppressor Integrated switching regulator controller with on-chip power FETIntegrated dual current-limited hotswap switchSupport non-isolated and isolated switching topologiesComprehensive protection circuitryTransient overvoltage protectionUndervoltage lockoutEarly power-loss indicator Thermal shutdown protection Foldback current limiting Programmable classification circuitLow-profile 5x 5mm 20-pin QFNPb-Free and RoHS-compliantVoice over IP telephones and adaptersWireless access points Security camerasPoint-of-sale terminals Internet appliances Network devicesHigh power applications (Si3401)1.Pin VSSA added on revisions CZand higher.2. Pin ISOSSFT added on revisionsCZ and higher. Function available on revision E silicon. For Rev CZ, or to disable this feature on Revision E, tie this pin to VDD.Ordering Information:See Ordering Guide on pagepage 17.元器件交易网Si3400/Si34012Rev. 0.9Functional Block DiagramSi3400/Si3401Rev. 0.93T A B L E O F C O N T E N TSSectionPage1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2. PD Hotswap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.3. Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Si3400/Si34014Rev. 0.91. Electrical SpecificationsTable 1. Absolute Maximum Ratings (DC)1Type DescriptionRating UnitVoltageCT1 to CT2–60 to 60V SP1 to SP2–60 to 60VPOS 2–0.3 to 60HSO–0.3 to 60VSS1 or VSS2–0.3 to 60SWO–0.3 to 60PLOSS to VPOS 2–60 to 0.3RDET –0.3 to 60RCL–0.3 to 5SSFT to VPOS 2–5 to 0.3EROUT to VSS1, VSS2, or VSSA –0.3 to VDD+0.3FB to VPOS–5 to 0.3RIMAX to VSS1, VSS2, or VSSA –0.3 to VDD+0.3VSS1 to VSS2 or VSSA –0.3 to 0.3VDD to VSS1, VSS2, or VSSA–0.3 to 5CurrentRCL 0 to 100mA RDET0 to 1CT1, CT2, SP1, SP2–400 to 400VPOS 2–400 to 400HSO 0 to 400PLOSS –0.5 to 5VDD 0 to 2SWO0 to 400VSS1, VSS2, or VSSA–400 to 0Ambient TemperatureStorage –65 to 150°C Operating–40 to 85Notes:1.Unless otherwise noted, all voltages referenced to VNEG. Permanent device damage may occur if the maximum ratingsare exceeded. Functional operation should be restricted to those conditions specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability.2. VPOS is equal to VPOSF and VPOSS tied together for test condition purposes.Si3400/Si3401Rev. 0.95Table 2. Absolute Maximum Ratings (Transient)1Transient surge defined in IEC60060 as a 1000V impulse of either polarity applied across CT1–CT2 or SP1–SP2. The shape of the impulse shall have a 300ns full rise time and a 50µs half fall time, with 201Ω source impedance.Type Description Rating UnitVoltageCT1 to CT2–82 to 82VSP1 to SP2–82 to 82VPOS 2–0.7 to 80HSO–0.7 to 80VSS1, VSS2, or VSSA –0.7 to 80SWO–0.7 to 80PLOSS to VPOS 2–80 to 0.7RDET–0.7 to 80CurrentCT1, CT2, SP1, SP2–5 to 5A VPOS 2–5 to 5ESD 3HBM, all pins–2 to 2kVNotes:1.Unless otherwise noted, all voltages referenced to VNEG. Permanent device damage may occur if the maximum ratingsare exceeded. Functional operation should be restricted to those conditions specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability.2. VPOS is equal to VPOSF and VPOSS tied together for test condition purposes.3. For more information regarding system-level ESD tolerance, refer to “AN315: Robust Electrical Surge Immunity for PoEPDs through Integrated Protection”.Table 3. Recommended Operating ConditionsDescriptionSymbol Min Typ Max Units |CT1–CT2| or |SP1–SP2|VPORT 2.8—57V Ambient Operating TemperatureTA–402585°CNote:Unless otherwise noted, all voltages referenced to VNEG. All minimum and maximum specifications are guaranteedand apply across the recommended operating conditions. Typical values apply at nominal supply voltage and ambient temperature unless otherwise noted.Si3400/Si34016Rev. 0.9Table 4. Electrical CharacteristicsParameter Description Min Typ Max UnitVPORTDetection 2.7—11V Classification14—22UVLO Turn Off——42UVLO Turn On30—36 Transient Surge162—79Input Offset Current VPORT < 10V——10µA Diode bridge leakage VPORT=57V——25µAIPORT Classification2Class 00—4mA Class 19—12Class 217—20Class 326—30Class 436—44IPORT Operating Current336V<VPORT<57V—2 3.1mACurrent Limit4Inrush—130— mA Operating350 (Si3400)470 (Si3401)525550—mAHotswap FET On-Resistance +R SENSE36V<VPORT<57V0.5— 1.4ΩPower loss VPORT Threshold273033V Switcher Frequency—350—kHzMaximum Switcher Duty Cycle5ISOSSFT connected toVDD —50—%Switching FET On-Resistance0.3—0.86ΩRegulated Feedback @ pin FB6DC Avg.— 1.23—VRegulated Output Voltage Tolerance6Output voltage tolerance @VOUT –5—5%Notes:1.Transient surge defined in IEC60060 as a 1000V impulse of either polarity applied to CT1–CT2 or SP1–SP2. Theshape of the impulse shall have a 300ns full rise time and a 50µs half fall time with 201Ω source impedance.2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified inTable10.3. IPORT includes full operating current of switching regulator controller.4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, thecurrent limit is set at the inrush level. After the capacitor has been charged within ~1.25V of VNEG, the operating current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.6. Applies to non-isolated applications only (VOUT on schematic in Figure1).Si3400/Si3401Rev. 0.97VDD accuracy @ 0.8mA 36V <VPORT <57V4.5—5.5V Softstart charging current —12—µA Thermal ShutdownJunction temperature—160—ºC Thermal Shutdown Hysteresis——25ºCTable 5. Total Power DissipationDescription ConditionMin Typ Max Units Power Dissipation VPORT =50V, V OUT =5V, 2A— 1.2—W Power Dissipation*VPORT =50V, V OUT =5V, 2A w/ diode bridges bypassed—0.7—W*Note: Silicon Laboratories recommends the on-chip diode bridges be bypassed when output power requirements are >10W(Si3401) or in thermally-constrained applications. For more information, see “AN313: Using the Si3400 and Si3401 in High Power Applications”.Table 6. Package Thermal CharacteristicsParameterSymbol Test ConditionTyp Units Thermal resistance (junction to ambient)θJAStill air; assumes a minimum of nine thermal vias are connected to a 2in 2 heat spreader plane for the package “pad” node (VNEG).44°C/WTable 4. Electrical Characteristics (Continued)ParameterDescription Min Typ Max Unit Notes:1.Transient surge defined in IEC60060 as a 1000V impulse of either polarity applied to CT1–CT2 or SP1–SP2. Theshape of the impulse shall have a 300ns full rise time and a 50µs half fall time with 201Ω source impedance.2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified inTable 10.3. IPORT includes full operating current of switching regulator controller.4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, thecurrent limit is set at the inrush level. After the capacitor has been charged within ~1.25V of VNEG, the operatingcurrent limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).Si3400/Si34018Rev. 0.92. Typical Application SchematicsFigure1.Schematic—Class 0 with Non-Isolated 5V Output**Note:This is a simplified schematic. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more details and complete application schematics.Table 7. Component Listing—Class 0 with 5V OutputItem Type Value Toler.Rating NotesC1Capacitor15µF20%100V Switcher supply capacitor. Several paral-lel capacitors are used for lower ESR.C2Capacitor0.1µF20%100V PD input supply capacitor.C3Capacitor1000µF20%10V Switcher load capacitor - 1000µF in par-allel with and X5R 22µF for lower ESR.C4Capacitor0.1µF20%16V VDD bypass capacitor.C5Capacitor0.1µF10%16V Softstart capacitor.C6Capacitor 3.3nF10%16V Compensation capacitor.C7Capacitor150pF10%16V Compensation capacitor.R1Resistor25.5kΩ1%1/16W Detection resistor.R2Resistor7.32kΩ1%1/16W Feedback resistor divider.R3Resistor 2.87kΩ1%1/16W Feedback resistor divider.R4Resistor30.1kΩ1%1/16W Feedback compensation resistor.D1Diode100V Schottky diode; part no. PDS5100.L1Inductor33µH20% 3.5A Coilcraft part no. DO5010333.Si3400/Si3401Rev. 0.99Figure 2.Schematic—Class 1 with Isolated 5.0V Output**Note: This is a simplified schematic. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-IsolatedDesigns” for more details and complete application schematics.Table 8. Components—Class 1 with Isolated 5.0V OutputItem Type Value Toler.Rating NotesC1Capacitor 15µF 20%100V Switcher supply capacitor. Several paral-lel capacitors are used for lower ESR.C2Capacitor 0.1µF 20%100V PD input supply capacitor.C3Capacitor1100µF20%10VSwitcher load capacitor. 100µF in parallel 1000µF and optional 1µH inductor for additional filtering.C4Capacitor 15nF 10%16V Feedback compensation.C5Capacitor 220nF 10%16V Feedback compensation.C7Capacitor 0.1µF 20%16V VDD bypass capacitor.C8Capacitor 1µF 20%16V Isolated mode soft start (tie ISOSSFT to VDD if this feature is not used).R1Resistor 25.5k Ω1%1/16W Detection resistor.R2Resistor 4.99k Ω1%1/16W Pull-up resistor.R3Resistor 100Ω1%1/16W Feedback compensation resistor.R4Resistor 10k Ω1%1/16W Feedback compensation resistor.R5Resistor 2.05k Ω1%1/16W Pull-up resistor.R6Resistor 36.5k Ω1%1/16W Feedback resistor divider.R7Resistor 12.1k Ω1%1/16W Feedback resistor divider.R8Resistor 127Ω1%1/16W Classification resistor.D1Diode 10A 40V Schottky diode; part no. PN PDS1040.D2Diode 1A 100V Snubber diode (1N4148)D3Diode 15V 9ASnubber diode (DFLT15A)T1Transformer 40µHCoilcraft part number FA2672 (5V).PS2911Optocoupler TLV431Voltage referenceSi3400/Si340110Rev. 0.93. Functional DescriptionThe Si3400 and Si3401 consist of two major functions: a hotswap controller/interface and a complete pulse-width-modulated switching regulator (controller and power FET).3.1. OverviewThe hotswap interfaces of the Si3400 and Si3401 provide the complete front end of an 802.3-compliant PD. The Si3400 and Si3401 also include two full diode bridges, a transient voltage surge suppressor, detection circuit, classification current source, and dual-level hotswap current limiting switch. This high level of integration enables direct connection to the RJ-45 connector, simplifies system design, and provides significant advantages for reliability and protection. The Si3400 and Si3401 require only four standard external components (detection resistor, optional classification resistor, load capacitor, and input capacitor) to create a fully 802.3-compliant interface. For more information about supporting higher-power applications, see “AN313: Using the Si3400 and Si3401 in High Power Applications” and “AN314: Power Combining Circuit for PoE for up to 18.5W Output”.The Si3400 and Si3401 integrate a complete pulse-width modulated switching regulator that includes the controller and power FET. The switching regulator utilizes a constant frequency pulse-width modulated controller optimized for all possible load conditions in PoE applications. The regulator integrates a low on-resistance (Ron) switching power MOSFET that minimizes power dissipation, increases overall regulator efficiency, and simplifies system design. An integrated error amplifier, precision reference, and programmable soft-start current source provide the flexibility of using a non-isolated buck regulator topology or an isolated flyback regulator topology.The Si3400 and Si3401 are designed to operate with both 802.3-compliant Power Sourcing Equipment (PSE) and pre-standard (legacy) PSEs that do not adhere to the 802.3 specified inrush current limits. The Si3400 and Si3401 are compatible with compliant and legacy PSEs because they use two levels for the hotswap current limits. By setting the initial inrush current limit to a low level, a PD based on the Si3400 or Si3401 minimizes the current drawn from either a compliant or legacy PSE during startup. After powering up, the Si3400 and Si3401 automatically switch to a higher-level current limit, thereby allowing the PD to consume up to 12.95W (the max power allowed by the 802.3 specification).The inrush current limit specified by the 802.3 standard can generate high transient power dissipation in the PD. By properly sizing the devices and implementing on-chip thermal protection, the Si3400 and Si3401 can go through multiple turn-on sequences without overheating the package or damaging the device. The switching regulator power MOSFET has been conservatively designed and sized to withstand the high peak currents created when converting a high-voltage, low-current supply into a low-voltage, high-current supply. Excessive power cycling or short circuit faults will engage the thermal overload protection to prevent the onboard power MOSFETs from exceeding their safe and reliable operating ranges.3.2. PD Hotswap ControllerThe Si3400 and Si3401 hotswap controllers change their mode of operation based on the input voltage applied to the CT1 and CT2 pins or the SP1 and SP2 pins, the 802.3-defined modes of operation, and internal controller requirements. Table9 defines the modes of operation for the hotswap interface.3.2.1. Rectification Diode Bridges andSurge SuppressorThe 802.3 specification defines the input voltage at the RJ-45 connector of the PD with no reference to polarity. In other words, the PD must be able to accept power of either polarity at each of its inputs. This requirement necessitates the use of two sets of diode bridges, one for the CT1 and CT2 pins and one for the SP1 and SP2 pins to rectify the voltage. Furthermore, the standard requires that a PD withstand a high-voltage transient surge consisting of a 1000V common-mode impulse with 300ns rise time and 50µs half fall time. Typically, the diode bridge and the surge suppressor have been implemented externally, adding cost and complexity to the PD system design.The diode bridge* and the surge suppressor have been integrated into the Si3400 and Si3401, thus reducing system cost and design complexity.*Note:Silicon Laboratories recommends that on-chip diode bridges be bypassed when >10W of output power isrequired.By integrating the diode bridges, the Si3400 and Si3401 gain access to the input side of the diode bridge. Monitoring the voltage at the input of the diode bridges instead of the voltage across the load capacitor provides the earliest indication of a power loss. This true early power loss indicator, PLOSS, provides a local microcontroller time to save states and shut down gracefully before the load capacitor discharges below the minimum 802.3-specified operating voltage of 36V. Integration of the surge suppressor enables optimization of the clamping voltage and guarantees protection of all connected circuitry.As an added benefit, the transient surge suppressor, when tripped, actively disables the hotswap interface and switching regulator, preventing downstream circuits from encountering the high-energy transients.3.2.2. DetectionIn order to identify a device as a valid PD, a PSE will apply a voltage in the range of 2.8V to 10V on the cable and look for the 25.5kΩ signature resistor. The Si3400 and Si3401 will react to voltages in this range by connecting an external 25.5kΩ resistor between VPOS and VNEG. This external resistor and internal low-leakage control circuitry create the proper signature to alert the PSE that a valid PD has been detected and is ready to have power applied. The internal hotswap switch is disabled during this time to prevent the switching regulator and attached load circuitry from generating errors in the detection signature.Since the Si3400 and Si3401 integrate the diode bridges, the IC can compensate for the voltage and resistance effects of the diode bridges. The 802.3 specification requires that the PSE use a multi-point,∆V/∆I measurement technique to remove the diode-induced dc offset from the signature resistance measurement. However, the specification does not address the diode's nonlinear resistance and the error induced in the signature resistor measurement. Since the diode's resistance appears in series with the signature resistor, the PD system must find some way of compensating for this error. In systems where the diode bridges are external, compensation is difficult and suffers from errors. Since the diode bridges are integrated in the Si3400 and Si3401, the IC can easily compensate for this error by offsetting resistance across all operating conditions and thus meeting the 802.3 requirements. An added benefit is that this function can be tested during the IC’s automated testing step, guaranteeing system compliance when used in the final PD application. For more information about supporting higher-power applications (above 12.95W), see “AN313: Using the Si3400 and Si3401 in High Power Applications” and “AN314: Power Combining Circuit for PoE for up to 18.5W Output”.3.2.3. ClassificationOnce the PSE has detected a valid PD, the PSE may classify the PD for one of five power levels or classes. A class is based on the expected power consumption of the powered device. An external resistor sets the nominal class current that can then be read by the PSE to determine the proper power requirements of the PD. When the PSE presents a fixed voltage between 15.5V and 20.5V to the PD, the Si3400 and Si3401 assert the class current from VPOS through the RCL resistor.Table 9. Hotswap Interface ModesInput Voltage (|CT1-CT2| or |SP1-SP2|)Si3400 and Si3401Mode0V to 2.7V Inactive2.7V to 11V Detection signature11V to 14V Detection turns off andinternal bias starts 14V to 22V Classification signature22V to 42V Transition region42V up to 57V Switcher operating mode(hysteresis limit based onrising input voltage)57V down to 36V Switcher operating mode(hysteresis limit based onfalling input voltage)The resistor values associated with each class are shown in Table10.The 802.3 specification limits the classification time to 75ms to limit the power dissipated in the PD. If the PSE classification period exceeds 75ms and the die temperature rises above the thermal shutdown limits, the thermal protection circuit will engage and disable the classification current source in order to protect the Si3400 and Si3401. The Si3400 and Si3401 stay in classification mode until the input voltage exceeds 22V (the upper end of its classification operation region). 3.2.4. Under Voltage LockoutThe 802.3 standard specifies the PD to turn on when the line voltage rises to 42V and for the PD to turn off when the line voltage falls to 30V. The PD must also maintain a large on-off hysteresis region to prevent wiring losses between the PSE and the PD from causing startup oscillation.The Si3400 and Si3401 incorporate an undervoltage lockout (UVLO) circuit to monitor the line voltage and determine when to apply power to the integrated switching regulator. Before the power is applied to the switching regulator, the hotswap switch output (HSO) pin is high-impedance and typically follows VPOS as the input is ramped (due to the discharged switcher supply capacitor). When the input voltage rises above the UVLO turn-on threshold, the Si3400 and Si3401 begin to turn on the internal hotswap power MOSFET. The switcher supply capacitor begins to charge up under the current limit control of the Si3400 and Si3401, and the HSO pin transitions from VPOS to VNEG. The Si3400 and Si3401 include hysteretic UVLO circuits to maintain power to the load until the input voltage falls below the UVLO turn-off threshold. Once the input voltage falls below 30V, the internal hotswap MOSFET is turned off.3.2.5. Dual Current Limit and Switcher Turn-OnThe Si3400 and Si3401 implement dual current limits. While the hotswap MOSFET is charging the switcher supply capacitor, the Si3400 and Si3401 maintain a low current limit. The switching regulator is disabled until the voltage across the hotswap MOSFET becomes sufficiently low, indicating the switcher supply capacitor is almost completely charged. When this threshold is reached, the switcher is activated, and the hotswap current limit is increased. This threshold also has hysteresis to prevent systemic oscillation as the switcher begins to draw current and the current limit is increased, which allows resistive losses in the cable to effectively decrease the input supply.The Si3400 and Si3401 stay in a high-level current limit mode until the input voltage drops below the UVLO turn-off threshold or excessive power is dissipated in the hotswap switch. This dual level current limit allows the system designer to design powered devices for use with both legacy and compliant PoE systems.An additional feature of the dual current limit circuitry is foldback current limiting in the event of a fault condition. When the current limit is switched to the higher level, 400mA of current can be drawn by the PD. Should a fault cause more than this current to be consumed, the voltage across the hotswap MOSFET will increase to clamp the maximum amount of power consumed. The power dissipated by the MOSFET can be very high under this condition. If the fault is very low impedance, the voltage across the hotswap MOSFET will continue to rise until the lower current limit level is engaged, further reducing the dissipated power. If the fault condition remains, the thermal overload protection circuitry will eventually engage and shut down the hotswap interface and switching regulator. The foldback current limiting occurs much faster than the thermal overload protection and is, therefore, necessary for comprehensive protection of the hotswap MOSFET.Table 10. Class Resistor ValuesClass Usage Power Levels Nominal ClassCurrent RCL Resistor (1%,1/16W)0Default0.44W to 12.95W< 4mA> 1.33kΩ(or open circuit) 1Optional0.44W to 3.84W10.5mA127Ω2Optional 3.84W to 6.49W18.5mA69.8Ω3Optional 6.49W to 12.95W28mA45.3Ω4Reserved Reserved40mA30.9Ω3.2.6. Power Loss IndicatorA situation can occur in which power is lost at the input of the diode bridge and the hotswap controller does not detect the fault due to the VPOS to VNEG capacitor maintaining the voltage. In such a situation, the PD can remain operational for hundreds of microseconds despite the PSE having removed the line voltage. If it is recognized early enough, the time from power loss to power failure can provide valuable time to gracefully shut down an application.Due to integration of the diode bridges, the Si3400 and Si3401 are able to instantaneously detect the removal of the line voltage and provide that early warning signal to the PD application. The PLOSS pin is an open drain output that pulls up to VPOS when a line voltage greater than 27V is applied. When the line voltage falls below 27V, the output becomes high-impedance, allowing an external pull-down resistor to change the logic state of PLOSS. The benefit of this indicator is that the powered device may include a microcontroller that can quickly save its memory or operational state before draining the supply capacitors and powering itself down. This feature can help improve overall manageability in applications, such as wireless access points.3.3. Switching RegulatorPower over Ethernet (PoE) applications fall into two broad categories, isolated and non-isolated. Non-isolated systems can be used when the powered device is self-contained and does not provide external conductors to the user or another application. Non-isolated applications include wireless access points and security cameras. In these applications, there is no explicit need for dc isolation between the switching regulator output and the hotswap interface. An isolated system must be used when the powered device interfaces with other self-powered equipment or has external conductors accessible to the user or other applications. For proper operation, the regulated output supply of the switching regulator must not have a dc electrical path to the hotswap interface or switching regulator primary side. Isolated applications include point-of-sale terminals where the user can touch the grounded metal chassis.The application determines the converter topology. An isolated application will require a flyback transformer-based switching topology while a non-isolated application can use an inductor-based buck converter topology. In the isolated case, dc isolation is achieved through a transformer in the forward path and a voltage reference plus opto-isolator in the feedback path. The application circuit shown in Figure2 is an example of such a topology. The non-isolated application in Figure1 makes use of a single inductor as the energy conversion element, and the feedback signal is directly supplied into the internal error amplifier. As can be seen from the application circuits, the isolated topology has an increased number of components, thus increasing the bill of materials (BOM) and system footprint.To optimize cost and ease implementation, each application should be evaluated for its isolated or non-isolated requirements.。
泉芯QX3400规格书(2014版)
（3）采样电 阻的选择 采 样 电 阻 是 用 于 设 置 输 出 电 压 的 ，因 此 ，要 得 到 更 一 致 的 输 出 电 压 ，请 采 用 误
VIN (管脚6):电压输入端。VIN给IC一个启动电压，当VOUT大于VIN，MOSFET的 偏 置 电 压 将 从 输 出 获 取 。 因 此 ， 一 旦 启 动 ， 操 作 完 全 独 立 于 VIN。 IC的 的 工 作 仅 仅 受限于输出电压和电池的串联内阻。
外部元件选择
（ 1） 电 感 的 选 择 由 于 采 用 1.5MHz的 快 速 开 关 工 作 频 率 ，QX3400 能 使 用 极 小 的 贴 片 电 感 。在 大
同步升压 DC/DC 转换器 QX3400 QX3400
特性:
功能描述
最高至 96% 的转换效率 低 电 压 启 动 ： 0.9V 关断电流: < 1μA 输 入 电 压 ： 0.9V～ 5.0V 输出电压：2.5V～5.0V (使用肖特基 二极管可高至 5.2V ) 低开关导通电阻RDS(ON), 内部开关 电阻: 0.35Ω 1.4MHz 固定开关频率 高开关导通电流: 1A 短路保护 小 体 积 封 装 : SOT-23-6 (无 铅 封 装 )
7 of 12
QX3400
电感电流一般设在电感标称的峰值电流（ＩＰ）的 20% 到 40% 。采用高频 铁 氧 体 磁 心 电 感 比 廉 价 的 铁 心 电 感 的 功 率 损 耗 要 小 得 多 ，并 能 提 高 电 路 的 效 率 。电 感 应 选 择 低 内 阻 的 ，以 减 小 内 阻 引 起 的 功 率 损 耗 。为 最 小 化 辐 射 噪 音 ，请 使 用 带 屏 蔽 环 的 工 形 绕 线 电 感 。 有 关 电 感 及 其 供 应 商 请 参 看 表 1。
ao3400中文资料
ao3400中文资料半导体（Semiconductor）是一种电导率在绝缘体至导体之间的物质，其电导率容易受控制，可作为信息处理的元件材料。
从科技或是经济发展的角度来看，半导体非常重要。
很多电子产品，如计算机、移动电话、数字录音机的核心单元都是利用半导体的电导率变化来处理信息。
常见的半导体材料有硅、锗、砷化镓等，而硅更是各种半导体材料中，在商业应用上最具有影响力的一种。
顾名思义：常温下导电性能介于导体(conductor)与绝缘体(insulator)之间的材料，叫做半导体（semiconductor）。
物质存在的形式多种多样，固体、液体、气体、等离子体等等。
我们通常把导电性和导电导热性差或不好的材料，如金刚石、人工晶体、琥珀、陶瓷等等，称为绝缘体。
而把导电、导热都比较好的金属如金、银、铜、铁、锡、铝等称为导体。
可以简单的把介于导体和绝缘体之间的材料称为半导体。
与导体和绝缘体相比，半导体材料的发现是最晚的，直到20世纪30年代，当材料的提纯技术改进以后，半导体的存在才真正被学术界认可。
半导体的分类，按照其制造技术可以分为：集成电路器件，分立器件、光电半导体、逻辑IC、模拟IC、储存器等大类，一般来说这些还会被分成小类。
此外还有以应用领域、设计方法等进行分类，虽然不常用，单还是按照IC、LSI、VLSI（超大LSI）及其规模进行分类的方法。
此外，还有按照其所处理的信号，可以分成模拟、数字、模拟数字混成及功能进行分类的方法。
基本定义电阻率介于金属和绝缘体之间并有负的电阻温度系数的物质。
半导体室温时电阻率约在10E-5～10E7欧·米之间，温度升高时电阻率指数则减小。
半导体材料很多，按化学成分可分为元素半导体和化合物半导体两大类。
锗和硅是最常用的元素半导体；化合物半导体包括Ⅲ-Ⅴ 族化合物（砷化镓、磷化镓等）、Ⅱ-Ⅵ族化合物( 硫化镉、硫化锌等)、氧化物(锰、铬、铁、铜的氧化物),以及由Ⅲ-Ⅴ族化合物和Ⅱ-Ⅵ族化合物组成的固溶体（镓铝砷、镓砷磷等）。
低压MOSFET场效应管
低压MOSFE场效应管我司的HM2301/SOT-23/3A/30V/PMOS 的优点：是足充电器/多节保护板/家电/航模/遥控玩具等大电流/低内阻的应用场合。
我司的HM2302/SOT-23/3A/30V/NMOS 的优点：是足3A的电流，内阻小，和市场低端的1A的产品不同，可以用于移动电源3A的电流，内阻小，和市场低端的1A的产品不同，可以用于移动电源我司的HM3400/SOT-23-3L/5.8A/30V/NMOS 的优点：是足 5.8A的电流/大SOT-23封装的，内阻小，和市场低端的小SOT-23 的不同，可以用于移动电源/充电器/多节保护板/家电/航模/遥控玩具等大电流/低内阻的应用场合。
我司的HM3401/SOT-23-3L/4.2A/30V/PMOS 的优点：是足 4.2A的电流/大SOT-23封装的，内阻小，和市场低端的小SOT-23 的不同，可以用于移动电源/充电器/多节保护板/家电/航模/遥控玩具等大电流/低内阻的应用场合。
我司的HM2310/SOT-23-3L/3A/60V/NMOS的优点：1.耐压可达60V,足3A电流，大SOT-23封装的。
2.可以用于LED照明等耐压高的产品应用。
我司的HM4953的优点：电流大内阻小，可以用于全彩屏市场。
我司的HM4430的优点：电流大内阻小，电流可达18A.目前市场上S0P8/NM0Sfe流最大的一款产品之一。
我司的HM4440的优点：耐压可达60V,目前市场上S0P8/NM0S寸压最大的一款产品之一。
我司的HM10N10的优点：内阻小，耐电流不止10A的。
产品应用：1. MP3/MP4/MP5/PMP 播放器2. MID/UMPC3. GPS/蓝牙耳机4. PDVD/车载DVD/汽车音响5. 液晶电视/液晶显示器6. 移动电源/电子烟7. 手机电池、锂电池保护板8. LED照明/LED电源9. LED显示屏10. 智能充电器11. 小家电、家电控制板12. 电脑主板、显卡。
三极管3400引脚定义
三极管3400引脚定义1. 引言三极管（Transistor）是一种半导体器件，常用于电子电路中的放大、开关和稳压等应用。
三极管3400是一款具有特定引脚定义的三极管型号，本文将对其引脚定义进行详细介绍。
2. 三极管3400引脚定义三极管3400具有三个引脚，分别是：发射极（Emitter）、基极（Base）和集电极（Collector）。
2.1 发射极（Emitter）发射极是三极管3400的一个引脚，用来控制电流流入三极管的区域。
发射极一般标记为E，通常与负极（地）相连。
2.2 基极（Base）基极是三极管3400的第二个引脚，用来控制三极管的放大倍数。
基极一般标记为B。
2.3 集电极（Collector）集电极是三极管3400的第三个引脚，用来控制电流从三极管流出的区域。
集电极一般标记为C。
3. 三极管3400引脚定义示意图下图是三极管3400的引脚定义示意图：C|||||B|||||E4. 三极管3400引脚定义应用举例三极管3400的引脚定义在电子电路设计中扮演着重要的角色，下面是一些常见的应用举例：4.1 放大器三极管3400可以作为放大器的关键元件，通过控制基极电流的变化来调节输出信号的放大倍数。
在放大器电路中，发射极接地，基极连接输入信号源，集电极接输出负载。
当输入信号经过基极时，控制基极电流的变化，从而实现对输出信号的放大。
4.2 开关三极管3400也可以作为开关使用，用来控制电路的通断。
在开关电路中，当基极电流为零时，三极管处于截止状态，电路断开；当基极电流大于零时，三极管处于饱和状态，电路闭合。
通过控制基极电流的变化，可以实现对电路的开关控制。
4.3 稳压器三极管3400还可以用作稳压器的核心元件，通过调节基极电流来实现对电路的稳压功能。
在稳压器电路中，发射极接地，基极通过稳压电阻连接到正电源，集电极连接到负载电路。
通过调节基极电流的大小，可以使输出电压保持稳定。
5. 总结本文对三极管3400的引脚定义进行了详细介绍。
nce3400xy场效应管参数
一、场效应管简介场效应管是一种半导体器件，它具有高输入电阻和低输入电流的特点，常被用于放大和开关电路。
场效应管的参数对其性能和应用起到关键作用。
二、场效应管的参数1. 输入电阻：场效应管的输入电阻通常很高，大于10MΩ，这使得它对输入信号有很好的隔离，可以用于放大弱信号。
2. 噪声系数：场效应管的噪声系数通常较低，这使得它在放大低频信号时具有较好的性能。
3. 耗散功率：场效应管的耗散功率取决于工作状态和工作条件，一般需要根据数据手册来选择合适的工作状态和散热措施。
4. 最大漏极—源极电压（Vds）：这个参数限定了场效应管可以承受的最大电压，超过这个电压会导致管子击穿损坏。
5. 最大漏极—源极电流（Id）：这个参数限定了场效应管可以承受的最大电流，超过这个电流会使管子损坏，因此在设计电路时需要根据这个参数来选择合适的管子。
6. 输入电容：输入电容越低，管子就能用来放大更高频率的信号，这对一些高频率应用来说很重要。
三、场效应管参数的选择1. 根据应用需求选择合适的参数。
不同应用需要的参数不同，例如放大器需要高输入电阻和低噪声系数，电源开关需要承受较大的漏极—源极电压和电流。
2. 仔细查阅数据手册。
在选择场效应管时，要仔细查阅数据手册，了解其各项参数，以便根据具体应用需求来选择合适的管子。
四、结论通过了解场效应管的参数和选择方法，我们可以更好地根据具体的应用需求来选择合适的场效应管，从而提高电路性能并确保电路的可靠性和稳定性。
场效应管是一种重要的半导体器件，其参数的选择对于电路性能和稳定性具有至关重要的作用。
在实际应用中，根据具体的需求和工作条件，我们需要仔细选择合适的场效应管，以确保电路正常工作。
在选择场效应管的参数时，首先需要考虑电路的具体应用需求。
不同的应用需求会对场效应管的参数有不同的要求。
例如在放大器电路中，需要具有高输入电阻和低噪声系数的场效应管，以确保输入信号的准确放大而不受到太多的干扰。
MOS管AO3400
MOS管AO3400免费提供MOS管AO3400参数以及AO3400中文资料和AO3400中文资料pdf下载阅读观看！说明AO3400结合了先进的沟槽MOSFET低电阻封装技术提供R DS （ON）极低。
该设备适合用作负载开关或在PWM应用中。
产品概要30V N沟道MOSFETV DS 30伏I D（在V GS = 10V时）5.8AR DS（ON）（在V GS = 10V时）<28米ΩR DS（ON）（在V GS = 4.5V时）<33米ΩR DS（ON）（在V GS = 2.5V时）<52米ΩMOS管AO3400参数品牌：AOS型号：AO3400批号：19+封装：SOT23-3供应商设备包：SOT-23-3包装/箱：TO-236-3、SC-59、SOT-23-3工作温度：-55°C ~ 150°C (TJ)安装形式：表面安装场效应晶体管特性：-功耗（最大值）：1.4W（Ta）Vgs（最大）：±12V输入电容（Ciss）（最大值）@Vds:630pF@15V栅极电荷（Qg）（最大值）@Vgs:********Vgs（th）（最大值）@Id:1.45V @ 250µA无线电数据系统开启（最大值）@Id，Vgs:1.45V @ 250µA 驱动电压（最大开启，最小开启）：2.5V，10V电流-25°C时的连续漏极（Id）：5.8A（Ta）漏源电压（Vdss）：30V技术：MOSFET（金属氧化物）场效应管类型：N沟道零件状态：初步系列：-制造商：Alpha Omega Semiconductor Inc.类别：分立半导体产品。
SL3400 N-Channel MOSFET数据手册说明书
Absolute Maximum Ratings (T A =25℃unless otherwise noted) Parameter Symbol Limit UnitDrain-Source VoltageV DS 30 V Gate-Source VoltageV GS ±12 V Drain Current-ContinuousI D5.8 A Drain Current-Pulsed (Note 1)I DM 30AMaximum Power DissipationP D1.4 W Operating Junction and Storage Temperature RangeT J ,T STG-55 To 150℃Thermal Characteristic Thermal Resistance,Junction-to-Ambient(Note 2)R θJA 89/W ℃Electrical Characteristics (T A =25℃unless otherwise noted)ParameterSymbolCondition Min Typ MaxUnit Off CharacteristicsDrain-Source Breakdown Voltage BV DSS V GS =0V I D =250μA 30 33 - V Zero Gate Voltage Drain CurrentI DSSV DS =30V,V GS =0V -- 1 μA SL3400N-ChannelPower MOSFETGate-Body Leakage Current I GSSV GS =±12V,V DS =0V- - ±100 nAOn Characteristics (Note 3) Gate Threshold VoltageV GS(th) V DS =V GS ,I D =250μA 0.7 1.4 V V GS =2.5V, I D =4A - 459m ΩV GS =4.5V, I D = 5.8A- 45 m Ω Drain-Source On-State ResistanceR DS(ON) V GS =10V, I D = 5.8A -41 m ΩForward Transconductance g FS V DS =5V,I D = 5.8A 10 - - SDynamic Characteristics (Note4) Input Capacitance C lss - 820- PF Output CapacitanceC oss - 99- PFReverse Transfer Capacitance C rssV DS =15V,V GS =0V,F=1.0MHz- 77 - PF Switching Characteristics (Note 4) Turn-on Delay Time t d(on) - 9.6- nSTurn-on Rise Time t r - 4.8 - nS Turn-Off Delay Time t d(off) - 39- nSTurn-Off Fall Time t fV DD =15V, R L =2.7Ω V GS =10V,R GEN =3Ω - 4 - nSTotal Gate Charge Q g - 9.5 - nCGate-Source Charge Q gs - 1.5 - nCGate-Drain ChargeQ gd V DS =15V,I D =5.8A,V GS =4.5V- 3 - nC Drain-Source Diode Characteristics Diode Forward Voltage (Note 3) V SDV GS =0V,I S = 5.8A - - 1.2 VDiode Forward Current(Note 2)I S - - 5.8 ANotes:1. Repetitive Rating: Pulse width limited by maximum junction temperature.2. Surface Mounted on FR4 Board, t ≤ 10 sec.3. Pulse Test: Pulse Width ≤ 300μs, Duty Cycle ≤ 2%.4. Guaranteed by design, not subject to production0.9 53128Typical Electrical and Thermal CharacteristicsVoutFigure 1:Switching Test CircuitT J-Junction Temperature(℃)Figure 3 Power DissipationVds Drain-Source Voltage (V)Figure 5 Output CharacteristicsV INVtFigure 2:Switching Waveforms.T J-Junction Temperature(℃)Figure 4 Drain CurrentI D- Drain Current (A)Figure 6 Drain-Source On-Resistance PDPower(W)ID-DrainCurrent(A）RdsonOn-Resistance(Ω)ID-DrainCurrent(A)Vgs Gate-Source Voltage (V)Figure 7 Transfer CharacteristicsVgs Gate-Source Voltage (V)Figure 9 Rdson vs VgsQg Gate Charge (nC)Figure 11 Gate ChargeT J-Junction Temperature(℃)Figure 8 Drain-Source On-ResistanceVds Drain-Source Voltage (V)Figure 10 Capacitance vs VdsVsd Source-Drain Voltage (V)Figure 12 Source- Drain Diode Forward ID-DrainCurrent(A)RdsonOn-Resistance(Ω)VgsGate-SourceVoltage(V)NormalizedOn-ResistanceCCapacitance(pF)Is-ReverseDrainCurrent(A)SOT-23 Package InformationDimensions in Millimeters SymbolMIN. MAX. A 0.900 1.150A1 0.000 0.100A2 0.900 1.050b 0.300 0.500c 0.080 0.150D 2.800 3.000E 1.200 1.400 E1 2.250 2.550 e 0.950TYP e1 1.800 2.000L 0.550REF L1 0.300 0.500θ 0°8°。
ao3400工作原理
ao3400工作原理ao3400是一种功率MOSFET器件，其工作原理是基于场效应晶体管的原理。
在了解ao3400的工作原理之前，我们先来了解一下场效应晶体管。
场效应晶体管是一种三端器件，由漏极（Drain）、源极（Source）、栅极（Gate）组成。
它的工作原理是通过控制栅极电压来改变漏极和源极之间的电流。
而ao3400作为一种功率MOSFET器件，也是基于场效应晶体管的原理来工作的。
ao3400的主要结构是由P型衬底和N型沟道构成。
当栅极施加正电压时，栅极与沟道之间会形成电场，使沟道中的载流子产生漂移运动，从而形成导电通道。
当沟道处于导通状态时，漏极和源极之间的电流可以流通。
在ao3400中，沟道的导电特性是由栅极电压来控制的。
当栅极施加正电压时，沟道中的N型材料会形成导电通道，电流可以流通。
而当栅极施加负电压时，沟道中的N型材料会形成耗尽层，导电通道被截断，电流无法流通。
ao3400还具有电阻特性。
当沟道导通时，沟道中的N型材料的电阻非常低，可以近似看作导线。
而当沟道截断时，沟道中的N型材料的电阻非常高，可以近似看作开路。
这种电阻特性使得ao3400可以用作开关器件。
ao3400的工作原理可以总结为：通过控制栅极电压，来改变沟道的导通状态，从而控制漏极和源极之间的电流。
当栅极施加正电压时，沟道导通，电流流通；当栅极施加负电压时，沟道截断，电流无法流通。
通过了解ao3400的工作原理，我们可以看到它在电子设备中的应用非常广泛。
例如，在电源管理电路中，ao3400可以用作电源开关，通过控制栅极电压来控制电源的通断，实现对电路的开关控制。
此外，在功率放大电路中，ao3400也可以作为电流放大器使用，通过控制栅极电压来调节电流的大小。
ao3400作为一种功率MOSFET器件，其工作原理是基于场效应晶体管的原理。
通过控制栅极电压来改变沟道的导通状态，从而控制电流的流通。
它在电子设备中具有重要的应用价值，可以用于电源开关、电流放大等电路中。
ao3400工作原理
ao3400工作原理ao3400是一种常用的场效应管（MOSFET），它在电子设备中起着重要的作用。
它的工作原理可以通过以下几个方面来解释。
ao3400是一种N沟道MOSFET，它由P型衬底、N型漏极和源极以及P型栅极组成。
当没有外加电压时，ao3400处于关闭状态，即没有电流通过。
这是因为在关闭状态下，P型栅极和P型衬底之间形成了一个反向偏置的二极管结构，阻止电流流动。
当外加正向电压到达一定阈值时，ao3400开始工作。
这个阈值电压称为门源电压（VGS），当VGS超过阈值电压时，电流开始从漏极到源极流动。
此时，ao3400处于导通状态。
这是因为在导通状态下，P型栅极和P型衬底之间的二极管结构被正向偏置，电流可以通过。
与其他场效应管不同的是，ao3400具有低电压驱动特性。
这意味着它可以在较低的门源电压下实现高电流的控制。
这使得ao3400在许多低功耗应用中得到广泛应用，比如便携式设备和电子开关等。
ao3400还具有良好的开关速度和低导通电阻。
这使得它在开关电路和功率放大电路中表现出色。
它的开关速度快，可以迅速响应输入信号的变化。
而低导通电阻可以减少功率损耗和提高效率。
然而，ao3400也有一些限制。
首先，它的漏极电流与门源电压呈指数关系。
这意味着当门源电压达到一定值时，漏极电流增加的速度会变得非常缓慢。
其次，ao3400的阈值电压存在一定的误差。
这意味着在实际应用中，需要对其进行校准或者采取其他措施来保证其性能稳定和可靠性。
总结起来，ao3400是一种常用的N沟道MOSFET，具有低电压驱动、良好的开关速度和低导通电阻等特性。
它在电子设备中发挥着重要的作用，特别适用于低功耗应用和开关电路。
尽管有一些限制，但通过合适的设计和使用，可以充分发挥ao3400的优势，提高电子设备的性能和效率。
三极管3400引脚定义
三极管3400引脚定义三极管3400是一种常用的晶体管，也被称为NPN型晶体管。
它由三个部分组成，即基极（Base）、发射极（Emitter）和集电极（Collector）。
1. 基极（Base）是三极管的输入端，用来控制电流。
基极通常用来接收信号，当外部输入的电压或电流作用于基极时，控制区域上的载流子会发生变化，引起发射极和集电极之间的电流放大。
2. 发射极（Emitter）是三极管的输出端，专门用于放大基极中的信号电流。
发射极可以认为是由N型半导体构成的掺杂区域，其主要作用是集中冗余载流子并与集电极相连。
3. 集电极（Collector）是三极管的输出端，专门用于输出放大后的信号电流。
集电极可以认为是由P型半导体构成的掺杂区域，其主要作用是接收由发射极发射过来的电子。
三极管3400的引脚定义如下：1. 引脚1（Collector）：集电极，用于连接三极管的输出端。
在电路中，该引脚是接收放大后的信号电流的正极。
2. 引脚2（Base）：基极，用于连接三极管的输入端。
在电路中，该引脚用于控制电流和放大输入信号。
3. 引脚3（Emitter）：发射极，用于连接三极管的输出端。
在电路中，该引脚是输出放大后的信号电流的负极。
三极管3400是一种常见的晶体管，广泛应用于电子设备和电路中。
它可以通过控制基极的电流来实现放大功能，同时可以保持输入和输出电路之间的隔离。
三极管的工作原理复杂，但它的引脚定义简单明确，容易理解和使用。
三极管3400是一种低功耗的晶体管，通常用于放大小信号，例如音频信号。
它具有高频率响应和高电流放大能力，因此在很多应用中都起着至关重要的作用。
根据3400晶体管的引脚定义，我们可以方便地将其集成到电路中，实现信号的放大和控制。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Description
The K D3400 uses advanced trench technology to provide excellent on-resistance extremely efficient and cost-effectiveness device. The K D3400 is universally used for all commercial-industrial applications.
F eat u res
*Lower Gate Charge BV DSS30 V *Small Package Outline R DS(ON)28 mΩ* RoHS Compliant I D 5.8 A P acka g e D i me n s ion s
Packag e：SOT-23-3L（SC-59）
A b s olu te Max i m u m Rat ing s
Parameter Symbo l Rat i ngs Un i t Drain-So u rce Vol t age V DS30 V Ga t e-So u rce Vol t age V GS+/- 12 V Con t in u o u s Drain C u rren t3I D@T A=25℃ 5.8 A Con t in u o u s Drain C u rren t3I D@T A=70℃ 4.9 A P u lsed Drain C u rren t1I DM30 A Power Dissipa t ion P
@T A=25℃ 1.38 W
D
Linear Dera t ing Fac t or0.01 W/℃o perating J u nction and Storage Temperat u re Range Tj, Ts t g -55~+150 ℃Th erma l Data
Parameter Symbo l Va l ue Un i t Thermal Resis t ance J u nc t ion-ambien t3Max.R t hj-amb90 ℃/W
Electrical Characteristics (Tj = 25℃unless otherwise specified)
Source-Drain Diode
Notes: 1. Pulse width limited by Max. junction temperature.
2. Pulse width≦300us, duty cycle≦2%.
3. Surface mounted on 1 in2 copper pad of FR4 board; 270℃/W when mounted on Min. copper pad.
Characteristics Curve
Fig 1. Typical Output Characteristics Fig 2. Transfer Characteristics
Fig 3. On-Resistance v.s. Drain Fig 4. On-Resistance v.s. Junction Current and Gate Voltage Temperature
Fig 5. On-Resistance v.s. Gate-Source Voltage Fig 6. Body Diode Characteristics
Fig 7. Maximum Safe Operating Area Fig 8. Single Pulse Power Rating
Junction-to-Ambient
Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics
Fig 11. Normalized Maximum Transient Thermal Impedance。