LF2641P-REV1
M2764A-1F1中文资料
1/10NOT FOR NEW DESIGNNovember 2000This is information on a product still in production but not recommended for new designs.M2764ANMOS 64 Kbit (8Kb x 8) UV EPROMs FAST ACCESS TIME: 180nss EXTENDED TEMPERATURE RANGE s SINGLE 5V SUPPLY VOLTAGE s LOW STANDBY CURRENT: 35mA max sTTL COMPATIBLE DURING READ and PROGRAMs FAST PROGRAMMING ALGORITHM s ELECTRONIC SIGNATURE sPROGRAMMING VOLTAGE: 12VDESCRIPTIONThe M2764A is a 65,536 bit UV erasable and elec-trically programmable memory EPROM. It is orga-nized as 8,192 words by 8 bits.The M27C64A is housed in a 28 pin Window Ce-ramic Frit-Seal Dual-in-Line package. The trans-parent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pat-tern can then be written to the device by following the programming procedure.Figure 1. Logic DiagramAI00776B13A0-A12P Q0-Q7V PPV CCM2764AGE V SS8128FDIP28W (F)Ob so l e t ePr od u c t (s ) -O bs o l e t eP r od u c t (s)Ob s oO bs o l e t eP r od u c t (s)Figure 2. DIP Pin Connections Warning: NC = Not Connected.Note: Except for the rating "Operating Temperature Range", stresses above those listed in the T able "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.Table 2. Absolute Maximum RatingsDEVICE OPERATIONThe seven modes of operations of the M2764A are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for V PP and 12V on A9for Electronic Signature.Read ModeThe M2764A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection.Output Enable (G) is the output control and should be used to gate data to the output pins, inde-pendent of device selection.Assuming that the addresses are stable, address access time (t AVQV ) is equal to the delay from E to output (t ELQV ). Data is available at the outputs after the falling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV -t GLQV .Standby ModeThe M2764A has a standby mode which reduces the maximum active power current from 75mA to 35mA. The M2764A is placed in the standby mode by applying a TTL high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.Two Line Output ControlBecause EPROMs are usually used in larger mem-ory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows :a.the lowest possible memory power dissipation,plete assurance that output bus contention will not occur.M2764A2/10Obs o l e t eP r od u c t (s) For the most efficient use of these two control lines,E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus.This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.System ConsiderationsThe power switching characteristics of fast EPROMs require careful decoupling of the devices.The supply current, I CC , has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be sup-pressed by complying with the two line output control and by properly selected decoupling ca-pacitors. It is recommended that a 1µF ceramic capacitor be used on every device between V CC and V SS . This should be a high frequency capacitorof low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V CC and V SS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.ProgrammingWhen delivered (and after each erasure for UV EPROM), all bits of the M2764A are in the “1" state.Data is introduced by selectively programming ”0s"into the desired bit locations. Although only “0s” will be programmed, both “1s” and “0s” can be present in the data word. The only way to change a “0" to a ”1" is by ultraviolet light erasure.The M2764A is in the programming mode when V PP input is at 12.5V and E and P are at TTL low.The data to be programmed is applied, 8 bits in parallel, to the data output pins. The levels required for the address and data inputs are TTL.Fast Programming AlgorithmFast Programming Algorithm rapidly programs M2764A EPROMs using an efficient and reliable method suited to the production programming en-vironment. Programming reliability is also ensured as the incremental program margin of each byte iscontinually monitored to determine when it hasIH IL ID Table 3. Operating ModesTable 4. Electronic SignatureDEVICE OPERATION (cont’d)M2764A3/10O bs c t Figure 3. AC Testing Input Output WaveformsInput Rise and Fall Times ≤ 20ns Input Pulse Voltages0.45V to 2.4V Input and Output Timing Ref. Voltages0.8V to 2.0VAC MEASUREMENT CONDITIONSFigure 4. AC Testing Load CircuitNote that Output Hi-Z is defined as the point where data is no longer driven.Note: 1.Sampled only, not 100% tested.Table 5. Capacitance (1) (T A = 25 °C, f = 1 MHz )Figure 5. Read Mode AC WaveformsM2764A4/10u Table 7A. Read Mode AC Characteristics (1)(T A = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )Note: 1.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .Table 6. Read Mode DC Characteristics (1)(T A = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )CC PP PP 2.Sampled only, not 100% tested.Table 7B. Read Mode AC Characteristics (1)(T A = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )M2764A5/10c t (s) CC PP PP Table 8. Programming Mode DC Characteristics (1)(T A = 25 °C; V CC = 6V ± 0.25V; V PP = 12.5V ± 0.3V)Notes: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .2. The Initial Program Pulse width tolerance is 1 ms ± 5%.3. The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending of the multiplication value of the iteration counter.4. Sampled only, not 100% tested.Table 9. Programming Mode AC Characteristics (1)(T A = 25 °C; V CC = 6V ± 0.25V; V PP = 12.5V ± 0.3V)M2764A6/10O bs o Figure 6. Programming and Verify Modes AC WaveformsFigure 7. Fast Programming Flowchart been successfully programmed. A flowchart of theM2764A Fast Programming Algorithm is shown on the last page. The Fast Programming Algorithm utilizes two different pulse types: initial and over-program.The duration of the initial P pulse(s) is 1ms, whichwill then be followed by a longer overprogram pulse of length 3ms by n (n is equal to the number of the initial one millisecond pulses applied to a particular M2764A location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are pro-vided for before the overprogram pulse is applied.The entire sequence of program pulses and byte verifications is performed at V CC = 6V and V PP =12.5V. When the Fast Programming cycle has been completed, all bytes should be compared to the original data with V CC = 5V and V PP = 5V.Program InhibitProgramming of multiple M2764A in parallel with different data is also easily accomplished. Except for E, all like inputs (including G) of the parallel M2764A may be common. A TTL low pulse applied to a M2764A’s E input, with V PP at 12.5V, will program that M2764A. A high level E input inhibits the other M2764As from being programmed.DEVICE OPERATION (cont’d)M2764A7/10Ob sol ebs o l e t eP r od u c t (s) Program VerifyA verify should be performed on the programmed bits to determine that they were correctly pro-grammed. The verify is accomplished with G = V IL ,E = V IL , P = V IH and V PP = 12.5V.Electronic SignatureThe Electronic Signature mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.This mode is functional in the 25°C ± 5°C ambient temperature range that is required when program-ming the M2764A.T o activate this mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M2764A. Two identifier bytes may then be se-quenced from the device outputs by toggling ad-dress line A0 from V IL to V IH . All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0 = V IL ) represents the manufac-turer code and byte 1 (A0 = V IH ) the device identifier code. For the SGS-THOMSON M2764A, these two identifier bytes are given below.ERASURE OPERATION (applies to UV EPPROM)The erasure characteristic of the M2764A is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M2764A in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M2764A is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M2764A window to prevent unintentional erasure. The recommended erasure procedure for the M2764A is exposure to short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultra-violet lamp with 12000 µW/cm 2 power rating. The M2764A should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be re-moved before erasure.-1180 ns, 5V ±5% -2200 ns, 5V ±5% blank250 ns, 5V ±5% -3300 ns, 5V ±5% -4450 ns, 5V ±5% -20200 ns, 5V ±10%-25250 ns, 5V ±10%FFDIP28W10 to 70 ° 6–40 to 85 °CExample: M2764A -1 F 1ORDERING INFORMATION SCHEMEFor a list of available options (Speed, V CC Tolerance, Package, etc...) refer to the current Memory Shortformcatalogue.For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you.M2764A8/10M2764ADrawing is not to scale9/10Ob so l e t ePr od u c t (s ) -O bs o l e t eP r od u c t (s) M2764A10/10Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners© 2000 STMicroelectronics - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.。
ISL6411中文资料
The ISL6411 is an ultra low noise triple output LDO regulator with microprocessor reset circuit and is optimized for powering wireless chip sets. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.84V (LDO2), and another ultra clean 2.84V (LDO3). On chip logic provides sequencing between LDO1 and LDO2 for BBP/MAC and I/O supply voltage outputs. LDO3 features ultra low noise that does not typically exceed 30µV RMS to aid VCO stability. High integration and the thin Quad Flat No-lead (QFN) package makes ISL6411 an ideal choice to power many of today’s small form factor industry standard wireless cards, such as PCMCIA, mini-PCI and Cardbus-32.
Valtek MaxFlo 4 Eccentric Rotary Plug Control Valv
Valtek MaxFlo 4 Eccentric Rotary Plug Control ValveMaxFlo 4 Eccentric Rotary Plug Control Valve2The Flowserve Valtek MaxFlo 4 control valve is a high performance eccentric rotary plug valve designed for the process industry. It features a large capacity, standard hardened trim and superior shaft blow-out protection. This valve is available in sizes 1 through 12 inches, ASME Class 150, 300 and 600 as well as DIN PN 10, PN16, PN 25, PN40 and PN63.An optional ISA 75.08.01 or DIN EN 558 series 1 long-pattern body makes this valve an easy drop-in replacement for a globe control valve.The MaxFlo 4 is suitable for most applications; its control valve features include:• Highest Rated Cv • Precise Control • Reliable Shut-off• Most Current Safety Standards • Fugitive Emissions Elimination •Integral Noise Reduction PlatesHighest Rated CvThe unique design of the MaxFlo 4 shaft and plug provide as much as 70% more Cvcompared to the competition. This allows customers to get more flow when neededand sometimes allows for a smaller, more economical valve to be used.Precise ControlThe MaxFlo 4 polygon connection between the shaft and plug is a proven superiormethod for making demanding mechanical connections that are stronger, more preciseand have a substantially longer service life. This reduces backlash and the high strengthof the polygon connections makes them capable of withstanding greater shock loadsunder extreme torque reversal conditions.Reliable Shut-offThe MaxFlo 4 double-offset eccentric plug rotates into the seat at an angle that eliminatessliding over the seat surface. This design reduces seat wear, and thereby decreases main-tenance requirements and costs. At the same time, a tight ANSI Class VI shutoff is easilyobtainable using the soft seat design.Safety StandardThe shaft is designed to meet the safety requirements of industry standard ASME B16.34to ensure that the shaft is retained even if the actuator is removed when the valve is stillpressurized. This is standard on every MaxFlo 4 to provide our customers with confidenceand safety.3Separate bonnet ensures positive anti-blowout, accommodates multiple packing options, and offers flexibility in material selection for demandingapplications.Heavy-duty rigid metal seat,with hardfaced or soft-seat options, provides tighter shutoff, and easier maintenance. Available in full area and several reductions in every size to suit your process needs.Blow out proof shaft required by ASME B16.34 2004 Sec 6.5 ensures safety. Standard on every MaxFlo 4.An economical flangeless configuration of the MaxFlo 4 is also available. The standard flanged body is the same length. To replace existing globe valves we offer the flanged body with the same face to face length as a globe valve (Per ISA 75.08.01).4Open Flow Path gives as much as 70%more C v than competitive valves that have the shaft obstructing the flow. In many cases it is possible to use a smaller, more economical MaxFlo 4.Flanged end post allows for easy maintenance.Hard stainless steel plug requires no breakout torque and increases valve life as the plug lifts off the seat immediately when it begins rotating.Precision NC machined plug and shaft significantly reduces maintenance costs byallowing replacement of only the necessary parts.Polygon shaft/plug connection for precise robust control.Shimless seat offers simplified assembly and easy maintenance.5Eliminate Fugitive EmissionsSpecial Flowserve packing sets, such as SureGuard XT live loaded packing, are available to control fugitive emissions. Packing options include: PTFE V-Ring, Braided PTFE, Graphite, Sureguard XT, Garlock SVS, LATTYflon 3265 LM and LATTYgraf 6995 NG (meeting requirements for TA-Luft, ISO 15848-1 class B and A, and EPA standards).Integral Noise-Reduction Plate OptionDesigned to reduce noise levels by 5 to 10 dBA, our integral plate fits into the valve body. It can be easily maintained using the same tools required for the seat retainer. It is perfectly suitable with all gases in the shaft-downstream direction, and the plate does not change the length of the valve.Integrated Control Valve SolutionOperated by a diaphragm, piston, or rack-and-pinion actuator coupled with a Logix digital positioner, the MaxFlo 4 maintains high positioning accuracy, repeatability, controlled high speed and reliable response. With the advanced diagnostic solutions that can be seamlessly integrated into a host control and/or plant asset management system, along with state-of-the-art features and performance, the MaxFlo 4 is the most economical Eccentric Rotary Plug valve in the market.NR Diaphragm Rotary ActuatorThe Flowserve NR diaphragm rotary actuator is a rugged single-acting actuator designed to provide high performance, long life and reliability. The diaphragm actuator is very sensitive to small changes in air supply, which allows it toprecisely move the valve plug without over shoot.6Logix 3000MD+ Digital PositionerEasiest calibration and configuration of any positioner available. Single, push-button calibration and DIP switch configuration allow you to fully commission the positioner in a matter of minutes. Using ValveSight Software DTM brings the availability of 24/7 diagnostics.For more information see document number LGENIM0059 and LGENIM3404 at .Logix 500MD+ Series Digital PositionerTo minimize your total cost of ownership and maximize productivity, Flowserve developed the Logix MD+ digital positioner. The Logix MD+ digital positioner allows for fast, simple commis-sioning, extremely accurate and reliable control, and diagnostic features that provide powerfuland easy ways to determine when maintenance is required.ValveSight™ Diagnostic Software – Prevention deliveredValveSight is a diagnostic solution for control valves that can be seamlessly integrated into a host control and/or plant asset management system. The power of ValveSight is the intel-ligent diagnostic engine -- which detects an emerging condition in the valve, actuator, posi-tioner, and control signal -- that may indicate a performance, safety, or environmental problem. ValveSight advises which corrective actions totake to prevent a failure.VR Spring Cylinder Rotary ActuatorThe Flowserve VR spring cylinder rotary actuator combines high torque and pneu-matic stiffness with excellent throttling capabilities. These characteristics are designed into a lightweight, rugged and compact assembly, making the Flowserve spring cylinder rotary actuator an excel-lent choice for quarter-turn applications.SuperNova Rack & Pinion Rotary ActuatorThe Flowserve SuperNova rack & pinion rotary actuator is designed forreliability, versatility and safety. Rugged, yet compact construction combined with technical solutions make this product extremely reliable in the severest of operating conditionsLogix 420 Digital PositionerThe Logix 420 is the latest addition to the digital positioner family from Flowserve. When mounted to the MaxFlo 4 eccentric rotary plugcontrol valve, Logix 420 provides the user with a cost competitive solutionfor the general service, explosion proof market. For more information see document numberLGENIM0106 at www .Unparalleled Service: Day or Night, WorldwideFlowserve Quick Response Centers (QRCs) are equipped with thousands of parts, including OEM andFlowserve custom-built products. Each has the manpower andequipment to expedite time-sensitiverepairs of any size.7To find your local Flowserve representative:For more information about Flowserve Corporation, visit or callUSA 1 800 225 6989 or International +1 972 910 0774FCD VLENBR0064-01-AQ Printed in USA. November 2015. © 2015 Flowserve Corporation United States Flowserve1350 N. Mt. Springs Parkway Springville, UT 84663USAPhone: +1 801 489 8611Fax: +1 801 489 3719AustriaFlowserve Control Valves GmbH Kasernengasse 69500 Villach AustriaPhone: +43 (0)4242 41181 0Fax: +43 (0)4242 41181 50FranceFlowserve France S.A.S.BP 60 63307 Thiers Cedex FrancePhone: 33 4738 04266Fax: 33 4738 01424IndiaFlowserve India Controls Pvt. Ltd Plot # 4, 1A, E.P .I.P , Whitefield Bangalore Kamataka India 560 066Phone: +91 80 284 10 289Fax: +91 80 284 10 286SingaporeFlowserve Pte. Ltd.12 Tuas Avenue 20Republic of Singapore 638824SingaporePhone: +65 6879 8900Fax: +65 6862 4940Saudi ArabiaFlowserve Abahsain Flow Control Co., Ltd.Makkah Road, Phase 4Plot 10 & 12, 2nd Industrial City Damman, Kingdom of Saudi ArabiaPhone: +966 3 857 3150 ext. 243Fax: +966 3 857 4243ChinaFlowserve Fluid Motion and Control (Suzhou) Co., Ltd.No. 35, Baiyu RoadSuzhou Industrial Park, Suzhou Jiangsu Province, P .R. 215021ChinaPhone: 86 512 6288 8790Fax: 86 512 6288 8736。
SST38LF6401RT 4M ×16 CMOS Advanced Multi-Purpose F
SummaryThe SST38LF6401RT is a 4M ×16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+) upgraded for space applications. It is manufactured with SST proprietary, high-performance CMOS SuperFlash ® technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST38L-F6401RT writes (program or erase) with a 3.0V to 3.6V power supply. This device conforms to JEDEC standard pin assignments for ×16 memories.SST38LF6401RT Parallel Rad Tolerant Flash MemoryFeatures• Density: 64 Mbit• Read access time: 90 ns • Page size (bytes): 8• Temperature range: –55°C to +125°C • Endurance: 10,000 cycles • Organized as 4M ×16• Single voltage read and write operations : 3.0V to 3.6V • Superior reliability, endurance: up to 10,000 cycles mini-mum, greater than 100 years data retention•Low-power consumption (typical values at 5 MHz)• Active current: 4 mA (typical)• Standby current: 3 µA (typical)• Auto low-power mode: 3 µA (typical)• 128-bit unique ID• Security-ID feature, 256 word, user one-time programmable• Protection and security features, hardware boot block protection/WP# input• Hardware Reset Pin (RST#)•Fast read and page read access times: 90 ns page read access times, 4-word page read buffer• Latched address and data• Fast erase times: sector-erase time: 18 ms (typical), block-erase time: 18 ms (typical), chip-erase time: 40 ms (typical)• Erase-suspend/resume capabilities• Fast word and write-buffer programming times:• Word-program time: 7 µs (typical)• Write buffer programming time: 1.75 µs/word(typical)• 16-word write buffer• Automatic write timing: internal V pp generation• End-of-write detection, toggle bits, data# polling, ry/by# output• CMOS I/O compatibility• JEDEC standard, Flash EEPROM pinouts and command sets• Pin, uniform (32 KWord) and non-uniform (8 KWord) op-tions available, user-controlled individual block (32 KWord) protection, using software only methods • Password protection • CFI Compliant•Packages available: 48-lead TSOP ceramic or plasticThe Microchip name and logo, the Microchip logo and SuperFlash are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies.© 2020, Microchip Technology Incorporated. All Rights Reserved. 11/20 DS00003649AWhat is SuperFlash Technology?SuperFlash Technology is an innovative, highly reliable and versatile type of NOR Flash memory invented by Silicon Storage Technology (SST, which is owned by Microchip). SuperFlash memory is much more flexible and reliable than competing non-volatile memories. This technology utilizes a split-gate cell architecture which uses a robust thick-oxide process that requires fewer mask steps resulting in a lower-cost nonvolatile memory solution with excellent data retention and higher reliability.Advantages of SuperFlash Technology• Fast, fixed program and erase times (typical chip-erase time: 40 ms)• No pre-programming or verify required prior to erase (Results in significantly lower power consumption)• Superior reliability (10K cycles and 100 years data retention)• Inherent small sector size (4 KB erase sector vs. 64 KB), results in faster re-write operations and contributes to lowering overall power consumptionSpace Environment• Full wafer lot traceability• 48-lead hermetic ceramic dual flat package (CDFP)• Space-grade screening and qualification (QML and ESCC flow)• T otal ionizing dose: better than 50 Krad, (biased & unbiased) • Heavy ions and protons tested• Single event latch-up immune with a LET > 78 MeV .cm²/mg • Full SEU characterization• No SEU corruption up to 46 MeV .cm²/mgFunctional Block Diagram®。
aurora_64b66b_protocol_spec_sp011
aurora_64b66b_protocol_spec_sp011Aurora 64B/66B Protocol SpecificationSP011 (v1.2) July 23, 2010Xilinx is disclosing to you this Specification (hereinafter "the Specification") for use in the development of designs in connection with semiconductor devices. Xilinx expressly disclaims any liability arising out of your use of the Specification. Xilinx does not convey any license under its patents, copyrights, or any rights of others in connection with the Specification. Y ou are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification without notice and at the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained in the Specification or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Specification.THE SPECIFICA TION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. YOU BEAR THE ENTIRE RISK AS TO ITS IMPLEMENTA TION AND USE. YOU ACKNOWLEDGE AND AGREE THA T YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, ITS EMPLOYEES OR CONTRACTORS. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STA TUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A P ARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DA TA OR LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICA TION, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.2008, 2010 Xilinx, Inc. All rights reserved.XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.Revision HistoryThe following table shows the revision history for this document.Date Version Revision03/31/08 1.0Initial Xilinx release.09/19/08 1.1Minor typographical edits. Changed block codes to blocks. Removed Not Ready blocks from Simplex in Table4-1, page36. Clarified simplex Aurora channel bonding inSection4.2.2“Channel Bonding,” page36. Added Appendix1, “References.”07/23/10 1.2Updated Section1.2“Scope” and Section8.1“Overview.”Deleted Sections 8.4 Transmitter Specifications, 8.5 Receiver Specifications, and 8.6Receiver Eye Diagrams.Table of ContentsSchedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schedule of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Preface: About This SpecificationSpecification Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Online Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12State Diagram Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Section1: Introduction and Overview1.1:Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2:Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Section2: Data Transmission and Reception2.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2:Block Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3:Frame Transmission Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1:Link-Layer Frame Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.2:64B/66B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.3:Serialization and Clock Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.4:Multi-Lane Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4:Frame Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.1:Deserialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.2:64B/66B Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3:Control Block Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.4.4:Multi-Lane Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.5:Data and Separator Block Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Section3: Flow Control3.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2:Native Flow Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.3:Native Flow Control Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4:Native Flow Control Block Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.5:User Flow Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6:User Flow Control Message Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Section4: Initialization and Error Handling4.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2:Aurora Channel Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.2.1:Lane Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.2.2:Channel Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.3:Wait For Remote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3:Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.4:CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Section5: PCS Layer5.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2:Aurora Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2.1:Block Codes in 64B/66B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2.2:Idle/Not Ready/Clock Compensation/Channel Bonding Block Code. . . . . . 405.2.3:Native Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.4:Data Block Code for Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.5:Separator Block Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.6:Separator-7 Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.7:User Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.8:Data Block Code for User Flow Control Message . . . . . . . . . . . . . . . . . . . . . . . . 445.2.9:User K-Block Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.3:64B/66B Scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.4:64B/66B Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.5:Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.6:Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section6: Channel Control6.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2:Idle Block Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.1:Not Ready Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.2:Idle Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.3:Clock Compensation Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.4:Channel Bonding Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.3:Native Flow Control Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.4:Frame Data Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.5:Strict-Alignment Frame Data Striping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.6:User Flow Control Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.7:Strict-Alignment User Flow Control Striping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.8:User K-Block Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Section7: PMA Layer7.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.2:Bit and Byte Ordering Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.3:Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Section8: Electrical Specifications8.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.2:Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.3:Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Appendix1: ReferencesSchedule of FiguresPreface: About This SpecificationFigure P-1:Properties of Literals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure P-2:State Machine Diagram Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Section1: Introduction and OverviewFigure 1-1:Aurora Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 1-2:A Simplex Connection Between a Pair of Aurora Lanes . . . . . . . . . . . . . . . . . 18Figure 1-3:A Single-Lane, Simplex Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 1-4:A Multi-Lane, Simplex Aurora Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 1-5:A Single-Lane, Full-Duplex Aurora Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 1-6:A Multi-Lane, Full-Duplex Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Section2: Data Transmission and ReceptionFigure 2-1:Mapping Frames to Encoded Block Codes for Transmission. . . . . . . . . . . . . 23Figure 2-2:Receiving Data from an Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 2-3:Data Block Used for Frame Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-4:Separator Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-5:Separator-7 Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 2-6:Example of Frame Data Transfer through a Single-Lane Channel . . . . . . . . 27Figure 2-7:Example of Frame Data Transfer through a Multi-Lane Channel . . . . . . . . . 27Section3: Flow ControlFigure 3-1:NFC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 3-2:UFC Block with UFC Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-3:Data Block Used to Carry UFC Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-4:Example UFC Messages for Single-Lane Channel . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-5:Example UFC Messages for a Multi-Lane Channel. . . . . . . . . . . . . . . . . . . . . . 32Section4: Initialization and Error HandlingFigure 4-1:Initialization Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 4-2:Block Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Section5: PCS LayerFigure 5-1:Idle/Not Ready/NFC Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 5-2:Native Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-3:Data Block Code Carrying Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-4:Separator Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-5:Separator-7 Block Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 5-6:User Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 5-7:Data Block Code Carrying User Flow Control Message Data. . . . . . . . . . . . . 44 Figure 5-8:User K-Block Code Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Section6: Channel ControlSection7: PMA LayerFigure 7-1:Serialization Order for Aurora 64B/66B Block Codes. . . . . . . . . . . . . . . . . . . . 49Section8: Electrical SpecificationsFigure 8-1:Differential Peak-To-Peak Voltage of Transmitter or Receiver. . . . . . . . . . . 51Appendix1: ReferencesSchedule of TablesPreface: About This SpecificationTable P-1:Radix Specifics of Literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table P-2:Examples of Extended Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Section1: Introduction and OverviewSection2: Data Transmission and ReceptionTable 2-1:Aurora 64B/66B Blocks Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 2-2:Normal Aurora 64B/66B Block Transmission Priority . . . . . . . . . . . . . . . . . . . . 22Table 2-3:Aurora 64B/66B Block Transmission Priority during Flow Control Countdown 23 Section3: Flow Control Section4: Initialization and Error HandlingTable 4-1:Required Block Transmission during Lane Initialization. . . . . . . . . . . . . . . . . 36Table 4-2:Required State Transition after Lane Initialization . . . . . . . . . . . . . . . . . . . . . . 36Table 4-3:Required State Transition after Successful Channel Bonding. . . . . . . . . . . . . 37Section5: PCS LayerTable 5-1:Valid Block Type Field Values in Aurora 64B/66B. . . . . . . . . . . . . . . . . . . . . . . 40Table 5-2:Valid Octet Count Field Values for Separator Block Code. . . . . . . . . . . . . . . . 43Table 5-3:Valid Block Type Field Values for User K-Blocks . . . . . . . . . . . . . . . . . . . . . . . 44 Section6: Channel Control Section7: PMA LayerSection8: Electrical SpecificationsAppendix1: ReferencesPreface About This SpecificationThis specification describes the Aurora 64B/66B protocol. Aurora is a lightweight link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocol using 64B/66B encoding instead of 8B/10B.Specification ContentsThis manual contains the following:Section1, “Introduction and Overview”provides an overview of the Aurora 64B/66B protocol.Section2, “Data Transmission and Reception”describes the procedures for transmitting and receiving data using an Aurora 64B/66B Channel.Section3, “Flow Control”describes the optional flow control features in the Aurora64B/66B protocol.Section4, “Initialization and Error Handling”describes the procedure used to preparean Aurora channel for operation.Section5, “PCS Layer”specifies the functions performed in the physical coding sub-layer (PCS) of the Aurora 64B/66B protocol.Section6, “Channel Control”defines the striping rules for using multi-lane channels. Section7, “PMA Layer”specifies the functions performed in the PMA layer of the Aurora 64B/66B Protocol.Section8, “Electrical Specifications”describes the AC specifications, covering both single- and multi-lane implementations.ConventionsThis document uses the following conventions.T ypographicalThe following typographical conventions are used in this document:Online DocumentThe following conventions are used in this document:NumericalConventionMeaning or UseExampleItalic fontReferences to other manualsSee the Development System Reference Guide for more information.Emphasis in textIf a wire is drawn so that itoverlaps the pin of a symbol, the two nets are not connected.To emphasize a term the first time it is used The state machine uses one-hot encoding.REG[FIELD]Abbreviations or acronyms for registers are shown in uppercasetext. Specific bits, fields, or ranges appear in bracketsREG[11:14]ConventionMeaning or UseExampleBlue textCross-reference link to a location in the current document See the section “AdditionalResources” for details.Refer to “Title Formats” inSection 1 for details.Red textCross-reference link to a location in another document See Figure 2-5 in the Virtex-II Platform FPGA User Guide.Blue, underlined textHyperlink to a website (URL)Go to /doc/10fb3b7b1711cc7931b716ea.htmlfor the latest speed files.Convention Meaning or Usen A decimal value[n:m ]Used to express a numerical range from n to m x Unknown value zHigh impedanceValues of LiteralsLiterals are represented by specifying three of their properties as listed and shown in Figure P-1 and in Table P-1 and Table P-2:1.Width in bits 2.Radix (Base)3.ValueTable P-1 shows the Radix specifics:All values are extended with zero except those with x or z in the most significant place; they extend with x or z respectively. A list of examples is shown in Table P-2:Figure P-1:Properties of LiteralsTable P-1:Radix Specifics of LiteralsRadix SpecifierRadixb Binary d Decimal h Hexadecimal oOctalTable P-2:Examples of Extended ValuesNumber Value Comment8’b000000000An 8-bit binary number with value of zero. (Zero extended to get 8 bits.)8’bx xxxxxxxxAn 8-bit binary number with value unknown. (x extended to get 8 bits.)8’b1x 0000001x An 8-bit binary number with value of 2 or 3, depending on the value of x.8’b0x 0000000x An 8-bit binary number with value of 0 or 1, depending on the value of x.8’hx xxxxxxxx An 8-bit hexadecimal number with value unknown.(x extended to get 8 bits.)8’hzx zzzzxxxx An 8-bit hexadecimal number with the upper four bits not driven and the lower four bitsunknown.8’b100000001An 8-bit binary number with value of one.8’hz1zzzz0001An 8-bit hexadecimal number with the upper four bits not driven and the lower four bits having value of one.8’bx1xxxxxxx1An 8-bit binary number that is odd.8’bx0xxxxxxx0An 8-bit binary number that is even.State Diagram ConventionsThis section describes the conventions used in the state diagrams for this document. The numbered sections correspond to the call-outs shown in the state machine diagram in Figure P-2, page 15.States1. A state is represented by a rectangle.2.The name of the state is indicated in bold.State T ransitions3.State transition is indicated by an arrow annotated in italics.State Machine OutputsOutputs are shown in plain text. Outputs can be shown inside of state rectangles or can be part of the annotation associated with a transition arrow. If a signal is not listed in a state rectangle or on a transition arrow, its value at that time is 0 (not asserted). If a registered output does not appear in the state rectangle or transition arrow annotation, then its value is unchanged from the previous value.Output T ypesOutputs are divided into three classes as shown in the examples below.4.Asserting control signals:go = 1link reset = 15.Register initialization:XYZ Register = 78New Counter = 0xmit = /SP/ (an ordered set)6.Incrementing or decrementing a register:XYZ Register = XYZ Register + 1New Counter = New Counter – 68’hz zzzzzzzz An 8-bit hexadecimal number with value not driven. (z extended to get 8 bits.)8’h0z 0000zzzzAn 8-bit hexadecimal number with upper nibble specified and the lower not driven.11’d n n An 11-bit decimal number with value n .6’h n nA 6-bit hexadecimal number with value n .w’b101(101)A binary number with value 5 and an unknown width.Table P-2:Examples of Extended Values (Cont’d)Number Value CommentFigure P-2:State Machine Diagram ConventionsSection1 Introduction and Overview1.1IntroductionAurora is a lightweight link-layer protocol that can be used to move data point-to-pointacross one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocolusing 64B/66B encoding instead of 8B/10B.1.2ScopeThe Aurora 64B/66B Protocol Specification defines the following:Electrical specifications: This includes signaling levels for an Aurora serial link.PMA layer: This includes specification for serialization bit ordering and byteordering.Physical coding sub-layer (PCS): This includes specification for data encoding anddecoding, data scrambling, the 64B/66B gearbox, clock compensation and channelbonding.Channel control: This includes specifications for multi-lane striping and forscheduling the transmission of data and control information.Cyclic redundancy check (CRC): The Aurora protocol recommends a CRCmechanism compatible with the standard 64B/66B scrambling algorithm.1.3OverviewThe Aurora protocol (Figure1-1, page18) describes the transfer of user data across anAurora channel, consisting of one or more Aurora lanes. Each Aurora lane is a serial dataconnection, either full-duplex or simplex. Devices communicating across the channel arecalled channel partners.Aurora interfaces allow user applications to transfer data through the Aurora channel. Theuser interface on each Aurora interface is not defined in this specification and can bedecided independently for each implementation of the protocol.Aurora channels have the following properties:Data is transferred through the Aurora channel in frames.Frames share the channel with control information such as flow control messages,clock compensation sequences and idles.Frames can be of any length, and can have any format. Only the delineation of framesis defined in this specification.Frames in Aurora do not have to be contiguous — they can be interrupted at any time by flow control messages or idles.There is no gap required between frames in Aurora.Figure 1-1:Aurora Protocol OverviewFigure1-2 shows a simplex connection between a pair of Aurora lanes, depicting the functional blocks comprising the PCS and PMA layers of an Aurora connection. These blocks are specified in detail in this document.Figure 1-2: A Simplex Connection Between a Pair of Aurora LanesAurora interfaces allow applications to communicate using Aurora channels. Aurora interfaces are made up of one or more Aurora lanes, either simplex or full-duplex. The four possible configurations of Aurora interfaces are shown in Figure1-3, Figure1-4,Figure1-5, page20, and Figure1-6, page20.Figure1-3 shows a single-lane, simplex Aurora interface transmitting to another single-lane, simplex Aurora interface. In this configuration, each interface uses a single lane to transmit or receive from the Aurora channel. Channel control in each interface initializes the channel passing control to the user application.Figure 1-3: A Single-Lane, Simplex Aurora ChannelFigure1-4 shows a multi-lane, simplex Aurora interface transmitting to another multi-lane, simplex Aurora interface. In multi-lane configurations, the channel control bonds the lanes to eliminate skew between channels as a part of the channel initialization procedure. During normal operation, the channel control logic distributes data and control information across all the lanes in the channel.Figure 1-4: A Multi-Lane, Simplex Aurora Channel。
AMS 6415R
SAE Technical Standards Board Rules provide that: “This report is published by SAE to advance the state of technical and engineering sciences. The use of this report is entirely voluntary, and its applicability and suitability for any particular use, including any patent infringement arising therefrom, is the sole responsibility of the user.”SAE reviews each technical report at least every five years at which time it may be reaffirmed, revised, or cancelled. SAE invites your written comments and suggestions.Copyright © 2003 SAE InternationalAll rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying,recording, or otherwise, without the prior written permission of SAE.TO PLACE A DOCUMENT ORDER:Tel: 877-606-7323 (inside USA and Canada)Tel: 724-776-4970 (outside USA)Steel, Bars, Forgings, and Tubing0.80Cr - 1.8Ni - 0.25Mo (0.38 - 0.43C) (SAE 4340)(Composition similar to UNS G43406)1.SCOPE:1.1Form:This specification covers an aircraft-quality, low-alloy steel in the form of bars, forgings, mechanical tubing, and forging stock.1.2Application:These products have been used typically for parts, 3.5 inches and under in nominal thickness at time of heat treatment, requiring a through-hardening steel capable of developing a minimum hardness of 40 HRC when properly hardened and tempered and also for parts of greater thickness but requiring proportionately lower hardness, but usage is not limited to such applications.1.2.1Certain design and processing procedures may cause these products to become susceptible to stress-corrosion cracking after heat treatment; ARP1110 recommends practices to minimize such conditions.2.APPLICABLE DOCUMENTS:The issue of the following documents in effect on the date of the purchase order forms a part of this specification to the extent supplied herein. The supplier may work to a subsequent revision of a document unless a specific document issue is specified. When the referenced document has been cancelled and no superseding document has been specified, the last published issue of that document shall apply.AEROSPACE MATERIALSPECIFICATIONAMS 6415RIssued JAN 1940RevisedJUN 2003Superseding AMS 6415P--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---2.1SAE Publications:Available from SAE, 400 Commonwealth Drive, Warrendale, PA 15096-0001 or .AMS 2251Tolerances, Low-Alloy Steel BarsAMS 2253Tolerances, Carbon and Alloy Steel TubingAMS 2259Chemical Check Analysis Limits, Wrought Low-Alloy and Carbon SteelsAMS 2301Steel Cleanliness, Aircraft Quality, Magnetic Particle Inspection ProcedureAMS 2370Quality Assurance Sampling and Testing, Carbon and Low-Alloy Steel Wrought Products and Forging StockAMS 2372Quality Assurance Sampling and Testing, Carbon and Low-Alloy Steel Forgings AMS 2806Identification, Bars, Wire, Mechanical Tubing, and Extrusions, Carbon and Alloy Steels and Heat and Corrosion Resistant Steels and AlloysAMS 2808Identification, ForgingsAMS-H-6875Heat Treatment of SteelAS1182Standard Machining Allowance, Aircraft-Quality and Premium-Quality Steel Bars and Mechanical TubingARP1110Minimizing Stress Corrosion Cracking in Wrought Forms of Steels and Corrosion Resistant Steels and Alloys2.2ASTM Publications:Available from ASTM, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959 or.ASTM A 255Determining Hardenability of SteelASTM A 370Mechanical Testing of Steel ProductsASTM E 112Determining Average Grain SizeASTM E 350Chemical Analysis of Carbon Steel, Low-Alloy Steel, Silicon Electrical Steel,Ingot Iron, and Wrought IronASTM E 381Macroetch Testing Steel, Bars, Billets, Blooms, and ForgingsASTM E 384Microindentation Hardness of Materials3.TECHNICAL REQUIREMENTS:3.1Composition:Shall conform to the percentages by weight shown in Table 1, determined by wet chemical methods in accordance with ASTM E 350, by spectrochemical methods, or by other analytical methodsacceptable to purchaser.--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---TABLE 1 - CompositionElement min maxCarbon0.380.43Manganese0.650.85Silicon0.150.35Phosphorus--0.025Sulfur--0.025Chromium0.700.90Nickel 1.65 2.00Molybdenum0.200.30Copper--0.353.1.1Check Analysis: Composition variations shall meet the applicable requirements of AMS 2259.3.2Condition:The product shall be supplied in the following condition; hardness and tensile strength shall be determined in accordance with ASTM A 370.3.2.1Bars:3.2.1.1Bars 0.500 Inch and Under in Nominal Diameter or Least Distance Between Parallel Sides:Cold finished having tensile strength not higher than 125 ksi or hardness not higher than 27HRC, or equivalent (See 8.2).3.2.1.2Bars Over 0.500 Inch in Nominal Diameter or Least Distance Between Parallel Sides:Hot finished and annealed, unless otherwise ordered, having hardness not higher than 235 HB, or equivalent (See 8.2). Bars ordered cold finished may have hardness as high as 255 HB, orequivalent (See 8.2).3.2.2Forgings: Normalized and tempered in accordance with AMS-H-6875 to a hardness not higherthan 269 HB, or equivalent (See 8.2).3.2.3Mechanical Tubing: Cold finished, unless otherwise ordered, having hardness not higher than 25HRC, or equivalent (See 8.2). Tubing ordered hot finished and annealed shall have hardness not higher than 99 HRB, or equivalent (See 8.2).3.2.4Forging Stock: As ordered by the forging manufacturer.--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---3.3Properties:The product shall conform to the following requirements; hardness testing shall be performed in accordance with ASTM A 370:3.3.1Macrostructure: Visual examination of transverse full cross-sections from bars, billets, tube rounds,and forging stock, etched in hot hydrochloric acid in accordance with ASTM E 381, shall show no pipe or cracks. Porosity, segregation, inclusions, and other imperfections shall be no worse than the macrographs of ASTM E 381 shown in Table 2.TABLE 2 - Macrostructure LimitsCross-Sectional AreaSquare Inches MacrographsUp to 36, incl S2 - R1 - C2Over 36 to 100, incl S2 - R2 - C33.3.2Average Grain Size: Shall be ASTM No. 5 or finer, determined in accordance with ASTM E 112.3.3.3Hardenability: Shall be J 12/16 inch (19 mm) = 53 HRC minimum and J 20/16 inch (31.8 mm) =50 HRC minimum, determined on the standard end-quench test specimen in accordance withASTM A 255 except that the steel shall be normalized at 1600 °F ± 25 and the test specimenaustenitized at 1550 °F ± 25.3.3.4Decarburization:3.3.4.1Bars and tubing ordered ground, turned, or polished shall be free from decarburization on theground, turned, or polished surfaces.3.3.4.2Allowable decarburization of bars, billets, and tube rounds ordered for redrawing or forging or tospecified microstructural requirements shall be as agreed upon by purchaser and vendor.3.3.4.3Decarburization of bars to which 3.3.4.1 or 3.3.4.2 is not applicable shall be not greater thanshown in Table 3.TABLE 3A - Maximum Decarburization, Inch/Pound UnitsNominal Diameter or Distance Between Parallel SidesInchesTotal Depth of DecarburizationInchUp to 0.375, incl0.010 Over 0.375 to 0.500, incl0.012 Over 0.500 to 0.625, incl0.014 Over 0.625 to 1.000, incl0.017 Over 1.000 to 1.500, incl0.020 Over 1.500 to 2.000, incl0.025 Over 2.000 to 2.500, incl0.030 Over 2.500 to 3.000, incl0.035 Over 3.000 to 4.000, incl0.045TABLE 3B - Maximum Decarburization, SI UnitsNominal Diameter or Distance Between Parallel SidesMillimetersTotal Depth of Decarburization MillimetersUp to 9.50, incl0.25 Over 9.50 to 12.50, incl0.30 Over 12.50 to 15.65, incl0.35 Over 15.65 to 25.00, incl0.40 Over 25.00 to 37.50, incl0.50 Over 37.50 to 50.00, incl0.60 Over 50.00 to 62.50, incl0.75 Over 62.50 to 75.00, incl0.90 Over 75.00 to 100.00, incl 1.15--` ` , , ` ` , ` , ` , , , , , ` , ` , , ` ` , , , ` ` , , -` -` , , ` , , ` , ` , , ` ---3.3.4.4Decarburization of tubing to which 3.3.4.1 or 3.3.4.2 is not applicable shall be not greater than shown in Table 4.3.3.4.5Decarburization shall be measured by the metallographic method, by the HR30N scalehardness testing method, or by a traverse method using microhardness testing in accordance with ASTM E 384. The hardness method(s) shall be conducted on a hardened but untempered specimen protected during heat treatment to prevent changes in surface carbon content. Depth of decarburization, when measured by a hardness method, is defined as the perpendiculardistance from the surface to the depth under that surface below which there is no further increase in hardness. Such measurements shall be far enough away from any adjacent surface to be uninfluenced by any decarburization on the adjacent surface. In case of dispute, the depth of decarburization determined using the microhardness traverse method shall govern.3.3.4.5.1When determining the depth of decarburization, it is permissible to disregard local areas provided the decarburization of such areas does not exceed the above limits by more than 0.005 inch (0.13 mm) and the width is 0.065 inch (1.65 mm) or less.3.4Quality:The product, as received by purchaser, shall be uniform in quality and condition, sound, and free from foreign materials and from imperfections detrimental to usage of the product.TABLE 4A - Maximum Decarburization, Inch/Pound Units Nominal Wall ThicknessInch Total DepthID Inch Total DepthOD Inch Up to 0.109, incl0.0080.015Over 0.109 to 0.203, incl 0.0100.020Over 0.203 to 0.400, incl 0.0120.025Over 0.400 to 0.600, incl 0.0150.030Over 0.600 to 1.000, incl 0.0170.035Over 1.0000.0200.040TABLE 4B - Maximum Decarburization, SI Units Nominal Wall ThicknessMillimeters Total DepthID MillimeterTotal DepthOD MillimeterUp to 2.75, incl0.200.35Over 2.75 to 5.00, incl 0.250.50Over 5.00 to 10.00, incl 0.300.60Over 10.00 to 15.00, incl 0.350.75Over 15.00 to 25.00, incl 0.400.90Over 25.000.501.00--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---3.4.1Steel shall be aircraft-quality conforming to AMS 2301.3.4.2Bars and mechanical tubing ordered hot rolled or cold drawn, or ground, turned, or polished, shallafter removal of the standard machining allowance in accordance with AS1182, be free fromseams, laps, tears, and cracks open to the ground, turned, or polished surface.3.4.3Grain flow of die forgings, except in areas which contain flash-line end grain, shall follow thegeneral contour of the forgings showing no evidence of reentrant grain flow.3.5Tolerances:Shall be as follows:3.5.1Bars: In accordance with AMS 2251.3.5.2Mechanical Tubing: In accordance with AMS 2253.4.QUALITY ASSURANCE PROVISIONS:4.1Responsibility for Inspection:The vendor of the product shall supply all samples for vendor’s tests and shall be responsible for the performance of all required tests. Purchaser reserves the right to sample and to perform anyconfirmatory testing deemed necessary to ensure that the product conforms to specifiedrequirements.4.2Classification of Tests:4.2.1Acceptance Tests: Composition (3.1), condition (3.2), macrostructure (3.3.1), average grain size(3.3.2), hardenability (3.3.3), decarburization (3.3.4), frequency-severity cleanliness rating (3.4.1),and tolerances (3.5) are acceptance tests and shall be performed on each heat or lot as applicable.4.2.2Periodic Tests: Grain flow of die forgings (3.4.3) is a periodic test and shall be performed at afrequency selected by the vendor unless frequency of testing is specified by purchaser.4.3Sampling and Testing:Shall be as follows:4.3.1Bars, Mechanical Tubing and Forging Stock: In accordance with AMS 2370.4.3.2Forgings: In accordance with AMS 2372.--` ` , , ` ` , ` , ` , , , , , ` , ` , , ` ` , , , ` ` , , -` -` , , ` , , ` , ` , , ` ---4.4Reports:The vendor of the product shall furnish with each shipment a report showing the results of tests for composition, macrostructure, hardenability, and frequency-severity cleanliness rating of each heat and condition and average grain size of each lot, and stating that the product conforms to the other technical requirements. This report shall include the purchase order number, heat and lot numbers, AMS 6415R, size, and quantity. If forgings are supplied, the size and melt source of stock used to make the forgings shall also be included.4.5Resampling and Retesting:Shall be as follows:--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---4.5.1Bars, Mechanical Tubing, and Forging Stock: In accordance with AMS 2370.4.5.2Forgings: In accordance with AMS 2372.5.PREPARATION FOR DELIVERY:5.1Sizes:Except when exact lengths or multiples of exact lengths are ordered, straight bars and tubing will be acceptable in mill lengths of 6 to 20 (1.8 to 6.1 m) feet but not more than 10% of any shipment shall be supplied in lengths shorter than 10 feet (3 m).5.2Identification:Shall be as follows:5.2.1Bars and Mechanical Tubing: In accordance with AMS 2806.5.2.2Forgings: In accordance with AMS 2808.5.2.3Forging Stock: As agreed upon by purchaser and vendor.5.3Protective Treatment:Bars and tubing ordered cold drawn, cold rolled, ground, turned, or polished shall be protected from corrosion prior to shipment.5.4Packaging:The product shall be prepared for shipment in accordance with commercial practice and incompliance with applicable rules and regulations pertaining to the handling, packaging, andtransportation of the product to ensure carrier acceptance and safe delivery.6.ACKNOWLEDGMENT:A vendor shall mention this specification number and its revision letter in all quotations and whenacknowledging purchase orders.7.REJECTIONS:Product not conforming to this specification, or to modifications authorized by purchaser, will be subject to rejection.8.NOTES:8.1 A change bar (|) located in the left margin is for the convenience of the user in locating areas wheretechnical revisions, not editorial changes, have been made to the previous issue of a specification.An (R) symbol to the left of the document title indicates a complete revision of the specification.Change bars and (R) are not used in original publications, not in specifications that contain editorial changes only.8.2Hardness conversion tables for metals are presented in ASTM E 140.8.3Terms used in AMS are clarified in ARP1917.8.5Purchase documents should specify not less than the following:AMS 6415RForm and size or part number of product desiredQuantity of product desired.8.6Similar Specifications:MIL-S-5000/AMS-S-5000 is listed for information only and shall not be construed as an acceptable alternate unless all requirements of this AMS are met.--``,,``,`,`,,,,,`,`,,``,,,``,,-`-`,,`,,`,`,,`---8.7Key Words:SAE 4340, bars, forgings, tubing, UNS G43406PREPARED UNDER THE JURISDICTION OF AMS COMMITTEE “E”。
Eaton 2.2 Molded Case Circuit Breakers Series G 产品
2Catalog Number SelectionThis information is presented only as an aid to understanding catalog numbers. It is not to be used to build catalog numbers for circuit breakers or trip units.Circuit Breaker/Frame Catalog Number SystemNotes1800A only.2Neutral inn left pole on GN; right pole on NG.3Breakers do not ship with lugs.Trip units are factory installable only.NG H 308039ZG E CAmperes080= 800120 = 1200Frame NGPerformance at 480 Vac S = 50 kAIC H = 65 kAIC C = 100 kAIC U = 150 kAIC 1Poles3 = Three4 = Four; neutral 20% protected 7 = Four; neutral 2100% protected 9 = Four; neutral 20/60/100% adjustable protectionTrip Unit33=310+ Electronic LS 32=310+ Electronic LSI 35=310+ Electronic LSG35B22=310+ Electronic LS(A), GFA, no trip 36=310+ Electronic LSIG36B22=310+ Electronic LSI(A), GFA, no trip 38=310+ Electronic ALSI w/ Maintenance Mode39=310+ Electronic ALSIGw/ Maintenance Mode39B22=310+ Electronic ALSI(A)w/ Maintenance Mode and GFA, no tripRatingBlank =80% rated C =100% ratedTerminations 3M =Metric tapped line/loadconductorsE =Imperial tapped line/loadconductorsFeatureBlank =No feature B20=High load alarm B21=Ground faultZG=Zone selective interlockinge s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w2Product Selection Guide and Ordering InformationT ype NGS Standard Interrupting Capacity—U e Max. 690 Vac, 50 kA l cu at 480 Vac or 415 VacT ype NGS Standard Interrupting Capacity—U e Max. 690 Vac, 50 kA I cu at 415 VacMolded Case Switches 78Notes1For AC use only.2NG MCCBs are suitable for 40°C or 50°C applications. Order suffix V3 to eliminate standard 40°C labeling.3Non-UL listed NG 1250 with 1250 ampere trip unit is also available.4Neutral 0% protected. NG, neutral in right pocket; GN, neutral in left pocket.5Neutral 100% protected (denoted by 7 in digit four).6Neutral 0%/60%/100% adjustable protection (denoted by 9 in digit four).7For AC use only. Molded case switch will trip above 14,000 amperes.8For two-pole applications, use outer poles of three-pole molded case switch.Maximum Continuous AmpereRatingat 40°C 12Number of Poles Circuit Breaker Frame Including Digitrip RMS 310+ Electronic Trip Unit with Imperial Tapped ConductorsL – Adjustable Long Delay PickupS–Adjustable Short Delay Pickup with Fixed Short Delay Time(I 2t Response) or Adjustable Short Delay Time (Flat Response)I – Adjustable Instantaneous Pickup by Setting Short Delay Time to InstantaneousG –Adjustable Ground Fault Pickup with Adjustable Ground Fault Delay (Flat Response)Neutral CTfor LSG and LSIG LS LSI LSG LSIG ALSI ALSIG Short Time Range Short Time Delay Ground Fault Pickup Ground Fault Delay 2–8 x I n ———2–8 x I n I–300 ms ——2–8 x I n —200–1200A I–500 ms 2–8 x I n I–300 ms 200–1200A I–500 ms 2–8 x I n I–300 ms ——2–8 x I n I–300 ms 200–1200A I–500 ms 8003NGS308033E NGS308032E NGS308035E NGS308036E NGS308038E NGS308039E NGFCT1204 4NGS408033E NGS408032E NGS408035E NGS408036E NGS408038E NGS408039E —4 5NGS708033E NGS708032E ——NGS708038E ——4 6NGS908033E NGS908032E ——NGS908038E ——1200 33NGS312033E NGS312032E NGS312035E NGS312036E NGS312038E NGS312039E NGFCT1204 4NGS412033E NGS412032E NGS412035E NGS412036E —NGS412039E —4 5NGS712033E NGS712032E ——NGS712038E ——4 6NGS912033ENGS912032E——NGS912038E——Maximum Continuous Ampere Rating at 40°C 12Number of PolesCircuit Breaker Frame Including Digitrip RMS 310+ Electronic Trip Unit with Metric Tapped ConductorsL – Adjustable Long Delay Pickup (By Adjustable Rating Plug)S–Adjustable Short Delay Pickup with Fixed Short Delay Time(I 2t Response) or Adjustable Short Delay Time (Flat Response)I – Adjustable Instantaneous Pickup by Setting Short Delay Time to InstantaneousG –Adjustable Ground Fault Pickup with Adjustable Ground Fault Delay (Flat Response)LS LSI LSG LSIG ALSI ALSIG Short Time Range Short Time Delay Ground Fault Pickup Ground Fault Delay 2–8 x I n ———2–8 x I n I–300 ms ——2–8 x I n —200–1200A I–500 ms 2–8 x I n I–300 ms 200–1200A I–500 ms 2–8 x I n I–300 ms ——2–8 x I n I–300 ms 200–1200A I–500 ms 1600 33NGS316033M NGS316032M NGS316035M NGS316036M NGS316038M NGS316039M 4 4NGS416033M NGS416032M NGS416035M NGS416036M NGS416038M NGS416039M 4 5NGS716033M NGS716032M ——NGS716038M —4 6NGS916033MNGS916032M——NGS916038M—Ampere Rating U e Maximum 690 VacThree-PoleCatalog Number Four-PoleCatalog Number 800MCS with Imperial line and load terminals NGK3080KSE MCS with Imperial line and load terminals NGK4080KSE 1200MCS with Imperial line and load terminals NGK3120KSE MCS with Imperial line and load terminals NGK4120KSE 1250MCS with Imperial line and load terminalsNGK3125KSEMCS with Imperial line and load terminalsNGK43125KSEe s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w2T ype NGH High Interrupting Capacity—U e Max. 690 Vac, 65 kA l cu at 480 Vac or 415 VacT ype NGC Very High Capacity—U e Max. 690 Vac, 100 kA l cu at 480 Vac or 415 VacNotes1For AC use only.2NG MCCBs are suitable for 40°C or 50°C applications. Order suffix V3 to eliminate standard 40°C labeling.3Neutral 0% protected. NG, neutral in right pocket; GN, neutral in left pocket.4Neutral 100% protected (denoted by 7 in digit four).5Neutral 0%/60%/100% adjustable protection (denoted by 9 in digit four).Maximum Continuous AmpereRatingat 40°C 12Number of Poles Circuit Breaker Frame Including Digitrip Electronic Trip UnitL – Adjustable Long Delay PickupS–Adjustable Short Delay Pickup with Fixed Short Delay Time (I 2t Response) or Adjustable Short Delay Time (Flat Response)I – Adjustable Instantaneous Pickup by Setting Short Delay Time to InstantaneousG –Adjustable Ground Fault Pickup with Adjustable Ground Fault Delay (Flat Response)Neutral CTfor LSG and LSIG LS LSI LSG LSIG ALSI ALSIG Short Time Range Short Time Delay Ground Fault Pickup Ground Fault Delay 2–8 x I n ———2–8 x I n I–300 ms ——2–8 x I n —200–1200A I–500 ms 2–8 x I n I–300 ms 200–1200A I–500 ms 2–8 x I n I–300 ms ——2–8 x I n I–300 ms 200–1200A I–500 ms 8003NGH308033E NGH308032E NGH308035E NGH308036E NGH308038E NGH308039E NGFCT1204 3NGH408033E NGH408032E NGH408035E NGH408036E NGH408038E NGH408039E —4 4NGH708033E NGH708032E ——NGH708038E ——4 5NGH908033E NGH908032E ——NGH908038E ——12003NGH312033E NGH312032E NGH312035E NGH312036E NGH312038E NGH312039E NGFCT1204 3NGH412033E NGH412032E NGH412035E NGH412036E —NGH412039E —4 4NGH712033E NGH712032E ——NGH712038E ——4 5NGH912033ENGH912032E——NGH912038E——Maximum Continuous AmpereRatingat 40°C 12Number of Poles Circuit Breaker Frame Including Digitrip RMS 310+ Electronic Trip Unit with Imperial Tapped ConductorsL – Adjustable Long Delay PickupS–Adjustable Short Delay Pickup with Fixed Short Delay Time (I 2t Response) or Adjustable Short Delay Time (Flat Response)I – Adjustable Instantaneous Pickup by Setting Short Delay Time to InstantaneousG –Adjustable Ground Fault Pickup with Adjustable Ground Fault Delay (Flat Response)Neutral CTfor LSG and LSIG LS LSI LSG LSIG ALSI ALSIG Short Time Range Short Time Delay Ground Fault Pickup Ground Fault Delay 2–8 x I n ———2–8 x I n I–300 ms ——2–8 x I n —200–1200A I–500 ms 2–8 x I n I–300 ms 200–1200A I–500 ms 2–8 x I n I–300 ms ——2–8 x I n I–300 ms 200–1200A I–500 ms 8003NGC308033E NGC308032E NGC308035E NGC308036E NGC308038E NGC308039E NGFCT1204 3NGC408033E NGC408032E NGC408035E NGC408036E NGC408038E NGC408039E —4 4NGC708033E NGC708032E ——NGC708038E ——4 5NGC908033E NGC908032E ——NGC908038E ——1200 33NGC312033E NGC312032E NGC312035E NGC312036E NGC312038E NGC312039E NGFCT1204 3NGC412033E NGC412032E NGC412035E NGC412036E —NGC412039E —4 4NGC712033E NGC712032E ——NGC712038E ——4 5NGC912033ENGC912032E——NGC912038E——e s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w2Accessories Selection Guide and Ordering InformationLine and Load TerminalsN-Frame circuit breakers do not include terminals as standard. When copper or Cu/Al terminals are required, order by catalog number.Line and Load T erminalsBase Mounting HardwareBase mounting hardware is included with a circuit breaker or molded case switch.Base Mounting Hardware 2Terminal Shield T erminal ShieldConductor Extension Kit Conductor Extension Kit 3Keeper NutNot required on NG-Frame. Terminals are threaded.Handle ExtensionIncluded with breaker. Additional handle extensions are available.Handle ExtensionInterphase BarriersThe interphase barriers provide additional electrical clearance between circuit breaker poles for special terminationapplications. Barriers are high dielectric insulating plates that are installed in the molded slots between the terminals. (Field installation only.)Interphase BarriersNotes1Single terminals individually packed.2Metric hardware included with breaker.3Included as standard on 100% rated 800/1200A breakers.MaximumBreaker AmperesTerminalBody MaterialWire TypeAWG Wire (Number of Conductors)AWG Wire Catalog Number 1Metric Wire Range mm 2Metric Catalog Number 1Standard Cu/Al Pressure T erminals 700Aluminum Cu/Al 1–500 (2)TA700NB150–240TA700NB1M 1000Aluminum Cu/Al 3/0–400 (3)TA1000NB195–185TA1000NB1M 1200Aluminum Cu/Al 4/0–500 (4)TA1200NB1120–240TA1200NB1M 1200AluminumCu/Al500–750 (3)TA1201NB1300–400TA1201NB1MOptional Copper and Cu/Al Pressure T ype T erminals 700Copper Cu 2/0–500 (2)T700NB170–240T700NB1M 1000Copper Cu 3/0–500 (3)T1000NB195–240T1000NB1M 1200CopperCu3/0–400 (4)T1200NB395–185T1200NB3MNumber of PolesDescriptionCatalog Number Three- and four-poleImperial hardware: 0.3125–18 x 1.25pan-head steel screws and lock washersBMH5Three- and four-poleMetric hardware: M8 pan-head steel screws and lock washersBMH5M DescriptionCatalog Number Three-pole terminal shieldNTS3KDescriptionCatalog Number Three-pole both ends Metric 5104A24G04Three-pole both ends English5104A24G02Description Catalog Number Single handle extensionHEX5DescriptionCatalog Number Interphase barriersIPB5e s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w2AccessoriesAllowable Accessory CombinationsDifferent combinations of accessories can be supplied, depending on the types of accessories and the number of poles in the circuit breaker.NG-Frame AccessoriesLegend■Applicable in indicated pole position❏May be mounted on left or right pole—not both ●Accessory available/modification availableNote1Contact Eaton.DescriptionReference PageThree-Pole Four-Pole LeftCenterRightLeftCenterRightNeu.Internal Accessories (Only One Internal Accessory Per Pole)Alarm lockout (Make/Break)V4-T2-104●■●■Auxiliary switch (1A, 1B)V4-T2-104●■●■Auxiliary switch (2A, 2B)V4-T2-104●■●■Auxiliary switch and alarm switch combination V4-T2-104●■●■Shunt trip—standardV4-T2-104■■Undervoltage release mechanism V4-T2-105■■External Accessories Base mounting hardware V4-T2-65●●●●●●●Interphase barriersV4-T2-65●●●●●●●Non-padlockable handle block V4-T2-102■■Padlockable handle lock hasp V4-T2-102❏❏❏❏Key interlock kitV4-T2-102❏❏❏❏Sliding bar interlock—requires two breakers V4-T2-102●●●Electrical operator V4-T2-102●●●●●●●Plug-in adapters V4-T2-108●●●●●●●Rear connecting studs V4-T2-102●●●●●●●Handle mechanisms V4-T2-407●●●●●●●Drawout cassette V4-T2-109●●●●●●●Handle extensionV4-T2-65●●●●●●●Ammeter/cause of trip display V4-T2-101●●●●●●●Cause of trip LED module V4-T2-101●●●●●●●Digitrip 310 test kitV4-T2-102●●●●●●●Modifications (Refer to Eaton)Moisture fungus treatment V4-T2-100●●●●●●●Freeze-tested circuit breakers—●●●●●●●Marine/Naval application, UL 489 Supplement SA and SB 1●●●●●●●e s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w22.2Molded Case Circuit BreakersSeries GTechnical Data and SpecificationsInterrupting Capacity RatingsUL 489/IEC 60947-2 Interrupting Capacity Ratings 1NG-Frame Digitrip Specifications SpecificationLegendBIM = Breaker Interface Module (A)= GF Alarm I s = Sensor Rating I n = Rating PlugI r= Long Delay Pickup Setting Note11600 amperes is not a UL or CSA listed rating. 1200 amperes is the maximum UL and CSA rating for NG.Circuit Breaker Type Number of Poles 240 (UL)Interrupting Capacity (kA Symmetrical Amperes)Volts AC (50/60 Hz)220–240380–415480600690I cu I cs I cu I cs I cu I cs NGS 12, 3, 4658585505050252010NGH 2, 3, 4100100100705065352513NGC2, 3, 420020010010050100653518Trip Unit Type Digitrip RMS 310+rms sensing YesBreaker T ype Frame N Ampere range320–1200A Interrupting rating at 480 volts 50, 65, 100 (kA)Protection Ordering options LS, LSG LSI, LSIG Fixed rated plug (I n )No No Overtemperature tripYesYesLong Delay Protection (L)Adjustable trip setting (I n )YesYesLong delay pickup 0.5–1.0 (I n ) 0.5–1.0 (I n ) Long delay time I 2t 12 seconds 12 seconds Long delay time I 4t No No Long delay thermal memory Yes Yes High load alarmNoNoShort Delay Protection (S)Short delay pickup 200–800% x (I n )200–800% x (I n )Short delay time I 2t 100 ms No Short delay time flatNo Inst–300 ms Short delay time zone selective interlocking YesYesInstantaneous Protection (I)Instantaneous pickup No 200–800% x (I n )Discriminator No No Instantaneous overrideYesYese s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w w .c m a f h .c o m2 2.2Molded Case Circuit BreakersSeries GSpecifications, continuedLegendBIM = Breaker Interface Module (A)= GF Alarm I s = Sensor Rating I n = Rating PlugI r= Long Delay Pickup Setting Notes1With cause of trip LED module (Trip-LED)2With separate ground fault alarm unit (GFAU).3With cause of trip display (DIGIVIEW or DIGIVIEWR06)Trip Unit Type Digitrip RMS 310+LS, LSGLSI, LSIGGround Fault Protection (G)Ground fault alarm NoNoGround fault pickup 1–5 x Ig (160A)1–5 x Ig (160A)Ground fault delay I 2t No No Ground fault delay flatInst–500 ms Inst–500 ms Ground fault zone selective interlocking Yes Yes Ground fault thermal memory YesYesSystem Diagnostics Status LEDs Yes Yes Cause of trip LEDsYes 1Yes 1Magnitude of trip information No No Remote signal contact—ground alarm Yes 2Yes 2Local auxiliary and bell alarm contact Optional Optional System Monitoring Digital display Yes 3Yes 3Current Yes 3Yes 3Power and energy No No Power quality—harmonics No No Power factor NoNoCommunications Eaton PowerNet No NoT esting Testing methodTest set Test sete s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w w .c m a f h .c o m22.2Molded Case Circuit BreakersSeries GDimensions and WeightsApproximate Dimensions in Inches (mm)NG-FrameNG-FrameApproximate Shipping Weight in Lbs (kg)NG-FrameNumber of Poles Width Height Depth 38.25 (209.6)16.00 (406.4) 5.50 (139.7)411.13 (282.6)16.00 (406.4)5.50 (139.7)Front View Three-PoleFront Cover CutoutSide View5.508.25Complete BreakerBreaker Type Three-Pole Four-Pole NGS, NGH, NGC45 (20.4)58 (26.3)e s y of C M A /F l o d y n e /H y d r a d y n e ŀ M o t i o n C o n t r o l ŀ H y d r a u l i c ŀ P n e u m a t i c ŀ E l e c t r i c a l ŀ M e c h a n i c a l ŀ (800) 426-5480 ŀ w w w .c m a f h .c o m。
场效应管AON6411参数大全
MaximumParameter Absolute Maximum Ratings T A =25°C unless otherwise noted PIN1Symbolt ≤ 10s Steady-State Steady-StateR θJCParameterTyp Max °C/W R θJA 144017Thermal CharacteristicsUnits Maximum Junction-to-Ambient A Continuous Drain Current GGate-Source Voltage Drain-Source Voltage -20T =25°C T =100°C Maximum Junction-to-Case°C/W°C/W Maximum Junction-to-Ambient A D 0.6550.8SymbolMin Typ Max Units BV DSS -20VV DS =-20V, V GS =0V-1T J =55°C -5I GSS ±100nA V GS(th)Gate Threshold Voltage -0.5-0.85-1.3V I D(ON)-340A 1.7 2.1T J =125°C 2.4532 2.5m Ω2.8 3.6m Ωg FS 115S V SD -0.57-1V I S-85A C iss 10290pF C oss 1910pF C rss 1395pFR g2.1 4.2ΩQ g (10V)235330nC Q g (4.5V)100140nC Q gs 21nC Q gd 36nC Maximum Body-Diode Continuous CurrentGInput Capacitance Output CapacitanceDYNAMIC PARAMETERS Reverse Transfer Capacitance V GS =0V, V DS =-10V, f=1MHz SWITCHING PARAMETERS Gate resistanceV GS =0V, V DS =0V, f=1MHzTotal Gate Charge V GS =-10V, V DS =-10V, I D =-20AGate Source Charge Gate Drain Charge Total Gate Charge Zero Gate Voltage Drain Current Gate-Body leakage current m ΩI S =-1A,V GS =0VV DS =-5V, I D =-20A V GS =-2.5V, I D =-20AForward Transconductance Diode Forward VoltageV GS =-4.5V, I D =-20A Electrical Characteristics (T J =25°C unless otherwise noted)STATIC PARAMETERS ParameterConditions Drain-Source Breakdown Voltage On state drain currentI D =-250µA, V GS =0V V GS =-10V, V DS =-5V V GS =-10V, I D =-20AR DS(ON)Static Drain-Source On-ResistanceI DSS µA V DS =V GS, I D =-250µA V DS =0V, V GS =±12V t D(on)9ns t r 18ns t D(off)282ns t f 90ns t rr 48nsQ rr178nCTHIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.Turn-On DelayTime Body Diode Reverse Recovery Charge I F =-20A, dI/dt=500A/µsTurn-On Rise Time Turn-Off DelayTime I F =-20A, dI/dt=500A/µsV GS =-10V, V DS =-10V, R L =0.5Ω,R GEN =3ΩTurn-Off Fall TimeBody Diode Reverse Recovery TimeA. The value of R θJA is measured with the device mounted on 1in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The Power dissipation P DSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's specific board design, and the maximum temperature of 150°C may be used if the PCB allows it.B. The power dissipation P D is based on T J(MAX)=150°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used.C. Repetitive rating, pulse width limited by junction temperature T J(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initial T J =25°C.Maximum UIS current limited by test equipment.D. The R θJA is the sum of the thermal impedance from junction to case R θJC and case to ambient.E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.F. These curves are based on the junction-to-case thermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX)=150°C. The SOA curve provides a single pulse rating.G. The maximum current rating is package limited.H. These tests are performed with the device mounted on 1 in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C.TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS17521000204060801000.511.522.53-I D (A )-V GS (Volts)Figure 2: Transfer Characteristics (Note E)1234551015202530R D S (O N )(m Ω)-I D (A)Figure 3: On-Resistance vs. Drain Current and Gate0.811.21.41.61.80255075100125150175N o r m a l i z e d O n -R e s i s t a n c eTemperature (°C)V GS =-4.5V I D =-20A V GS =-10V I D =-20AV GS =-2.5VI D =-20A25°C125°CV DS =-5VV GS =-2.5VV GS =-10V020*********12012345-I D (A )-V DS (Volts)Fig 1: On-Region Characteristics (Note E)V GS =-1.5V-2V-10V-2.5V-4.5VV GS =-4.5V 1840Voltage (Note E)1.0E-051.0E-041.0E-031.0E-021.0E-011.0E+001.0E+011.0E+020.00.20.40.60.81.0-I S (A )-V SD (Volts)Figure 6: Body-Diode Characteristics (Note E)25°C125°CFigure 4: On-Resistance vs. Junction Temperature (Note E)01234560246810R D S (O N )(m Ω)-V GS (Volts)Figure 5: On-Resistance vs. Gate-Source Voltage(Note E)I D =-20A25°C125°CTYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS1752100050100150200255075100125150P o w e r D i s s i p a t i o n (W )T CASE (°C)Figure 13: Power De-rating (Note F)0204060801000255075100125150C u r r e n t r a t i n g ID (A )1101001000100000.00010.01110010000P o w e r (W )T A =25°C11010010001101001000-I A R (A ) P e a k A v a l a n c h e C u r r e n tTime in avalanche, t A (µs)Figure 12: Single Pulse Avalanche capability(Note C)T A =25°CT A =150°CT A =100°CT A =125°C18400.0010.010.11100.00010.0010.010.11101001000Z θJ A N o r m a l i z e d T r a n s i e n t T h e r m a l R e s i s t a n c ePulse Width (s)Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)Single PulseD=T on /TT J,PK =T A +P DM .Z θJA .R θJA T onTP DIn descending orderD=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulseT CASE (°C)Figure 14: Current De-rating (Note F)Pulse Width (s)Figure 15: Single Pulse Power Rating Junction-to-Ambient (Note H)R θJA =55°C/WVdsChargeGate Charge Test Circuit & WaveformVdsUnclamped Inductive Switching (UIS) Test Circuit & Waveforms2E = 1/2 LI AR ARVddResistive Switching Test Circuit & Waveforms90%10%VddIdVgsBV DSSI ARVdd。
TPS2554 and TPS2555 Evaluation Module User's Guide
User's GuideSLVU462–June2011TPS2554and TPS2555Evaluation Module This user’s guide describes the evaluation module(EVM)for the TPS2554and TPS2555.TPS2554and TPS2555are precision-adjustable,current-limited,power-distribution switches.The document contains an operational description of the EVM,schematic,board layout,and bill of materials.Contents1Description (2)1.1Features (2)1.2Applications (2)2Schematic (3)3General Configuration and Description (4)3.1Physical Access (4)3.2Current-Limit Setpoint (4)3.3Test Setup (4)4EVM Assembly Drawings and Layout Guidelines (5)4.1Layout Guidelines (5)4.2PCB Drawings (5)5Bill of Materials (8)List of Figures1TPS2554/5EVM Schematic (3)2Typical TPS2554/5EVM Test Setup (5)3Top-Side Placement and Routing (6)4Layer-Two Routing (6)5Layer-Three Routing (7)6Bottom-Side Placement and Routing (7)List of Tables1User Interface (4)2Test Points (4)3EVM Bill of Materials (8)1 SLVU462–June2011TPS2554and TPS2555Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedDescription 1DescriptionThe TPS2554EVM-010evaluation module allows reference circuit evaluation of the Texas Instruments TPS2554and TPS2555power-distribution switches.1.1Features•Precision adjustable,current-limited,power-distribution switch•Fast overcurrent response–1µs typical•80-mΩ,high-side MOSFET•Operating range:4.5V to5.5V1.2Applications•USB ports/hubs•Notebook personal computers(PC)2TPS2554and TPS2555Evaluation Module SLVU462–June2011Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedGeneral Configuration and Description 3General Configuration and Description3.1Physical AccessTable1lists the TPS2554/5EVM connector functionality,and Table2describes the test point availability.er InterfaceConnector Label DescriptionJ1VIN Input connectorJ2VOUT Output connectorJ3J3Input voltage jumper.Shunt can be removed to measure input current.J4J4Output voltage jumper.Shunt can be removed to measure output current.J5EN Enable jumper.Leave open to enable TPS2554and install shunt to enable TPS2555.J6ILIM_SEL Current limit select.Install shunt to select ILIM0(2.4A nominal),and remove shunt toselect ILIM1(1.2A nominal).D1(RED)FLT Fault LEDTable2.Test PointsTest Point Color Label DescriptionTP3RED IN Power switch input(IC side of J3shunt)TP4BLK GND Power switch input groundTP1WHT FLT Fault pin outputTP2RED VOUT Power switch outputTP5BLK GND Power switch output groundTP6WHT EN Enable pin input3.2Current-Limit SetpointR4and R5configure the current-limit setpoint for ILIM0and ILIM1,respectively(see J6in Table1).ILIM0or ILIM1setpoint can be adjusted using the following example by substituting R4or R5for RILIMx .In thisexample IOS=2A.The following example is an approximation only and does not take into account the resistor tolerance or the variation of ILIM.For exact variation of ILIM,see the TPS2554/TPS2555data sheet,SLVSAM0.IOS=48000/RILIMx=2ARILIMx=48000/IOS=48000/2=24000ΩChoose RILIMx=23.7kΩIOS=48000/23700=2.03A3.3Test SetupFigure2shows a typical test setup for TPS2554/5EVM.4TPS2554and TPS2555Evaluation Module SLVU462–June2011Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedV INOscilloscope EVM Assembly Drawings and Layout GuidelinesFigure2.Typical TPS2554/5EVM Test Setup4EVM Assembly Drawings and Layout Guidelines4.1Layout Guidelines•TPS2554/55placement:Place the TPS2554/55near the USB output connector and the150-µF OUT pin filter capacitor.Connect the exposed pad to the GND pin and the system ground plane using a viaarray.•IN pin bypass capacitance:Place the100-nF bypass capacitor near the IN and GND pins,and make the connection using a low-inductance trace.•ILIM0and ILIM1pin connections:Current-limit accuracy can be compromised by stray current leakage from a higher voltage source to the ILIM0or ILIM1pins.Ensure that adequate spacing existsbetween IN pin copper/trace and ILIM0pin trace to prevent contaminate buildup during the PCBassembly process.If a low-current-limit setpoint is required(RILIMx >200kΩ),use ILIM1for this case,as it is further away from the IN pin.4.2PCB DrawingsThe Figure3through Figure6show component placement and layout of the EVM.5 SLVU462–June2011TPS2554and TPS2555Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedEVM Assembly Drawings and Layout Guidelines Figure 3.Top-Side Placement and RoutingFigure yer-Two Routing6TPS2554and TPS2555Evaluation ModuleSLVU462–June 2011Submit Documentation FeedbackCopyright ©2011,Texas Instruments Incorporated EVM Assembly Drawings and Layout Guidelinesyer-Three RoutingFigure6.Bottom-Side Placement and Routing7 SLVU462–June2011TPS2554and TPS2555Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedEvaluation Board/Kit Important NoticeTexas Instruments(TI)provides the enclosed product(s)under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,DEMONSTRATION,OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.Persons handling the product(s)must have electronics training and observe good engineering practice standards.As such,the goods being provided are not intended to be complete in terms of required design-,marketing-,and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards.This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility,restricted substances(RoHS),recycling(WEEE),FCC,CE or UL,and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide,the board/kit may be returned within30 days from the date of delivery for a full refund.THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,EXPRESSED,IMPLIED,OR STATUTORY,INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods.Further,the user indemnifies TI from all claims arising from the handling or use of the goods.Due to the open construction of the product,it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE,NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT,SPECIAL,INCIDENTAL,OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products,and therefore our arrangement with the user is not exclusive.TI assumes no liability for applications assistance,customer product design,software performance,or infringement of patents or services described herein.Please read the User’s Guide and,specifically,the Warnings and Restrictions notice in the User’s Guide prior to handling the product.This notice contains important safety information about temperatures and voltages.For additional information on TI’s environmental and/or safety programs,please contact the TI application engineer or visit /esh.No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine,process,or combination in which such TI products or services might be or are used.FCC WarningThis evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,DEMONSTRATION,OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.It generates,uses,and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part15 of FCC rules,which are designed to provide reasonable protection against radio frequency interference.Operation of this equipment in other environments may cause interference with radio communications,in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.EVM Warnings and RestrictionsIt is important to operate this EVM within the input voltage range of0V to5.5V and the output voltage range of0V to5.5V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.If there are questions concerning the input range,please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output.If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation,some circuit components may have case temperatures greater than85°C.The EVM is designed to operate properly with certain components above85°C as long as the input and output ranges are maintained.These components include but are not limited to linear regulators,switching transistors,pass transistors,and current sense resistors.These types of devices can be identified using the EVM schematic located in the EVM User's Guide.When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2011,Texas Instruments IncorporatedIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to 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such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAudio /audio Communications and Telecom /communicationsAmplifiers Computers and Peripherals /computersData Converters Consumer Electronics /consumer-appsDLP®Products Energy and Lighting /energyDSP Industrial /industrialClocks and Timers /clocks Medical /medicalInterface Security /securityLogic Space,Avionics and Defense /space-avionics-defense Power Mgmt Transportation and /automotiveAutomotiveMicrocontrollers Video and Imaging /videoRFID Wireless /wireless-appsRF/IF and ZigBee®Solutions /lprfTI E2E Community Home Page Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2011,Texas Instruments Incorporated。
PSL641U保护调试手册
PSL641U保护调试步骤PSL641U保护调试步骤 (1)1.装置上电检查及版本核对 (3)2.硬件 (3)3.现场信息确认 (3)a)CT的二次额定值为5A或1A (3)b)现场直流电压为110V或220V，与装置是否一致。
(3)c)GPS对时方式 (3)d)后台通讯和串口打印 (4)4.菜单结构图 (5)5.试验仪介绍（以博电为例） (5)6.试验前的准备 (8)a)设置定值（附定值清单） (8)b)检查功能软压板 (10)c)检查是否有硬压板功能 (11)7.检查交流输入 (11)a)交流模件端子X1定义 (11)b)保护模拟量通道采样精度校准 (12)c)测量模拟量通道采样精度校准 (13)8.保护试验 (13)a)相间过流保护 (13)b)零序过电流 (14)c)低频减载 (15)d)低压减载 (17)e)过负荷 (19)f)合闸加速 (19)g)重合闸 (19)h)手动同期合闸（需投入“同期合闸”软压板） (20)9.告警及其他功能 (21)a)TV断线 (21)b)小电流接地选线地选线（以下功能都需投入“接地选线”软压板） (21)10.其他注意事项 (21)a)61850通讯设置 (21)b)调试其他注意事项（详见PS640U系列数字式装置FAQ） (21)c)网络打印设置 (21)11.附录 (22)a)附表1：程序V1.1版本内部定值 (22)b)附表2：程序V1.2版本内部定值 (22)c)附表3：TRIP跳合闸模件 (23)版权声明当前版本V1.00南京国电南京自动股份有限公司版权所有我们对本文档及其中的内容具有全部的知识产权。
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PSP641技术说明书V1.0
PSP 641数字式备用电源自投装置技术说明书使用说明书国电南京自动化股份有限公司PSP 641数字式备用电源自投装置技术说明书使用说明书编写承文新姚卫兵审核马文龙批准郭效军2000年10月* 本公司保留对此说明书修改的权利，请注意最新版本资料。
第一部分技术说明书（2000.10）目次声明 (1)安全标准 (1)1装置简介 (1)2技术参数 (4)2.1 额定参数 (4)2.2 主要技术性能 (4)2.3 绝缘性能 (5)2.4 抗电磁干扰性能 (6)2.5 机械性能 (6)2.6 环境条件 (6)3装置硬件 (7)3.1 机箱结构 (7)3.2 交流插件 (7)3.3 CPU插件 (8)3.4 电源插件 (10)3.5 逻辑及跳闸插件 (10)4功能说明 (13)4.1 逻辑可编程备投原理 (13)4.2 典型备用电源自投方式 (15)4.3 数据记录 (26)5与变电站自动化系统配合 (27)6定值及整定说明 (28)PSP641 数字式备用电源自投装置的整定值清单及说明 (28)·声明· 1声明恭喜您购买了国电南京自动化股份有限公司的数字式保护及自动化产品—数字保护及自动化技术的国内领先者。
所有国电南京自动化股份有限公司的PS系列数字式保护及自动化产品符合严格的技术规范和ISO9001产品质量标准，经得起恶劣的现场工作环境的考验。
拥有丰富的数字式保护及自动化设备的开发经验、对用户常年24小时的技术支持，您尽可以信赖国电南京自动化股份有限公司的产品。
PS系列产品采用完全汉化的显示技术，人机界面友好，使您免除查找说明书操作的烦恼。
每款产品均配置了基于PC机调试界面的接口，结合本公司提供的Psview调试软件包，大大改善了现场调试手段。
PS640系列产品采用防水、防尘、抗振动设计，适合安装于开关柜等环境条件较为恶劣的现场运行。
机箱面板采用先进的工业美学设计，使用方便，倍感亲切。
京瓷零件手册TASKalfa 3500i 4500i 5500i 零件手册
Notes
Quantity 120 230 240
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31 14 19
31
22
15
102 103 103
18
28 30 27
24
101
4 10
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23 20 18
102 101 102
Description
COVER TOP TRAY COVER RIGHT LOWER F COVER RIGHT MIDDLE R COVER RIGHT LOWER R COVER EXIT COVER TRAY REAR COVER ISU BOTTOM COVER INNER LEFT COVER INNER FEED F COVER HANDLE COVER MAIN SWITCH MOUNT FRONT COVER LEFT STOPPER ORIGINAL STRAP FRONT COVER LABEL SW CAUTION EN EMBLEM SHEET EMBLEM 5500 SHEET EMBLEM 4500 SHEET EMBLEM 3500 PLATE MAGNET SHEET COVER FRONT COVER FRONT A PARTS COVER FRONT SP STOPPER CONTAINER PLATE FRONT COVER WIRE FRONT LOW PARTS,HUMIDITY SENSOR,SP COVER HUMIDITY SENSOR SHEET HUMIDITY SENSOR A SHEET HUMIDITY SENSOR B SHEET COVER HUMIDITY SENSOR COVER FRONT RIGHT LOWER SPACER USB SHEET COVER FRONT B SEAL DUCT DLP B LABEL SW CAUTION SET A
HY57V641620F(L_S)TP_series(Rev1.0)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.Rev. 1.0 / Apr. 2007164Mb Synchronous DRAM based on 1M x 4Bank x16 I/O Document Title4Bank x 1M x 16bits Synchronous DRAMRevision HistoryRevision No.History Draft Date Remark 0.1Initial Draft Jan. 2007Preliminary1.0Final VersionApr. 2007Rev. 1.0 / Apr. 20072DESCRIPTIONThe Hynix HY57V641620F(L/S)TP series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620F(L/S)TP is organized as 4banks of 1,048,576x16.HY57V641620F(L/S)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-stricted by a '2N' rule)FEATURESORDERING INFORMATIONNote: 1. HY57V641620FTP Series: Normal power 2. HY57V641620FLTP Series: Low power3. HY57V641620FSTP Series: Super Low power Part Number Clock Frequency OrganizationInterfaceOperation Temp.PackageHY57V641620F(L/S)TP-5200MHz 4Banks x 1Mbits x16LVTTL0o C to 7054 Pin TSOP (Lead Free)HY57V641620F(L/S)TP-6166MHz HY57V641620F(L/S)TP-7143MHz HY57V641620F(L/S)TP-H 133MHz HY57V641620F(L/S)TP-5I 200MHz -40o C to 85HY57V641620F(L/S)TP-6I 166MHz HY57V641620F(L/S)TP-7I 143MHz HY57V641620F(L/S)TP-HI133MHz•Voltage: VDD, VDDQ 3.3V supply voltage•All device pins are compatible with LVTTL interface • 54 Pin TSOPII (Lead or Lead Free Package)•All inputs and outputs referenced to positive edge of system clock•Data mask function by UDQM, LDQM•Internal four banks operation•Auto refresh and self refresh •4096 Refresh cycles / 64ms•Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst•Programmable CAS Latency; 2, 3 Clocks •Burst Read Single Write operationPIN ASSIGNMENTSRev. 1.0 / Apr. 2007 3PIN DESCRIPTIONSYMBOL TYPE DESCRIPTIONCLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLKCKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshCS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQMBA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activityA0 ~ A11Address Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7 Auto-precharge flag: A10RAS, CAS, WERow Address Strobe,Column Address Strobe,Write EnableRAS, CAS and WE define the operationRefer function truth table for detailsUDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write modeDQ0 ~ DQ15Data Input / Output Multiplexed data input / output pinVDD / VSS Power Supply / Ground Power supply for internal circuits and input buffersVDDQ / VSSQ Data Output Power /GroundPower supply for output buffersNC No Connection No connectionRev. 1.0 / Apr. 2007 4FUNCTIONAL BLOCK DIAGRAM1Mbit x 4banks x 16 I/O Synchronous DRAMRev. 1.0 / Apr. 2007 5Rev. 1.0 / Apr. 2007 6BASIC FUNCTIONAL DESCRIPTIONMode RegisterBA1BA0A11A10A9A8A7A6A5A4A3A2A1A0OP CodeCAS LatencyBTBurst LengthOP CodeA9Write Mode0Burst Read and Burst Write1Burst Read and Single WriteBurst TypeA3Burst Type 0Sequential 1InterleaveBurst LengthA2 A1A0Burst Length A3 = 0A3=1 00011 00122 01044 01188 100Reserved Reserved 101Reserved Reserved 1 10Reserved Reserved 111Full PageReservedCAS LatencyA6A5 A4CAS Latency 00 0Reserved 0 0 1Reserved0 1 020 1 1 3 1 0 0Reserved 1 0 1Reserved 1 1 0Reserved 111ReservedRev. 1.0 / Apr. 20077ABSOLUTE MAXIMUM RATINGDC OPERATING CONDITION (T A = 0 to 70o C / -40 to 85o C )Note: 1. All voltages are referenced to V SS = 0V2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.AC OPERATING TEST CONDITION (T A = 0 to 70o C / -40 to 85o C , V DD =3.3±0.3V, V SS =0V)Note: 1.ParameterSymbolRating UnitAmbient Temperature T A0 ~ 70(Commercial part)oC -40 ~ 85(Industrial part)oCStorage TemperatureT STG -55 ~ 125o CVoltage on Any Pin relative to VSS V IN , V OUT -1.0 ~ 4.6V Voltage on VDD supply relative to VSS V DD , V DDQ-1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power DissipationP D 1W Soldering Temperature . TimeT SOLDER260 . 10o C . SecParameterSymbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ3.0 3.3 3.6V 1Input High Voltage VIH 2.0 3.0VDDQ + 0.3V 1, 2Input Low VoltageVIL-0.3-0.8V1, 3ParameterSymbol Value Unit NoteAC Input High/Low Level VoltageVIH / VIL 2.4 / 0.4V Input Timing Measurement Reference Level Voltage Vtrip 1.4V Input Rise/Fall TimetR / tF 1ns Output Timing Measurement Reference Level Voltage Voutref 1.4V Output Load Capacitance for Access Time MeasurementCL30pF1Rev. 1.0 / Apr. 20078CAPACITANCE (f=1MHz, V DD =3.3V)DC CHARACTERRISTICS I (T A = 0 to 70o C / -40 to 85o C )Note: 1. V IN = 0 to 3.3V, All other balls are not tested under V IN =0V 2. D OUT is disabled, V OUT =0 to 3.6ParameterPinSymbol Min Max Unit Input capacitanceCLKCI1 2.0 4.0pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM CI2 2.5 5.0pF Data input / output capacitanceDQ0 ~ DQ15CI/O3.05.5pFParameterSymbol Min Max Unit Note Input Leakage Current ILI -11uA 1 Output Leakage Current ILO -11uA 2 Output High Voltage VOH 2.4-V IOH = -4mA Output Low VoltageVOL-0.4VIOL = +4mARev. 1.0 / Apr. 20079DC CHARACTERISTICS II (T A = 0 to 70o C / -40 to 85o C )Note: 1. I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V641620FTP Series: Normal Power HY57V641620FLTP Series: Low PowerHY57V641620FSTP Series: Super Low PowerParameterSymbolTest ConditionSpeed Unit Note567HOperating Current IDD1Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA 120110100100mA 1Precharge Standby Cur-rentin Power Down ModeIDD2P CKE ≤ VIL(max), tCK = 15ns 2mA IDD2PS CKE ≤ VIL(max), tCK = ∞2mAPrecharge Standby Cur-rentin Non Power Down ModeIDD2NCKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks.All other pins ≥ VDD-0.2V or ≤ 0.2V 18mAIDD2NS CKE ≥ VIH(min), tCK = ∞Input signals are stable.15Active Standby Current in Power Down ModeIDD3P CKE ≤ VIL(max), tCK = 15ns 3mAIDD3PSCKE ≤ VIL(max), tCK = ∞3Active Standby Current in Non Power Down ModeIDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks.All other pins ≥ VDD-0.2V or ≤ 0.2V 40mAIDD3NSCKE ≥ VIH(min), tCK = ∞Input signals are stable.35Burst Mode Operating CurrentIDD4tCK ≥ tCK(min), IOL=0mA All banks active120110100100mA 1Auto Refresh CurrentIDD5tRC ≥ tRC(min), All banks active170160150150mA 2Self Refresh CurrentIDD6CKE ≤ 0.2VNormal1mA3Low power 400uA Super Low power300uA3, 4Rev. 1.0 / Apr. 200710AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)Note: 1. Assume t R / t F (input rise and fall time) is 1ns. If t R & t F > 1ns, then [(t R +t F )/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If t R > 1ns, then (t R /2-0.5)ns should be added to the parameter.ParameterSymbol 567H Unit NoteMin Max Min Max Min Max Min Max System Clock Cycle TimeCL = 3tCK3 5.01000 6.010007.010007.51000ns CL = 2tCK210101010ns Clock High Pulse Width tCHW 1.75- 2.0- 2.0- 2.5-ns 1Clock Low Pulse Width tCLW1.75-2.0- 2.0- 2.5-ns 1Access Time From Clock CL = 3tAC3- 4.5- 5.4- 5.4- 5.4ns 2CL = 2tAC2- 6.0- 6.0- 6.0- 6.0ns Data-out Hold Time tOH 2.0- 2.0- 2.5- 2.5-ns Data-Input Setup Time tDS 1.5- 1.5- 1.5- 1.5-ns 1Data-Input Hold Time tDH 0.8-0.8-0.8-0.8-ns 1Address Setup Time tAS 1.5- 1.5- 1.5- 1.5-ns 1Address Hold Time tAH 0.8-0.8-0.8-0.8-ns 1CKE Setup Time tCKS 1.5- 1.5- 1.5- 1.5-ns 1CKE Hold Time tCKH 0.8-0.8-0.8-0.8-ns 1Command Setup Time tCS 1.5- 1.5- 1.5- 1.5-ns 1Command Hold TimetCH0.8-0.8-0.8-0.8-ns 1CLK to Data Output in Low-Z Time tOLZ 1.0- 1.0- 1.5- 1.5-ns CLK to Data Output in High-Z TimeCL = 3tOHZ3- 4.5- 5.4- 5.4- 5.4ns CL = 2tOHZ2- 6.0- 6.0- 6.0- 6.0nsRev. 1.0 / Apr. 200711AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)Note: 1. A new command can be given t RRC after self refresh exit.ParameterSymbol 567H Unit Note Min Max Min Max Min Max Min Max RAS Cycle Time OperationtRC55-60-63-63-ns RAS Cycle Time Auto Refresh tRRC55-60-63-63-ns RAS to CAS Delay tRCD 15-18-20-20-ns RAS Active Time tRAS 38.7100K 42 100K 42 100K 42120K ns RAS Precharge TimetRP 15-18-20-20-ns RAS to RAS Bank Active Delay tRRD 10-12-14-15-ns CAS to CAS DelaytCCD1-1-1-1-CLK Write Command to Data-In De-laytWTL0 -0 -0 -0 -CLK Data-in to Precharge Command tDPL 2-2-2-2-CLKData-In to Active Command tDAL tDPL + tRPDQM to Data-Out Hi-Z tDQZ 2-2-2-2-CLK DQM to Data-In Mask tDQM 0-0-0-0-CLK MRS to New Command tMRD 2-2-2-2-CLK Precharge to Data Output High-ZCL = 3tPROZ33-3-3-3-CLK CL = 2tPROZ22-2-2-2-CLK Power Down Exit Time tDPE 1-1-1-1-CLK Self Refresh Exit Time tSRE 1-1-1-1-CLK 1Refresh TimetREF-64-64-64-64msCOMMAND TRUTH TABLECommand CKEn-1CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note Mode Register Set H X L L L L X OP codeNo Operation H X H X X XX X L H H HBank Active H X L L H H X RA VReadH X L H L H X CA LVRead with Autopre-chargeHWriteH X L H L L X CA LVWrite with Autopre-chargeHPrecharge All BanksH X L L H L X X H XPrecharge selectedBankL V Burst Stop H X L H H L X XDQM H X V XAuto Refresh H H L L L H X XBurst-Read-Single-WRITE H X L L L L XA9 ball High(Other balls OP code)MRSModeSelf Refresh1Entry H L L L L H XX Exit L HH X X XXL H H HPrecharge power down Entry H LH X X XXXL H H HExit L HH X X XXL H H HClock Suspend Entry H LH X X XXXL V V VExit L H X XRev. 1.0 / Apr. 200712PACKAGE INFORMATION400mil 54pin Thin Small Outline PackageRev. 1.0 / Apr. 200713。
士兰微SL库存型号推荐---赛矽电子何小姐
士兰微SL库存型号推荐SA7527(料管)士兰微SOP-8 1000SA1117BH-1.8TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-3.3TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-2.5TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-5.0TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-ADJTR 士兰微SOT-223 20000/箱 2500/盘SD4840P67K65 士兰微DIP-8 2000/盒SD4841P67K65 士兰微DIP-8 2000/盒SD4842P67K65 士兰微DIP-8 2000/盒SD4843P67K65 士兰微DIP-8 2000/盒SD45215 士兰微SOP-8 25000/箱 2500/盘SD4844P67K65 士兰微DIP-8 2000/盒SD4870TR 士兰微SOT23-6 3000/盘SC5272 士兰微TO-22OF 1000SC5262 士兰微TO-22OF 1000SD42522 士兰微SOP-8 2500/盘SD42525E 士兰微SOT89 2500/盘SA7527(盘装)士兰微SOP-8 2500/盘SDH6802 士兰微DIP-8 2000/盒SD6863 士兰微DIP-8 2000/盒SD6861P 士兰微DIP-8 2000/盒GB45215 士兰微SOP-8 25000/箱 2500/盘SD6834 士兰微DIP-8 2000/盒SD6832 士兰微DIP-8 2000/盒SD6864 士兰微DIP-8 2000/盒SD6953B 士兰微SOT-6 3000/盘WY0365 士兰微DIP-8 2000/盒SD45216 士兰微SOP-8 25000/箱 2500/盘SA1117BH-1.2TR 士兰微SOT-223 25000/箱 2500/盘SD6834G 士兰微DIP-8 2000/盒SD45214 士兰微SOP-8 25000/箱 2500/盘SD6835 士兰微DIP-8 2000/盒SD42527 士兰微SOP-8 2500/盘SD42560E 士兰微ESOP-8 2500/盘SC8113 士兰微TO-22OF 1000SD6834B 士兰微DIP-8 2000/盒SD7530S 士兰微SOP-8 2500/盘SD45217 士兰微SOP-8 2500SD6900 士兰微SOT-6 3000/盘SD4871 士兰微SOT-23-6 3000/盘SD6800 士兰微SOP-8 盘SD6901S 士兰微SOP-8 盘SD6902S 士兰微SOP-8 盘SA1117BH-1.5TR 士兰微SOT-223 2500/盘SA9801 士兰微SOP-20 100SD6857 士兰微SOP-8 3000SD6954 士兰微DIP-8 2000SD6830 士兰微DIP-8 2000SVD1N60B 士兰微TO-92 2000/盒SVD1N60DB 士兰微TO-92 2000/盒SVD2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD7N65AF 士兰微TO-22OF 1000/盒SVD10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C100T 士兰微TO-220T 5000/箱/ 1000/盒SBD20C100F 士兰微TO-22OF 5000/箱/ 1000/盒SVD1N60M 士兰微TO-251 24000/箱 4800/盒SVD1N60M(J)士兰微TO-251 4500/盒SVD12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N60M 士兰微TO-251 24000/箱 4800/盒SVD2N60M(J) 士兰微TO-251 4500/盒SFR16S20T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100F 士兰微TO-22OF 5000/箱/ 1000/盒SBD10C150T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100T 士兰微TO-220T 5000/箱/ 1000/盒SVD5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SFR20S20T 士兰微TO-220T 5000/箱/ 1000/盒SVF1N60N 士兰微TO-126 200/包SVF10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N60D 士兰微TO-252 2500/盘SVF4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65M 士兰微TO-251 24000/箱 4800/盒SVF5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N80F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF840F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60MJ 士兰微TO-251 4500/盒SVF2N70M 士兰微TO-251 24000/箱 4800/盒SVF13N60AF 士兰微TO-22OF 1000/盒SVD2N60MJ 士兰微TO-251 4500/盒SVF12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60N 士兰微TO-126 3000/盒 200/包SVF5N60D 士兰微TO-252 2500/盘SVF13N50F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N70F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60M 士兰微TO-251 24000/箱 4800/盒SVF9N90F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N90F 士兰微TO-, 22OF 5000/箱/ 1000/盒SVF2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65D 士兰微TO-252 2500/盘SVF830F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C45T 士兰微TO-220T 5000/箱/ 1000/盒SVF20N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF1N60B 士兰微TO-92 2000/盒SVD7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF830T 士兰微TO-220F 5000/箱SVD830T 士兰微TO-220T 10SVF2N60D 士兰微TO-252 2500SVF3N80F 士兰微TO-220F 1000/盘SVF4N60F 士兰微TO-220F 1000SBD20C150T 士兰微TO-220T 1000/盒SVF4N65MJ 士兰微TO-251 4500/盒SVF4N65M(S) 士兰微TO-251 4500/盒SVF2N60M(S) 士兰微TO-251 4800PCS/盒SBD20C150F 士兰微TO-220F 1000SVD2N70M 士兰微TO-251 4500/盒SVF1N60D 士兰微TO-252 2500/盒SVF8N80F 士兰微TO-220F 1000/盒SBD10C200F 士兰微TO-220F 1000/盒SBD20C200F 士兰微TO-220F 1000/盒SVF1N60M(S) 士兰微TO-251 80/管SVF4N60EF 士兰微TO-220F 1000/盒SVF5N60MJ 士兰微TO-251 4500/盒SFR10S40T 士兰微TO-220 50 SBD20C45F 士兰微TO-220 1000/盒SA7527STR 士兰微SOP-8 2500/盘。
74、CD、LM、LF系列芯片大全
74/CD/LM/LF系列芯片大全74系列:7400 TTL 2输入端四与非门7401 TTL 集电极开路2输入端四与非门 7402 TTL 2输入端四或非门7403 TTL 集电极开路2输入端四与非门 7404 TTL 六反相器7405 TTL 集电极开路六反相器7406 TTL 集电极开路六反相高压驱动器 7407 TTL 集电极开路六正相高压驱动器 7408 TTL 2输入端四与门7409 TTL 集电极开路2输入端四与门 7410 TTL 3输入端3与非门74107 TTL 带清除主从双J-K 触发器 74109 TTL 带预置清除正触发双J-K 触发器 7411 TTL 3输入端3与门 74112 TTL 带预置清除负触发双J-K 触发器 7412 TTL 开路输出3输入端三与非门 74121 TTL 单稳态多谐振荡器74122 TTL 可再触发单稳态多谐振荡器 74123 TTL 双可再触发单稳态多谐振荡器 74125 TTL 三态输出高有效四总线缓冲门 74126 TTL 三态输出低有效四总线缓冲门 7413 TTL 4输入端双与非施密特触发器 74132 TTL 2输入端四与非施密特触发器 74133 TTL 13输入端与非门 74136 TTL 四异或门74138 TTL 3-8线译码器/复工器 74139 TTL 双2-4线译码器/复工器 7414 TTL 六反相施密特触发器74145 TTL BCD—十进制译码/驱动器 7415 TTL 开路输出3输入端三与门74150 TTL 16选1数据选择/多路开关 74151 TTL 8选1数据选择器 74153 TTL 双4选1数据选择器 74154 TTL 4线—16线译码器74155 TTL 图腾柱输出译码器/分配器 74156 TTL 开路输出译码器/分配器74157 TTL 同相输出四2选1数据选择器 74158 TTL 反相输出四2选1数据选择器 7416 TTL 开路输出六反相缓冲/驱动器 74160 TTL 可预置BCD 异步清除计数器 74161 TTL 可予制四位二进制异步清除计数器74162 TTL 可预置BCD 同步清除计数器 74163 TTL 可予制四位二进制同步清除计数器74164 TTL 八位串行入/并行输出移位寄存器74165 TTL 八位并行入/串行输出移位寄存器74166 TTL 八位并入/串出移位寄存器 74169 TTL 二进制四位加/减同步计数器7417 TTL 开路输出六同相缓冲/驱动器 74170 TTL 开路输出4×4寄存器堆 74173 TTL 三态输出四位D 型寄存器74174 TTL 带公共时钟和复位六D 触发器 74175 TTL 带公共时钟和复位四D 触发器 74180 TTL 9位奇数/偶数发生器/校验器 74181 TTL 算术逻辑单元/函数发生器 74185 TTL 二进制—BCD 代码转换器 74190 TTL BCD同步加/减计数器 74191 TTL 二进制同步可逆计数器74192 TTL 可预置BCD 双时钟可逆计数器 74193 TTL 可预置四位二进制双时钟可逆计数器74194 TTL 四位双向通用移位寄存器 74195 TTL 四位并行通道移位寄存器74196 TTL 十进制/二-十进制可预置计数锁存器74197 TTL 二进制可预置锁存器/计数器 7420 TTL 4输入端双与非门 7421 TTL 4输入端双与门7422 TTL 开路输出4输入端双与非门 74221 TTL 双/单稳态多谐振荡器74240 TTL 八反相三态缓冲器/线驱动器 74241 TTL 八同相三态缓冲器/线驱动器 74243 TTL 四同相三态总线收发器74244 TTL 八同相三态缓冲器/线驱动器 74245 TTL 八同相三态总线收发器74247 TTL BCD—7段15V 输出译码/驱动器 74248 TTL BCD—7段译码/升压输出驱动器 74249 TTL BCD—7段译码/开路输出驱动器 74251 TTL 三态输出8选1数据选择器/复工器74253 TTL 三态输出双4选1数据选择器/复工器74256 TTL 双四位可寻址锁存器74257 TTL 三态原码四2选1数据选择器/复工器74258 TTL 三态反码四2选1数据选择器/复工器74259 TTL 八位可寻址锁存器/3-8线译码器7426 TTL 2输入端高压接口四与非门 74260 TTL 5输入端双或非门 74266 TTL 2输入端四异或非门 7427 TTL 3输入端三或非门74273 TTL 带公共时钟复位八D 触发器 74279 TTL 四图腾柱输出S-R 锁存器7428 TTL 2输入端四或非门缓冲器 74283 TTL 4位二进制全加器74290 TTL 二/五分频十进制计数器 74293 TTL 二/八分频四位二进制计数器74295 TTL 四位双向通用移位寄存器 74298 TTL 四2输入多路带存贮开关 74299 TTL 三态输出八位通用移位寄存器 7430 TTL 8输入端与非门 7432 TTL 2输入端四或门74322 TTL 带符号扩展端八位移位寄存器 74323 TTL 三态输出八位双向移位/存贮寄存器7433 TTL 开路输出2输入端四或非缓冲器 74347 TTL BCD—7段译码器/驱动器 74352 TTL 双4选1数据选择器/复工器 74353 TTL 三态输出双4选1数据选择器/复工器 74365 TTL 门使能输入三态输出六同相线驱动器 74365 TTL 门使能输入三态输出六同相线驱动器 74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器 74373 TTL 三态同相八D 锁存器74374 TTL 三态反相八D 锁存器 74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D 锁存器 74378 TTL 单边输出公共使能六D 锁存器 74379 TTL 双边输出公共使能四D 锁存器 7438 TTL 开路输出2输入端四与非缓冲器 74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器 74390 TTL 双十进制计数器 74393 TTL 双四位二进制计数器 7440 TTL 4输入端双与非缓冲器 7442 TTL BCD—十进制代码转换器74352 TTL 双4选1数据选择器/复工器 74353 TTL 三态输出双4选1数据选择器/复工器 74365 TTL 门使能输入三态输出六同相线驱动器 74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器 74373 TTL 三态同相八D 锁存器74374 TTL 三态反相八D 锁存器 74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D 锁存器 74378 TTL 单边输出公共使能六D 锁存器 74379 TTL 双边输出公共使能四D 锁存器 7438 TTL 开路输出2输入端四与非缓冲器 74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器 74390 TTL 双十进制计数器 74393 TTL 双四位二进制计数器 7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74447 TTL BCD—7段译码器/驱动器7445 TTL BCD—十进制代码转换/驱动器 74450 TTL 16:1多路转接复用器多工器 74451 TTL 双8:1多路转接复用器多工器 74453 TTL 四4:1多路转接复用器多工器 7446 TTL BCD—7段低有效译码/驱动器 74460 TTL 十位比较器 74461 TTL 八进制计数器 74465 TTL 三态同相2与使能端八总线缓冲器74466 TTL 三态反相2与使能八总线缓冲器 74467 TTL 三态同相2使能端八总线缓冲器 74468 TTL 三态反相2使能端八总线缓冲器 74469 TTL 八位双向计数器7447 TTL BCD—7段高有效译码/驱动器 7448 TTL BCD —7段译码器/内部上拉输出驱动 74490 TTL 双十进制计数器74491 TTL 十位计数器74498 TTL 八进制移位寄存器7450 TTL 2-3/2-2输入端双与或非门 74502 TTL 八位逐次逼近寄存器 74503 TTL 八位逐次逼近寄存器7451 TTL 2-3/2-2输入端双与或非门 74533 TTL 三态反相八D 锁存器 74534 TTL 三态反相八D 锁存器 7454 TTL 四路输入与或非门74540 TTL 八位三态反相输出总线缓冲器 7455 TTL 4输入端二路输入与或非门 74563 TTL 八位三态反相输出触发器 74564 TTL 八位三态反相输出D 触发器74573 TTL 八位三态输出触发器 74574 TTL 八位三态输出D 触发器 74645 TTL 三态输出八同相总线传送接收器 74670 TTL 三态输出4×4寄存器堆 7473 TTL 带清除负触发双J-K 触发器 7474 TTL 带置位复位正触发双D 触发器 7476 TTL 带预置清除双J-K 触发器 7483 TTL 四位二进制快速进位全加器 7485 TTL 四位数字比较器7486 TTL 2输入端四异或门7490 TTL 可二/五分频十进制计数器 7493 TTL 可二/八分频二进制计数器 7495 TTL 四位并行输入输出移位寄存器 7497 TTL 6位同步二进制乘法器LM/LF系列:LM12 80W OPERATIONAL AMPLIFIER 80瓦运算放大器LM124 LM224 LM324 LM2902 Low Power Quad Operational Amplifier 低电压双路运算放大器LM324 Low Power Quad Operational Amplifier 低电压双路运算放大器LM129 LM329 Precision Reference 精密电压基准芯片LM135 LM235 LM335 精密温度传感器芯片 LM1458 LM1558 Dual Operational Amplifier 双运算放大器LM158 LM258 LM358 LM2904 Low Power Dual Operational Amplifier 低压双运算放大器 LM18293 Four Channel Push-Pull Driver 四通道推拉驱动器LM1868 AM/FM Radio System 调幅/调频收音机芯片LM1951 Solid State 1 Amp Switch 1安培固态开关LM2574 Simple Switcher 0.5A Step-Down Voltage Regulator 0.5A 降阶式电压调节器 LM1575 LM2575 1A Step-Down Voltage Regulator 1A 降阶式电压调节器LM2576 3A Step-Down Voltage Regulator 3A 降阶式电压调节器LM1577 LM2577 Simple Switch Step-Down Voltage Regulator 降阶式电压调节器 LM2587 Simple Switch 5A Flyback Regulator 5A 返馈开关式电压调节器 LM1893 LM2893 Carrier Current Transceiver 载体电流收发器LM193 LM293 LM393 LM2903 Low Power Low Offset Voltage Dual Comparator 双路低压低漂移比较器LM2907 LM2917 Frequency to Voltage Converter 频率电压转换器LM101A LM201A LM301A Operational Amplifiers 运算放大器芯片 LM3045 LM3046 LM3086 Transistor Array 晶体管阵列LM111 LM211 LM311 Voltage Comparator 电压比较器LM117 LM317 3-Terminal Adjustable Regulator 三端可调式稳压器LM118 LM218 LM318 Operational Amplifier 运算放大器LM133 LM333 3A Adjustable Negative Regulator 3安培可调负电压调节器LM137 LM337 3-Terminal Adjustable Negative Regulator 可调式三端负压稳压器LM34 Precision Fahrenheit Temperature Sensor 精密华氏温度传感器LM342 3-Terminal Positive Regulator 三端正压稳压器LM148 LM248 LM348 / LM149 LM349 双LM741运算放大器LM35 Precision Centigrade Temperature Sensors 精密摄氏温度传感器LM158 LM258 LM358 LM2904 Low Power Dual Operational Amplifiers 低压双运算放大器LM150 LM350 3A Adjustable Regulator 3安培可调式电压调节器LM380 2.5W Audio Amplifier 2.5瓦音频放大器LM386 Low Voltage Audio Power Amplifier 低压音频功率放大器LM3886 High-Performance 68W Audio Power Amplifier With Mute 高性能68瓦音频功率放大器/带静音LM555 LM555C Timer Circuit 时基发生器电路LM556 LM556C Timer Circuit 双时基发生器电路 LM565 Phase Locked Loop 相位跟随器LM567 Tone Decoder 音频译码器LM621 BrushLess Motor Commutator 无刷电机换向器LM628 LM629 Precision Motion Controller 精密位移控制器LM675 Power Operational Amplifier 功率运算放大器LM723 Voltage Regulator 电压调节器LM741 Operational Amplifier 运算放大器 LM7805 LM78xx 系列稳压器 LM7812 LM78xx 系列稳压器 LM7815 LM78xx 系列稳压器 LM78L00 3-Terminal Positive Voltage Regulator 三端正压调节器 LM78L05 3-Terminal Positive Voltage Regulator三端正压调节器 LM78L09 3-Terminal Positive Voltage Regulator 三端正压调节器LM78L12 3-Terminal Positive Voltage Regulator 三端正压调节器 LM78L15 3-Terminal Positive Voltage Regulator 三端正压调节器 LM78L62 3-Terminal Positive Voltage Regulator 三端正压调节器 LM78L82 3-Terminal Positive Voltage Regulator三端正压调节器 LM340 LM78Mxx Series 3-Terminal Positive Regulator 三端正压稳压器 LM7905 3-Terminal Nagative Voltage Regulator 三端负压调节器 LM7912 3-Terminal Nagative Voltage Regulator 三端负压调节器 LM7915 3-Terminal Nagative Voltage Regulator 三端负压调节器 LM79Mxx 3-Terminal Nagative Voltage Regulator 三端负压调节器 LF147 LF347 Wide Bandwidth Quad JFET input operational amplifier 宽带 J 型场效应输入运算放大器 LF351 Wide Bandwidth Quad JFET input operational amplifier 宽带 J 型场效应输入运算放大器 LF353 Wide Bandwidth Quad JFET input operational amplifier 宽带 J 型场效应输入运算放大器 LF444 Quad Low Power JFET input operational amplifier 双低压 J 型场效应输入运算放大器系列: CD 系列: CD4000 双 3 输入端或非门+单非门 TI CD4001 四 2 输入端或非门 HIT/NSC/TI/GOL CD4002 双 4 输入端或非门 NSC CD4006 18 位串入/串出移位寄存器 NSC CD4007 双互补对加反相器 NSC CD4008 4 位超前进位全加器 NSC CD4009 六反相缓冲/变换器 NSC CD4010 六同相缓冲/变换器 NSC CD4011 四 2 输入端与非门 HIT/TI CD4012 双 4 输入端与非门 NSC CD4013 双主-从 D 型触发器FSC/NSC/TOS CD4014 8 位串入/并入-串出移位寄存器 NSC CD4015 双 4 位串入/并出移位寄存器 TI CD4016 四传输门 FSC/TI CD4017 十进制计数/分配器FSC/TI/MOT CD4018 可预制 1/N 计数器 NSC/MOT CD4019 四与或选择器 PHICD4020 14 级串行二进制计数/分频器 FSC CD4021 08 位串入/并入-串出移位寄存器PHI/NSC CD4022 八进制计数/分配器 NSC/MOT CD4023 三 3 输入端与非门NSC/MOT/TI CD4024 7 级二进制串行计数 / 分频器 NSC/MOT/TI CD4025 三 3 输入端或非门 NSC/MOT/TI CD4026 十进制计数 /7 段译码器 NSC/MOT/TICD4027 双 J-K 触发器 NSC/MOT/TI CD4028 BCD 码十进制译码器 NSC/MOT/TI CD4029 可预置可逆计数器 NSC/MOT/TI CD4030 四异或门 NSC/MOT/TI/GOLCD4031 64 位串入 / 串出移位存储器 NSC/MOT/TI CD4032 三串行加法器NSC/TI CD4033 十进制计数/7 段译码器 NSC/TI CD4034 8 位通用总线寄存器NSC/MOT/TI CD4035 4 位并入/串入-并出/串出移位寄存 NSC/MOT/TI CD4038 三串行加法器 NSC/TI CD4040 12 级二进制串行计数 / 分频器 NSC/MOT/TICD4041 四同相/反相缓冲器 NSC/MOT/TI CD4042 四锁存 D 型触发器 NSC/MOT/TI CD4043 4 三态 R-S 锁存触发器("1"触发 NSC/MOT/TI CD4044 四三态 R-S 锁存触发器("0"触发 NSC/MOT/TI CD4046 锁相环 NSC/MOT/TI/PHI CD4047 无稳态 / 单稳态多谐振荡器 NSC/MOT/TI CD4048 4 输入端可扩展多功能门 NSC/HIT/TI CD4049 六反相缓冲/变换器 NSC/HIT/TI CD4050 六同相缓冲/变换器 NSC/MOT/TI CD4051 八选一模拟开关 NSC/MOT/TI CD4052 双 4 选 1 模拟开关 NSC/MOT/TI CD4053 三组二路模拟开关 NSC/MOT/TI CD4054 液晶显示驱动器 NSC/HIT/TICD4055 BCD-7 段译码 / 液晶驱动器 NSC/HIT/TI CD4056 液晶显示驱动器NSC/HIT/TI CD4059 “N”分频计数器 NSC/TI CD4060 14 级二进制串行计数 / 分频器 NSC/TI/MOT CD4063 四位数字比较器 NSC/HIT/TI CD4066 四传输门NSC/TI/MOT CD4067 16 选 1 模拟开关 NSC/TI CD4068 八输入端与非门/与门NSC/HIT/TI CD4069 六反相器 NSC/HIT/TI CD4070 四异或门 NSC/HIT/TI CD4071四 2 输入端或门 NSC/TI CD4072 双 4 输入端或门 NSC/TI CD4073 三 3 输入端与门NSC/TI CD4075 三 3 输入端或门 NSC/TI CD4076 四 D 寄存器 CD4077 四 2 输入端异或非门 HIT CD4078 8 输入端或非门/或门 CD4081 四 2 输入端与门 NSC/HIT/TI CD4082 双 4 输入端与门 NSC/HIT/TI CD4085 双 2 路 2 输入端与或非门 CD4086 四2 输入端可扩展与或非门 CD4089 二进制比例乘法器 CD4093 四 2 输入端施密特触发器 NSC/MOT/STCD4094 8 位移位存储总线寄存器 NSC/TI/PHI CD4095 3 输入端 J-K 触发器 CD4096 3 输入端 J-K 触发器 CD4097 双路八选一模拟开关 CD4098 双单稳态触发器 NSC/MOT/TI CD4099 8 位可寻址锁存器 NSC/MOT/ST CD40100 32 位左/右移位寄存器 CD40101 9 位奇偶较验器 CD40102 8 位可预置同步 BCD 减法计数器CD40103 8 位可预置同步二进制减法计数器 CD40104 4 位双向移位寄存器CD40105 先入先出 FI-FD 寄存器 CD40106 六施密特触发器 NSCTI CD40107 双 2 输入端与非缓冲 / 驱动器 HARTI CD40108 4 字×4 位多通道寄存器 CD40109 四低-高电平位移器 CD40110 十进制加/减,计数,锁存,译码驱动 ST CD40147 10-4 线编码器 NSCMOT CD40160 可预置 BCD 加计数器 NSCMOT CD40161 可预置 4 位二进制加计数器 NSCMOT CD40162 BCD 加法计数器 NSCMOT CD40163 4 位二进制同步计数器 NSCMOT CD40174 六锁存 D 型触发器 NSCTIMOT CD40175 四 D 型触发器 NSCTIMOT CD40181 4 位算术逻辑单元/函数发生器 CD40182 超前位发生器 CD40192 可预置 BCD 加/减计数器(双时钟 NSCTI CD40193 可预置 4 位二进制加/减计数器 NSCTI CD40194 4 位并入/串入-并出/串出移位寄存 NSCMOTCD40195 4 位并入/串入-并出/串出移位寄存 NSCMOT CD40208 4×4 多端口寄存器CD4501 4 输入端双与门及 2 输入端或非门 CD4502 可选通三态输出六反相/缓冲器CD4503 六同相三态缓冲器 CD4504 六电压转换器 CD4506 双二组 2 输入可扩展或非门 CD4508 CD4510 CD4511 CD4512 CD4513 CD4514 CD4515 CD4516 CD4517 CD4518 CD4519 CD4520 CD4521 CD4522 CD4526 CD4527 CD4528 CD4529CD4530 CD4531 CD4532 CD4536 CD4538 CD4539 CD4541 CD4543 CD4544CD4547 CD4549 CD4551 CD4553 CD4555 CD4556 CD4558 CD4560 CD4561CD4573 CD4574 CD4575 CD4583 CD4584 CD4585 CD4599 双 4 位锁存 D 型触发器可预置 BCD 码加/减计数器 BCD 锁存,7 段译码,驱动器八路数据选择器 BCD 锁存,7 段译码,驱动器(消隐 4 位锁存,4 线-16 线译码器 4 位锁存,4 线-16 线译码器可预置 4 位二进制加/减计数器双 64 位静态移位寄存器双 BCD 同步加计数器四位与或选择器双 4 位二进制同步加计数器 24 级分频器可预置 BCD 同步 1/N 计数器可预置 4 位二进制同步 1/N 计数器 BCD 比例乘法器双单稳态触发器双四路/单八路模拟开关双 5 输入端优势逻辑门 12 位奇偶校验器 8 位优先编码器可编程定时器精密双单稳双四路数据选择器可编程序振荡/计时器 BCD 七段锁存译码,驱动器BCD 七段锁存译码,驱动器 BCD 七段译码/大电流驱动器函数近似寄存器四 2 通道模拟开关三位 BCD 计数器双二进制四选一译码器/分离器双二进制四选一译码器/分离器 BCD 八段译码器 "N"BCD 加法器 "9"求补器四可编程运算放大器四可编程电压比较器双可编程运放/比较器双施密特触发器六施密特触发器 4 位数值比较器 8 位可寻址锁存器。
XT4N 160 电路保护设备说明书
Certificates and Declarations (Document Number)
Data Sheet, Technical Information Declaration of Conformity - CE Environmental Information GL Certificate Instructions and Manuals LR Certificate REACH Declaration RoHS Information
2
1 piece 145 mm 210 mm 168 mm
3.5 kg 8015644696122
Environmental
RoHS Status
Following EU Directive 2011/65/EU and Amendment 2015/863 July 22, 2019
Additional Information
Rated Ultimate ShortCircuit Breaking Capacity (Icu)
Rated Uninterrupted Current (Iu) Release Release Type Short-Circuit
Power Distribution
AC 120 cycles per hour
CB 160 A 50 / 60 Hz 690 V
8 kV
1000 V
690 V AC
(220 V AC) 65 kA (230 V AC) 65 kA (240 V AC) 65 kA (380 V AC) 36 kA (415 V AC) 36 kA (440 V AC) 36 kA (500 V AC) 30 kA (525 V AC) 20 kA (690 V AC) 10 kA (220 V AC) 65 kA (230 V AC) 65 kA (240 V AC) 65 kA (380 V AC) 36 kA (415 V AC) 36 kA (440 V AC) 36 kA (500 V AC) 30 kA (525 V AC) 20 kA (690 V AC) 10 kA
AON6411替代型号DMP2002UPS
20V P-CHANNEL ENHANCEMENT MODE MOSFETFeaturesDescriptionThis new generation P-Channel Enhancement Mode MOSFET is designed to minimize R DS(ON) and yet maintain superior switching performance. This device is ideal for use in notebook battery power management and load switch.Applications∙ SwitchPowerDI5060-8 (Type K)∙Thermally Efficient Package-Cooler Running Applications ∙ High Conversion Efficiency∙ Low R DS(ON) – Minimizes On State Losses∙ <1.1mm Package Profile – Ideal for Thin Applications ∙ Lead-Free Finish; RoHS Compliant (Notes 1 & 2)∙ Halogen and Antimony Free. “Green” Device (Note 3) ∙Qualified to AEC-Q101 Standards for High ReliabilityMechanical Data∙ Case: PowerDI5060-8 (Type K)∙ Case Material: Molded Plastic, ―Green ‖ Molding Compound; UL Flammability Classification Rating 94V-0 ∙ Moisture Sensitivity: Level 1 per J-STD-020∙ Terminal Finish - Matte Tin Annealed over Copper Leadframe; Solderable per MIL-STD-202, Method 208 ∙Weight: 0.097 grams (Approximate)GTop ViewPin1Bottom ViewSInternal SchematicTop View Pin ConfigurationOrdering Information (Note 4)Notes:1. EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. All applicable RoHS exemptions applied.2. See /quality/lead_free.html fo r more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.3. Halogen- and Antimony-free "Green‖ products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.4. For packaging details, go to our website at /products/packages.html.Marking InformationPowerDI5060-8 (Type K)= Manufacturer’s MarkingP2002US = Product Type Marking Code YYWW = Date Code MarkingYY = Last Two Digits of Year (ex: 16 = 2016) WW = Week Code (01 to 53)SSSGGreenP2002USMaximum Ratings (@T A = +25°C, unless otherwise specified.)Thermal CharacteristicsElectrical Characteristics (@T A = +25°C, unless otherwise specified.)(Note 7)(Note 7)Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with thermal bias to bottom layer 1inch square copper plate.6. Short duration pulse test used to minimize self-heating effect.7. Guaranteed by design. Not subject to product testing.8. Package limited.R D S (O N ), D R A I N -S O U R C E O N -R E S I S T A N C E (N O R M A L I Z E D )I D , D R A I N C U R R E N T (A )30.03025.0 25 20.020 15.0 1510.0 10 5.050.00.00240.00220.0020.5 1 1.5 2 2.5 3V DS , DRAIN-SOURCE VOLTAGE (V) Figure 1. Typical Output Characteristic0.01 0.0090.008 0.007 0.006 0.0050.40.6 0.8 1 1.2 1.4 1.6 1.8V GS , GATE-SOURCE VOLTAGE (V) Figure 2. Typical Transfer Characteristic0.00180.00160.004 0.003 0.0020.0010.00140.002426101418 222630I D , DRAIN-SOURCE CURRENT (A)Figure 3. Typical On-Resistance vs. Drain Currentand Gate Voltage1.624681012V GS , GATE-SOURCE VOLTAGE (V) Figure 4. Typical Transfer Characteristic0.00220.0021.40.0018 1.20.0016 0.00140.001210.80.001510 15 20 25 30 I D , DRAIN CURRENT(A)Figure 5. Typical On-Resistance vs. Drain Currentand Temperature0.6-50-25 0 25 50 75 100 125 150 T J , JUNCTION TEMPERATURE (℃) Figure 6. On-Resistance Variation withTemperature-55= -15A= -20AR D S (O N ), D R A I N -S O U R C E R D S (O N ), D R A I N -S O U R C E O N -R E S I S T A N C E (Ω)O N -R E S I S T A N C E (Ω)I D , D R A I N C U R R E N T (A )R D S (O N ), D R A I N -S O U R C E O N -R E S I S T A N C E (Ω)T A I S , S O U R C E C U R R E N T (A )C T , J U N C T I O N C A P A C I T A N C E (p F )0.0034 10.0030.00260.80.60.00220.00180.40.0014 0.20.00130-50 -25 0 25 50 75 100 125 150 T J , JUNCTION TEMPERATURE (℃) Figure 7. On-Resistance Variation with Temperature100000-50-25 0 25 50 75 100 125 150T A , AMBIENT TEMPERATURE (℃)Figure 8. Gate Threshold Variation vs AmbientTemperature25 20 15 100001050 00.2 0.4 0.6 0.8 1 V SD , SOURCE-DRAIN VOLTAGE (V)Figure 9. Diode Forward Voltage vs. Current10 100010004 8 12 16 20V DS , DRAIN-SOURCE VOLTAGE (V) Figure 10. Typical Junction Capacitance8100641020 050 100 150 200 250 300 350 400 450 500Q g (nC)Figure 11. Gate Charge10.11 10100V DS , DRAIN-SOURCE VOLTAGE (V) Figure 12. SOA, Safe Operation AreaI D = -1mAI D = -250µAV DS = -10V, I D = -20A= 1s = 100ms = 10ms= 1msR D S (O N ), D R A I N -S O U R C E O N -R E S I S T A N C E (Ω)V G S (V )I D , D R A I N C U R R E N T (A )V G S (T H ), G A T E T H R E S H O L D V O L T A G E (V )10.10.010.0011E-061E-050.00010.001 0.01 0.1 1 101001000t1, PULSE DURATION TIME (sec)Figure 13. Transient Thermal Resistancer (t ), T R A N S I E N T T H E R M A L R E S I S T A N C E1 b( 8x)1Package Outline DimensionsPlease see /package-outlines.html for the latest version.b1( 8x)PowerDI5060-8 (Type K)。