第三章EDA工具

Difficult to select the input stimulus pattern to cover all possible verifications More time consuming

Less accurate and may give wrong results occasionally Limited to digital circuits only
• Accuracy: high abstraction model,
example using SystemC, should be cycle- or pin accurate • Performance: fast enough to run RTOS • Usage: for both SW and HW teams • Availability: available early in the design cycle to meet time-tomarket, HW/SW co-design, coverification


Flexible Easy debugging Transparent fast
Logic Simulation - cont’t
• Event-Driven is most basic algorithm • Event: Signal of a net different from
Dynamic Timing Verification
• Dynamic Timing Verification

• Event-driven simulation algorithm
with timing violation checking
With Vectors Logic Simulation + Delay Factors No false path But take excessive time to develop stimulus, run through all vectors
• What is ESL design

• ESL hardware design tools utilize
industry standard languages for transaction level modeling

Using high-level modeling and simulation techniques to create an “executable specification” of the design or a “virtual platform”.
SPICE Circuit Simulation
• Developed at UC Berkeley in early 1970s • Models and simulates the electrical-level circuit behavior accurately • Widely used due to open release to public users • Solves the whole circuit as a single entity • Slow and limited to small circuit less than 100,000 element • Earlier attempts to speed up simulation, • •
Outlines
• Introduction • ESL Design Tool • EDA for Cell-based Design

Dynamic & Static Verification Synthesis Design for Testing Place & Route Physical Checking/Extraction
Architecture Exploration Benchmarking SW Development HW/SW CoVerification RTL Verification
ESL
Signals & Gates
Verilog VHDL
Layout
ESL Design
• ESL design enabling:
EDA Companies and Tools
EDA Market
Global Income of EDA Market Source: Gartner Dataquest
Trends of EDA Tools: RTL, GL and ESL Source: Gartner Dataquest
Design Technology Needs as Geometries Shrink
第三章
SoC设计与EDA工具
Outlines
• Introduction • ESL Design Tool • EDA for Cell-based Design

Dynamic & Static Verification Synthesis Design for Testing Place & Route Physical Checking/Extraction
• Two kind of formal verifications:
• •
Logic Equivalence Checking
• Trend: ESL arithmetic
C/C++, SystemC, SystemVerilog
synthesis tool
ESL – High Abstraction Level
Function Calls
Matlab
Algorithm Design
Transactions
SystemC SystemVeril og
Dynamic Simulatiபைடு நூலகம்n vs. Formal Verification
• Simulation vs. formal verification
RTL RTL
Gate Dynamic Simulation
Gate Formal Verification
Formal Verification –cont.
Programmable Language for ESL Design
• Use high level language to build
modules

C/C++ e Programmble Language System C SystemVerilog
Requirement of Simulation Environment

Dynamic & Static Verification Synthesis Design for Testing Place & Route Physical Checking/Extraction
Overview of EDA Companies and Tools
ESL Design
Formal Verification
• Use of analytical techniques to
prove that the “implementation” conforms to its “specification” • Faster than simulation • Finds tough corner case bugs that could be missed in simulation • Without the vectors, but design constraints


System-level design Pre-silicon embedded software design HW/SW co-design Architecture exploration Virtual prototyping Co-simulation/co-verification
people nor is it intended to turn people in automations • Tool development cannot operate independently from the development of design methodologies • Tools are not methods
time to time • Algorithm

While (Events in Current Time Slots) For-each Event

Evaluation Propagation Scheduling
Static Verification
• Formal Verification • Static Timing Analysis
• Tools have a shelf-life. Don’t try to
make them last forever.


It is impossible to develop “plug & Play” tools
Focus on methodologies
Outlines
• Introduction • ESL Design Tool • EDA for Cell-based Design
Logic Simulation
• Software to simulate circuit
behavior in virtual time (process events sequentially) • Cover Behavior, RTL and gates level digital circuit • Pros:
Overview of EDA Companies and Tools
Dynamic simulation & Static Verification
Verification Methodologies
• (Dynamic) Simulation •
Uses computer to simulate how the design behaves in response to input stimulus variations in real time (Static) Verification Investigates the design and Proves that its functionality is equivalent to the design specification Assures that its performance should meet the design requirement in all possible operating environment

Dynamic vs. Static Verification
• Dynamic simulation mimics the
physical behavior


• Static verification tends to validate the
design still works under all possible working conditions
including waveform relaxation and iterative method, failed to commercialize Fast SPICE simulation technology achieved commercial success until late 1990s Widely used for analog circuit design
Source: Synopsys Mini DAC04
Source: Synopsys
Design Technology Needs as Geometries Shrink – cont.
Tool, Automation and Methods
• Automation is not intended to replace