大学计算机组织与结构习题

前二章作业
1.计算机的四个基本功能（Functions）是什么？
2.在计算机的top-level structure view中，四个structural components 是什
么？
3.谁提出了store-program concept ?你能用汉语简单地描述这个存储程序的
概念吗？
4.CPU的英文全称是什么？汉语意义是什么？
5.ALU的英文全称是什么？汉语意义是什么？
6.V on Neumann 的IAS机的五大部件都是什么？
7.在第一章中我们认识到的四个结构性部件（第2题）与V on Neumann的
IAS机（第6题）中部件有本质差别吗？
8.Fundamental Computer Elements 有哪几个？它们与计算机的四个基本功
能的关系是什么？
9.Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？
10.本书的次标题和第二章第二节标题均为“Designing for
Performance”,Performance 主要指什么？Performance Balance的（balance）平衡要平衡什么？
11.本书作者将他要研究的范围局限在“desktop, workstation , server“中，它
们的中文名称是什么？各自的工作范围是什么？
Chapter 3Homework
1.PC means _________.
A. personal computer
B. programming controller
C. program counter
D. portable computer
2. PC holds _______________ .
A. address of next instruction
B. next instruction
C. address of operand
D. operand
3. At the end of fetch cycle, MAR holds _____.
A. address of instruction
B. instruction
C. address of operand
D. operand
4. Interrupt process steps are __________.
A. suspending , resuming , branching & processing
B. branching , suspending , processing & resuming
C. suspending , branching , processing & resuming
D. processing , branching , resuming & suspending
5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .
A. 0 to n-1
B. 1 to n
C. 0 to 2n-1
D. 1 to 2n
6.The length of the address code is 32 bits, so addressing range (or the range of address) is ________________.
A. 4G
B.from –2G to 2G
C.4G-1
D. from 1 to 4G
7.There are three kinds of BUSes. Which is not belong to them?
A. address bus
B. system bus
C. data bus
D. control bus
Questions
1.Translate the following terms (Note: function)
PC, MAR, MBR, IR, AC, bus, system bus, data bus , address bus , control bus , handler*, opcode, Bus arbitrate* , multiplexed bus* , interrupt, ISR, Instruction cycle , fetch cycle , execute cycle
(带“*”为选做题)
2.Page90 problems
3.1
What general categories of functions are specified by computer instruction?
3. Describe simply the operations of PC and IR in an instruction cycle.
4.Suppose the length of word is n-bit, describe simply operand(操作数) format and instruction format.
5. Describe simply the procedure of the interruption
6. Describe simply the types and functions of the BUS.
一：选择题
1.The computer memory system refers to _________
A.RAM
B.ROM
C.Main memory
D.Register , main memory, cache, external memory
2.If the word of memory is 16 bits, which the following answer is right ?
A.The address width is 16 bits
B.The address width is related with 16 bits
C.The address width is not related with 16 bits
D.The address width is not less than 16 bits
3.The characteristics of internal memory compared to external memory
A.Big capacity, high speed, low cost
B.Big capacity, low speed, high cost
C.small capacity, high speed, high cost
D.small capacity, high speed, low cost
4．On address mapping of cache, any block of main memory can be mapped to
any line of cache, it is ___________ .
A) Associative Mapping B) Direct Mapping
C) Set Associative Mapping D) Random Mapping
5. Cache’s write-through polity means write operation to main memory _______.
A)as well as to cache
B)only when the cache is replaced
C)when the difference between cache and main memory is found
D)only when direct mapping is used
6.Cache’s write-back polity means write operation to main memory ______________.
a)as well as to cache
b)only when the relative cache is replaced
c)when the difference between cache and main memory is found
d)only when using direct mapping
7. On address mapping of cache, the data in any block of main memory can be mapped to fixed line of cache, it is _________________.
associative mapping B) direct mapping
C)set associative mapping D) random mapping
8.On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is _________________.
associative mapping B) direct mapping
D)set associative mapping D) random mapping
二：计算题(from page 126)
Problem 4.1 , Problem 4.3 , Problem 4.4 , Problem 4.5 , , Problem 4.7, Problem 4.10
第五章作业
1.which type of memory is volatile?
A.ROM
B. E2PROM
C. RAM
D. flash memory
2.which type of memory has 6-transistor structure?
A. DRAM
B. SRAM
C. ROM
D. EPROM
ing hamming code, its purpose is of one-bit error.
A. detecting and correcting
B. detecting
C. correcting
D. none of all
4.Flash memory is .
A. read-only memory
B. read-mostly memory
C. read-write memory
D. volatile
5.Which answer about internal memory is not true?
A. RAM can be accessed at any time, but data would be lost when power down..
B. When accessing RAM, access time is non-relation with storage location.
C. In internal memory, data can’t be modified.
D. Each addressable location has a unique address.
Page161 Problems: 5.4 5.5 5.6 5.7 5.8
第六章作业
一、选择题
1. RAID levels_________make use of an independent access technique.
A. 2
B. 3
C. 4
D. all
2. In RAID 4, to calculate the new parity, involves _________reads.
A. one
B. two
C. three
D.four
3. During a read/write operation, the head is ___________
A. moving
B. stationary
C. rotating
D. above all
4. On a movable head system, the time it takes to position the head at the track is know as______.
A. seek time
B. rotational delay
C. access time
D. transfer time
5. RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.
A. parity
B. user data
C. OS
D. anyone
6. Recording and retrieval via _________called a head
A. conductive coil
B. aluminium
C. glass
D. Magnetic field
7.In Winchester disk track format, _________is a unique identifier or address used to locate a particular sector.
A. SYNCH
B. Gap
C. ID field
D. Data field
8. Data are transferred to and from the disk in ________.
A. track
B. sector
C. gap
D. cylinder
9. In _________, each logical strip is mapped to two separate physical disk.
A. RAID 1
B. RAID 2
C. RAID 3
D. RAID 4
10. With _________, the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.
A. RAID 1
B. RAID 2
C. RAID 3
D. RAID 4
11. The write-once read-many CD, known as ________.
A. CD-ROM
B. CD-R
C. CD-R/W
D. DVD
二、How are data written onto a magnetic disk?
三、In the context of RAID, what is the distinction between parallel access and independent access?
Homework in Chapter 7
1.“When the CPU issues a command to the I/O module, it must wait until the I/O
operation is complete”. It is programmed I/O , the word “wait”means ___________________.
a. the CPU stops and does nothing
b. the CPU does something else
c. the CPU periodically reads & checks the status of I/O module
d. the CPU wait the Interrupt Request Signal
2.See Figure 7.7. To save (PSW & PC) and remainder onto stack, why the
operations of restore them is reversed? Because the operations of stack are ________________.
a. first in first out
b. random
c. last in first out
d. sequenced
ing stack to save PC and remainder, the reason is ____________________ .
a.some information needed for resuming the current program at the point of
interrupt
b.when interrupt occurs, the instruction is not executed over, so the instruction
at the point of interrupt must be executed once again
c.the stack must get some information for LIFO
d.the start address of ISR must transfer by stack
4.The signals of interrupt request and acknowledgement exchange between CPU
and requesting I/O module. The reason of CPU’s acknowledgement is ________________
a.to let the I/O module remove request signal
b. to let CPU get the vector
from data bus
c.both a & b
d. other aims
5.In DMA , the DMA module takes over the operations of data transferring from
CPU, it means _________________________
a.the DMA module can fetch and execute instructions like CPU does
b.the DMA module can control the bus to transfer data to or from memory
using stealing cycle technique
c.the DMA module and CPU work together(co-operate) to transfer data into or
from memory
d.when DMA module get ready, it issues interrupt request signal to CPU for
getting interrupt service
6.Transfer data with I/O modules, 3 types of techniques can be used. Which one is
not belong them?
a. Interrupt-driven I/O
b. programmed I/O
c. direct I/O access
d. DMA
7.Think 2 types of different data transferring, to input a word from keyboard and to
output a data block of some sectors to harddisk. The best choice is to use ___________.
a. interrupt-driven I/O and DMA
b. DMA and programmed I/O C. both interrupt-driven I/Os d. both DMAs
paring with interrupt-driven I/O, DMA further raises the usage rate of CPU
operations, because __________
a. it isn’t necessary for CPU to save & restore scene
b. it isn’t necessary for CPU to intervene the dada transfer
c. it isn’t necessary for CPU to read & check status repeatedly
d. both a and b
9.Simply script the all actions when using Interrupt-driven I/O technique to
transferring data with I/O module.
(please insert the “vector “at step3 & step5)
10.See Figure 7.7 & 7.8. Redraw figure 7.8, and mark the sequence number
according to Figure 7.7, to indicate the sequence of the information flowing.
11. According to DMA technique, write all information of CPU sending to DMA module, and write at which time the DMA module issues interrupt request signal to CPU and why the INTR is issued ?.
Chapter9 homework
1.Suppose bit long of two’s complement is 5 bits, which arithmetic operation brings OVERFLOW?
A. 5+8
B. (-8)+(-8)
C. 4-(-12)
D.15-7
2.Overflow occurs sometime in ______arithmetic operation.
A. add
B. subtract
C. add and subtract
D. multiply
3. In twos complement, two positive integers are added, when does overflow occurs?
A. There is a carry
B. Sign bit is 1
C. There is a carry, and sign bit is 0
D. Can’t determine
4. An 8-bit twos complement 1001 0011 is changed to a 16-bit that equal to____.
A.1000 0000 1001 0011
B. 0000 0000 1001 0011
C.1111 1111 1001 0011
D.1111 1111 0110 1101 11
5. An 8-bit twos complement 0001 0011 is changed to a 16-bit that equal to____.
A. 1000 0000 1001 0011
B. 0000 0000 0001 0011
C. 1111 1111 0001 0011
D. 1111 1111 1110 1101
6.Booth’s algorithm is used for Twos complement ______.
A. addition
B. subtraction
C. multiplication
D. division
7. In floating-point arithmetic, addition can divide to 4 steps: ______.
A. load first operand, add second operand, check overflow and store result
B. compare exponent, shift significand, add significands and normalize
C. fetch instruction, indirectly address operand, execute instruction and interrupt
D. process scheduling states: create, get ready, is running and is blocked
8. In floating-point arithmetic, multiplication can divide to 4 steps: ______.
A. load first operand, add second operand, check overflow and store result
B. fetch instruction, indirectly address operand, execute instruction and interrupt
C. process scheduling states: create, get ready, is running and is blocked
D. check for zero, add exponents, multiply significands, normalize, and round.
9.The main functions of ALU are?
A. Logic
B. Arithmetic
C. Logic and arithmetic
D. Only addition
10. Which is true?
A. Subtraction can not be finished by adder and complement circuits in ALU
B. Carry and overflow are not same
C.In twos complement, the negation of an integer can be formed with the
following rules: bitwise not (excluding the sign bit), and add 1.
D. In twos complement, addition is normal binary addition, but monitor sign bit for
overflow
Page326：9.4, 9.5 and 9.7(其中9.4选作)
To prove: in twos complement, sign-extension rule (converting between different bit length) and negation rule ( (-X)补= X补+ 1).
Chapter 10 and Chapter 11
1: In instruction, the number of addresses is 0, the operand(s)’address is implied, which is(are) in_______.
A. accumulator
B. program counter
C. top of stack
D. any register
2: Which the following addressing mode can achieve the target of branch in program?
A.Direct addressing mode
B.Register addressing mode
C.Base-register addressing mode
D.Relative addressing mode （有问题）
3: In index-register addressing mode , the address of operand is equal to
A.The content of base-register plus displacement
B.The content of index-register plus displacement
C.The content of program counter plus displacement
D.The content of AC plus displacement
4: The address of operand is in the instruction, it is_________ ?
A.Direct addressing mode
B.Register indirect addressing mode
C.Stack addressing mode
D.Displacement addressing mode
5: Which the following is not the area that the source and result operands can be stored in ?
A.Main or virtual memory
B.CPU register
C.I/O device
D.Instruction
6: Compared with indirect addressing mode , the advantage of register indirect addressing mode is
rge address space
B.Multiple memory reference
C.Limit address space
D.Less memory access
7:With base-register ADDRESSING , the ______________ register can be used.
A. BASE
B. INDEX
C. PC
D. ANY
8:The disadvantage of INDIRECT ADDRESSING is ____________.
A. large addressing range
B. no memory access
C. more memory access
D. large value range
9:Which is not an advantage with REGISTER INDIRECT?
A. just one times of operand’s access
B. large memory space
C. large value range
D. no memory reference
10:The REGISTER ADDRESSING is very fast, but it has _________________.
A. very less value range
B. very less address space
C. more memory access
D. very complex address’ calculating
11:The disadvantage of IMMEDIATE ADDRESSING is ___________.
A. limited address range
B. more memory access
C. limit value range
D. less memory access
12:In instruction, the number of addresses is 2, one address does double duty both _______________.
A. a result and the address of next instruction
B.an operand and a result
C.an operand and the address of next instruction
D.two closed operands
13.In instruction, the number of addresses is 3, which are _______________.
A. two operands and one result
B. two operands and an address of next instruction
C. one operand, one result and an address of next instruction
D. two operands and an address of next instruction
14.The address is known as a type of data, because it is represented by __________.
A. a number of floating point
B. a signed integer
C. an unsigned integer
D. a number of hexadecimal
15.Which is not a feature of Pentium .
A. complex and flex addressing
B. abundant instruction set
C. simple format and fixed instruction length
D. strong support to high language
16. Which is not a feature of Power PC .
A. less and simple addressing mode
B. basic and simple instruction set
C. variable instruction length and complex format
D. strong support to high language
Chapter 12 and Chapter 18
1. After the information flow of fetch subcycle, the content of MBR is_____________.
A.oprand
B.address of instruction
C. instruction
D. address of operand
2. After the information flow of instruction subcycle, the content of MBR is_____________.
A.oprand
B.address of instruction
C. instruction
D. address of operand
3. The worse factor that limits the performance of instruction pipeline is _________________.
A.conditional branch delaying the operation of target address
B. the stage number of pipeline c an’t exceed 6
C. two’s complement arithmetic too complex
D. general purpose registers too few
4.The most factor to affect instruction pipeline effectiveness is __________.
A. The number of stages
B. the number of instruction
C. the conditional branch instruction
D. the number of pipelines
5. RISC rejects ______.
A. few, simple addressing modes
B. a limited and simple instruction set
C. few, simple instruction formats
D. a few number of general purpose registers
6. RISC rejects ______.
A.a large number of general-purpose registers
B. indirect addressing
C. a single instruction size
D. a small number of addressing mode
7. Which is NOT a characteristic of RISC processor.
A. a highly optimized pipeline.
B. Register to register
operations
C. a large number of general-purpose registers
D. a complexed instruction
format
8.Control unit use some input signals to produce control signals that open the gates
of information paths and let the micro-operations implement. Which is NOT the input signals of control unit/
A.clock and flags
B.instruction register
C.interrupt request signal
D.memory read or write
9.Control unit use some output signals to cause some operations. Which is not
included in the output signals?
A.signals that cause data movement
B.signals that a ctivate specific functions(e.g. add/sub/…)
C.flags
D.read or write or acknowledgement
10. Symmetric Multi-Processor (SMP) system is tightly coupled by _______.
A. high-speed data-link and distributed memory
B. shared RAIDs and high-speed data-link
C. distributed caches and shared memory
D. interconnect network and distributed memory
11. The SMP means __________.
A.Sharing Memory Processes
B.Split Memory to Parts
D.Stack and Memory Pointer D.Symmetric Multi-Processo r
12.The “MESI” means states of ____________ .
A.Modified, Exclusive, Stored and Inclusive
B.Modified, Expected, Shared and Interrupted
C.Modified, Exclusive, Shared and Invalid
D.Moved, Exchanged, Shared and Invalid
13.The protocol “MESI” is also called __________.
A. write back policy
B. write-update protocol
C. write-invalidate protocol
D. write through policy
Chapter 12
1.Which register is user –visible but is not directly operated in 8086 ?
A. DS
B. SP
C. IP
D. BP
2.The indirect sub-cycle is occurred _____________ ?
A. before fetch sub-cycle
B. after execute sub-cycle
C. after interrupt sub-cycle
D. after fetch sub-cycle and before execute sub-cycle
3.Within indirect sub-cycle , the thing the CPU must do is ______________?
A. fetch operand or store result
B. fetch operand’s address from memory
C. fetch next instruction from memory
D. nothing
4.In general, which register is used for relative addressing ---- the content in
this register plus the A supplied by instruction to make a target address in branch or loop instructions.
A. SP
B. IR
C. BR
D. PC
5.The Memory Address Register connects to ____________ BUS .
A. system
B. address
C. data
D. control
6.The Memory Buffer Register links to ________ BUS.
A. system
B. address
C. data
D. control
7.After Indirect cycle , there is a ______________ cycle .
A. Fetch
B. Indirect
C. Execute
D. Interrupt
8.The Interrupt cycle is __________ ______ Execute cycle .
A. always after
B. never after
C. sometime after
D. maybe before
9.The correct cycle sequence is _________________ .
A. Fetch , Indirect , Execute and Interrupt
B. Fetch , Execute , Indirect and Interrupt
C. Fetch , Indirect , Interrupt and Execute
D. Indirect , Fetch , Execute and Interrup
10.The aim of the indirect cycle is to get __________________.
A. an operand
B. an instruction
C. an address of an instruction
D. an address of an operand
11.Which is not in the ALU ?
A. shifter
B. adder
C. complementer
D. accumulator
12.The registers in the CPU is divided _____registers and ________registers .
A. general purpose , user-visible
B. user-visible , control and status
C. data , address
D. general purpose , control and status
13.The Base register is a(n) __________ register in 8086.
A. general purpose
B. data
C. address
D. control
14.The Instruction Pointer is a(n) __________ register in 8086.
A. general purpose
B. data
C. address
D. control
15.The Index register is a(n) __________ register in 8086.
A. general purpose
B. data
C. address
D. control
16.The Stack Pointer is a(n) __________ register in 8086.
A. general purpose
B. data
C. address
D. control
17.The Accumulator is a(n) __________ register in 8086.
A. general purpose
B. data
C. address
D. control
18.The Programming Status W ord is a(n) __________ register .
A. general purpose
B. data
C. address
D. control
Show all the micro-operations and control signals for the following instruction:
1. ADD AX, X; —The contents of AC adds the contents of location X, result is stored to AC.
2. MOV AX, [X];
—Operand pointed by the content of location X is moved to AX, that means ((X))->AX
—[ ] means indirect addressing.
3. ADD AX, [BX];
—Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX
—[ ] means register indirect addressing.
4. JZ NEXT1; —If (ZF)=0,then jump to (PC)+ NEXT1.
5. CALL X; —Call x function, save return address on the top of stack.
6. RETURN; —From top of stack return to PC.。