verilog的串口发送程序例程

`include "uart_tx.v"
module licheng(clk,,rst_n,rs232_tx);
input clk; //时钟信号50M
input rst_n; //复位信号,低有效
output rs232_tx; //数据输出信号
wire clk_bps1;
speed_select_tx speed_tx( //数据发送波特率控制模块
.clk(clk),
.rst_n(rst_n),
.clk_bps(clk_bps1)
);
uart_tx uart_tx(
.clk(clk),
.rst_n(rst_n),
.clk_bps(clk_bps1),
.rs232_tx(rs232_tx)
);
endmodule
//=================================波特率产生模块=====================================
module speed_select_tx(clk,rst_n,clk_bps);//波特率设定
input clk; //50M时钟
input rst_n; //复位信号
output clk_bps; //接收数据中间采样点,
reg[12:0] cnt;//分频计数器
reg clk_bps_r;//波特率时钟寄存器
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt<=13'd0;
else if(cnt==5207)
cnt<=13'd0;
else
cnt<=cnt+1'b1;//波特率时钟启动
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
clk_bps_r<=1'b0;
else if(cnt== 2603)//当波特率计数到一半时,进行采样存储
clk_bps_r<=1'b1;
else
clk_bps_r<=1'b0;
end
assign clk_bps = clk_bps_r;//将采样数据输出给uart_tx模块endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////// module uart_tx(
clk,
rst_n,
clk_bps,
rs232_tx
);
input clk;
input rst_n;
input clk_bps;//中间采样点
output rs232_tx;//发送数据信号
reg [7:0]rx_data;
reg tx_en;//发送信号使能,高有效
reg [3:0] num;
initial begin
rx_data=8'b11111111;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_en <= 1'b0;
// num<=0;
end
else begin
if(num==4'd11) begin
tx_en <= 1'b0;
end
else
begin
tx_en <= 1'b1;
end
end
end
reg rs232_tx_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
num<=4'd0;
rs232_tx_r <= 1'b1;
end
else begin
if(tx_en) begin
if(clk_bps) begin
num<=num+1'b1;
case(num)
4'd0: rs232_tx_r <= 1'b0;//起始位
4'd1: rs232_tx_r <= rx_data[0];//数据位开始
4'd2: rs232_tx_r <= rx_data[1];
4'd3: rs232_tx_r <= rx_data[2];
4'd4: rs232_tx_r <= rx_data[3];
4'd5: rs232_tx_r <=rx_data[4];
4'd6: rs232_tx_r <= rx_data[5];
4'd7: rs232_tx_r <= rx_data[6];
4'd8: rs232_tx_r <= rx_data[7];
4'd9: rs232_tx_r <= 1'b1;//数据结束位,1位
default: rs232_tx_r <= 1'b1;
endcase
end
end
else
num<=4'd0;//发送完成,复位
end
end
assign rs232_tx =rs232_tx_r; endmodule。