An extended fault-tolerant link-state routing protocol

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基于MRAS的无直流母线电压传感器PMSM滑模控制

基于MRAS的无直流母线电压传感器PMSM滑模控制常海赐;滕青芳;靳宇星【摘要】针对永磁同步电机直流母线电压传感器故障的问题，提出一种无直流母线电压传感器的永磁同步电机滑模控制策略。

设计了基于自适应技术的模型参考自适应观测器，以精确估计直流母线电压值，从而保证电机正常运行，利用滑模控制技术，设计了积分滑模面，以保证电机转速、直轴、交轴电流能够快速收敛到给定值。

同时采用连续幂次函数设计滑模控制律，消除了滑模抖振。

仿真结果表明，所设计的直流母线电压观测器能够精确观测直流母线电压值，当直流母线电压传感器故障时亦能够保证系统的正常运行，且滑模控制器能够使转速、电流更快的跟随给定值，使系统具有更强的鲁棒性。

%In view of the fault of DC bus voltage sensor of the permanent magnet synchronous mo-tor (PMSM),the sliding mode control strategy of PMSM for DC bus voltage sensor is proposed. A model reference adaptive observer is designed to exactly estimate DC bus voltage and to ensure the normal operation of the motor with adaptive techniques.By making use of the sliding mode control techniques,an integral sliding surface is designed to ensure that the motor speed,direct-axis and quadrature-axis current can quickly converge to the given value.At the same time,the control law is designed by using the continuous power function to eliminate the chattering of slid-ing mode.The simulation results show that the designed DC bus voltage observer can accurately observe DC bus voltage value to guarantee the normal operation of the system when DC bus volt-age sensor is fault.The sliding mode controllercan make the rotating speed and current follow the given value faster,and make the system more robust.【期刊名称】《兰州交通大学学报》【年(卷),期】2016(035)006【总页数】7页(P76-82)【关键词】永磁同步电机;直流母线电压;模型参考自适应观测器;滑模控制【作者】常海赐;滕青芳;靳宇星【作者单位】兰州交通大学自动化与电气工程学院，甘肃兰州 730070;兰州交通大学自动化与电气工程学院，甘肃兰州 730070;兰州交通大学自动化与电气工程学院，甘肃兰州 730070【正文语种】中文【中图分类】TM351永磁同步电机（permanent magnet synchronous motor，PMSM）因其结构简单、高效率、高功率密度和形状、尺寸灵活多样等突出优点，在工业、交通、军事等领域被广泛的应用.对于一个典型的电压源逆变器驱动PMSM控制系统而言，需要一个直流母线电压传感器来传递直流母线信息.通过传感器检测直流母线电压信息，不仅增加了成本和体积，而且当直流母线电压传感器出现故障时控制系统无法精确获取直流母线电压值，进而损害系统的可控性［1－3］.针对上述问题，有两种容错方案，即硬件冗余法和解析冗余法［4－6］.硬件冗余即增加冗余传感器法，这样既增加生产成本，也使系统体积更加庞大，使系统结构复杂化.故硬件冗余法较少采用；解析冗余则基于系统数学模型，通过软件算法实现电机直流母线电压辨识，具有编程灵活、功能强大、易于实现和成本低廉等优点，因此是电机容错系统的首选容错方案［7－9］.PMSM直流母线电压的容错方案，国外学者研究较多.文献［10］采用直接替换法，当直流母线电压传感器出现故障时，直接采用额定直流母线电压值代替实际值，以保证系统的持续运行，该方法局限于直流母线电压恒定的系统，不能适用于母线电压随时间波动的系统，比如混合动力电动汽车；文献［11］采用自适应磁链观测法，提出了一种在线直流母线电压观测器，但因设计复杂而难于实现，且该方法只能针对感应电机系统.文献［12］针对电力牵引系统的单相PWM整流器，利用电网侧已知信息设计了龙贝格状态观测器以重构直流母线电压，因其需要得到电网侧的实时信息，具有一定的局限性.基于此，设计一个简单有效的直流母线电压观测器来实时观测直流母线电压值很有必要.针对永磁同步电机控制系统采用自适应技术，设计了模型参考自适应（model reference adaptive system，MRAS）观测器对直流母线电压进行实时在线观测.传统的矢量控制一般采用PI控制器作为转速和电流调节器，在一定条件下它能起调节作用，但当系统参数变化或存在外部干扰时（例如，模型不确定、参数摄动、摩擦阻力和负载扰动等），则难以保证电机系统获得满意性能［13－15］.为了改善控制系统的的鲁棒性，一些非线性控制方法相继被提出.其中滑模（sliding mode，SM）变结构控制因为对PMSM系统参数时变和外部扰动的强鲁棒性，成为国内外的研究热点［16－18］.滑模控制无需精确的数学模型，可根据当前的系统状态构造滑模面，通过控制量的切换作用，迫使系统沿着既定的“滑动模态”运动.具有响应速度快、对外界参数不敏感、易于实现等优点［19］，在永磁同步电机控制领域被广泛使用.为提高PMSM控制系统的响应速度和抗负载扰动能力，本文根据矢量控制原理，设计了积分滑模控制器（integral sliding mode controller，ISMC），使得电机转速、直轴电流、交轴电流能快速收敛到给定值.此外采用连续幂次函数代替传统开关函数，以消除抖振、保证系统的稳定性.假设磁路不饱和，空间磁场呈正弦分布，不计涡流和磁滞损耗，PMSM定子电流方程在dq两相旋转坐标系下可表示为式中：ud，uq，id，iq，Ld，Lq分别为定子电压、电流、电感在dq轴的分量；Rs为定子电阻；ψf为永磁体磁链；np为磁极对数；wr为转子机械角速度. PMSM机械转动方程为式中：J为转动惯量；T1为负载转矩；Bm为阻力.电磁转矩可以表示为对于隐极式永磁同步电机而言，由于Ld＝Lq＝L，因此，电磁转矩可表示为Te＝1.5npψfiq.针对三相六开关电压源逆变器驱动PMSM控制系统，基于模型参考自适应观测器和滑模变结构控制理论，提出了PMSM无直流母线电压传感器积分滑模控制策略.系统结构框图如图1所示，该系统主要包括：模型参考自适应观测器、转速环积分滑模控制器、q轴电流积分滑模控制器、d轴电流积分滑模控制器、SVPWM模块及电压源逆变器等.2.1 模型参考自适应观测器设计对于由电压源型逆变器驱动的三相永磁同步电机，定子相电压是由施加在功率开关门极上的PWM信号和直流母线电压所决定的.因此定子电压幅值可近似的表示为式中：ma为调制系数；Vdc为直流母线电压；γ是由PWM开关方式决定的.当直流母线电压传感器发生故障，直流母线电压值无法获得的情况下，可将定子电压值近似为式中：Vdc（nom）为给定的直流母线电压值；若定义α＝Vdc／Vdc（nom），则us＝αu.通过准确观测α就可以得到真正的直流母线电压值.1）参考模型由式（1）可得模型自适应观测器的参考模型为式中：2）可调模型考虑直流母线电压是未知的，模型参考自适应观测器的可调模型表示（表示的估计值）如下：式中为反馈项，kv为反馈系数.对参考模型式（6）和可调模型式（7）做差，得到两个模型的输出之差（，表示的误差值）如式（8）所示.将式（8）写成向量形式如下：式中：为了得到使观测器稳定的自适应律，选择如下Lyapunov函数：式中：kα为正增益.对式（10）求导可得为保证误差系统式（8）稳定，需满足V1≤0.为此可做如下假设：则因为直流母线电压的变化率远小于定子电流变化率，可以认为因此可以得到从而得到的自适应律为为了提高直流母线电压的估计精度，本文采用基于比例积分作用的模型参考自适应观测器：式中：kp，ki分别为比例和积分增益.则Vdc的估计值可由得到.由以上分析可构造出基于MRAS的PMSM直流母线电压观测器结构框图，如图2所示.2.2 积分滑模控制器设计2.2.1 电机转速控制器设计转速控制器的设计目的就是寻找合适控制律，使得电机实际转速ωr能够快速准确地跟随给定转速，因此定义速度误差为eω＝－ωr.为提高电机转速的响应速度和跟踪精度，设计如下积分滑模面：式中：c1为常数；t→∞.根据式（2）和式（3）可进一步得到为避免滑模控制中由于开关项sign（·）函数引起的高频抖振现象，通常的做法是采用饱和函数sat（·）函数代替sign（·）函数，但是当系统进入稳态后，抖振现象依然存在.为了彻底消除这种抖振现象，本文通过引入连续幂次函数fal（·）函数将滑模控制律设计为其中：η1为滑模正增益；连续幂次函数fal（·）的定义如下：其中：δ为滤波因子；ε为非线性因子；当ε∈（0，1）时式（16）具有小误差大增益，这种特性是传统的饱和函数sat（·）所不具备的.根据式（14）和式（15）可以得出转速积分滑模控制器的输出为根据以上各式可得出PMSM转速控制器结构框图，如图3所示.为验证以式（17）为输出时滑模控制器的稳定性，定义Lyapunov函数为对上式求导，并将式（13）和式（17）代入得当δ1＞0，ε1∈（0，1）时Lyapunov函数V2正定，且其导数≤0，因此当采用式（17）所示的滑模控制律时，系统满足Lyapunov稳定性条件.2.2.2 电机交、直轴电流控制器设计交、直轴电流控制器用于精确跟踪dq轴电流，因此将dq轴电流误差定义为其中分别为dq轴坐标系下的定子电流参考值，且＝0.采用和转速环一样的控制策略将滑模切换面设计为进一步可得到同转速环一样，为减小dq轴电流脉动采用连续幂次函数函数fal（·）将电流环滑模控制趋近律取为由式（20）和式（21）即可求得交、直轴电流的输出为稳定性证明，同转速环，略.为验证所设计系统的正确性和有效性，采用Matlab／Simulink／Simspace进行了仿真研究，所采用的PMSM各项参数如表1所列.仿真过程中采样时间设置为100μs，电机参考转速1 000r／min，带2N·m负载启动，直流母线电压参考值Vdc（nom）＝300V.转速滑模控制器的参数为：c1＝0.2，η1＝2 400，ε1＝0.5，δ＝0.1；电流滑模控制器参数为：c2＝c3＝0.01，η2＝η3＝500，ε2＝ε3＝0.5，δ2＝δ3＝0.1；直流母线电压MRAS观测器中PI 控制器参数选择为：kp＝0.01，ki＝0.02.图4至图7分别给出了系统的直流母线电压观测曲线图和电机转速、转矩以及dq 轴电流曲线图.从图4可以看出所设计的MRAS观测器能够快速、准确地估计出系统直流母线电压值.图5至图7可以看出基于积分滑模的转速控制器、电流控制器能够使系统具有良好的转速、转矩响应以及稳定的dq轴电流值.针对PMSM驱动系统中直流母线电压传感器故障的情况，本文采用MRAS技术设计了一种简单易于实现的MRAS直流母线电压观测器，利用已知的转速、定子电流等信息精确估算出了直流母线电压值，保证了永磁同步电机在直流母线电压传感器故障状态下的正常运行，提高了PMSM的运行可靠性；采用积分滑模控制器作为系统的转速和电流控制器，提高了系统的响应速度，减小了转矩和电流脉动，将连续幂次函数fal（.）函数引入滑模控制律中，有效的消除了滑模抖振，提高了滑模控制器的控制性能.仿真结果表明了本文控制策略的正确性和实用性.【相关文献】［1］ Foo G H B，Zhang X，Vilathgamuwa D M.A sensor fault detection and isolation method in interior permanent－magnet synchronous motor drives based on an extended kalman filter［J］.IEEE Transactions on Industrial Electronics，2013，60（8）：3485－3495.［2］ Zakzouk N E，Abdelsalam A K，Helal A A，et al.DC－link voltage sensorless control technique for singlephase two－stage photovoltaic grid－connected system［C］／／IEEE International Energy Conference.Piscataway，NJ：IEEE Press，2014：58－64.［3］王本振，邓堪谊，于艳君，等.直流母线电压对载波频率成份法无位置传感器控制的影响分析［J］.微电机，2010，43（10）：10－12.［4］滕青芳，柏建勇，朱建国，等.基于滑模模型参考自适应观测器的无速度传感器三相永磁同步电机模型预测转矩控制［J］.控制理论与应用，2015，32（2）：150－161.［5］ Berriri H，Naouar M W，Slama－Belkhodja I.Easy and fast sensor fault detection and isolation algorithm for electrical drives［J］.IEEE Transactions on Power Electronics，2012，27（2）：490－499.［6］ Wallmark O，Harnefors L，Carlson O.Control algorithms for a fault－tolerant PMSM drive［J］.IEEE Transactions on Industrial Electronics，2007，54（4）：1973－1980. ［7］滕青芳，李国飞，朱建国，等.基于扩张状态观测器的无速度传感器容错逆变器驱动永磁同步电机系统自抗扰模型预测转矩控制［J］.控制理论与应用，2016，33（5）：676－684.［8］ Kim G S，Lee K B.Fault diagnosis and fault－tolerant control of a dc－link voltage sensor for PV inverters［C］／／International Power Electronics and Motion Control Conference.Piscataway，NJ：IEEE Press，2012：1408－1412.［9］滕青芳，左瑜君，柏建勇，等.基于MRAS观测器的无速度传感器永磁同步电机模型预测控制［J］.兰州交通大学学报，2014，33（4）：6－11.［10］ Jeong Y S，Sul S K，Schulz S E，et al.Fault detection and fault－tolerant control of interior permanent－magnet motor drive system for electric vehicle［J］.IEEE Transactions on Industry Applications，2005，3（1）：458－1463.［11］ Salmasi F R，Najafabadi T A，Jabehdar－Maralani P.An adaptive flux observer with online estimation of DC－link voltage and rotor resistance for VSI－based induction motors［J］.IEEE Transactions on Power E－lectronics，2010，25（5）：1310－1319. ［12］ Youssef A B，El Khil S K，Slama－Belkhodja I.State observer－based sensor fault detection and isolation，and fault tolerant control of a single－phase PWM rectifier for electric railway traction［J］.IEEE Transactions on Power Electronics，2013，28（12）：5842－5853.［13］王德贵.永磁同步电机调速系统的变参数PI控制［J］.伺服控制，2014（6）：39－41. ［14］ Tursini M，Parasiliti F，Zhang D.Real－time gain tuning of PI controllers for high－performance PMSM drives［J］.IEEE Transactions on Industry Applications，2002，38（4）：1018－1026.［15］鲁文其，胡育文，杜栩杨，等.永磁同步电机新型滑模观测器无传感器矢量控制调速系统［J］.中国电机工程学报，2010，30（33）：78－83.［16］茅靖峰，吴爱华，吴国庆，等.永磁同步电机幂次变速趋近律积分滑模控制［J］.电气传动，2014（6）：50－53.［17］郑剑飞，冯勇，陆启良.永磁同步电机的高阶终端滑模控制方法［J］.控制理论与应用，2009，26（6）：697－700.［18］张晓光，赵克，孙力.永磁同步电动机混合非奇异终端滑模变结构控制［J］.中国电机工程学报，2011（27）：116－122.［19］刘金琨，孙富春.滑模变结构控制理论及其算法研究与进展［J］.控制理论与应用，2007，24（3）：407－418.。

Fault-Tolerant Systems 11.1. What is a Fault

11Fault-Tolerant Systems11.1. What is a Fault ?Any action that does not conform to the given specification of a system is viewed as a fault. Historically, models of failures have been linked with the users level of interaction with a system. A VLSI designer may focus on stuck-at-0 and stuck-at-1 faults only, where the output of a gate is permanently stuck to either a 0 or a 1 regardless of input variations. A system level hardware designer, on the other hand, may be ready to view a failure as any arbitrary or erroneous behavior of a module as a whole. A drop in the power supply voltage, or radio interferences due to a lightning, or a cosmic shower, often causes transient failures that may temporarily perturb the system state without causing any permanent damage to the system. Finally, even if hardware does not fail, software may fail due to improper or unexpected changes in the specifications of the system. Before any discussion about how to tolerate such faults, it is important to present a proper characterization of the various kinds of faults that can occur in a system.11.2. Classification of FaultsOur view of a distributed system is essentially a process-level view, so we begin with the description of some important types of failures that are visible at the process level. Note that each type of failure at any level may be caused by a failure at some lower level of abstraction. Thus, a process may cease to produce an output when a wire in the circuit breaks. A complete characterization of the relationship between faults at different levels is beyond the scope of our discussion. Our classification of failures is as follows:Halting Failure. When a process that is expected to produce one or more messages, or change the values of some process variables, ceases to do so on a permanent basis, a halting failure occurs. Note that this is an irreversible change. Halting failures are also known as crash failures.In a variation of this model, halting failures are treated as reversible, i.e. a process may play dead for a finite period of time, and then resume operation. This includes thecase in which the faulty process is repaired and restarted after some time. Such failures are called napping failuresByzantine Failure. Byzantine failures correspond to completely arbitrary failure patterns, and is the weakest of all the failure models. As an example, let N.i denote the set of neighbors of a process i. Assume that i is expected to send a value x to every process in N.i. If process i does not send the intended value x to each of its neighbors, then the failure is called a byzantine failure. The following are some examples of inconsistent behaviors possibly caused by byzantine failure:¥ Two distinct neighbors j and k receive values x and y, where x ≠ y.¥ Every neighbor receives a value z where z ≠ x.¥ One or more neighbors do not receive any value from process i.Some of the possible causes of byzantine failures are¥ The total or partial breakdown of a link joining i with one of its neighbors ¥ Software problems in process i¥ Hardware synchronization problems - assume that every neighbor is connected to the same bus, and trying to read the same copy sent out by i, but since the clocksare not synchronized, they may not read the value x exactly at the same time. If x is a time-sensitive variable, then different neighbors of i may receive differentvalues from process i.¥ Malicious action by process i.Transient Failure. Certain types of fault actions have temporary effects on the global state of a system. Such failures perturb the global state in an arbitrary way, but the effect of the agent inducing this failure is not perceived thereafter. This is called a transient failure.A special kind of transient failure applicable to message-passing models only is the omission failure. Consider a transmitter process sending a sequence of messages to a receiver process. If the receiver does not receive some of the messages sent by the transmitter, then it is an omission failure. In real life, this can be caused either by transmitter malfunction, or by the loss of messages in transit.Software Failure. Software does not fade or erode with time. Assume that a system running under the control of a program S is producing intended results. If the system suddenly fails to do so even if there is no hardware failure, there is a problem withspecifications. If {P}S{Q} is a triple in programming logic, and the precondition P is inadvertently weakened, then there is no guarantee that the postcondition Q will always hold!The situation can be explained using the example of a pop machine. This pop machine delivers a can of pop, when a user inserts 50cents into the machine. The machine is designed to accept quarters and dimes only. If an uninformed user tries to buy a can of pop with ten nickels, then the machine will fail to deliver the pop, since the machine is not designed to accept nickels! This malfunction may be viewed as a software failure.Temporal Failure. Real time systems require actions to be completed within a specific amount of time. When this deadline is not met, a temporal failure occurs.11.3. Specification of FaultsWe present here a general model for specifying an arbitrary type of failure. This model was proposed by Arora and Gouda in [AG93]. A system description consists of (i) a set of specified actions S representing the fault-free system, and (ii) a set of fault actions F. The actions of F can be expressed using notations similar to those used in S.The faulty system consists of the union of all the actions in both S and F, and will be denoted by S F. An example of such a specification follows.Assume that a system, in absence of any fault, sends out the message "a" infinitely often (i.e. the output is an infinite sequence aaaaa...). However, a failure "occasionally" causes a message to change from "a" to "b". This description can be translated to the following specification1 :define x : booleana , b: messageinitially x = true;S::do x → send a odF::do true → send b odWith a weakly fair scheduler, the difference between the behaviors of S and S F becomes perceptible to the outside world.1 This specification is not unique. Many other specifications are possible.A halting failure of S can be represented using the following specification for F:F :: do true →x := false odAfter this fault action is executed, the system ceases to produce an output -- a condition that cannot be reversed using the actions in S or F.Now, consider a system that receives a message msg, and forwards it to each of its N neighbors {0, 1, 2, ..., N-1}. This can be specified byS::initially j = 0, flag = falsedo¬flag ∧ msg = a→x := a; flag := true(j < N) ∧ flag→send x to j; j := j+1j = N→j := 0; flag := falseodThe following fault action on the above system specifies a form of byzantine failure, since it can cause the process to send a to some neighbors, and send b to some others.F::do flag→x := b od{b ≠ a}Under the broad class of byzantine failures, specific fault behaviors can be modeled using appropriate specifications. Consider the following example. Here, the fault-free system executes a non-terminating program that sends out the integer sequence 0,1,2,0,1,2 .... Once the fault actions are executed, the faulty system changes every third integer from 2 to 9.define k : integer; {k is the body of a message}x : boolean;initially k = 0; x = true;S::do k < 2 →send k; k := k+1x ∧ (k = 2)→send k; k := k+1k ≥ 3 →k := 0;odF::do x→¬ x¬ x ∧ (k = 2) →send 9; k:= k+1odNo separate specification is necessary for software failures -- it is adequate to explicitly write down the preconditions and the postconditions of the fault-free system, and observe that these hold for the application at hand.Finally, temporal failures are detected using a special predicate "timeout", which becomes true when an event does not take place within a predefined deadline. An example is given below: Consider a process i broadcasting a message every 60 seconds to all of its neighbors. Assume that the message propagation delay is negligibly small. If process j does not receive any message from process i within 62 seconds (i.e., it keeps a small allowance before passing a verdict), it permanently sets a boolean flag f.i. indicating that process i has undergone a termporal failure. This can be specified asdefine f.i: booleaninitially f.i = falseS::¬ f.i ∧ message received from process i → skipF::timeout (i,j)→ f.i := trueHere, the truth of the predicate timeout (i,j) implies that the deadline has elapsed on the arrival of the message from j to i. It is quite possible that process i did not undergo a halting failure, but slowed down due to unknown reasons. The exact mechanism for asserting the predicate timeout (i,j) is as follows: Process j has a local variable called timer that is initialized to the value of the deadline T. After this, timer is decremented with every tick of the local clock. If (timer = 0), then the predicate timeout is asserted, otherwise, after the event occurs, timer is reset to T and the next countdown begins.Note that the correct use of timeout is based on the existence of synchronized clocks. If the local clocks of the processes i and j are not synchronized (at least approximately), then they can drift arbitrarily -- as a result, there will no correlation between i's measure of 60 seconds and j's measure of 70 seconds. In an extreme case, j's 62 seconds can be less than i's 60 seconds, so that even if process i sends a message every 60 seconds, process j will timeout and set f.i.11.4. Fault-Tolerant SystemsThe first step in designing a fault-tolerant system is to understand what is meant by tolerating a fault. There are three different concepts in the area of fault-tolerance:¥ Fault Masking¥ Fault Recovery¥ Graceful DegradationFault MaskingIn this case, the occurrence of faults does not have any visible effect in the eyes of an external observer. Let {P}S{Q} be a computation, and F represent the fault-actions.Then the system masks the actions of F iff wp(S F , Q) = P', and P ⇒ P'.Fault RecoveryEvery fault-tolerant system cannot mask failures. In such a cse, the faulty behavior will be visible in the eyes of an external observer. An important issue in such cases is the duration of the fault actions and the faulty behavior. Let S be a computation that satisfies the triple {P}S{Q}, and F denote the fault actions. Also, let R be a predicate representing the "weakest postcondition" in presence of failures. This implies {P}S F {R}, and intuitively R is the "worst-case result" produced by the faulty system. If R ⊆ Q , then the system is able to mask the actions of F . Otherwise, the fault is not of the masking type. However, if the failure is transient and the actions of F are no longer enabled following the corruption of the global state, then in some cases the system eventually recovers, and satisfies the postcondition Q . This is possible when R ⇒wp(S,Q). Fig. 11.1. illustrates the situation.timecompleteshere completeshereFig. 11.1. An illustration of fault recoverySystems that (i) guarantee recovery when started from an arbitrary initial state (i.e. P = true) and (ii) maintain the desired postcondition, are known as self-stabilizing systems.Graceful DegradationMany systems can neither mask, nor fully recover from the effect of failures. However, some of them exhibit a degraded behavior that falls short of the normal behavior, but is still "acceptable." The notion of acceptability is highly subjective, and is entirely dependent on the user running the application. Some examples of degraded behavior are as follows:1. Consider a taxi booth where customers call to order a taxi. Under normal conditions,(i) each customer ordering a taxi must eventually get it, and (ii) these requests must be serviced in the order in which they are received at the booth. In case of a failure, a degraded behavior which may be acceptable corresponds to the case when only condition(i) is satisfied.2. While routing a message between two points in a network, a program computes the shortest path. In the presence of a failure, if this program returns another path which is not the shortest path but one that is "marginally longer" than the shortest one, then this may be considered acceptable.3. A pop machine returns a can of soda when a customer inserts 50cents in quarters, dimes, or nickels. After a failure, if the machine refuses to accept dimes and nickels, but returns a can of soda only if the customer deposits two quarters, then it may be considered acceptable.Detection of FailuresThe implementation of fault-tolerance of any type requires a mechanism for detecting failures. This in turn depends on specific assumptions about the degree of synchronization like the existence of synchronized clocks, lower bound on the processor speed, or upper bound on message propagation delays, as described in Section 2.1.3. The transition from a fully synchronous to a fully asynchronous system is a gradual one, and it is possible to deal with a system that is only partially synchronous. The implementation of fault-tolerance depends on the degree of synchronization.As the first example, let us consider whether a halting failure can be detected in a message passing system. Without any assumption about synchronized clocks, or an upper bound of message propagation delays, or a lower bound of process execution speeds, it is impossible to detect a halting failure, because it is not feasible to distinguish between a crashed process, and a healthy process which is executing actions "very slowly." However, in a fully synchronous system, timeout can be used to detect halting failures.As another example, consider how omission failures can be detected. The problem is as hard as the detection of halting failures, unless the channels are FIFO. With a FIFO channel, a sender process i can attach a sequence number seq with every message m as described below:do true →send <seq, m>;seq := seq + 1odWhenever a receiver process j receives two consecutive messages whose sequence numbers are m and n, and n ≠ m+1, it suspects an omission failure.The detection of byzantine failures also requires a fully synchronous system. Several protocols for masking inconsistencies caused by byzantine failures are available in the published literature -- these are known as byzantine agreement protocols.In the following sections, we will present specific examples of implementing fault-tolerance with halting and omission failures. Byzantine agreement and self-stabilizing systems will be presented in subsequent chapters.11.5. Halting FailuresNext we present examples of two widely used methods for masking the effect of halting failures.Triple Modular redundancyIn synchronous systems, a widely used method of masking the effects of halting failures is the use of triple modular redundancy. Consider a process B that receives an input value x from a process A, computes the function y = f(x), and sends it to a third process C. If B fails by stopping, then C does not receive any value of y.Fig 11.2. Implementing fault-tolerance using Triple Modular RedundancyTo mask the effect of B's failure, process B is replaced by three processes B0, B1, and B2 as shown in Fig. 10.1. Even if one of these three processes undergoes a halting failure, process C still receives the correct value of f(x), as long as it computes the majority of the three incoming values. Note that when the majority is computed, the output of the faulty process can be substituted by an arbitrary default value. A generalization of this approach leads to n-modular redundancy that helps mask the halting failure of m or fewer processes, where n ≥ 2m+1.Atomic transactionsIn a distributed database system, let A be a composite object with components A.0, A.1, ..., A.n. Consider a transaction that assigns a new value x.i to each component A.i. We will represent this operation by A := x. The transaction A := x is called atomic, when "either all or none" of the assignments A.i := x.i are completed. Note that a halting failure can allow a fraction of these assignments to be completed, and violate the atomicity property.To make such a transaction look atomic in the face of crash failures, Lampson proposed the idea of stable storage. A stable storage maintains two copies of A (i.e two copies of every component A.i), and allows two operations update and inspect to access the components. Let us designate the two copies of A by A0 and A1 (Fig 11.3). Process P, which performs the update operation, updates each copy, stamps these updates with (i) the timestamp T, and (ii) a unique signature S called checksum, which is a function of x and T.Fig. 11.3 The model of a stable storage. P performs the update operationand Q performs the inspect operation{procedure update}1A0 := x;{copy 0 updated -- operation not necessarily atomic} 2T0 := time;{timestamp assigned to copy 0}3S0 := checksum (x, T0){signature assigned to copy 0}4A1 := x;{copy 1 updated -- operation not necessarily atomic} 5T1 := time;{timestamp assigned to copy 1}6S1 := checksum (x, T1){signature assigned to copy 1}Process Q, which performs the inspect operation, checks for both the copies, and based on the times of updates as well as the values of the checksums, chooses the correct version of A that satisfies the criterion of atomic update.{procedure inspect}A if S0 = checksum (A0, T0) ∧S1 = checksum (A1, T1) ∧T0 > T1→accept A0B S0 = checksum (A0, T0) ∧S1 = checksum (A1, T1) ∧T0 < T1→accept A0 or A1C S0 = checksum (A0, T0) ∧S1 ≠ checksum (A1, T1) →accept A0D S0 ≠ checksum (A0, T0) ∧S1 = checksum (A1, T1) →accept A1f iCase A corresponds to a failure between steps 3 and 4 of an update. Case B represents no failure -- so any one of the copies is acceptable. Case C indicates a failure between steps 1-3, and case D indicates a failure between steps 4-6. It is important to note that as long as A0 and A1 are properly initialized, and P fails by stopping at any point during steps 1-6 of the update operation, one of the guards A-D must be true for process Q.Stable storage is widely used in client-server models to survive crashes. The two copies A0 and A1 are maintained on two disks on two separate drives. Data can also be recovered when instead of a halting failure by process P, one of the two disks crashes.11.6 Omission FailuresOmission failures are usually caused by transient malfunctions of the channel. In the OSI model of a computer network, omission failures are typically handled either in the data-link layer or in the transport layer. The principle behind handling omission failures is to detect the disappearance of an expected message or an acknowledgement (using sequence numbers and timeouts), and then arrange for a retransmission. Due to the transient nature of this failure, it is assumed that if a message is sent "a large number of times", then it will eventually be received.A widely used transport layer protocol for handling omission failures is the sliding window protocol. This protocol works on a channel where message propagation delays have upper bounds. In the sliding window protocol, there are two processes, a sender process S and a receiver process R, connected by a pair of channels as shown in Fig.11.4. The channel is not a FIFO channel. Process S sends out a sequence of messages m[0], m[1], m[2], ...from an infinite tape, and process R, after receiving each message m[i], decides whether to accept it and forward it to the upper layers of protocol, and then sends an acknowledgement back to S. Both messages and acknowledgements may occasionally be lost or delayed, that is determined by timeouts and retransmissions. The goal of the sliding window protocol is to satisfy the following three crieria:W1.Every message sent out by S should eventually be received by R.W2. No message should be accepted and forwarded to the upper protocol layers more than once.W3. The receiving process R should always forward messages m[i] before m[i+1].Thus, if S sends out the sequence a b c d e ..., then from the persprective of process R, W1 rules out accepting this sequence as a c d e ..., W2 rules out the possibility of accepting it as a b b c c c d e ..., and W3 prevents it from being accepted as a c b d e ....An obvious solution is the so called stop-and-wait protocol. Process S will send one message m[i], and wait for its acknowledgement from R. If the message or the acknowledgement is lost, then m[i]is retransmitted. Otherwise, the next message m[i+1] is sent by S.Fig 11.4. Sliding window protocolThe approach is logically correct, but this restricted version suffers from poor throughput in as much as the sender has to wait for at least two round-trip delays before transmitting a new message. An obvious generalization is the sliding window protocol, that is based on the following scheme:¥The sender is allowed to continue the send action without receiving the acknowledgements of at most w messages (w > 0), where w is called thewindow size". If no acknowledgement to the previous w messages is receivedwithin an expected period of time, then the sender resends those w messages.¥ The receiver anticipates the sequence number j of the next incoming message. If the anticipated message is received, then R accepts it, sends the correspondingacknowledgement back to S, and increments j. Otherwise, R sends out anacknowledgement corresponding to the sequence number j-1 of the previousmessage accepted by it.It is important to note that both the messages and the acknowledgements have to include the sequence number which is an integral part of the decision making process. Thus the i th message will be sent out by S as (m[i], i), and the corresponding acknowledgement will be returned by R as (ack, i). The program is described below.program window;{program for process S}define next, last, w : integer;initially next = 0, last = -1, w > 0;and both channels are emptydo last < next ≤ last + w→send (m[next], next);next := next + 1(ack, j) is received→if j > last→ last := jj ≤ last→ skipf itimeout (r,s)→∀i: last < i ≤ last + w :: send (m[i]. i)od{program for process R}define j : integer;initially j = 0;do(m[next], next) is received→if j = next→accept the message;send (ack, j);j:= j+1j ≠ next→send (ack, j-1)fi;odTo demonstrate that this protocol satisfies the three criteria W1 - W3, we outline an inductive proof.Basis. Message m[0] is eventually accepted by R. To show this, note that if m[0]is lost in transit, then either the guard (j ≠next)is enabled for R, or no acknowledgement is returned, and (last = -1)holds. Messages are sent by S until (next = w-1), and the acknowledgements returned (if any) by R have no impact on the state of S. After this, the guard timeout is enabled for process S, and it sends m.0 through m[w-1] for a second round. In a finite number of rounds of retransmission, m.0 must reach R, the guard (j=next) is enabled, and m[0] is accepted. Furthermore, since j can only increase after a message is accepted, the condition (j = 0) cannot be asserted for a second time. So, m.0 is accepted exactly once.Inductive Step. Assume that R has accepted every message from m[0]through m[k] (k > 0), j = k+1, m[k+1] has already been transmitted by S, so the condition last < k+1 ≤ next holds. We need to show that eventually m[k+1] is accepted by R.If m[k+1] is lost in transit, then no guard is enabled for R. When the remaining messages in the current window are sent out by S, the acknowledgements (ack, k) returned by R do not cause S to increment the value of last beyond k.Eventually the guard timeout is enabled for process S, and it retransmits messages m[last+1] through m[last + w] -- this includes m[k+1]. In a finite number of rounds of retransmission, m[k+1] is received and accepted by R.Finally, for process R, the value of j never decreases. Therefore m[i] is always accepted before m[i+1]The Alternating Bit ProtocolThe alternating bit protocol is a special version of the sliding window protocol, for which w=1.A major hurdle in implementing the sliding window protocol described earlier is that, an arbitrarily large sequence number must accompany the body of the message. Accordingly, neither messages nor acknowledgements can be represented in bounded space. The alternating bit protocol avoids this problem by appending only a 1-bit sequence number to the body of the message. However, the scheme works only when the channels are FIFO. Accordingly, the alternating bit protocol is suitable for application in the data-link layer. The protocol is described below:program ABP;{program for process S}define sent, b : 0 or 1;next : integer;initially next = 0, sent = 1, b = 0and both channels are emptydo sent ≠b→send (m[next], b);next := next +1; sent := b(ack, j) is received →if j = b → b := 1-bj ≠ b →skipf itimeout (r,s)→send (m[next-1], b)od{program for process R}define j : 0 or 1;initially j = 0;do(m[next], b) is received →if j = b → accept the message;send (ack, j);j:= 1 - jj ≠ b → send (ack, 1-j)odWithout going through a formal proof, we demonstrate why the FIFO property of the channel is considered essential for the alternating bit protocol.Fig 11.5. A global state of the alternating bit protocol.Consider the global state of Fig 11.5 that was reached in the following way. m[0] was transmitted by S and accepted by R, but its achnowledgement (ack, 0) was delayed -- so S transmitted m[0]once more. When (ack, 0)finally reached S,it sent out m[1].Since the channel is not FIFO, assume that m[1] reached R before m[0]. This was accepted by R, and (ack,1) was sent back to S. On receipt of this (ack,1) S sent out m[2].Now m[0] with a tag 0 reaches R, and R accepts it, as it mistakes it for m[2] since both m[0] and m[2] have the same tag 0! Clearly this possibility is ruled out when the channels are FIFO.11.7. Concluding RemarksThe examples presented in this chapter illustrate methods of implementing primarily the masking type of fault-tolerance. If the specification of the possible type of fault F is known, then in an F-tolerant system, no occurrence of F should be perceptible to the user of the protocol.Many variations of sliding-window protocol are used in real aplications. Unlike the one discussed in this chapter, most handle two-way communications, where each node can act both as a sender and Another generalization that reduces the number of retransmissions involve the use of a receive buffer. Good messages that are received by R after the loss or the corruption of an earlier message are not discarded, but saved in R's local buffer, and acknowledged. Eventually, the sender learns about it through the timeout mechanism, and selectively transmits the lost or the corrupted messages.An important class of fault-tolerant systems deals with reaching consensus, where a number of processes communicate with one another in a faulty environment to reach an agreement. Distributed consensus is an extensively studied area of research, and some。

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AAAIMS（An Analytical Information Management System）分析信息管理系统Abacus 算盘Access security 存取安全Access time 存取时间Active 有源的Ada programming language Ada 程序设计语言Adapter 适配器Adapter card 转接卡Add-on 外接式附件Address 地址ADSL(Asymmetric Digital Subscriber Line) 非对称数字客户线路After-image record 残留影像记录Algorithm 算法Alpha testing ɑ测试3Alteration switch 变换开关ALU(Arithmetic/Logic Unit)运算器Amplitude 幅度Analog data 模拟数据Analog cellular 模拟移动电话Analog signal 模拟信号Analysis block 分析块Animation 动画制作ANSL(American National Standards Label)美国国家标准标号Answerback memory 应答存储器Anti-noise coding 反噪声编码Antivirus software 反病毒软件APL(A Programming Language) APL 语言Application development cycle 应用开发周期Application program 应用程序4Application software 应用软件Arithmetic operation 算术运算ARP(Automatic Receive Program)自动接受程序Artificial network 仿真网络ASCII(American standard Code for Information Interchange)美国信息交换用标准代码Assembler 汇编程序Assembly language 汇编语言Asynchronous 异步的Asynchronous transmission 异步传输ATM(Asynchronous Transfer Mode) 异步传输模式ATM(Automated Teller Machine)自动出纳机Attribute 属性Auctions on the web 网上拍卖Audio board 声板5Audio file 声音文件Audio input device 声音输入装置Audio-player 播放Audit program 审查程序Auditing system 审查系统Authoring system 写作系统6BBackbone system 主干系统Backup file 备份文件Backward compatibility 反向兼容性Backward recovery 向后恢复Band printer 带式打印机Bandwidth 带宽Bandwidth limitation 带宽限制Bar code 条形码Bar-code reader 条形码读出器Basic exchange format 基本交换格式BASIC programming language BASIC 程序设计语言Batch processing 批处理Beeper 传呼机7Beta testing β测试Binary digit 二进制数字Binary file 二进制文件Binary number system 二进制数字系统Binary system 二进制BIOS(Basic Input/Output System)基本输入/输出系统Bit 量，位Bit(binary digit)位，二进制位，比特Bit-mapped display screen 位映像显示器Block check 块检验Blocking software 封锁软件Bookmark 书签Bootleg version 盗版BPS(Business Professional System) 商业专用系统Bridge 网桥8Broadcast image 广播图象Browser 浏览程序Building blocks 组件Built-in function 内部功能Bus 总线Bus network 总线网络Bus slot 总线槽Business terminal equipment 商务终端设备Button 按扭Byte 字节，位组9CC programming language C 程序设计语言C++ programming language C++程序设计语言Cable length 电缆长度Cable modem 电缆调制解调器Cache memory 超高速缓冲存储器CAD(Computer-Aided Design) 计算机辅助设计CADD(Compute-Aided Design and Drafting) 计算机辅助设计与制图Call-back system 回叫系统CAM(Computer-Aided Manufacturing) 计算机辅助生产Capacity 容量Carrier wave 载波Cartridge tape 盒式磁带CASE(Computer-Aided Software Engineering) 计算机辅助软件工程10CBT(Computer-Based Training) 利用计算机的训练CCD（Charge Coupled Device）电荷藕合器件CD writer 刻录机CDC(Code-Directing Character) 代码引导字符CDP(Certified Data Processor)合格数据处理程序Cell 单元，细胞，信元Cell address 单元地址Cell pointer 单元指示器CEO(Chip Enable Output) 芯片启动输出CERT(Character Error Rate Tester) 字符出错率测试程序Chain printer 链式打印机Channel command 通道命令Character 字符Character-recognition 字符识别Chat room 聊天室11Check bit 校验位，检验位Child record 子记录Chip 芯片，晶片Circuit switching 电路转接，线路交换CIS(Communication Information System) 通信信息（情报）系统Clear entry 消除输入Click 点击Client 客户，委托程序，委托进程，客户机Client-server 客户服务器Clipboard 剪贴板Clouds 云Cluster 簇，束，线束，群集Coaxial tree network 同轴树状网络COBOL programming language COBOL 程序设计语言Coding 编码，编程序12Collision 冲突Color display screen 彩色显示屏Communication 通信Communication parties 传输单元Communications channel 通信信道Communications controller 通信控制器Communications hardware 通信硬件Communications network 通信网络Communications satellites 通信卫星Communications server 通信服务器Communications service 通信业务Communications software 通信软件Communications technology 通信技术Compatibility 兼容性，一致性，互换性Compiler 编译程序13Component 分量，成分，元件，组件，部件Compression 压缩Computer 计算机Computer-based information system 计算机信息系统Computer crime 计算机犯罪Computer industry 计算机行业Computer literacy 计算机扫盲Computer online service 计算机联机服务Computer professional 计算机专业人员Computer programmer 计算机程序设计员Concentration 集中Concentrator 集中器，集线器Concurrent-use license 并行使用许可证Connection 连接Connectivity 连通性，连接性14Connectivity diagram 连通图表Contact 接触点Control structure 控制结构Control unit 控制器，控制部件Controller card 控制器插件Coprocessor 协同处理程序，协同处理机Copy command 复制命令Copyright 版权Copyright protection 版权保护Counterfeit software 盗版软件Courseware 课件CPU(Central Processing Unit) 中央处理机Cracker 黑客CRT(Cathode Ray Tube) 阴极射线管CTS(Clear To Send) 清除发送15Cursor 光标Cursor-movement key 光标移动键Custom software 客户软件Cut command 剪切命令Cyberculture 计算机文化，控制论优化Cybernation 计算机控制化16DDaisy chain 菊链DAT(Data Acquisition Test) 数据采集测试Data access method 数据存取法Data acquisition 数据采集Data compression 数据压缩Data dictionary 数据字典Data file 数据文件Data flow diagram 数据流程图Data integrity 数据完整性Data manipulation language 数据操纵语言Data mining 数据开采Data recovery 数据恢复Data redundancy 数据冗余Data storage hierarchy 数据存储层次17Data transmission 数据传输Data transmission factor 数据传输系数Data warehouse 数据仓库Database 数据库Database server 数据库服务器Database software 数据库软件DBA(Data Base Administrator) 数据库管理程序DBMS(Data Base Management System) 数据库管理系统Debugging 调试Decision making system 判定系统，决策系统Decision table 判定表Dedicated computer 专用计算机Default value 缺省值，系统设定值Delete 删除Democratic network 共同控制网络18Design 设计Desk checking 桌面检验Desktop accessory 桌面附件Desktop publication system 桌面出版系统Developing information system 信息开发系统Dialog box 对话框Dial-up connection 拨号上网Dial-up Internet communication 拨号网间通信Digital 数码的Digital camera 数码照相机Digital cellular phone 数字移动电话Digital signal 数字信号Digital signal processor 数字信号处理器Digital signature 数字签名Digitized speech 数字化语音19DIMS(Data Information and Manufacturing system) 数据信息和制造系统Direct access storage 直接存取存储器，直接访问存储器Direct file organization 直接文件组织Direct implementation 直接实现Direct synchronous multiplexing 直接同步复用Directory 目录，号码表Disk 磁盘Disk drive 磁盘驱动器Diskette 软磁盘，软盘Display 显示Display screen 显示屏幕Disrupt 使混乱，破坏，分裂，瓦解Distance learning 远程学习Distributed database 分布式数据库Disturbance 干扰20DM(Data Memory) 数据存储器DNS(Domain Naming System) 域命名系统Document 文件，资料，文献，文卷Document file 资料文件Documentation 文件编制，资料，文档DOS(Disk Operating System) 磁盘操作系统Dot 点Dot-matrix printer 点阵打印机Download 下载Downsizing 规模缩小化Downward compatibility 向下兼容性Draft-quality 粗劣的印刷质量，草稿字体印刷质量DRAM(Dynamic Random Access Memory) 动态随机存取存储器Drawing program 绘图程序Driver 驱动器21Drum printer 鼓式打印机Drum scanner 鼓形扫描器DSS(Decision Support System) 决策支援系统DTP(Data Transmission Protocol) 数据传送协议Dumb terminal 哑终端，简易终端DVP(Data Validation Program) 数据验证程序Dynamic linking 动态链接22EEBCDIC(Extended Binary Coded Decimal Interchange) 扩充的二-十进制交换码E-cash 电子货币E-commerce 电子商务EDI(Electronic Data Interchange) 电子数据交换EEPROM(Electrically Erasable Read Only Memory) 电可擦只读存储器EIC(External Interface Control) 外部借口控制EIS(External Interrupt Support) 外部中断支援Electroluminescent display 电致发光显示屏Electromagnetic spectrum 电磁光谱Electronic conference 电子会议Electronic image 电子图象Electronic network 电子网络23Electronic secretary 电子秘书Electronic ticketing machine 电子售票机Electronic tutor 电子教案装置Electrostatic plotter 静电绘图机Elementary field 基本字段ELF(Extensible Language Facility) 可扩充的语言功能E-mail 电子邮件Embedded computer 嵌入式计算机Emulation 仿真，仿效Encapsulation 封闭，封装，密封Encryption 加密，编密码End-to-end delay 端到端的时延End-to-end digital connectivity 端到端的数字连接End-user 终端用户ENIAC(Electronic Numerical Integrator and Calculator) 电子数字积分24器和计算器Enter key 输入键EPL(Encoder Programming Language) 编码器程序设计语言EPROM(Erasable Programmable Read Only Memory) 可擦可编程只读存储器EPSS(Error Processing Sub-system) 错误处理子系统Ergonomics 人类工程学Error correction 纠错法ESS(Electronic Switching System) 电子交换系统Evaluation system 评价系统Even parity 偶数奇偶校验Exchange service 交换业务Executable 可执行文件Execution cycle 执行周期Execution program 执行程序Expansion bus 扩展总线25Expansion card 扩充插件卡Expansion slot 扩展槽Expert system 专家系统External hard disk drive 外部硬盘驱动器External modem 外部调制解调器26FFAT(File Allocation Table) 文件分配表Fault freedom 容错性能Fault tolerant system 容错系统Fax 传真Fax machine 传真机FCB(File Control Block) 文件控制块Feasibility study 可行性研究，可能性研究FEC(Forward Error Correction) 向前纠错Fiber-optic cable 光缆Field 字段，场，域Field protect 字段保护Fifth-generation programming language 第五代程序设计语言File 文件27File extension 文件扩充File management system 文件管理系统File name 文件名File server 文件服务程序File virus 文件病毒Filter 过滤，滤波Financial planning system 财务规划系统Find command 查找命令Finder 寻找程序，定位程序，录像器Fingerprint security system 指纹安全系统Firewall 防火墙Firmware 固件Fixed disk drive 固定磁盘驱动器Flatbed plotter 平板绘图仪Flatbed scanner 平板扫描仪28Flat-panel display 平面显示器Flat-panel technique 平面技术Flexible telecommunication networking 灵活的通信联网Floppy disk 软磁盘FLOPS(Floating-point Operations Per Second) 每秒浮点运算次数Flowchart 流程图Font 字型，字体Format selection 格式选择Formatting 格式化，格式编排Formula 公式FORTH programming language FORTH 程序设计语言Forward recovery 正向恢复Fourth-generation programming language 第四代程序设计语言Fragmenting 分割29Frame grabber 帧接受器，帧捕获器Free ware 免费软件Frequency 频率Front-end processor 前端处理机FTP(File Transfer Protocol)文件传送协议Full-duplex 全双工Function 功能，函数，作用Function key 功能键Fuzzy logic 模糊逻辑30GGame port 博弈端口Garbage 无用信息Gateway 关口，网间连接GDS(Group Display System) 群显示系统Genealogy 家谱学，系统GES(General Edit System) 通用逻辑系统GIS(Geographic Information System) 几何图形信息系统Global communication 全球通信GPS(Global Positioning System) 全球定位系统Grammar checker 语法检验程序Graphics 图形学，制图技术Graphics accelerator 图形加速器Graphics coprocessor 图形协同处理程序31Grid 网格，坐标网络Gross index 粗索引Groupware 群件GUI(Graphical User Interface) 图形用户接口32HHacker 黑客Half-duplex transmission 半双工传输Handheld scanner 手持式扫描仪Handshaking 信号交换，接续Hard disk 硬磁盘Hard return 硬回车Hard-copy terminal 硬拷贝终端Hardware 硬件Hardware compatibility 硬件兼容性HDTV(High Definition Television) 高分辨率电视Help menu 求助菜单，求助工程单Head-mounted display 头盔式显示器Hidden computer 隐式计算机33Hierarchical database 分级数据库Hierarchy 分级，分层，层次Hierarchy chart 分级图表High resolution 高分辨率High-level programming language 高级程序设计语言Hold 握住Home directory 主目录Home network 本地网络Home record 引导记录，起始记录Host 主机Host adaptation 主机适应性Host computer 主计算机Host operating system 主操作系统Host-to-host 主机到主机HTML(Hyper text Markup Language) 超文本标记语言34Hybrid network 混合式网络HTTP(Hypertext Transfer Protocol) 超级文本传输协议Hyperlink 超级链接Hypertext 超文本35IIcon 图符Identification system 识别系统Image file 映像文件Imaging system 成像系统IML(Initial Micro-code Load) 初始微码装入Impact 影响，冲击Impact printer 击打式打印机Importing file 输入文件Incremental backup 增量备份法Indexed file organization 索引文件组织Inference engine 推理机Information 信息，情报Information capacity 信息容量36Information function 信息函数Information management 信息管理Information overload 信息超载Information system 信息系统Information technology 信息技术Information transmission system 信息传输系统Information unit 信息单位Information utility 实用程序，信息应用程序，信息公用设施Inheritance 继承Initialize 初始化Ink-jet plotter 喷墨绘图仪Ink-jet printer 喷墨印刷机Input control 输入控制器Input device 输入设备Input hard ware 输入硬件37Inquiry and communication system 查询与通信系统Insert 插入Insertion point 插入点Install 安装，建立Instruction cycle 指令周期Integrated circuit 集成电路Integrated software package 组合软件包Intellectual property 知识产权Intelligent robot 智能机器人Intelligent terminal 智能终端Interactive presentation 交互式演示Inter activity 交互性Interface 接口Intermediate node 中间网点Internal bus 内部总线38Internal hard disk drive 内部硬盘驱动器Internal modem 内部调制解调器International standard interface 国际标准接口Internet 互联网，信息网络实体Interpreter 解释程序，翻译机，转换机ISAM(Indexed Sequential Access Method) 索引顺序存取法ISDN(Integrated Services Digital Network) 综合服务数字网络Isolation 隔离，绝缘ISP(Internally Stored Program) 内部存储程序ISP(Internet Service Provider) 因特网服务提供商39JJAD(Joint Application Design) 联合应用程序设计Jerk 乱窜Jitter 抖动Job file 作业文件Job management 作业管理程序Junk mail 垃圾邮件Justification range 调整范围40KKey field 关键字字段Key search 关键字查找Keyboard 键盘Keyboard console 键盘控制台Kilobyte 千字节Knowledge base 知识库Knowledge engineer 知识工程师Knowledge engineering 知识工程Knowledge system 知识系统41LLanguage translator 语言翻译程序Large-scale integrated circuit 大规模集成电路Laser 激光，激光器Laser communication 激光通信系统Laser printer 激光打印机Latency 延迟，执行时间Latent image 潜像Law 法律Layer 分层LCD(Liquid Crystal Display) 液晶显示器LEO(Low Earth Orbit) 近地轨道License 许可证Light pen 光笔Line printer 行式打印机42Line terminal multiplexer 终端复用器Linear 线性的，一次的Link 连接，连线，链接Linkage instruction 连接命令LISP programming language LISP 程序设计语言Live conversation 实际的对话Load 装入，加载Load server 加载服务器Local-area network 局域网Logic bomb 逻辑炸弹（病毒）Logic error 逻辑错误Logical operation 逻辑操作LOGO programming language LOGO 程序设计语言Look through 搜寻43Loop 循环，回路，环路Loss less 无损耗Lossy 有损耗的，有损失的44MMAC(Memory access Controller) 存储器存取控制器Machine cycle 机器周期Machine language 机器语言Macintosh （苹果公司生产的一种型号的）计算机Macro 宏，宏指令，宏定Macro virus 宏病毒Magnetic tape 磁带Magneto optical disk 磁光盘Mail server 邮件服务器Mailing list 邮件列表Main memory 主存储器Mainframe computer 主计算机Maintenance 维护，维修MAN(Maintenance Alert Network) 维护警报网45Manager 管理程序，管理人员Manipulate 控制，操纵Manipulation 操纵，控制，处理，操作Manual function 手动功能，人工功能Manufacturing support system 制造支持系统Marker 标记符Marketing model 市场销售模型Mark-recognition device 标记识别装置Master file 主文件Mathematic characterization of continuous image 连续图象的数学表征MDA(Multi-Dimensional Analysis) 多维分析MDT(Modified Data Tag) 修改过的数据标志Meeting software 会议软件Mega 兆Memory cycle 存储周期46Mega byte 兆字节Megahertz 兆赫Member record 成员记录Memory 记忆存储，存储器Memory expansion card 存储器扩充卡Memory module 存储模块Menu bar 菜单条Menu-driven program generator 菜单驱动程序生成程序MED(Micro-Electronic Device) 微电子器件Meta-data 元数据MICR(Magnetic Ink Character Recognition) 磁性墨水字符识别Microcomputer 微型计算机Micro controller 微控制器Microprocessor 微处理器Microwave 微波47Middleware communication model 媒件通信模型MIDI(Music Instrument Digital Interface) 乐器数字接口Miniaturization 小型化MIPS(Million Instructions Per Second) 每秒百万条指令Mirror 镜像MIS(Management Information System) 信息管理系统MMX technology MMX 技术Model 模型，机样，型号Modem 调制解调器Module design 模块设计Monitor 监视器，监督Monitor mode 监控方式Monochrome display 单色显示Mouse 鼠标Mouse pointer 鼠标指示器48Moving pictures 活动图象MPP(Massively Parallel Processor) 巨型并行处理器Multifunction device 多功能装置Multimedia 多媒体Multimedia environment 多媒体环境Multipartite virus 复合性病毒Multiplexer 多路转接器Multiplexing 多路转换Multipoint line 多点线路Multi-port 多端口Multiprocessing 多重处理Multiprogramming 多道程序设计（控制）Multitasking 多任务Multi-user platform 多用户平台49NNarrow band services 窄带业务Nationwide network 全国范围的网络Natural language 自然语言Natural language processing 自然语言处理NC language processor NC 语言处理器Necessary bandwidth 必要带宽Net ware 网件Network 网络Network adapter 网络适配器Network computer 网络计算机Network database 网络数据库Network facilities resources 网络设备资源Network harms 网络损害50Network information resources 网络信息资源Network interface card (NIC) 网络接口卡Network piracy 网络盗版Network server 网络服务程序，网络服务器Networked hypertext protocol 网络超文本协议Neural network 神经网络Node 节点，网点Non-interacting control system 非交互式控制系统Non-procedural language 非过程语言Non-volatile chain 非易失链NOS(Network Operating System) 网络操作系统Null set 空集Numeric key 数字键51OOAS(Office Automation System) 办公自动化系统Object 目标，对象，结果，物体Object code 目标代码OCR(Optical Character Recognition) 光符识别Odd parity 奇数奇偶校Off-line equipment 脱机设备Off-line storage 脱机存储器Off-the-shelf software 现成的软件OLE(Object Linking and Embedding) 对象的链接与嵌入OMR(Optical Mark Recognition) 光标记识别Onboard 板载的One-level code 一级代码One-to-many 一对多的52Online processing 联机处理Online storage 联机存储器OODBS(Object Oriented Data Base System) 面向目标的数据库系统OOO(Out Of Order) 发生故障，次序混乱Open network 开放式网络Operating environment 操作环境，运行环境Operating system 操作系统Operation control 操作控制Operator 运算符，操作员Optical card 光卡Optical disk 光盘Optical Ethernet 光以太网Optimization 优化Optoelectronic receiver 光电子接收机Organization 机构，组织，结构，体系53Organization chart 组织图，结构图OS/360(Operating System/360) 360 型操作系统OSI(Open System Interconnection) 开放系统互连Output 输出Owner record 主记录，自由记录54PPackage 分组Packaged software 封装式软件包Packet 包，数据包，分组报文Packet switching 包交换Pager 页面调度程序Painting 涂色Parallel data transmission 并行数据传输Parallel implementation 并行执行Parallel port 并行端口Parallel processing 并行处理Parent record 母记录Parity bit 奇偶校验位Parity scheme 奇偶校验方案55PASCAL programming language PASCAL 程序设计语言Passive 无源的Passive network 无源网络Password 口令Path 路径PBX(Private Branch Exchange) 专用交换分机，用户交换机PC(Personal Computer) 个人计算机PC application software 个人计算机应用软件PC host operating system 个人计算机主机操作系统PCI（peripheral Component Interconnect）外围部件互连PCMCIA(Personal Computer Memory Card International Association) 个人电脑内存储卡国际协会PDA(Personal Digital Assistant) 个人数字助理PDL(Picture Description Language) 画面描述语言Peak 峰值56Peer-to-peer 层间，层到层PEM(Processing Element Memory) 处理单元存储器Perception system 感知系统Peripheral device 外围设备Personal finance software 个人财务软件Personal identification code 个人识别代码PERT chart editing PERT 图编辑PGP(Programmable Graphics Processor) 可编辑图形处理机Phonetic keyboard 语音键盘Photo-digital store 光数字存储器Photolithographic mask layer 光刻掩蔽层Physical storage 物理存储器PIM(Processor Interface Module) 处理程序接口模块PIN(Personal Identification Number) 个人识别号码Pixel store 像素存储器57PL/1 programming language PL/1 程序设计语言Platform position computer 平台位置计算机Plotter 绘图仪Plug and play system 即插即用系统Plug-in card 插件Pointing device 指示装置Point-of-sale terminal 销售点终端Point-to-point line 点对点线路，专用线Polymorphism 多形性，多机组合形势Pop-up menu 弹出选项单Port 端口，进出口Portable operating system 可移植操作系统Portable terminal 便携式终端POST(Power-on Self Test) 通电自检Power supply 电源，供电58PPP(Parallel Pattern Processor) 并行模式处理程序Precision 精确度Preliminary design 初步设计Presentation layer 表示层Presentation graphic 表示图形Presentation software 显示软件Preventive maintenance 预防性维护Previewing 预检，预览Primary storage 主存储器Print server 打印服务程序Printer 打印机Printing document 打印文档Privacy 保密性Procedural error 过程错误Procedural language 过程型语言59Procedure 过程，程序，步骤Process 处理，进程Process model 过程模型Processing 处理，加工Processing hardware 处理硬件Processor 处理程序，处理机Production language compiler 产生式语言编译程序Productivity 生产率Productivity tool 生产率工具Professional programmer 专业程序设计员Program 程序，计划，规划，方案Program file 程序文件Program flowchart 程序流程图Program independence 程序独立性Programmer 程序设计人员，编程器60Programming 程序设计，编程Programming language 程序设计语言Programming procedure 程序设计过程Project management software 工程工程管理，计划管理Project management software 工程工程管理软件PROLOG programming language PROLOG 程序设计语言Proprietary software 专有软件Proprietary system 专用系统Protocol 协议Prototype 样机，原型Prototyping 原型开发，样机研究Pseudo-code 伪代码Public communication carriers 公共通信载体Public domain 公用域Pull-down menu 下拉菜单61Pulse code modulation 脉冲码调制62QQBE(Query By Example) 仿效实例询问QIC(Quality Insurance Chain) 质量保证链Query 询问，查询Query facility 询问功能软件Query language 询问语言Query-and-reporting processor 询问和报告处理程序Quiet code 静止代码QWERTY keyboard QWERTY 键盘63RRAD(Rapid Access Device) 快速存取设备RAM(Random Access Memory) 随机存取存储器,内存Random access storage 随机存取存储器Random file organization 随机文件结构Raster graphics 光栅图形Reading 读，读取Real-time processing 实时处理Reasoning 推理，推论，推导Recalculation 重算Receiving entity 接收实体Receiving system 接收系统Record 记录Reference mark 参考标记64Reference model 参考模型Reference software 参考软件Refresh rate 更新率，刷新率Refreshable program 可刷新程序Regenerate 再生Register 寄存器Relational database 关系数据库Relational model 关系模型Release 释放Reliable 可靠的Reliability 可靠性Remote-control 遥控Remote device 远程设备Remote terminal 远程终端Removable hard disk 可移动硬盘65Repeater 中继器Repeater spacing 中继距离Replace command 替换命令Report generator 报告生成程序Resistor 电阻器Resolution 分辨率Retrieval performance 检索性能Return key 返回键RFI(Read Frequency Input) 读频率输入RGB monitor 红、绿、蓝显示器RIB(Resource Information Block) 资源信息块Ring network 环形网络RISC microprocessor RISC 微处理机Robot 机器人，自动仪Robotics 机器人学，机器人技术66Rollback 重新运行，重算ROM BIOS (Read-Only Basic Input/Output System) 只读存储器基本输入/输出系统Root record 根记录Router 发送程序，路由确定程序，路由器Row 行RPG(Report Program Generator) 报表程序生成程序RPS(Random Pattern Search) 随机模式搜索RS(Record Separator) 记录分隔符Run 运行Rupture 裂断，破裂67SSampling rate 取样率SAR(Source Address Register) 源地址寄存器Satellite 卫星，人造地球卫星Save 存储，保存Save area 保存区Scan 扫描Scanning device 扫描设备，扫描装置Scheduling software 调度软件Screen 屏幕Scrolling 卷动，滚动Scrubbing 除掉，刷去SCSI(Small Computer System Interface) 小型计算机系统接口SDL(System Development Language) 系统开发语言68Search 检索，查找Search command 查找命令Search engine 查找机Searching tool 搜寻工具Second-generation programming language 第二代程序设计语言Secondary application 辅助应用程序Secondary storage 辅助存储器，二级存储器Secondary storage sub system 辅助存储子系统Section overhead 段开销Sector 扇区，分段Security 安全性，保密性，安全措施Security system 安全系统Seek time 查找时间，定位时间Selection control 选择控制Semiconductor 半导体69Semiconductor memory 半导体存储器Semi-structured information 半结构化问题Sender 发送器Sensor 传感器Sequence control 顺序控制Sequential file organization 顺序文件组织Sequential storage 顺序存储器Serial 串行的Serial data transmission 串行数据传输Serial port 串行端口Serial processing 串行处理Server 服务器Service-independent network 与业务无关的网络Session layer 会话层Shared database 共享数据库70Sharing resource 共享资源SHELL software system SHELL 软件系统Shrink-wrapped multiprocessing operating system 精缩环绕多处理操作系统Silicon 硅SIMM(Single in-line Memory Module) 单列直插式存储模块Simplex transmission 单项传输Simulation programming language 模拟程序设计语言Simulator 模拟程序，模拟器Single user 用户Smalltalk programming language Smalltalk 程序设计语言Smart card 智能卡，收费卡Softcopy 软拷贝Software 软件，软设备Software engineer 软件工程师Software engineering 软件工程71Software license 软件许可证Software package 软件包，程序包Software piracy 软件非法翻印，软件侵犯版权Software suite 软件套件Software tool 软件工具Solid error 固定错误Sorting database 分类数据库Sound 声音Sound card 声卡Sound output 声音输出Source code 源代码Source date entry 源数据录入Source program file 源程序文件SPA(Signal Processing Auxiliary) 信号处理辅助设备Speech recognition system 语音识别系统72Speech synthesis 语音合成Speed 速度Speed up 加速Spelling checker 拼法检验程序Split 分发，分散Spreadsheet 电子数据表SQL(Structured Query Language) 结构化查询语言Squeeze 压缩Standardized port 标准化的端口Star network 星形网络STM(Short Term Memory) 短期存储器Storage 存储，存储器Storage hardware 存储硬件Strategic decision 战略性决策Streaming audio 流式音频73Streaming video 流式视频Stress 应力Structure chart 结构图Structured information 结构化信息Structured programming 结构化程序设计Structured walkthrough 结构化普查Subprogram 辅程序，子程序Supercomputer 巨型计算机Superconductor 超导体Supervisor 管理程序，主管人SVDF(Segmented Virtual Display File) 分段虚拟显示文件Swapping 交互，调动Switch 打开，开关，交换机Switching technique 交换技术Synchronous DXC 同步数字交叉连接74Synchronous transmission 同步传输Synchronous transmission system 同步传输系统Syntax 语法，句法Syntax error 语法错误System 系统，体制，装置System analysis 系统分析System analyst 系统分析员System clock 系统时钟System design 系统设计System development 系统开发System engineer 系统工程师System flowchart 系统流程图System implementation 系统实现方法System maintenance 系统维护System recovery 系统恢复75System software 系统软件System testing 系统测试System unit 系统单元76TTabulating machine 制机表Target variable 目标变量Task management 任务管理程序TCT(Terminal Control Table) 终端控制表Telecommunication 远程通信，电信Teleconference 电信会议Telemedicine 电视医疗Telephone network 电话网Telephony 电话学Telex network 用户电报网Tel net 电信网，远程通信网络Terminal 终端Terminal address 终端地址77Terminal emulation 终端仿真Test 测试，检验Test equipment 测试设备Text 正文，文本Text segment 正文段Textual messages 文本信息Thesaurus 主题词表，同义词汇Third-generation programming language 第三腮程序设计语言Through-mode fashion 贯通方式Time slicing 时间分片Time-sharing 分时，时间分配Tong-haul telecommunication system 长途通信系统Top-down program design 自顶向下程序设计Top management 主管，主控Touch screen 触屏TPI(Target Position Indicator) 目标位置指示器TPS(Transaction Processing System) 事务处理系统TPT(Time Priority Table) 时间优先表Track 磁道，轨道，声道Trackball 跟踪球Traffic segregation 流量隔离Transaction 事项，事务处理，交易Transaction file 细目文件，事项文件Transient error 瞬时错误Transmission 传输，发送，传送Transmission unit 传输单元Translate 转换Tributary signals 支路信号Trojan horse 特洛伊木马True color 真彩色79Tuple 元组，字节组Turing test 图灵测试Twisted-pair wire 绞合线Typeface 字样80UUndo command 作废命令Unexpected halt 意外停机Unicode 单一代码UNIVAC(Universal Automatic Computer) 通用自动计算机Universal access 统一的接入Universal product code 通用产品代码Universally 普遍地，通用地UNIX operating system UNIX 操作系统Unprotected field 非保护字段Unstructured file 非结构文件Unstructured information 非结构信息UPS(Uninterruptible Power Supply) 不间断供电电源Upward compatibility 向上兼容性81URL(User Requirements Language) 用户要求语言USE(User System Evaluator) 用户系统评价程序User 用户，使用者User interface 用户接口Utility control console 实用控制台Utility program 实用程序Utility unit 实用设备VValue 值，算式Variable format 可变格式Varying bandwidth 可变宽带Vector graphics 向量图Version 文本，版本Very-high-level programming language 超高级程序设计语言Video compression 视频压缩Video computer system 可视计算机系统Video conference 视频会议Video file 可见文件Video memory 视频存储器Video scan 视频扫描Virtual classroom 虚拟教室83Virtual container 虚容器Virtual memory 虚拟机存储器Virtual office 虚拟办公室Virus 病毒Visual 图象的Visual programming 直观程序设计VLSI(Very-large-scale Integration) 超大规模集成电路Voice encoding techniques 语音编码技术Voice mail 声音邮件Voice output device 声音输出装置Voice recognition system 声音识别系统Volatile file 易变文件Volatile memory 易失性存储器VR(Virtual Reality) 虚拟现实VRAM(Video Random Access Memory) 视频随机存取存储器84VRM(Virtual Resource Manager) 虚拟资源管理程序VSAM(Virtual Sequential Access Method) 虚拟顺序存取法85WWait state 等待状态WAN(Wide Area Network) 广域网络Web browser 网页浏览器Web business 网上商务Web site 网站Wideband subscriber loop system 宽带用户环路系统Window mode 窗口方式Windows operating system Windows 操作系统。

双转换无中断电源1000VA SU1000RTXL2UA商品说明说明书

SmartOnline 120V 1kVA 800W Double-Conversion UPS, 2U, Extended Run, Network Card Options, USB, DB9 SerialMODEL NUMBER:SU1000RTXL2UADescription1000VA on-line, double-conversion UPS system for critical server, network and telecommunications equipment. 2U rackmount form factor with an installed depth of only 13.5 inches. Extended runtime available with optional BP24V15RT2U (limit 1), BP24V28-2U (limit 1), BP24V70-3U (multi-pack compatible) or BP24V36-2US (multi-pack compatible) external battery packs. Full-time sine wave 120V output with +/-2% voltage regulation. Online, double-conversion Uninterruptible Power Supply (UPS) actively converts raw incoming AC power to DC, then re-converts output back to completely regulated, filtered AC output. Operates continuously without using battery power during brownouts to 65V and overvoltages to 150V. Highly efficient operation in optional economy mode saves BTU heat output and energy costs. NEMA 5-15P input plug; NEMA 5-15R output receptacles. Network-grade AC surge and noise suppression. Zero transfer time between AC and battery operation. Network management interfaces support simultaneous communications via USB port, DB9 serial port and slot for network management card options. Built-in DB9 port offers both enhanced RS-232 enabled monitoring data, plus contact closure monitoring ability. HID-compliant USB interface enables integration with built-in power management and auto shutdown features of Windows and Mac OS X.Supports simultaneous detailed monitoring of equipment load levels, self-test data and utility power conditions via all 3 network interfaces. PowerAlert monitoring software is available via free download. Emergency Power Off (EPO) interface. Integrated two-bank PDU switching supports load shedding and remote reboot of connected equipment. 3-stage metered current monitoring and battery charge status LEDs. LED display panel easily rotates for viewing in rackmount or tower configurations. Dataline surge suppression for dialup, DSL or network Ethernet connection. Utility power and voltage regulation LEDs. Audible alarm. Self-test. Fault-tolerant auto-bypass mode. 4-post rackmount accessories included; 2-9USTAND tower kit and 2POSTRMKITWM 2-post rack & wallmount accessories available. Field-replaceable, hot-swappable internal batteries and external battery packs. Attractive all-black color scheme. $250,000 Ultimate Lifetime Insurance (U.S., Canada, and Puerto Rico only).FeaturesSmartOnline high performance UPS system is ideal for critical voice, data, medical and industrial network applicationsqTrue on-line, double-conversion UPS provides perfectly regulated sine wave output within 2% of 120V under all usage conditionsqMaintains continuous operation through blackouts, voltage fluctuations and surges with zero transfer timeqHighly efficient operation in optional economy mode setting, saving BTU heat output and energy costs q Highlights1000VA / 1kVA / 800 watt on-line double-conversion 2Urack/tower UPSq120V +/-2% output at 50/60Hz,high efficiency economy modeoptionqExpandable runtime, Hot-swapbatteries; 13.5 in / 34.3cminstalled depthqUSB, RS232 & EPO ports; slotfor Network Management CardoptionsqFront panel status LEDs withdetailed load and batterymeteringq2 independently switchableoutput load banksqNEMA 5-15P input; 5-15RoutletsqTo use the Auto Probe feature,this product requires aWEBCARDLX network interface (sold separately) running LXfirmware update 15.5.2 or later qPackage IncludesSU1000RTXL2Ua OnlineDouble-Conversion UPSSystemqUSB and DB9 CablesqMounting hardware for 4 postrack enclosuresqInstruction manualqSpecificationsRemoves harmonic distortion, fast electrical impulses, frequency variations and other hard to solve power problems not addressed by other UPS typesqCorrects line voltage conditions as low as 65V and as high as 150V back to 120V (+/-2%) values q Standard internal battery set offers 14 minutes runtime at half load (400W) and 4.5 minutes at full load (800W)qExtended runtime available with optional BP24V15RT2U (limit 1), BP24V28-2U (limit 1), BP24V70-3U (multi-pack compatible) and BP24V36-2US (multi-pack compatible) external battery packsqSome external battery configurations require the use of External Battery Configuration Software (see manual)qIntelligent battery management system extends battery lifeq Compact rack-mount form factor installs using only 2 rack spaces (2U) with a maximum installed depth of only 13.5 inchesqShips with all mounting accessories for 4-post rack-mount installationq Optional 2POSTRMKITWM enables 2-post rack-mount or wallmount installation q Optional 2-9USTAND accessory enables small-footprint upright tower placementq Fault tolerant electronic bypass maintains utility output during a variety of UPS fault conditions q Network interfaces support simultaneous communications via built-in USB, DB9 serial / contact-closure and network management card slotqCompatible with UPS management card options TLNETCARD, WEBCARDLX, SNMPWEBCARD,MODBUSCARD and RELAYIOCARDqHID-compliant USB interface enables integration with built-in power management and auto shutdown features of Windows and macOSqUSB & Serial ports enable data-saving unattended shutdown when used with PowerAlert software,available via FREE download from /products/power-alert qBuilt-in Emergency Power Off (EPO) interface with cable q NEMA 5-15P input plug/NEMA 5-15R output receptaclesq Integrated 2 bank switched PDU enables remote outlet management for load shedding or remote reboot of individual devices (each load bank consists of one outlet)qFront panel LEDs offer current monitoring and battery charge level informationq UPS ships fully assembled in full compliance with DOT regulations, no time consuming connection of internal batteries by user requiredqSingle line TEL/DSL or network Ethernet line surge suppressionq $250,000 Ultimate Lifetime Insurance (U.S., Canada, and Puerto Rico only)q© 2023 Eaton. All Rights Reserved. Eaton is a registered trademark. All other trademarks are the property of their respective owners.。

lbp3500维修手册

Indicates an item requiring care to avoid electric shocks.
Indicates an item requiring care to avoid combustion (fire).
Indicates an item prohibiting disassembly to avoid electric shocks or problems.
1.3 Product Specifications ................................................................................................................................1- 1 1.3.1 Specifications .......................................................................................................................................................... 1- 1
1.4 Name of Parts.............................................................................................................................................1- 3 1.4.1 External View........................................................................................................................................................... 1- 3 1.4.2 Cross Section .......................................................................................................................................................... 1- 4

附录B–CANopen错误代码

附录 B – CANopen 错误代码本附录给出了各种 ABB 变频器的交叉参考表。

这些表中包含 CANopen 错误寄存器位号、错误代码和含义、以及相应的变频器错误代码和/或消息。

如果变频器在二进制字（故障字）中表明存在一个故障，那么在“附加信息”栏内会给出字的名称以及相应的位号。

请注意在面板中给出的一些错误消息不会出现在二进制故障字中，反之亦然。

在变频器手册中给出了每种错误的原因和纠正方法。

附录 B – CANopen 错误代码ACS 400CANopen 错误变频器故障寄存器位代码含义名称附加信息b01000一般错误HW 错误：偶发故障中断故障字2, b13 b12310连续过电流过电流故障字1, b0输出过载故障字1, b4 b12320短路/接地泄漏故障电流故障字1, b3 b12330接地泄漏输出接地故障故障字, b15 b23110电网电源过压直流过压故障字1, b1 b23130断相直流总线纹波过大故障字1, b11 b23220直流回路欠压直流欠压故障字1, b5 b34210温度过高的设备ACS 400温度过高故障字1, b2 b34310温度过高的变频器电机温度过高故障字1, b8b55210测量电路HW 错误：较差的模拟输入；无效脉冲计数故障字2, b11b55300操作设备面板缺失故障字1, b9 b55530EEPROM HW 错误：较差的或新的 FPROM故障字2, b8HW 错误：检测到新 FPROM故障字2, b9HW 错误：FPROM 下装不成功故障字2, b10 b56320参数错误参数不一致故障字1, b10 b57121电机过载停止电机堵转故障字1, b12 b57510串行接口1DDCS 回路故障字2, b2 b57520串行接口2串行通讯缺失故障字1, b13 b58110进程数据监控模拟输入1故障故障字1, b6模拟输入2故障故障字1, b7 b59000外部错误外部故障故障字1, b14 b7FF55变频器专用HW 错误：调制器堵转故障字2, b15 b7FF57变频器专用类型代码错误故障字2, b12 b7FF5D变频器专用应用故障故障字2, b1 b7FF5E变频器专用HW错误：SW 断言过期故障字2, b14 b7FF6A变频器专用欠载故障字2, b0附录 B – CANopen 错误代码ACS 600 - 标准应用程序v5.x ACS 800 - 标准应用程序ASXR7xxxCANopen错误变频器故障寄存器位代码含义名称附加信息b01000一般错误保留系统故障字, b15b12120接地故障EARTH FAULT故障字1, b4b12310连续过流OVERCURRENT故障字1, b1b12340短路SHORT CIRC故障字1, b0SC（INU1）故障字1, b12SC（INU2）故障字1, b13SC（INU3）故障字1, b14SC（INU4）故障字1, b15b23130电源缺相SUPPLY PHASE故障字2, b0b23210直流回路过压DC OVERVOLT故障字1, b2b23220直流回路欠压DC UNDERVOLT故障字2, b2b34100环境温度AMBIENT TEMP故障字2, b7b34210温度过高的设备ACS 600 TEMP故障字1, b3b34310温度过高的变频器THERMISTOR故障字1, b5MOTOR TEMP故障字1, b6b55210测量电路PPCC LINK故障字2, b11b55300操作设备PANEL LOSS故障字2, b13b55530EEPROM FLT（F1_4）系统故障字, b2FLT（F1_5）系统故障字, b3b56100内部软件错误由系统故障字指定检查系统故障字b56200用户软件USER MACRO系统故障字, b1b57000附加模块I/O COMM故障字2, b6b57121电机堵转MOTOR STALL故障字2, b14b57123电机超频OVERFREQ故障字1, b9b57305增量编码器1故障ENCODER FLT故障字2, b5b57510串行接口1COMM MODULE故障字2, b12b57520串行接口2CH2 COM LOSS故障字1, b11b58110进程数据监控AI < MIN FUNC故障字2, b10b59000外部错误EXTERNAL FLT故障字2, b8b7FF51设备专用 (1)LINE CONV故障字1, b10b7FF52设备专用 (2)NO MOT DATA故障字2, b1b7FF53设备专用 (3)CABLE TEMP故障字2, b3b7FF54设备专用 (4)RUN DISABLED故障字2, b4b7FF55设备专用 (5)OVER SWFREQ故障字2, b9附录 B – CANopen 错误代码CANopen错误变频器故障寄存器位代码含义名称附加信息b7FF56设备专用 (6)MOTOR PHASE故障字2, b15b7FF57设备专用 (7)FLT (F1_7)系统故障字, b0b7FF58设备专用 (8)FLT (F2_12)系统故障字, b4b7FF59设备专用 (9)FLT (F2_13)系统故障字, b5b7FF5A设备专用 (10)FLT (F2_14)系统故障字, b6b7FF5B设备专用(11)FLT (F2_15)系统故障字, b7b7FF5C设备专用 (12)FLT (F2_16)系统故障字, b8b7FF5D设备专用 (13)FLT (F2_17)系统故障字, b9b7FF5E设备专用 (14)FLT (F2_18)系统故障字, b10b7FF5F设备专用 (15)FLT (F2_19)系统故障字, b11b7FF60设备专用 (16)FLT (F2_3)系统故障字, b12b7FF61设备专用 (17)FLT (F2_1)系统故障字, b13b7FF62设备专用 (18)FLT (F2_0)系统故障字, b14b7FF6A设备专用 (25)UNDERLOAD故障字1, b8附录 B – CANopen 错误代码ACS 600 - 标准应用程序v2.8/3.0CANopen 错误变频器故障寄存器位代码含义名称b12120接地故障EARTH FAULTb12310连续过电流OVERCURRENTb12340短路SHORT CIRCb23130端相SUPPLY PHASEb23210直流回路过压DC OVERVOLTb23220直流回路欠压DC UNDERVOLTb34100环境温度AMBIENT TEMPb34210温度过高的设备ACS 600 TEMPTHERMISTORb34310温度过高的变频器MOTOR TEMPb55300操作设备PANEL LOSSb56200用户软件USER MACROb57000附加模块I/O COMMb57121电机堵转MOTOR STALLb27123电机超频OVERFREQb57305增量编码器1故障ENCODER ERRb57510串行接口1COMM MODULEb58110进程数据监控AI < MIN FUNCb59000外部错误EXTERNAL FLTb7FF51设备专用 (1)LINE CONVb7FF52设备专用 (2)NO MOT DATAb7FF54设备专用 (4)RUN DISABLEDb7FF56设备专用 (6)MOTOR PHASEb7FF63设备专用 (19)ID RUN FAILb7FF64设备专用 (20)WRITE PROTCTb7FF65设备专用 (21)ID RUN SELb7FF66设备专用 (22)PARAM LOCKb7FF67设备专用 (23)MOTOR STARTSb7FF68设备专用 (24)ID N CHANGEDb7FF69设备专用 (25)MACRO CHANGEb7FF6A设备专用 (26)UNDERLOAD附录 B – CANopen 错误代码ACS 600 – 运动控制应用程序CANopen 错误变频器故障寄存器位代码含义名称附加信息b12120接地故障EARTH FAULT故障字1, b16b12310连续过电流OVERCURRENT故障字2, b6b12340短路SHORT CIRC故障字2, b21b23130电源缺相SUPPLY PHASE故障字1, b3b23210直流回路过压DC OVERVOLT故障字2, b5b23220直流回路欠压DC UNDERVOLT故障字2, b4b34210温度过高的设备ACS 600 TEMP故障字2, b11b34310温度过高的变频器MOTOR TEMP故障字2, b9b55210测量电路PPCC LINK故障字2, b10b56200用户软件USER MACRO故障字1, b6b57000附加模块I/O CONFIG故障字1, b10I/O COMM故障字 1, b19 b57121电机堵转MOTOR STALL故障字2, b20b57123电机超频OVERFREQ故障字2, b23b57305增量编码器1故障ENC COMM ERR故障字1, b13b57320位置POSITION ERR故障字1, b20b57510串行接口1COMM MODULEb7FF52设备专用(2)NO MOT DATA故障字1, b9b7FF56设备专用 (6)MOTOR PHASE故障字2, b22b7FF6A设备专用 (25)UNDERLOAD故障字 2, b2b7FF6B设备专用 (26)ENC SSI ERR故障字1, b11b7FF6C设备专用 (27)SPD ALT ERR故障字1, b14b7FF6D设备专用 (28)SPD DIFF ERR故障字1, b15b7FF6E设备专用 (29)POS LIM ERR故障字1, b21b7FF6F设备专用 (30)OVERSPEED故障字1, b22附录 B – CANopen 错误代码ACS 600–起重机应用程序CANopen 错误变频器故障寄存器位代码含义名称附加信息b12120接地故障EARTH FAULT故障字2, 位.4b12310连续过电流OVERCURRENT故障字2, 位.3b12340短路SHORT CIRCUIT故障字2, 位.11b23130电源缺相SUPPLY PHASE故障字2, 位.13b23210直流回路过压DC OVERVOLT故障字2, 位.1b23220直流回路欠压DC UNDERVOLT故障字2, 位.2b34100环境温度AMBIENT TEMP故障字1, 位.13b34210温度过高的设备ACS 600 TEMP故障字2, 位.7b34310温度过高的变频器THERMISTOR故障字1, 位.14MOTOR TEMP故障字2, 位.8 b55210测量电路PPCC LINK故障字2, 位.12b55300操作设备PANEL LOSS故障字1, 位.11b56200用户软件USER MACRO故障字2, 位.6b57000附加模块I/O COMM故障字1, 位.12b57123电机超频OVERFREQ故障字2, 位.9b57305增量编码器1故障ENCODER ERR故障字2, 位 .14b57310速度（编码器）MOT OVERSP故障字1, 位 .1b57510串行接口1COMM MODULE故障字1, 位.16b57520串行接口 2MF COMM ERR故障字1, 位.10b59000外部错误EXTERNAL FLT故障字1, 位.9b7FF56设备专用MOTOR PHASE故障字2, 位 .5b7FF73设备专用TORQ FLT故障字1, 位 .2b7FF74设备专用BRAKE FLT故障字1, 位 .3b7FF75设备专用TORQ PR FLT故障字1, 位 .5b7FF76设备专用MAS OSC FLT故障字1, 位 .6b7FF77设备专用CHOPPER FLT故障字1, 位 .7b7FF78设备专用INV OVERLO故障字1, 位 .8b7FF79设备专用MF RUN FLT故障字1, 位.15b7FF7A设备专用START INHIBIT故障字2, 位 .10附录 B – CANopen 错误代码ACS 1000DCS 400CANopen 错误变频器故障寄存器位代码含义名称b01000一般错误保留b57510串行接口1COMM MODULECANopen 错误变频器故障寄存器位代码含义代码消息附加信息b122212号连续过电流 F 14ARMATURE OVERCURRENT故障字1, b13 b122221号连续过电流 F 13FIELD OVERCURRENT故障字 1, b12 b23110电网电源过压 F 10MAINS OVERVOLTAGE故障字 1, b9 b23120电网电源欠压 F 1AUX VOLTAGE FAULT故障字1, b0F 9MAINS UNDERVOLTAGE故障字1, b8b23320电枢电路 F 15ARMATURE OVERVOLTAGE故障字1, b14 b34210温度过高的设备 F 7CONVERTER OVERTEMP故障字 1, b6 b34310温度过高的变频器 F 8MOTOR OVERTEMP故障字1, b7 b55220运算电路 F 2HARDWARE FAULT故障字1, b1 b56100内部软件 F 3SOFTWARE FAULT故障字 1, b2 b57121电机堵转 F 19MOTOR STALLED故障字 2, b2 b57302测速电机极性错误 F 17TACHO POLARITY FAULT故障字2, b0 b57305增量编码器1故障 F 16SPEED MEAS FAULT故障字 1, b15 b57310速度 F 18OVERSPEED故障字 2, b1 b57510串行接口1 F 20COMMUNICATION FAULT故障字2, b3 b59000外部错误 F 22EXTERNAL FAULT故障字2, b5 b7FF0D设备专用 F 11MAINS SYNC FAULT故障字1, b10 b7FF18设备专用 F 6TYPECODE READ FAULT故障字1, b5 b7FF19设备专用 F 4PAR FLASH READ FAULT故障字 1, b3 b7FF70设备专用 F 21LOCAL CONTROL LOST故障字2, b4 b7FF71设备专用 F 5COMPATIBILITY FAULT故障字1, b4 b7FF72设备专用 F 12FIELD UNDERCURRENT故障字 1, b11附录 B – CANopen 错误代码DCS 500CANopen 错误变频器故障寄存器位代码含义代码控制面板的文字附加信息b12120接地故障 F 5EARTH FAULT故障字1, b4 b12220连续过电流 F 2OVERCURRENT故障字1, b1 b23110电网电源过压 F 30MAINS OVERVOLTAGE故障字1, b12 b23120电网电源欠压 F 1AUXIL. UNDERVOLTAGE故障字1, b0F 29MAINS UNDERVOLTAGE故障字1, b11b23320电枢电路 F 28ARMATURE OVERVOLTAGE故障字1, b2 b34200设备温度 F 4CONVERTER OVERTEMP.故障字1, b3 b34300温度变频器 F 6MOTOR 1 OVERTEMP.故障字 1, b5F 48MOTOR 2 OVERTEMP.故障字1, b8b34310温度过高的设备 F 7MOTOR 1 OVERLOAD故障字1, b6F 27MOTOR 2 OVERLOAD故障字1, b9b57121电机堵转 F 23MOTOR STALLED故障字2, b14 b57305增量编码器1故障 F 14SPEED MEAS. FAULT故障字 2, b5 b57310速度（编码器） F 37MOTOR OVERSPEED故障字2, b15 b57500通讯（附加） F 44I/O-BOARD NOT FOUND故障字1, b7 b57510串行接口1 F 60FIELDBUS TIMEOUT故障字3, b13 b7FF0A设备专用 F 52NO BRAKE ACK故障字1, b10 b7FF0D设备专用 F 31NOT IN SYNCHRONISM故障字 1, b13 b7FF0E设备专用 F 32FIELD EX.1 OVERCURR故障字1, b14 b7FF0F设备专用 F 33FIELD EX.1 COMERROR故障字1, b15 b7FF10设备专用 F 34ARM. CURRENT RIPPLE故障字2, b0 b7FF11设备专用 F 35FIELD EX.2 OVERCURR故障字2, b1 b7FF12设备专用 F 36FIELD EX.2 COMERROR故障字 2, b2 b7FF13设备专用 F 38PHASE SEQUENCE FAULT故障字2, b3 b7FF14设备专用 F 39NO FIELD ACK.故障字2, b4 b7FF16设备专用 F 40NO EXT. FAN ACK.故障字2, b6 b7FF17设备专用 F 41NO MAIN CONT. ACK.故障字2, b7 b7FF18设备专用 F 17TYPE CODING FAULT故障字 2, b8 b7FF19设备专用 F 18BACKUP READ FAULT故障字2, b9 b7FF1A设备专用 F 50NO C FAN ACK故障字 2, b10 b7FF1B设备专用 F 20LOCAL & DISCONNECTED故障字2, b11 b7FF1C设备专用 F 42FIELD EX.1 NOT OK故障字 2, b12 b7FF1D设备专用 F 43FIELD EX.2 NOT OK故障字2, b13 b7FF2E设备专用 F 66CURRENT DIFFERENCE故障字3, b14 b7FF2F设备专用F65REVERSAL FAULT故障字3, b15附录 B – CANopen 错误代码DCS 600CANopen 错误变频器故障寄存器位代码含义代码控制面板的文字附加信息b12120接地故障 F 5EARTH FAULT故障字1, b4b12220连续过电流 F 2OVERCURRENT故障字1, b1b23110电网电源过压 F 30MAINS OVERVOLTAGE故障字1, b12b23120电网电源欠压 F 1AUXIL. UNDERVOLTAGE故障字1, b0F 29MAINS UNDERVOLTAGE故障字1, b11b23320电枢电路 F 28ARMATURE OVERVOLTAGE故障字1, b2b34200设备温度 F 4CONVERTER OVERTEMP.故障字1, b3b34300温度过高的变频器 F 6MOTOR 1 OVERTEMP.故障字1, b5F 48MOTOR 2 OVERTEMP.故障字1, b8b34310温度过高的变频器 F 7MOTOR 1 OVERLOAD故障字 1, b6F 27MOTOR 2 OVERLOAD故障字1, b9b55300操作设备PANEL LOSS故障字3, b13b55530EEPROM F 18CON FLASH故障字3, b14b56100内部软件SYSTEM FAULT故障字3, b7F 20CON-SYSTEM FAULT故障字3, b15b57121电机堵转 F 23MOTOR STALLED故障字 2, b14b57305增量编码器1故障 F 14SPEED MEAS. FAULT故障字2, b5b57310速度（编码器） F 37MOTOR OVERSPEED故障字2, b15b57500通讯（附加） F 44I/O BOARD NOT FOUND故障字1, b7b57510串行接口1DDCS CH. 0 COMM. FAULT故障字2, b11b57520串行接口2M/F LINK故障字3, b11b7FF0D设备专用 F 31NOT IN SYNCHRONISM故障字1, b13b7FF0E设备专用 F 32FIELD EX.1 OVERCURR故障字 1, b14b7FF0F设备专用 F 33FIELD EX.1 COMERROR故障字1, b15b7FF10设备专用 F 34ARM. CURRENT RIPPLE故障字2, b0b7FF11设备专用 F 35FIELD EX.2 OVERCURR故障字2, b1b7FF12设备专用 F 36FIELD EX.2 COMERROR故障字2, b2b7FF13设备专用 F 38PHASE SEQUENCE FAULT故障字 2, b3b7FF14设备专用 F 39NO FIELD ACK.故障字 2, b4b7FF16设备专用 F 40NO EXT. FAN ACK.故障字 2, b6b7FF17设备专用 F 41NO MAIN CONT. ACK.故障字 2, b7b7FF18设备专用 F 17TYPE CODING FAULT故障字2, b8b7FF1A设备专用 F 50NO C FAN ACK故障字 2, b10b7FF1C设备专用 F 42FIELD EX.1 NOT OK故障字2, b12b7FF1D设备专用 F 43FIELD EX.2 NOT OK故障字2, b13b7FF7B设备专用CON COMMUNIC故障字3, b10。

Indradrive 系列故障代码

Error MessagesF9001 Error internal function call.F9002 Error internal RTOS function callF9003 WatchdogF9004 Hardware trapF8000 Fatal hardware errorF8010 Autom. commutation: Max. motion range when moving back F8011 Commutation offset could not be determinedF8012 Autom. commutation: Max. motion rangeF8013 Automatic commutation: Current too lowF8014 Automatic commutation: OvercurrentF8015 Automatic commutation: TimeoutF8016 Automatic commutation: Iteration without resultF8017 Automatic commutation: Incorrect commutation adjustment F8018 Device overtemperature shutdownF8022 Enc. 1: Enc. signals incorr. (can be cleared in ph. 2) F8023 Error mechanical link of encoder or motor connectionF8025 Overvoltage in power sectionF8027 Safe torque off while drive enabledF8028 Overcurrent in power sectionF8030 Safe stop 1 while drive enabledF8042 Encoder 2 error: Signal amplitude incorrectF8057 Device overload shutdownF8060 Overcurrent in power sectionF8064 Interruption of motor phaseF8067 Synchronization PWM-Timer wrongF8069 +/-15Volt DC errorF8070 +24Volt DC errorF8076 Error in error angle loopF8078 Speed loop error.F8079 Velocity limit value exceededF8091 Power section defectiveF8100 Error when initializing the parameter handlingF8102 Error when initializing power sectionF8118 Invalid power section/firmware combinationF8120 Invalid control section/firmware combinationF8122 Control section defectiveF8129 Incorrect optional module firmwareF8130 Firmware of option 2 of safety technology defectiveF8133 Error when checking interrupting circuitsF8134 SBS: Fatal errorF8135 SMD: Velocity exceededF8140 Fatal CCD error.F8201 Safety command for basic initialization incorrectF8203 Safety technology configuration parameter invalidF8813 Connection error mains chokeF8830 Power section errorF8838 Overcurrent external braking resistorF7010 Safely-limited increment exceededF7011 Safely-monitored position, exceeded in pos. DirectionF7012 Safely-monitored position, exceeded in neg. DirectionF7013 Safely-limited speed exceededF7020 Safe maximum speed exceededF7021 Safely-limited position exceededF7030 Position window Safe stop 2 exceededF7031 Incorrect direction of motionF7040 Validation error parameterized - effective thresholdF7041 Actual position value validation errorF7042 Validation error of safe operation modeF7043 Error of output stage interlockF7050 Time for stopping process exceeded8.3.15 F7051 Safely-monitored deceleration exceeded (159)8.4 Travel Range Errors (F6xxx) (161)8.4.1 Behavior in the Case of Travel Range Errors (161)8.4.2 F6010 PLC Runtime Error (162)8.4.3 F6024 Maximum braking time exceeded (163)8.4.4 F6028 Position limit value exceeded (overflow) (164)8.4.5 F6029 Positive position limit exceeded (164)8.4.6 F6030 Negative position limit exceeded (165)8.4.7 F6034 Emergency-Stop (166)8.4.8 F6042 Both travel range limit switches activated (167)8.4.9 F6043 Positive travel range limit switch activated (167)8.4.10 F6044 Negative travel range limit switch activated (168)8.4.11 F6140 CCD slave error (emergency halt) (169)8.5 Interface Errors (F4xxx) (169)8.5.1 Behavior in the Case of Interface Errors (169)8.5.2 F4001 Sync telegram failure (170)8.5.3 F4002 RTD telegram failure (171)8.5.4 F4003 Invalid communication phase shutdown (172)8.5.5 F4004 Error during phase progression (172)8.5.6 F4005 Error during phase regression (173)8.5.7 F4006 Phase switching without ready signal (173)8.5.8 F4009 Bus failure (173)8.5.9 F4012 Incorrect I/O length (175)8.5.10 F4016 PLC double real-time channel failure (176)8.5.11 F4017 S-III: Incorrect sequence during phase switch (176)8.5.12 F4034 Emergency-Stop (177)8.5.13 F4140 CCD communication error (178)8.6 Non-Fatal Safety Technology Errors (F3xxx) (178)8.6.1 Behavior in the Case of Non-Fatal Safety Technology Errors (178)8.6.2 F3111 Refer. missing when selecting safety related end pos (179)8.6.3 F3112 Safe reference missing (179)8.6.4 F3115 Brake check time interval exceeded (181)Troubleshooting Guide | Rexroth IndraDrive Electric Drivesand ControlsI Bosch Rexroth AG VII/XXIITable of ContentsPage8.6.5 F3116 Nominal load torque of holding system exceeded (182)8.6.6 F3117 Actual position values validation error (182)8.6.7 F3122 SBS: System error (183)8.6.8 F3123 SBS: Brake check missing (184)8.6.9 F3130 Error when checking input signals (185)8.6.10 F3131 Error when checking acknowledgment signal (185)8.6.11 F3132 Error when checking diagnostic output signal (186)8.6.12 F3133 Error when checking interrupting circuits (187)8.6.13 F3134 Dynamization time interval incorrect (188)8.6.14 F3135 Dynamization pulse width incorrect (189)8.6.15 F3140 Safety parameters validation error (192)8.6.16 F3141 Selection validation error (192)8.6.17 F3142 Activation time of enabling control exceeded (193)8.6.18 F3143 Safety command for clearing errors incorrect (194)8.6.19 F3144 Incorrect safety configuration (195)8.6.20 F3145 Error when unlocking the safety door (196)8.6.21 F3146 System error channel 2 (197)8.6.22 F3147 System error channel 1 (198)8.6.23 F3150 Safety command for system start incorrect (199)8.6.24 F3151 Safety command for system halt incorrect (200)8.6.25 F3152 Incorrect backup of safety technology data (201)8.6.26 F3160 Communication error of safe communication (202)8.7 Non-Fatal Errors (F2xxx) (202)8.7.1 Behavior in the Case of Non-Fatal Errors (202)8.7.2 F2002 Encoder assignment not allowed for synchronization (203)8.7.3 F2003 Motion step skipped (203)8.7.4 F2004 Error in MotionProfile (204)8.7.5 F2005 Cam table invalid (205)8.7.6 F2006 MMC was removed (206)8.7.7 F2007 Switching to non-initialized operation mode (206)8.7.8 F2008 RL The motor type has changed (207)8.7.9 F2009 PL Load parameter default values (208)8.7.10 F2010 Error when initializing digital I/O (-> S-0-0423) (209)8.7.11 F2011 PLC - Error no. 1 (210)8.7.12 F2012 PLC - Error no. 2 (210)8.7.13 F2013 PLC - Error no. 3 (211)8.7.14 F2014 PLC - Error no. 4 (211)8.7.15 F2018 Device overtemperature shutdown (211)8.7.16 F2019 Motor overtemperature shutdown (212)8.7.17 F2021 Motor temperature monitor defective (213)8.7.18 F2022 Device temperature monitor defective (214)8.7.19 F2025 Drive not ready for control (214)8.7.20 F2026 Undervoltage in power section (215)8.7.21 F2027 Excessive oscillation in DC bus (216)8.7.22 F2028 Excessive deviation (216)8.7.23 F2031 Encoder 1 error: Signal amplitude incorrect (217)VIII/XXII Bosch Rexroth AG | Electric Drivesand ControlsRexroth IndraDrive | Troubleshooting GuideTable of ContentsPage8.7.24 F2032 Validation error during commutation fine adjustment (217)8.7.25 F2033 External power supply X10 error (218)8.7.26 F2036 Excessive position feedback difference (219)8.7.27 F2037 Excessive position command difference (220)8.7.28 F2039 Maximum acceleration exceeded (220)8.7.29 F2040 Device overtemperature 2 shutdown (221)8.7.30 F2042 Encoder 2: Encoder signals incorrect (222)8.7.31 F2043 Measuring encoder: Encoder signals incorrect (222)8.7.32 F2044 External power supply X15 error (223)8.7.33 F2048 Low battery voltage (224)8.7.34 F2050 Overflow of target position preset memory (225)8.7.35 F2051 No sequential block in target position preset memory (225)8.7.36 F2053 Incr. encoder emulator: Pulse frequency too high (226)8.7.37 F2054 Incr. encoder emulator: Hardware error (226)8.7.38 F2055 External power supply dig. I/O error (227)8.7.39 F2057 Target position out of travel range (227)8.7.40 F2058 Internal overflow by positioning input (228)8.7.41 F2059 Incorrect command value direction when positioning (229)8.7.42 F2063 Internal overflow master axis generator (230)8.7.43 F2064 Incorrect cmd value direction master axis generator (230)8.7.44 F2067 Synchronization to master communication incorrect (231)8.7.45 F2068 Brake error (231)8.7.46 F2069 Error when releasing the motor holding brake (232)8.7.47 F2074 Actual pos. value 1 outside absolute encoder window (232)8.7.48 F2075 Actual pos. value 2 outside absolute encoder window (233)8.7.49 F2076 Actual pos. value 3 outside absolute encoder window (234)8.7.50 F2077 Current measurement trim wrong (235)8.7.51 F2086 Error supply module (236)8.7.52 F2087 Module group communication error (236)8.7.53 F2100 Incorrect access to command value memory (237)8.7.54 F2101 It was impossible to address MMC (237)8.7.55 F2102 It was impossible to address I2C memory (238)8.7.56 F2103 It was impossible to address EnDat memory (238)8.7.57 F2104 Commutation offset invalid (239)8.7.58 F2105 It was impossible to address Hiperface memory (239)8.7.59 F2110 Error in non-cyclical data communic. of power section (240)8.7.60 F2120 MMC: Defective or missing, replace (240)8.7.61 F2121 MMC: Incorrect data or file, create correctly (241)8.7.62 F2122 MMC: Incorrect IBF file, correct it (241)8.7.63 F2123 Retain data backup impossible (242)8.7.64 F2124 MMC: Saving too slowly, replace (243)8.7.65 F2130 Error comfort control panel (243)8.7.66 F2140 CCD slave error (243)8.7.67 F2150 MLD motion function block error (244)8.7.68 F2174 Loss of motor encoder reference (244)8.7.69 F2175 Loss of optional encoder reference (245)Troubleshooting Guide | Rexroth IndraDrive Electric Drivesand Controls| Bosch Rexroth AG IX/XXIITable of ContentsPage8.7.70 F2176 Loss of measuring encoder reference (246)8.7.71 F2177 Modulo limitation error of motor encoder (246)8.7.72 F2178 Modulo limitation error of optional encoder (247)8.7.73 F2179 Modulo limitation error of measuring encoder (247)8.7.74 F2190 Incorrect Ethernet configuration (248)8.7.75 F2260 Command current limit shutoff (249)8.7.76 F2270 Analog input 1 or 2, wire break (249)8.7.77 F2802 PLL is not synchronized (250)8.7.78 F2814 Undervoltage in mains (250)8.7.79 F2815 Overvoltage in mains (251)8.7.80 F2816 Softstart fault power supply unit (251)8.7.81 F2817 Overvoltage in power section (251)8.7.82 F2818 Phase failure (252)8.7.83 F2819 Mains failure (253)8.7.84 F2820 Braking resistor overload (253)8.7.85 F2821 Error in control of braking resistor (254)8.7.86 F2825 Switch-on threshold braking resistor too low (255)8.7.87 F2833 Ground fault in motor line (255)8.7.88 F2834 Contactor control error (256)8.7.89 F2835 Mains contactor wiring error (256)8.7.90 F2836 DC bus balancing monitor error (257)8.7.91 F2837 Contactor monitoring error (257)8.7.92 F2840 Error supply shutdown (257)8.7.93 F2860 Overcurrent in mains-side power section (258)8.7.94 F2890 Invalid device code (259)8.7.95 F2891 Incorrect interrupt timing (259)8.7.96 F2892 Hardware variant not supported (259)8.8 SERCOS Error Codes / Error Messages of Serial Communication (259)9 Warnings (Exxxx) (263)9.1 Fatal Warnings (E8xxx) (263)9.1.1 Behavior in the Case of Fatal Warnings (263)9.1.2 E8025 Overvoltage in power section (263)9.1.3 E8026 Undervoltage in power section (264)9.1.4 E8027 Safe torque off while drive enabled (265)9.1.5 E8028 Overcurrent in power section (265)9.1.6 E8029 Positive position limit exceeded (266)9.1.7 E8030 Negative position limit exceeded (267)9.1.8 E8034 Emergency-Stop (268)9.1.9 E8040 Torque/force actual value limit active (268)9.1.10 E8041 Current limit active (269)9.1.11 E8042 Both travel range limit switches activated (269)9.1.12 E8043 Positive travel range limit switch activated (270)9.1.13 E8044 Negative travel range limit switch activated (271)9.1.14 E8055 Motor overload, current limit active (271)9.1.15 E8057 Device overload, current limit active (272)X/XXII Bosch Rexroth AG | Electric Drivesand ControlsRexroth IndraDrive | Troubleshooting GuideTable of ContentsPage9.1.16 E8058 Drive system not ready for operation (273)9.1.17 E8260 Torque/force command value limit active (273)9.1.18 E8802 PLL is not synchronized (274)9.1.19 E8814 Undervoltage in mains (275)9.1.20 E8815 Overvoltage in mains (275)9.1.21 E8818 Phase failure (276)9.1.22 E8819 Mains failure (276)9.2 Warnings of Category E4xxx (277)9.2.1 E4001 Double MST failure shutdown (277)9.2.2 E4002 Double MDT failure shutdown (278)9.2.3 E4005 No command value input via master communication (279)9.2.4 E4007 SERCOS III: Consumer connection failed (280)9.2.5 E4008 Invalid addressing command value data container A (280)9.2.6 E4009 Invalid addressing actual value data container A (281)9.2.7 E4010 Slave not scanned or address 0 (281)9.2.8 E4012 Maximum number of CCD slaves exceeded (282)9.2.9 E4013 Incorrect CCD addressing (282)9.2.10 E4014 Incorrect phase switch of CCD slaves (283)9.3 Possible Warnings When Operating Safety Technology (E3xxx) (283)9.3.1 Behavior in Case a Safety Technology Warning Occurs (283)9.3.2 E3100 Error when checking input signals (284)9.3.3 E3101 Error when checking acknowledgment signal (284)9.3.4 E3102 Actual position values validation error (285)9.3.5 E3103 Dynamization failed (285)9.3.6 E3104 Safety parameters validation error (286)9.3.7 E3105 Validation error of safe operation mode (286)9.3.8 E3106 System error safety technology (287)9.3.9 E3107 Safe reference missing (287)9.3.10 E3108 Safely-monitored deceleration exceeded (288)9.3.11 E3110 Time interval of forced dynamization exceeded (289)9.3.12 E3115 Prewarning, end of brake check time interval (289)9.3.13 E3116 Nominal load torque of holding system reached (290)9.4 Non-Fatal Warnings (E2xxx) (290)9.4.1 Behavior in Case a Non-Fatal Warning Occurs (290)9.4.2 E2010 Position control with encoder 2 not possible (291)9.4.3 E2011 PLC - Warning no. 1 (291)9.4.4 E2012 PLC - Warning no. 2 (291)9.4.5 E2013 PLC - Warning no. 3 (292)9.4.6 E2014 PLC - Warning no. 4 (292)9.4.7 E2021 Motor temperature outside of measuring range (292)9.4.8 E2026 Undervoltage in power section (293)9.4.9 E2040 Device overtemperature 2 prewarning (294)9.4.10 E2047 Interpolation velocity = 0 (294)9.4.11 E2048 Interpolation acceleration = 0 (295)9.4.12 E2049 Positioning velocity >= limit value (296)9.4.13 E2050 Device overtemp. Prewarning (297)Troubleshooting Guide | Rexroth IndraDrive Electric Drivesand Controls| Bosch Rexroth AG XI/XXIITable of ContentsPage9.4.14 E2051 Motor overtemp. prewarning (298)9.4.15 E2053 Target position out of travel range (298)9.4.16 E2054 Not homed (300)9.4.17 E2055 Feedrate override S-0-0108 = 0 (300)9.4.18 E2056 Torque limit = 0 (301)9.4.19 E2058 Selected positioning block has not been programmed (302)9.4.20 E2059 Velocity command value limit active (302)9.4.21 E2061 Device overload prewarning (303)9.4.22 E2063 Velocity command value > limit value (304)9.4.23 E2064 Target position out of num. range (304)9.4.24 E2069 Holding brake torque too low (305)9.4.25 E2070 Acceleration limit active (306)9.4.26 E2074 Encoder 1: Encoder signals disturbed (306)9.4.27 E2075 Encoder 2: Encoder signals disturbed (307)9.4.28 E2076 Measuring encoder: Encoder signals disturbed (308)9.4.29 E2077 Absolute encoder monitoring, motor encoder (encoder alarm) (308)9.4.30 E2078 Absolute encoder monitoring, opt. encoder (encoder alarm) (309)9.4.31 E2079 Absolute enc. monitoring, measuring encoder (encoder alarm) (309)9.4.32 E2086 Prewarning supply module overload (310)9.4.33 E2092 Internal synchronization defective (310)9.4.34 E2100 Positioning velocity of master axis generator too high (311)9.4.35 E2101 Acceleration of master axis generator is zero (312)9.4.36 E2140 CCD error at node (312)9.4.37 E2270 Analog input 1 or 2, wire break (312)9.4.38 E2802 HW control of braking resistor (313)9.4.39 E2810 Drive system not ready for operation (314)9.4.40 E2814 Undervoltage in mains (314)9.4.41 E2816 Undervoltage in power section (314)9.4.42 E2818 Phase failure (315)9.4.43 E2819 Mains failure (315)9.4.44 E2820 Braking resistor overload prewarning (316)9.4.45 E2829 Not ready for power on (316)。

英文文献翻译(can总线的发展)

英文文献翻译二〇年月日In February 1986, Robert Bosch in SAE (Society of Automotive Engineers) General Assembly introduced a new type of serial bus - CAN Controller Area Network, it is time for the birth of CAN. Today, almost every one in Europe, new passenger cars are equipped with CAN LAN. Similarly, CAN is also used for other types of vehicles, from trains to ships or for industrial control. CAN has become a worldwide one of the most important of the bus - or even leading the serial bus. In 1999, nearly 6 10 million CAN controller into used. In 2000, market sales of more than 100 million CAN device.Earlier in 1980, Bosch engineers began to demonstrate at the time serial bus used for passenger car system is feasible. Because there is no ready-made network solution can fully meet the requirements of automotive engineers, then, in early 1983, Uwe Kiencke start of a new serial bus. The main direction of the new bus to add new features to reduce the electrical cable so that it can be used for products, rather than to drive technology. Mercedes-Benz engineers from the early development of the state of the bus description, and Intel is also preparing for a major manufacturer of semiconductor production. One consultant was hired from Germany, Braunschweig-Wolfenbüttel University of Applied Science, Professor Dr. Wolfhard Lawrenz given the name of the new network program "Controller Area Network", referred to as CAN. From Karlsruhe University, Professor Dr. Horst Wettstein provides theoretical support.February 1986, CAN was born. In the Detroit Society of Automotive Engineers Congress, from Bosch to study the new bus system known as the "cars Serial Controller Area Network." Uwe Kiencke, Siegfried Dais and Martin Litschel introduced the program of the multi-master network. This program is based on non-destructive arbitration mechanism, to ensure high-priority packet delay-free transmission. Also, do not need to set the bus master controller. In addition, CAN Father - the few professors and Bosch's Wolfgang Borst, Wolfgang Botzenhard, Otto Karl, Helmut Schelling, Jan Unruh have achieved a number of species in the error detection mechanisms in CAN? The error detection but also fault node automatically disconnect feature to ensure continued communication between the remaining nodes. Transmission of messages not based on packet transmitter / receiver node address identification (almost true for the other bus), but by the content packet identification. Meanwhile, the identifier used to identify the message also provides the packet is the priority in the system.When this innovative communication solution on the majority of text in place, the mid-1987, Intel plans two months ahead of delivery of its first CAN controller: 82 526, this is the first time CAN hardware implementation of the program. In just four years time, vision becomes a reality. Soon after, Philips Semiconductors introduced the 82C200. This is the first of two CAN controller acceptance filtering and message control, there are many different. On the one hand, the main push of FullCAN Intel Philips Lord than by pushing BasicCAN takes less CPU load; the other hand, FullCAN device can receive a relatively limited number of messages, BasicCAN controller requires less silicon . Today's CAN controllers, the "grandchildren" generation are in the same module acceptance filtering and message control, there are still considerable differences, to create a BasicCAN and FullCAN camps.Standardization and consistency in early 1990, Bosch CAN standard (CAN 2.0 version) was submitted to the International Organization for Standardization. In a number of administrative discussion, should some of the major demands of the French automobile manufacturers to increase the "Vehicle Area Network (V AN)" content, and was published in November 1993 CAN international standard ISO11898. In addition to CAN agreement, it also provides up to 1Mbps baud rate of the physical layer. Meanwhile, the international standard ISO11519-2 also provides fault-tolerant CAN data transmission method. In 1995, the international standard ISO11898 was extended to the form described in Appendix 29 CAN identifiers. But sadly, all published in the CAN specification contain errors or incomplete. Therefore, in order to avoid incompatible CAN applications, Bosch CAN chip, the company has been carrying out verification whether the reference model based on Bosch's CAN workpiece. In addition, in recent years under the leadership of Professor in Lawrenz, in Germany Braunschweig / Wolfenbüttel University of Applied Science CAN conformance testing, test model is based on international standards, test standards ISO16845.Currently, amendments are being standardized in the CAN specification. ISO11898-1 as "CAN data link layer", ISO11898-2 as "non-fault-tolerant CAN physical layer", ISO11898-3 known as "fault-tolerant CAN physical layer." International standard ISO11992 (truck and trailer interface) and ISO11783 (agriculture and forestry machinery) are standard in the United States based on the J1939 CAN-based application of the definition of sub-agreements, but they are not complete. Although it had been a pioneer in the development of CAN，CAN starting point for research is applied to bus systems, but the first market application of CANbut from other areas. Particularly in Northern Europe, CAN has long been a very popular application.In the Netherlands, the elevator manufacturer Kone using CAN bus. Kvaser Swiss Engineering Office has proposed to apply to a number of textile-CAN (Lindauer Dornier and Sulzer), by providing them with machine protocol. This area, in the leadership of Lars-Berno Fredriksson, the company established a "CAN Textile Machinery user group." By 1989, they had developed communication theory, and in early 1990 to help build "CAN Kingdom" development environment. Although the CAN Kingdom is not an OSI reference model based on the application layer, but it is considered a high-level protocol based on CAN prototype. In the Netherlands, Philips Medical Systems decided to use X-ray machine CAN constitute the internal network, a CAN of industrial users. Released mainly by Tom Suters "Philips message specification - PMS" CAN network presented the first application layer. Weingarten of Applied Science from the German university professor, Dr. Konrad Etschberger also holds the same view. He managed Steinbeis Transfer Center for Process Automation (Stzp) company (now renamed IXXAT Automation Corporation), and developed a similar program. In any case, the first high-level agreement is taking shape.Most of the pioneer CAN use monolithic approach, communication, network management, application code combinations in the same software. Even if some users have more standard modules available, but the face of all solutions, they must also flawed. CAN must be sustained and stable development of high-level agreements - even today, some users still underestimate the problem. Earlier in 1990, began planning the establishment of a user organization to standardize the different solutions. Few months in early 1992, when the magazine's director of VMEbus (Press: Franzis) Holger Zeltwanger to users and manufacturers together to discuss the establishment of a neutral for the development of CAN technology platform, but also to analyze the market for the serial bus .May 1992, CiA "CAN in Automation" Users Group was established. Only a few weeks, CiA is a technology magazine published the first, which is on the physical layer. CiA recommends using only follow the ISO11898 of the CAN transceiver. Until now, at the time of the CAN network in use is very common but not compatible with RS-485 transceiver has basically disappeared, even though it is provided by the manufacturer. CiA is one of the first tasks of the provisions of CAN application layer.According to Philips Medical Systems (PMS) and Stzp provide content to rely on the assistance of the rest of CiA members, CAL - "CAN application layer" also known as the "Green Paper" was born. CAN application in the development of norms, CiA a major task for experts and other CAN CAN exchange of information between learners. Thus, since 1994, CiA CAN annual convening an international conference (iCC). Another theory is to draw on the LA V, an association of agricultural means of transport. Begin later in 1980, a vehicle based on CAN bus system of agriculture (LBS) to be worked out. But in the end work completed, the International Standardization Committee decided to solutions offered to support the US - J1939. It is also a CAN-based application of sub-agreement, by the SAE's Truck and Bus Association to develop. J1939 is a non-modular program, easy to learn, but very poor flexibility. From theory to practice, of course, produce an integrated CAN module 15 semiconductor device manufacturers mainly focus on the automotive industry.From mid-1990, Infineon and Motorola, the company's passenger car manufacturers in Europe have a large number of CAN controller. As the next wave, from the late 1990s, the Far East, semiconductor manufacturers have begun to offer CAN controllers. In 1994, NEC launched the legend in the CAN chip 72005, but this step too soon - the time, this device can not be put into use. Since 1992, Mercedes-Benz (Mercedes) started to use their advanced CAN bus technology. The first step by the use of electronic controllers to manage engine CAN; second step operation using the controller receives the signal people. This use of two physically separate CAN bus system, they connect through the gateway. Other bus companies have also come to learn in Stuttgart, in their passenger cars also use two sets of CAN bus system.Now, after V olvo, Saab, V olkswagen, BMW later, Renault and Fiat have also begun to use their vehicles CAN bus. Earlier in 1990, Ohio, mechanical engineering company engineers and Allen-Bradley Company, Honeywell micro switch started a joint venture project, the content is based on the CAN communication and control. However, soon after, a key member of the team left the joint venture terminated. But the Allen-Bradley Company and Honeywell to continue to engage in the work of their respective companies. This led to two high-level agreement: "Devicenet" and "Smart Distributed System (SDS)", and this two agreements in the lower layer is very similar to the communication layer. Earlier in 1994, Allen-Bradley DeviceNet specifications will be handed over to an organization dedicated to promote DeviceNet "OpenDeviceNet Vendor Association (ODV A)". And Honeywell were given up efforts in the SDS, making SDS more like Honeywell's internal solutions. DeviceNet tailored specifically for factory automation, therefore, making it similar to the Profibus-DP and Interbus agreement contender. If considered only from the plug and play functionality, DeviceNet has become the specific application in the field of leadership.In Europe, some companies try to use the CAL. Although the CAL in theory is correct, and can be put into application in industry, but each user must design a new sub-agreement, because CAL is a true application layer. CAL CAN can be seen as an application program necessary theoretical step, but it will not be promoting this area. Since 1993, the Esprit project ASPIC range, led by the European Association for Bosch developed a prototype, this developed into a CANopen. It is a CAL-based sub-protocol for internal network control product components. In theory, the Applied Science from the University of Reutlingen, Germany, Professor Dr. Gerhard Gruhler, and from Newcastle (UK) University Mohammed Farsi active participation of all is one one of the most successful activists. After completion of the project, CANopen specification CiA handed over to the organization, its maintenance and development. In 1995, CiA CANopen published a complete version of the communication sub-agreement; in just 5 years, it has become embedded in Europe's most important network standards. CANopen defines not only the application layer and communication sub-agreements for programmable systems, different device, interface, application sub-protocol defines the status page, which is the industry (such as: printers, maritime applications, medical systems) decided to use CANopen of an important reason. DeviceNet and CANopen, are located in two different markets the standard application layer protocol (EN 50325). DeviceNet for factory automation and control; CANopen is suitable for all mechanical embedded network. This has created two different application, therefore, necessary to define the application layer specification history (can be a lot of embedded systems specific exclusion).Although the CAN protocol CAN outlook has 15 years of history, but it is still in improving. Since 2000, a company formed by several mission organizations ISO defines a time-triggered CAN protocol packet transmission. Dr. Bernd Mueller, Thomas Fuehrer, Bosch company and the semiconductor industry experts, academic experts, this agreement is defined as "time-triggered communications, CAN (TTCAN)", plan for the future standard for the ISO11898-4. The CAN has been expansion of silicon to achieve, not only closed loop to support the time-triggeredmessage transmission, but also realize CAN of x-by-wire applications. Because the CAN protocol has not changed, so, in the same physical layer, transmission time can be achieved not only triggered messages can also be achieved to trigger the message transmission event. CAN TTCAN will extend the lifetime of 5-10 years. Now, CAN in the global market is still at the starting point, when taken seriously, the one can expect a CAN bus system in the next 10-15 years, the development trend. It should be emphasized that the reality: Over the past few years, the United States and the Far East manufacturers will be in their serial production of automotive components using CAN. In addition, a large number of potential new applications (eg: entertainment) is present - not only for passenger cars, can also be used for family consumption. Meanwhile, the combined application of high-level protocol on the CAN special security system is solid growth in demand. BIA Professional Committee of Germany and the German safety standards authority TÜV has a number of CAN-based security system has been certified. CANopen-Safety is first obtained permission of the CAN BIA solutions, DeviceNet-Safety will immediately follow. Global Rating Association one of the leaders, Germanischer Lloyd is preparing to propose to CANopen firmware used in maritime transport. In other matters, the specification defined by the network automatically switches to convert the redundant CANopen bus system.CAN list of historical events1983：Start of the Bosch internal project to develop an in-vehicle network1986：Official introduction of CAN protocol1987：First CAN controller chips from Intel and Philips Semiconductors1991：Bosch’s CAN specification 2.0 published1991：CAN Kingdom CAN-based higher-layer protocol introduced by Kvaser 1992：CAN in Automation international users and manufacturers group established1992：CAN Application Layer (CAL) protocol published by CiA1992：First cars from Mercedes-Benz used CAN network1993：ISO 11898 standard published1994：1st international CAN Conference (iCC) organized by CiA1994：Devicenet protocol introduction by Allen-Bradley1995：ISO 11898 amendment (extended frame format) published1995：CANopen protocol published by CiA2000：Development of the time-triggered communication protocol for CAN (TTCAN)1986年2月，Robert Bosch 公司在SAE（汽车工程协会）大会上介绍了一种新型的串行总线——CAN控制器局域网,那是CAN诞生的时刻。

《电子信息系统机房设计规范》GB50174-2008.

GB50174-2008电子信息系统机房设计规范1 总则1.0.1 为规范电子信息系统机房设计，确保电子信息系统设备安全、稳定、可靠地运行，做到技术先进、经济合理、安全适中、节能环保，制订本规范。

1.0.2 本规范适用于新建、改建和扩建建筑物中的电子信息系统机房设计。

1.0.3 电子信息系统机房的设计应遵循近期建设规模与远期发展规划协调一致的原则。

1.0.4 电子信息系统机房设计除应符合本规范外，尚应符合国家现行有关标准和规范的规定。

2 术语2.0.1 电子信息系统electronic information system由计算机、通信设备、处理设备、控制设备及其相关的配套设施构成，按照一定的应用目的和规则，对信息进行采集、加工、存储、传输、检索等处理的人机系统。

2.0.2 电子信息系统机房electronic information system room主要为电子信息设备提供运行环境的场所，可以是一幢建筑物或者建筑物的一部分，包括主机房、辅助区、支持区和行政管理区等。

2.0.3 主机房computer room主要用于电子信息处理、存储、交换和传输设备的安装和运行的建筑空间。

包括服务器机房、网络机房、存储机房等功能区域。

2.0.4 辅助区auxiliary room用于电子信息设备和软件的安装、调试、维护、运行监控和管理的场所，包括进线间、测试机房、监控中心、备件库、打印室、维修室等区域。

2.0.5 支持区support area支持并保障完成信息处理过程和必要的技术作业的场所，包括变配电室、柴油发电机房、UPS 室、电池室、空调机房、动力站房、消防设施用房、消防和安防控制室等。

2.0.6 行政管理区administrative area用于日常行政管理及客户对托管设备进行管理的场所，包括工作人员办公室、门厅、值班室、盥洗室、更衣间和用户工作室等。

2.0.7 场地设施infrastructure电子信息系统机房内，为电子信息系统提供运行保障的设施。

PC87366中文资料

PC87366 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game PortsGeneral DescriptionThe PC87366,a member of National Semiconductor’s 128-pin LPC SuperI/O family,combines National’s System Hardware Monitoring capability with a Musical Instrument Digital Interface (MIDI)Port and game port inputs for up to two joysticks.The PC87366is PC99and ACPI compliant,and offers a single-chip solution to the most commonly used PC I/O peripherals.System Hardware Monitoring provides minimum power con-sumption and maximum operating efficiency within the system environment.It integrates National’s diode-based or thermistor-based Temperature Sensor (TMS)with National’s Voltage Lev-el Monitor (VLM)for full,PC system thermal control.The PC87366monitors system voltages using 8-bit Analog to Dig-ital (A/D)conversion with seven analog input channels and four internal measuring points.The PC87366also incorporates:Fan Speed Control and Monitor (FSCM)for three fans,extended wake-up support for a wide range of wake-up events,system design protection features,a Floppy Disk Controller (FDC),a Keyboard and Mouse Controller (KBC),a full IEEE 1284Parallel Port,two enhanced Serial Ports (UARTs),one with Infrared (IR)sup-port,ACCESS.bus ®Interface (ACB),System Wake-Up Control (SWC),General-Purpose Input/Output (GPIO)sup-port for 40ports,Interrupt Serializer for Parallel IRQs and an enhanced WATCHDOG ™ timer (WDT).Outstanding FeaturesqSystem Hardware Monitoring including:—Diode-based or thermistor-based T emperature Sen-sor (TMS)—Voltage Level Monitor (VLM) with VID inputs q MIDI interface compatible with MPU-401UART mode q Game port inputs for up to two joysticksqExtended Wake-Up support,including legacy/ACPI power button support,direct power supply control in response to wake-up events,power-fail recovery qProtection features,including chassis intrusion detection,GPIO lock and pin configuration lockq Fan Speed Control and Monitor for three fans q Serial IRQ support (15options)q Interrupt Serializer (11Parallel IRQs to Serial IRQ)qBus interface,based on Intel’s LPC Interface Speciﬁ-cation Revision 1.0,September 29th,1997q ACCESS.bus interface,SMBus physical layer compatible q40GPIO Ports (29standard,including 15with Assert IRQ/SMI/PWUREQs interrupts;11V SB -powered)q Blinking LEDsq128-pin PQFP PackageBlock DiagramSystem Wake-UpSerial Port 2IEEE 1284Parallel PortPorts Keyboard &Mouse I/F SCL ACCESS.bus Floppy Disk ControllerFloppy Drive InterfaceKeyboard &Serial Infrared Interface InterfaceControl Bus InterfaceLPC Interface I/O3 Control WATCHDOGTimer WDOSerial Port 1Serial InterfaceOutputs Fan Speed Control & Monitor Interface Mouse Controllerwith IRGPIO Ports3 Monitor InputsSDA Serial IRQ Analog Inputs System Parallel Port Interface Diode InterfaceSMI PortsHardware MonitoringV REF MIDIInterface MIDI &Game PortsGame Inputs Wake-Up EventsPWUREQ Power Control V DD V BdAT V SBAV DD ACCESS.bus® is a registered trademark of Digital Equipment Corporation.I2C® is a registered trademark of Philips Corporation.IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.Microsoft® and Windows® are registered trademarks of Microsoft Corporation.TRI-STATE® is a registered trademark of National Semiconductor Corporation.WATCHDOG‰ is a trademark of National Semiconductor Corporation.SMBus® is a registered trademark of Intel Corporation.© 1999 National Semiconductor CorporationPRELIMINARYJanuary 11,1999PC87366128-Pin LPC SuperI/O with System Hardware Monitoring,MIDI and Game PortsFeatures•Voltage Level Monitor (VLM)—Seven analog inputs that can support both positive and negative voltages—Four internal measuring points—Three thermistor-based temperature monitoring channels—Internal or external V REF—VID inputs—Meets ACPI and DMI requirements for system volt-age monitoring•Temperature Sensor (TMS)—Up to two remote diode inputs—Environment temperature sensing via an internal di-ode—A/D analog channels provide thermal inputs to di-rectly sense die temperature of remote diodes —Meets ACPI and DMI requirements for thermal man-agement—Standby mode to minimize power consumption •Extended Wake-Up—Legacy and ACPI power button support—Direct power supply control in response to wake-up events—Power-fail recovery•Musical Instrument Digital Interface (MIDI) Port —Compatible with MPU-401 UART mode—16-byte Receive and T ransmit FIFOs—Loopback mode supportq Game Port—Full digital implementation—Supports up to two analog joysticks •Protection—Chassis intrusion detection (CHASI, CHASO)—GPIO lock—Pin conﬁguration lock•40 General-Purpose I/O (GPIO) Ports—29standard,with Assert IRQ/SMI/PWUREQ for15 ports—11 V SB-powered—Programmable drive type for each output pin(open-drain, push-pull or output disable)—Programmable option for internal pull-up resistor on each input pin—Output lock option—Input debounce mechanism•Fan Speed Control and Fan Speed Monitor (FSCM)—Supports different fan types—Speed monitoring for three fanst Digital ﬁltering of the tachometer input signalt Alarm for fan slower than programmable thresh-old speedt Alarm for fan stop—Three speed control lines with Pulse Width Modula-tion (PWM)t Output signal in the range of 6 Hz to 93.75 KHzt Duty cycle resolution of 1/256•LPC System Interface—Synchronous cycles, up to 33 MHz bus clock—8-bit I/O cycles—Up to four DMA channels—8-bit DMA cycles—Basic read,write and DMA bus cycles are13clock cycles long•PC99 and ACPI Compliant—PnP Conﬁguration Register structure—Flexible resource allocation for all logical devices t Relocatable base addresst15 IRQ routing optionst4optional8-bit DMA channels(where applicable)•Floppy Disk Controller (FDC)—Programmable write protect—FM and MFM mode support—Enhanced mode command for three-mode Floppy Disk Drive (FDD) support—Perpendicular recording drive support for 2.88 MB—Burst and non-burst modes—Full support for IBM T ape Drive register(TDR)im-plementation of AT and PS/2 drive types—16-byte FIFO—Software compatible with the PC8477,which con-tains a superset of the FDC functions in themicroDP8473,the NEC microPD765A and theN82077—High-performance, digital separator—Standard 5.25” and 3.5” FDD support•Parallel Port—Software or hardware control—Enhanced Parallel Port(EPP)compatible with new version EPP 1.9 and IEEE 1284 compliant—EPP support for version EPP1.7of the Xircom spec-iﬁcation—EPP support as mode4of the Extended Capabilities Port (ECP)—IEEE 1284 compliant ECP, including level 2—Selection of internal pull-up or pull-down resistor for Paper End (PE) pin—PCI bus utilization reduction by supporting a de-mand DMA mode mechanism and a DMA fairnessmechanism—Protection circuit that prevents damage to the paral-lel port when a printer connected to it powers up oris operated at high voltages,even if the device is inpower-down—Output buffers that can sink and source 14 mA•Serial Port 1 (UART1)—Software compatible with the 16550A and the 164502Features(Continued)3—Shadow register support for write-only bit monitoring —UART data rates up to 1.5 Mbaud•Serial Port 2 with Infrared (UART2)—Software compatible with the 16550A and the 16450—Shadow register support for write-only bit monitoring —UART data rates up to 1.5 Mbaud —HP-SIR—ASK-IR option of SHARP-IR —DASK-IR option of SHARP-IR—Consumer Remote Control supports RC-5,RC-6,NEC, RCA and RECS 80—Non-standard DMA support −1 or 2 channels —PnP dongle support •Keyboard and Mouse Controller (KBC)—8-bit microcontroller—Software compatible with the 8042AH and PC87911microcontrollers— 2 KB custom-designed program ROM —256 bytes RAM for data—Five programmable dedicated open-drain I/O lines —Asynchronous access to two data registers and onestatus register during normal operation —Support for both interrupt and polling —93 instructions —8-bit timer/counter—Support for binary and BCD arithmetic—Operation at 8MHz,12MHz or 16MHz (programma-ble option)—Can be customized by using the PC87323,which in-cludes a RAM-based KBC as a development plat-form for KBC code•ACCESS.bus Interface (ACB)—Serial interface compatible with SMBus physical layer —Compatible with Philips’ I 2C ®—ACB master and slave—Supports polling and interrupt controlled operation —Optional internal pull-up on SDA and SCL pins•WATCHDOG Timer (WDT)—Times out the system based on user-programmabletime-out period—System power-down capability for power saving —User-deﬁned trigger events to restart WATCHDOG —Optional routing of WATCHDOG output on IRQand/or SMI lines•System Wake-Up Control (SWC)—Power-up request upon detection of Keyboard,Mouse,RI1,RI2,RING activity and General-Pur-pose Input Events, as follows:t Preprogrammed Keyboard or Mouse sequence t External modem ring on serial portt Ring pulse or pulse train on the RING input signal t Preprogrammed CEIR address in a preselectedstandard (NEC, RCA or RC-5)t General-Purpose Input Events t IRQs of internal logical devices —Optional routing of power-up request on IRQ,SMIand/or PWBTOUT—Battery-backed event conﬁguration—Programmable V SB -powered output for blinkingLEDs (LED1, LED2) control•Clock Sources—48 MHz clock input—LPC clock, up to 33 MHz—On-chip low frequency clock generator for wake-up•Power Supplies— 3.3V supply operation —Main (V DD and AV DD )—Standby (V SB )—Battery backup (V BA T )—All pins are 5V tolerant and back-drive protected,ex-cept LPC bus pins•Strap Configuration—Base Address (BADDR)strap to determine the baseaddress of the Index-Data register pair—T est strap to force the device into test mode (re-served for National Semiconductor use)—Power Supply and LED Conﬁguration (PSLDC0,1)straps to determine the power suppy control func-tions and the V SB power-up defaults of LED2—Power Supply On Polarity (PSONPOL)strap to setPSON active state and output typeDatasheet Revision RecordRevision Date Status CommentsNovember1998Draft0.3Speciﬁcation subject to change without notice;MIDI andGame Port information is incompleteJanuary1999Preliminary1.0Speciﬁcation subject to change without notice;PowerSupply Control and LED sections in Chapter2areincompleteItem Topic Change/Correction Location 4Table of ContentsDatasheet Revision Record (4) (4)1.0Signal/Pin Connection and Description1.1CONNECTION DIAGRAM (16)1.2BUFFER TYPES AND SIGNAL/PIN DIRECTORY (17)1.3PIN MULTIPLEXING (22)1.4DETAILED SIGNAL/PIN DESCRIPTIONS (24)1.4.1ACCESS.bus Interface (ACB) (24)1.4.2Bus Interface (24)1.4.3Clock (24)1.4.4Fan Speed Control and Monitor (FSCM) (24)1.4.5Floppy Disk Controller (FDC) (25)1.4.6Game Port (26)1.4.7General-Purpose Input/Output (GPIO) Ports (26)1.4.8Infrared (IR) (26)1.4.9Keyboard and Mouse Controller (KBC) (27)1.4.10Musical Instrument Digital Interface (MIDI) Port (27)1.4.11Parallel Port (28)1.4.12Power and Ground (28)1.4.13Protection (29)1.4.14Serial Port 1 and Serial Port 2 (29)1.4.15Strap Configuration (30)1.4.16System Hardware Monitoring (30)1.4.17System Wake-Up Control (31)1.4.18WATCHDOG Timer (WDT) (31)1.5INTERNAL PULL-UP AND PULL-DOWN RESISTORS (32)2.0Device Architecture and Configuration2.1OVERVIEW (34)2.2CONFIGURATION STRUCTURE AND ACCESS (34)2.2.1The Index-Data Register Pair (34)2.2.2Banked Logical Device Registers Structure (36)2.2.3Standard Logical Device Configuration Register Definitions (37)2.2.4Standard Configuration Registers (39)2.2.5Default Configuration Setup (40)2.2.6Power States (40)2.2.7Address Decoding (41)2.3PROTECTION (41)2.3.1Chassis Intrusion Detection (41)2.3.2Pin Configuration Lock (41)2.3.3GPIO Pin Function Lock (42)2.4POWER SUPPLY CONTROL (PSC) (42)2.5LED OPERATION AND STATES (44)2.6POWER SUPPLY CONTROL AND LED CONFIGURATION (44)2.7REGISTER TYPE ABBREVIATIONS (45)2.8SUPERI/O CONFIGURATION REGISTERS (45)2.8.1SuperI/O ID Register (SID) (46)2.8.2SuperI/O Configuration 1 Register (SIOCF1) (46)2.8.3SuperI/O Configuration 2 Register (SIOCF2) (47)2.8.4SuperI/O Configuration 3 Register (SIOCF3) (48)2.8.5SuperI/O Configuration 4 Register (SIOCF4) (49)2.8.6SuperI/O Configuration 5 Register (SIOCF5) (50)2.8.7SuperI/O Revision ID Register (SRID) (50)2.8.8SuperI/O Configuration 8 Register (SIOCF8) (51)2.8.9SuperI/O Configuration A Register (SIOCFA) (52)2.8.10SuperI/O Configuration B Register (SIOCFB) (53)2.8.11SuperI/O Configuration C Register (SIOCFC) (54)2.8.12SuperI/O Configuration D Register (SIOCFD) (55)2.9FLOPPY DISK CONTROLLER (FDC) CONFIGURATION (56)2.9.1General Description (56)2.9.2Logical Device 0 (FDC) Configuration (56)2.9.3FDC Configuration Register (57)2.9.4Drive ID Register (58)2.10PARALLEL PORT CONFIGURATION (59)2.10.1General Description (59)2.10.2Logical Device 1 (PP) Configuration (60)2.10.3Parallel Port Configuration Register (60)2.11SERIAL PORT 2 CONFIGURATION (61)2.11.1General Description (61)2.11.2Logical Device 2 (SP2) Configuration (61)2.11.3Serial Port 2 Configuration Register (61)2.12SERIAL PORT 1 CONFIGURATION (62)2.12.1Logical Device 3 (SP1) Configuration (62)2.12.2Serial Port 1 Configuration Register (62)2.13SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION (63)2.13.1Logical Device 4 (SWC) Configuration (63)2.14KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION (64)2.14.1General Description (64)2.14.2Logical Devices 5 and 6 (Mouse and Keyboard) Configuration (65)2.14.3KBC Configuration Register (66)2.15GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION (67)2.15.1General Description (67)2.15.2Implementation (67)2.15.3Logical Device 7 (GPIO) Configuration (68)2.15.4GPIO Pin Select Register (69)2.15.5GPIO Pin Configuration Register (70)2.15.6GPIO Event Routing Register (71)62.16ACCESS.BUS INTERFACE (ACB) CONFIGURATION (72)2.16.1General Description (72)2.16.2Logical Device 8 (ACB) Configuration (72)2.16.3ACB Configuration Register (73)2.17FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION (74)2.17.1General Description (74)2.17.2Logical Device 9 (FSCM) Configuration (74)2.17.3Fan Speed Control and Monitor Configuration 1 Register (75)2.17.4Fan Speed Control and Monitor Configuration 2 Register (76)2.17.5Fan Speed Control OTS Configuration Register (76)2.18WATCHDOG TIMER (WDT) CONFIGURATION (77)2.18.1Logical Device 10 (WDT) Configuration (77)2.18.2WATCHDOG Timer Configuration Register (77)2.19GAME PORT (GMP) CONFIGURATION (78)2.19.1Logical Device 11 (GMP) Configuration (78)2.19.2Game Port Configuration Register (78)2.20MIDI PORT (MIDI) CONFIGURATION (79)2.20.1Logical Device 12 (MIDI) Configuration (79)2.20.2MIDI Port Configuration Register (79)2.21VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION (80)2.21.1Logical Device 13 (VLM) Configuration (80)2.22TEMPERATURE SENSOR (TMS) CONFIGURATION (80)2.22.1Logical Device 14 (TMS) Configuration (80)3.0System Wake-Up Control (SWC)3.1OVERVIEW (81)3.2FUNCTIONAL DESCRIPTION (82)3.3EVENT DETECTION (83)3.3.1Modem Ring (83)3.3.2Telephone Ring (83)3.3.3Keyboard and Mouse Activity (84)3.3.4CEIR Address (84)3.3.5Standby General-Purpose Input Events (84)3.3.6GPIO-Triggered Events (84)3.3.7Software Event (84)3.3.8Module IRQ Wake-Up Event (85)3.4SWC REGISTERS (85)3.4.1SWC Register Map (85)3.4.2Wake-Up Events Status Register 0 (WK_STS0) (88)3.4.3Wake-Up Events Status Register (WK_STS1) (89)3.4.4Wake-Up Events Enable Register (WK_EN0) (90)3.4.5Wake-Up Events Enable Register 1 (WK_EN1) (91)3.4.6Wake-Up Configuration Register (WK_CFG) (92)3.4.7Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0) (93)3.4.8Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1) (94)3.4.9Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0) (95)3.4.10Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1) (96)3.4.11Wake-Up Extension 1 Enable Register 0 (WK_X1EN0) (97)3.4.12Wake-Up Extension 1 Enable Register 1 (WK_X1EN1) (98)3.4.13Wake-Up Extension 2 Enable Register 0 (WK_X2EN0) (99)3.4.14Wake-Up Extension 2 Enable Register 1 (WK_X2EN1) (100)3.4.15Wake-Up Extension 3 Enable Register 0 (WK_X3EN0) (101)3.4.16Wake-Up Extension 3 Enable Register 1 (WK_X3EN1) (102)3.4.17PS/2 Keyboard and Mouse Wake-Up Events (103)3.4.18PS/2 Protocol Control Register (PS2CTL) (104)3.4.19Keyboard Data Shift Register (KDSR) (104)3.4.20Mouse Data Shift Register (MDSR) (105)3.4.21PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) (105)3.4.22CEIR Wake-Up Control Register (IRWCR) (106)3.4.23CEIR Wake-Up Address Register (IRWAD) (107)3.4.24CEIR Wake-Up Address Mask Register (IRWAM) (107)3.4.25CEIR Address Shift Register (ADSR) (108)3.4.26CEIR Wake-Up Range 0 Registers (108)3.4.27CEIR Wake-Up Range 1 Registers (109)3.4.28CEIR Wake-Up Range 2 Registers (109)3.4.29CEIR Wake-Up Range 3 Registers (110)3.4.30Standby General-Purpose I/O (SBGPIO) Register Overview (111)3.4.31Standby GPIO Pin Select Register (SBGPSEL) (114)3.4.32Standby GPIO Pin Configuration Register (SBGPCFG) (115)3.4.33Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0) (117)3.4.34Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0) (117)3.4.35Standby GPOS Data Out Register 1 (SB_GPDO1) (118)3.4.36Standby GPIS Data In Register 1 (SB_GPDI1) (118)3.5SWC REGISTER BITMAP (119)4.0Fan Speed Control4.1OVERVIEW (123)4.2FUNCTIONAL DESCRIPTION (123)4.3FAN SPEED CONTROL REGISTERS (124)4.3.1Fan Speed Control Register Map (124)4.3.2Fan Speed Control Pre-Scale Register (FCPSR) (124)4.3.3Fan Speed Control Duty Cycle Register (FCDCR) (125)4.4FAN SPEED CONTROL BITMAP (125)5.0Fan Speed Monitor5.1OVERVIEW (126)5.2FUNCTIONAL DESCRIPTION (126)5.3FAN SPEED MONITOR REGISTERS (127)5.3.1Fan Speed Monitor Register Map (127)85.3.2Fan Monitor Threshold Register (FMTHR) (128)5.3.3Fan Monitor Speed Register (FMSPR) (128)5.3.4Fan Monitor Control and Status Register (FMCSR) (128)5.4FAN SPEED MONITOR BITMAP (129)6.0General-Purpose Input/Output (GPIO) Port6.1OVERVIEW (130)6.2BASIC FUNCTIONALITY (131)6.2.1Configuration Options (131)6.2.2Operation (131)6.3EVENT HANDLING AND SYSTEM NOTIFICATION (132)6.3.1Event Configuration (132)6.3.2System Notification (132)6.4GPIO PORT REGISTERS (133)6.4.1GPIO Pin Configuration (GPCFG) Register (134)6.4.2GPIO Pin Event Routing (GPEVR) Register (135)6.4.3GPIO Port Runtime Register Map (135)6.4.4GPIO Data Out Register (GPDO) (136)6.4.5GPIO Data In Register (GPDI) (136)6.4.6GPIO Event Enable Register (GPEVEN) (137)6.4.7GPIO Event Status Register (GPEVST) (137)7.0WATCHDOG Timer (WDT)7.1OVERVIEW (138)7.2FUNCTIONAL DESCRIPTION (138)7.3WATCHDOG TIMER REGISTERS (139)7.3.1WATCHDOG Timer Register Map (139)7.3.2WATCHDOG Timeout Register (WDTO) (139)7.3.3WATCHDOG Mask Register (WDMSK) (140)7.3.4WATCHDOG Status Register (WDST) (141)7.4WATCHDOG TIMER REGISTER BITMAP (141)8.0ACCESS.bus Interface (ACB)8.1OVERVIEW (142)8.2FUNCTIONAL DESCRIPTION (142)8.2.1Data Transactions (142)8.2.2Start and Stop Conditions (142)8.2.3Acknowledge (ACK) Cycle (143)8.2.4Acknowledge after Every Byte Rule (144)8.2.5Addressing Transfer Formats (144)8.2.6Arbitration on the Bus (144)8.2.7Master Mode (145)8.2.8Slave Mode (147)8.2.9Configuration (147)8.3ACB REGISTERS (148)8.3.1ACB Register Map (148)8.3.2ACB Serial Data Register (ACBSDA) (148)8.3.3ACB Status Register (ACBST) (149)8.3.4ACB Control Status Register (ACBCST) (150)8.3.5ACB Control Register 1 (ACBCTL1) (151)8.3.6ACB Own Address Register (ACBADDR) (152)8.3.7ACB Control Register 2 (ACBCTL2) (152)8.4ACB REGISTER BITMAP (153)9.0Game Port (GMP)9.1OVERVIEW (154)9.2FUNCTIONAL DESCRIPTION (154)9.2.1Game Device Axis Position Indication (154)9.2.2Capturing the Position (155)9.2.3Button Status Indication (156)9.2.4Operation Modes (156)9.2.5Operation Control (157)9.3GAME PORT REGISTERS (158)9.3.1Game Port Register Map (158)9.3.2Game Port Control Register (GMPCTL) (159)9.3.3Game Port Legacy Status Register (GMPLST) (160)9.3.4Game Port Extended Status Register (GMPXST) (161)9.3.5Game Port Interrupt Enable Register (GMPIEN) (162)9.3.6Game Device A X-Axis Position Low Byte (GMPAXL) (163)9.3.7Game Device A X-Axis Position High Byte (GMPAXH) (163)9.3.8Game Device A YAxis Position Low Byte (GMPAYL) (163)9.3.9Game Device A Y-Axis Position High Byte (GMPAYH) (163)9.3.10Game Device B X-Axis Position Low Byte (GMPBXL) (164)9.3.11Game Device B X-Axis Position High Byte (GMPBXH) (164)9.3.12Game Device B Y-Axis Position Low Byte (GMPBYL) (164)9.3.13Game Device B Y-Axis Position High Byte (GMPBYH) (164)9.3.14Game Port Event Polarity Register (GMPEPOL) (165)9.4GAME PORT BITMAP (166)10.0Musical Instrument Digital Interface (MIDI) Port10.1OVERVIEW (167)10.2FUNCTIONAL DESCRIPTION (167)10.2.1Internal Bus Interface Unit (168)10.2.2Port Control and Status Registers (168)10.2.3Data Buffers and FIFOs (168)10.2.4MIDI Communication Engine (168)10.2.5MIDI Signals Routing Control Logic (169)10.2.6Operation Modes (169)10.2.7MIDI Port Status Flags (170)1010.2.8MIDI Port Interrupts (171)10.2.9Enhanced MIDI Port Features (172)10.3MIDI PORT REGISTERS (173)10.3.1MIDI Port Register Map (173)10.3.2MIDI Data In Register (MDI) (173)10.3.3MIDI Data Out Register (MDO) (173)10.3.4MIDI Status Register (MSTAT) (174)10.3.5MIDI Command Register (MCOM) (174)10.3.6MIDI Control Register (MCNTL) (175)10.4MIDI PORT BITMAP (176)11.0Voltage Level Monitor (VLM)11.1OVERVIEW (177)11.2FUNCTIONAL DESCRIPTION (177)11.2.1Voltage Measurement, Channels 0 through 10 (178)11.2.2Thermistor-Based Temperature Measurement, Channels 11 to 13 (179)11.2.3 V OS, V HIGH and V LOW Limits, OTS and ALERT Output, IRQ and SMI (179)11.2.4Power-On Reset Default States (180)11.2.5Standby Mode (180)11.3ANALOG SUPPLY CONNECTION (180)11.3.1Recommendations (180)11.3.2Reference Voltage (181)11.4REGISTER BANK OVERVIEW (181)11.5VLM REGISTERS (182)11.5.1VLM Register Map (182)11.5.2Voltage Event Status Register 0 (VEVSTS0) (183)11.5.3Voltage Event Status Register 1 (VEVSTS1) (183)11.5.4Voltage Event to SMI Register 0 (VEVSMI0) (184)11.5.5Voltage Event to SMI Register 1 (VEVSMI1) (185)11.5.6Voltage Event to IRQ Register 0 (VEVIRQ0) (186)11.5.7Voltage Event to IRQ Register 1 (VEVIRQ1) (186)11.5.8Voltage ID Register (VID) (187)11.5.9Voltage Conversion Rate Register (VCNVR) (188)11.5.10VLM Configuration Register (VLMCFG) (189)11.5.11VLM Bank Select Register (VLMBS) (189)11.5.12Voltage Channel Configuration and Status Register (VCHCFST) (190)11.5.13Read Channel Voltage Register (RDCHV) (191)11.5.14Channel Voltage High Limit Register (CHVH) (191)11.5.15Channel Voltage Low Limit Register (CHVL) (191)11.5.16Overtemperature Shutdown Limit Register (OTSL) (191)11.6VLM REGISTER BITMAP (192)11.6.1VLM Control and Status Registers (192)11.6.2VLM Channel Registers (192)11.7USAGE HINTS (193)11.7.2Measuring Out of Range Positive and Negative Voltages (194)12.0Temperature Sensor (TMS)12.1OVERVIEW (195)12.2FUNCTIONAL DESCRIPTION (195)12.2.1Register Bank Overview (196)12.2.2T OS, T HIGH and T LOW Limits, OTS and ALERT Output, IRQ and SMI (196)12.2.3ALERT Response Read Sequence (197)12.2.4Power-On Reset Default States (197)12.2.5Temperature Data Format (198)12.2.6Standby Mode (198)12.2.7Diode Fault Detection (198)12.3TMS REGISTERS (199)12.3.1TMS Register Map (199)12.3.2Temperature Event Status Register (TEVSTS) (200)12.3.3Temperature Event to SMI Register (TEVSMI) (201)12.3.4Temperature Event to IRQ Register (TEVIRQ) (202)12.3.5TMS Configuration Register (TMSCFG) (203)12.3.6TMS Bank Select Register (TMSBS) (203)12.3.7Temperature Channel Configuration and Status Register (TCHCFST) (204)12.3.8Read Channel Temperature Register (RDCHT) (205)12.3.9Channel Temperature High Limit Register (CHTH) (205)12.3.10Channel Temperature Low Limit Register (CHTL) (205)12.3.11Channel Overtemperature Limit Register (CHOTL) (205)12.4TMS REGISTER BITMAP (206)12.4.1TMS Control and Status Registers (206)12.4.2TMS Channel Registers (206)12.5USAGE HINTS (206)12.5.1Remote Diode Selection (206)12.5.2ADC Noise Filtering (207)12.5.3PC Board Layout (207)12.5.4Twisted Pair and Shielded Cables (209)13.0Legacy Functional Blocks13.1KEYBOARD AND MOUSE CONTROLLER (KBC) (210)13.1.1General Description (210)13.1.2KBC Register Map (210)13.1.3KBC Bitmap Summary (210)13.2FLOPPY DISK CONTROLLER (FDC) (211)13.2.1General Description (211)13.2.2FDC Register Map (211)13.2.3FDC Bitmap Summary (212)13.3PARALLEL PORT (213)13.3.1General Description (213)13.3.3Parallel Port Bitmap Summary (214)13.4UART FUNCTIONALITY (SP1 AND SP2) (216)13.4.1General Description (216)13.4.2UART Mode Register Bank Overview (216)13.4.3SP1 and SP2 Register Maps for UART Functionality (217)13.4.4SP1 and SP2 Bitmap Summary for UART Functionality (219)13.5IR FUNCTIONALITY (SP2) (221)13.5.1General Description (221)13.5.2IR Mode Register Bank Overview (221)13.5.3SP2 Register Map for IR Functionality (222)13.5.4SP2 Bitmap Summary for IR Functionality (223)14.0Device Characteristics14.1GENERAL DC ELECTRICAL CHARACTERISTICS (225)14.1.1Recommended Operating Conditions (225)14.1.2Absolute Maximum Ratings (225)14.1.3Capacitance (225)14.1.4Power Consumption under Recommended Operating Conditions (226)14.2DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES (226)14.2.1Input, CMOS Compatible (226)14.2.2Input, PCI 3.3V (226)14.2.3Input, SMBus Compatible (227)14.2.4Input, Strap Pin (227)14.2.5Input, TTL Compatible (227)14.2.6Input, TTL Compatible with Schmitt Trigger (227)14.2.7Output, PCI 3.3V (228)14.2.8Output, Totem-Pole Buffer (228)14.2.9Output, Open-Drain Buffer (228)14.2.10Input, Analog (228)14.2.11Input, Analog (228)14.2.12Input, Analog (229)14.2.13Output, Analog (229)14.2.14Output, Analog (229)14.2.15Exceptions (229)14.3INTERNAL RESISTORS (230)14.3.1Pull-Up Resistor (230)14.3.2Pull-Down Resistor (230)14.4ANALOG CHARACTERISTICS (230)14.4.1VLM (230)14.4.2TMS (230)14.5AC ELECTRICAL CHARACTERISTICS (232)14.5.1AC Test Conditions (232)14.5.2Clock Timing (232)14.5.3LCLK and LRESET (233)14.5.5Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing (235)14.5.6Modem Control Timing (236)14.5.7FDC Write Data Timing (236)14.5.8FDC Drive Control Timing (237)14.5.9FDC Read Data Timing (237)14.5.10Standard Parallel Port Timing (238)14.5.11Enhanced Parallel Port Timing (238)14.5.12Extended Capabilities Port (ECP) Timing (239)。

Fault-tolerant systems

we have applied several improvement: we
ideas. First, we use an algorithmic rent number of particles.
recombination of most particles. To study the kinetics of these large numbers of interacting particles, a full Monte Carlo simulation of their movements is needed. One of the main points of interest is computing the number of ions that escape from the high-energy electron tracks. To be able to simulate the movements of the positive ions and the thermalized initial spatial distribution obtain information by comparing electrons, an of these particles must be and
b Department of Physics and Astronomy, Vrije Universiteit, De Boelelaan 1081, 1081 HV Amsterdam, Netherlands
Abstract
Ion recombination in nonpolar liquids is an important problem in radiation chemistry. We have designed and implemented a parallel Monte Carlo simulation for this computationally intensive task on a network of workstations. The main problem with parallelizing this application is that the amount of work performed by each process decreases during execution, resulting in high communication overhead and load imbalances. We address this problem by dynamically adjusting the number of processors that are used. We have evaluated the performance of the parallel program on two systems, one using Ethernet and the other using Myrinet. On Ethernet, the program suffers from a large communication overhead. Using the Myrinet

《电子信息系统机房设计规范》GB50174-2008要点

1.0.2 本规范适用于新建、改建和扩建建筑物中的电子信息系统机房设计。

1.0.3 电子信息系统机房的设计应遵循近期建设规模与远期发展规划协调一致的原则。

1.0.4 电子信息系统机房设计除应符合本规范外，尚应符合国家现行有关标准和规范的规定。

2.0.3 主机房computer room主要用于电子信息处理、存储、交换和传输设备的安装和运行的建筑空间。

包括服务器机房、网络机房、存储机房等功能区域。

2.0.7 场地设施infrastructure电子信息系统机房内，为电子信息系统提供运行保障的设施。

科技英语翻译专业词汇-控制和生医

Automation and Controllingsensor 传感器sufficient and necessary condition 充要条件dry friction 静摩擦follower 跟随器，输出放大器，从动轮，跟踪装置integral 积分duty 工作状态FM(frequency modulation ) 调频Geometry 几何(学)autopilot 自动驾驶仪forced response 强迫响应performance index 性能指数performance specification 性能指标polar plot 极坐标图trial and error 试探法Bar Code 条形码Bill of Materials (BOM) 物料清单CAD (Computer Aided Design) 计算机辅助设计CAM (Computer Aided Manufacturing) 计算机辅助制造Computer Integrated Manufacturing (CIM) 计算机集成制造CMOS (Complimentary Metal-Oxide-Semiconductor) n. 互补金属氧化物半导体——一种应用于大规模集成电路芯片制造的原料）是微机主板上的一块可读写的RAM芯片，用来保存当前系统的硬件配置和用户对某些参数的设定。

ControlNet 控制网，一种高速串行通信系统，适用于需要进行实时应用信息交换的设备之间的通讯。

conveyor 传送带DAC (Digital-to-Analog Converter) 数字模拟信号转换器Data Acquisition 数据采集Fiber Optics 光纤Fieldbus 现场总线Ethernet 以太网GUI (Graphical User Interface) 图形用户界面programming language 程序设计语言program debugger 程序调试器direct current dynamo 直流发电机kinetic energy 动能automatization 自动化human-simulating-intelligent control 仿人工智能控制reference frame 参考系servo 伺服机构extrusion 挤压billet 胚料dual 对偶的，二元的，二体的，双的actuator 激励源（如电流源、电压源）；致动器AS-I (Actuator-Sensor Interface) 执行器传感器接口Analog Input Module 模拟信号输入模块Analog Output Module 模拟信号输出模块Brushless Servomotor 无电刷伺服电机Crossdocking 直接转运，一项使产品组合顺利进行的作业。

《电子信息系统机房设计规范》GB_50174-2008

《电子信息系统机房设计规范》GB 50174-2008GB50174-2008电子信息系统机房设计规范Code for Design of Electronic Information System Room 目次1总则(1)2术语(2)3机房分级与性能要求(6)3.1机房分级(6)3.2性能要求(6)4机房位置及设备布置(7)4.1机房位置选择(7)4.2机房组成(7)4.3设备布置(8)5环境要求(9)5.1温度、相对湿度及空气含尘浓度(9)5.2噪声、电磁干扰、振动及静电(9)6建筑与结构(1 o)6.1一般规定(1 o)6.2人流、物流及出入口(1 0)6.3防火和疏散(1 1)6.4室内装修(1 1)7空气调节(1 3)7.1一般规定(1 3)7.2负荷计算(1 3)7.3气流组织(1 4)7.4系统设计(1 4)7.5设备选择(1 6)8电气(1 7)8.1供配电(1 7)8.2照明(1 8)8.3静电防护(2 0)8.4防雷与接地(2 0)9电磁屏蔽(2 2)9.1一般规定(2 2)9.2结构型式(2 2)9.3屏蔽件(2 3)10机房布线(2 4)11机房监控与安全防范(2 6) 11.1一般规定(2 6)11.2环境和设备监控系统(2 6) 11.3安全防范系统(2 7)12给水排水(2 8)12.1一般规定(2 8)12.2管道敷设(2 8)13消防(2 9)13.1一般规定(2 9)13.2消防设施(2 9)13.3安全措施(3 0)附录A各级电子信息系统机房技术要求(31)本规范用词说明(3 8)附：条文说明(3 9)1 总则1.0.1 为规范电子信息系统机房设计，确保电子信息系统设备安全、稳定、可靠地运行，做到技术先进、经济合理、安全适中、节能环保，制订本规范。

1.0.2 本规范适用于新建、改建和扩建建筑物中的电子信息系统机房设计。

1.0.3 电子信息系统机房的设计应遵循近期建设规模与远期发展规划协调一致的原则。

FAULT-TOLERANT SYNCHRONISATION DEVICE FOR A REAL-T

专利名称：FAULT-TOLERANT SYNCHRONISATION DEVICE FOR A REAL-TIME COMPUTERNETWORK发明人：TOILLON, PATRICE,COLAS, GERARD申请号：EP01989646.3申请日：20011220公开号：EP1352324B1公开日：20040714专利内容由知识产权出版社提供摘要：The invention enables fault-tolerant synchronisation of real-time equipment (11, 21, 22) connected to a computer network (41) over several tens of metres, with the option of including or not such equipment in the synchronisation device. The invention provides global scheduling of the real-time computer platform in the form of minor and major cycles in order to reduce the waiting time during sensor acquisition, associated calculation and preparation of the output towards the actuator in an integrated modular avionic architecture (IMA). For this purpose, the invention uses a synchronisation bus (61) which is separate from the data transfer network (41) and circuits (113, 213, 223) that interface with said specific bus (61) in order to process the synchronisation signals from the real-time local clocks (112, 212, 222) at each piece of equipment (11, 21, 22) in a fault-tolerant, decentralised manner.申请人：THALES,THALES SA,THALES地址：FR国籍：FR代理机构：Nguyen Van Yen, Christian 更多信息请下载全文后查看。

CommScope数据中心网线管理解决方案商品说明书

CommScope’s data center cabling management solution increases infrastructure visibility and reduces downtime to deliver better stability and reliability for a major provider of enterprise data center services. CustomerNTT CommunicationsLocationHong KongBuilding a better data center to meet growing customer demandT o expand data center capacity to meet growing demand from its enterprise customers, NTT Communications launched Financial Data Center T ower 2 (FDC2) in Hong Kong in 2015. FDC2 features a Tier 4-ready design and an array of leading-edge technological innovations to help enhance the business performance of NTT Communications’ customers. Improved data center stability and reliability were NTT Communications’key requirements for the facility. The data center’s infrastructure is fully fault tolerant throughout its electrical, storage and distribution networks. Each system communicates with the others via fiber or copper cables with dual paths to ensurea reliable high-speed connection and maximum bandwidth.In order to provide the best service toits customers and minimize risk, NTT Communications wanted to deploy a proven, high-quality cabling infrastructure Success StoryIntelligent infrastructure solutions from CommScopeboost data center performance for NTT Communicationssolution. They also wanted to more effectively monitor and manage the infrastructure in the new data center on a real-time basis. The company is actively developing software to integrate the monitoring and management of the various networks and systems across their enterprise, and wanted a physical layer monitoring solution that could be compatible with its overall monitoring system. imVision® enhances NTT Communications’ data center stability and reliabilityIn addition to supplying high-quality fiber and copper cabling forthe NTT Communications data center, CommScope introducedan intelligent cabling management solution to create a comprehensive data center solution that delivers the stability and reliabilityNTT Communications demanded.CommScope’s imVision® cabling management solution is integrated with NTT Communications’ Data Center Management System (DCMS). It is designed and developed by NTT Communications to manage and monitor all aspects of data center operations—including copper and fiber network connectivity—automatically on a real-time basis. The data collected is not only used for tracking network performance, but also provides customers end-to-end visibility with an extended guarantee on their Service Level Agreement (SLA) at the cabling connectivity level.From detecting, monitoring and documenting connectivity to tracking devices and initiating work orders, imVision offers a comprehensive solution incorporating these key features:• Inventory records on structured cabling, iPatch® port status and equipment to save time checking the free port on a panel and identifying the connection channel.• Event alerts for any incident on the iPatch panel—for example,an unscheduled patch cord added or removed—to reduce the labor required to locate the incident and reduce the effects on corresponding services.• Downtime reports for each incident help NTT Communications prove the quality of service on layer 1 (physical cabling) toits customers.• Work orders for patching work are created automatically to reduce human error and provide real-time updates on inventory when the work order is completed.Deployed by a CommScope PartnerPRO®providerCommScope PartnerPRO® Network provider Lantro HK handledthe deployment of the iPatch components and imVision solutionfor the NTT Communications data center. T o meet the customer’s unique specifications, Lantro HK assigned a multifunctional team that included project managers, engineers and technicians. Collaborating with CommScope to address NTT Communications’ requirements, the team prepared design documents and developed testing and commissioning procedures and matrix tables to achieve the project’s goals. They also prepared a mockup of the imVision system and a proof-of-concept test prior to implementation.Enabling a faster, more targeted response to system problemsAfter deploying imVision and using it for a period of time,NTT Communications compared data center system performance with imVision to the previous manual method of handling incidents and tracing cabling records. Dramatic improvements were noted by NTT Communications across the board, including:• Network incident management: Time from incident occurrence to resolution decreased by almost two-thirds—from an average of 90 minutes to just 31 minutes.• Problem management: Automating the entire problem management process eliminated the 30 percent of network downtime that is caused by human error.• Real-time monitoring: The ability to track both authorized changes and detected changes in real time has reduced mean time to response and increased overall system availability.• Connection trace: T racing customer connectivity using a single connection ID has sped up the process of locating the failure point and correcting the problem.Further integrating the imVision system with its DCMS,NTT Communications is now able to provide customers with higher visibility of their physical layer connectivity together withall other aspects of data center service performance on onesign-on customer platform, anywhere, any time.Everyone communicates. It’s the essence of thehuman experience. How we communicate is evolving.T echnology is reshaping the way we live, learn and thrive.The epicenter of this transformation is the network—our passion. Our experts are rethinking the purpose, roleand usage of networks to help our customers increase bandwidth, expand capacity, enhance efficiency, speed deployment and simplify migration. From remote cellsites to massive sports arenas, from busy airports tostate-of-the-art data centers—we provide the essential expertise and vital infrastructure your business needs to succeed. The world’s most advanced networks rely on CommScope connectivity.Visit our website or contact your local CommScope representative for more information.© 2017 CommScope, Inc. All rights reserved.All trademarks identified by ® or ™ are registered trademarks or trademarks, respectively, of CommScope, Inc. This document is for planning purposes only and is not intended to modify or supplement any specifications or warranties relating to CommScope products or services.。

Snap-stabilizing pif and useless computations

Snap-Stabilizing PIF and Useless ComputationsAlain Cournier St´e phane Devismes Vincent VillainLaRIA,CNRS FRE2733Universit´e de Picardie Jules Verne,Amiens(France)AbstractA snap-stabilizing protocol,starting from any arbitrary initial conﬁguration,always behaves accordingto its speciﬁcation.In other words,a snap-stabilizing protocol is a self-stabilizing protocol which stabilizesin0time unit.Here,we propose theﬁrst snap-stabilizing Propagation of Information with Feedback(PIF)protocol for arbitrary networks working with an unfair daemon,i.e.,the weakest scheduling assumption.An interesting aspect of our solution is that,starting from any conﬁguration,the number of reception(resp.acknowledgement)of corrupted messages(i.e.,messages not initiated by the root)by any processoris bounded.Keywords:Fault-tolerance,self-stabilization,snap-stabilization,wave protocols,PIF.1IntroductionThe concept of Propagation of Information with Feedback(PIF),also called Wave Propagation,has been introduced by Chang[1]and Segall[2].The PIF scheme can be informally described as follows:a node, called root or initiator,initiates a wave by broadcasting a message m into the network(broadcast phase). Each non-root processor acknowledges to the root the receipt of m(feedback phase).The wave terminates when the root has received an acknowledgment from all other processors.In arbitrary distributed systems,any processor may need to initiate a PIF wave.Thus,any processor can be the initiator of a PIF wave and several PIF protocols may run simultaneously.To cope with the current executions,every processor maintains the identity of the initiators.PIF protocols have been extensively used in distributed systems for solving a wide class of problems,e.g.,spanning tree construction,distributed inﬁmum functions computations,snapshot, termination detection,reset,or synchronization(see[3]for details).So,designing efﬁcient fault-tolerant PIF protocols is highly desirable.Many fault-tolerant schemes have been proposed and implemented,but the most general technique to design a system tolerating arbitrary transient faults is self-stabilization[4].A self-stabilizing system,regardless of the initial states of the processors and messages initially in the links, is guaranteed to converge into the intended behavior inﬁnite time.A particular class of self-stabilizing protocols is snap-stabilizing protocols[5].A snap-stabilizing protocol guarantees that,starting from any conﬁguration,it always behaves according to its speciﬁcation.In other words,a snap-stabilizing protocol is a self-stabilizing protocol which stabilizes in zero time unit.Of course,a snap-stabilizing protocol is optimal in terms of stabilization time.The notion of zero stabilization time is a surprising result in the stabilization area. Clearly,the snap-stabilization does not guarantee that all components of the network never work in a fuzzy manner.However,the snap-stabilizing property ensures that if an execution of a protocol is initiated by some processors,then the protocol behaves as expected.Furthermore,after this initialization,the protocol does not introduce any additional fuzzy behavior.Consider,for instance,a snap-stabilizing PIF protocol.Starting from any conﬁguration,the protocol ensures that when a processor has a message m to broadcast,then: eventually starts the broadcast of m,every processor different of will receive the message m,and send an acknowledgment which will reach.Related Works.Several PIF protocols have been proposed in the self-stabilizing area,e.g.,[6,7,8]for tree networks,and[10,11]for arbitrary networks.The self-stabilizing PIF protocols have also been usedin the area of self-stabilizing synchronizers[13,14,15].The most general method to“repair”the system is to reset the entire system after a transient fault is detected.Reset protocols are also PIF-based protocols. Several reset protocols exist in the self-stabilizing literature(see[16,17,14,10,18]).Self-stabilizing snapshot protocols[19,10]are also based on the PIF scheme.Snap-Stabilizing PIF for oriented and un-oriented tree networks are proposed in[5,9].The PIF protocols for trees of[5,8]are also optimal in terms of space. Theﬁrst snap-stabilizing PIF protocol for arbitrary networks has been presented in[12].The drawback of this latter solution([12])is that the protocol needs to know the exact size of the network(i.e.,the number of processors).So this size must be constant and the protocol cannot work on dynamical networks.This drawback is solved in[20]using a composition of three algorithms.Contribution.The complexity analysis of the protocols in[12,20]reveals that they are very efﬁcient in terms of rounds for the stabilization time((1)),delay1(()where is the number of processors),and execution time2(()),respectively.However,the correctness of these protocols is proven assuming a (weakly)fair daemon only.Roughly speaking,a daemon is considered as an adversary which tries to prevent the protocol to behave as expected,and fairness means that the daemon cannot prevent forever a processor to execute an enabled action.A more(the most)general daemon is the unfair daemon:an unfair daemon can prevent forever an action to be executed except if it is the only enabled action.A well-known property of protocols working under an unfair daemon is that each round of their computations is bounded in number of steps.So,as the protocols in[12,20]are not proven assuming an unfair daemon,the time complexities in terms of steps cannot a priori be bounded.Therefore,we propose in this paper a novel snap-stabilizing PIF protocol proven assuming an unfair daemon as well as its step complexity analysis.This new solution keeps the advantages of the earlier solutions,i.e.,efﬁcient time complexities in terms of rounds,low memory requirement,and resilience to dynamic topological changes.However,the snap-stabilizing property of our PIF protocol does not guarantee that the network never works in a fuzzy manner.In particular,if we focus on any non-initiator processor,the snap-stabilization does not guarantee that never receives corrupted messages(i.e.,messages not sent by the initiator).Nevertheless,we will see that,using our protocol,the number of corrupted messages that may receive is bounded by the size of the network(Theorem9).Also, we will see that does not acknowledge every corrupted message:the number of these corrupted acknowl-edgments(acknowledgment due to a corrupted message)is bounded by a constant independent of the network (Theorem10).For many PIF-based applications,the acknowledgment messages are crucial.For instance,in a distributed inﬁmum functions computation,the computation is distributed during the broadcast phase and the result is computed and stored into the acknowledgment message.So,the cost of local computations gen-erated by acknowledgments of corrupted messages can be very signiﬁcant.Hence,bounding the number of corrupted acknowledgments by a small constant greatly enhances the quality of the solution.Outline of the paper.The rest of the paper is organized as follows:in Section2,we describe the model in which our protocol is written.In the same section,we state what it means for a protocol to be snap-stabilizing and give a formal statement of the protocol solved in this paper(PIF).In Section3,we present our PIF protocol.In the following section(Section4),we give its proof of snap-stabilization as well as some complexity results.Finally,we make concluding remarks in Section5.2Computational ModelNetwork.We consider a network as an undirected connected graph(,)where is a set of proces-sors and is the set of bidirectional asynchronous communication links.We state that is the size of ()and its degree(i.e.,the maximal value among the local degrees of the processors).We assume that the network is rooted,i.e.,among the processors,we distinguish a particular one,r,which is called the root of the network.In the network,and are neighbors if and only if a communication link(,)exists(i.e.,(,)).Every processor can distinguish all its links.To simplify the presentation,we refer to a link(,)of a processor by the label.We assume that the labels of,stored in the set,are locally ordered by.We also assume that is a constant input from the system.Programs.In our model,protocols are semi-uniform,i.e.,each processor executes the same program except r.We consider the local shared memory model of computation which is an abstraction of the message-passing model.In this model,the program of every processor consists in a set of shared variables(henceforth,referred to as variables)and an orderedﬁnite set of actions inducing a priority.This priority follows the order of appearance of the actions into the text of the protocol.A processor can write to its own variable only,and read its own variables and that of its neighbors.Each action is constitued as follows:The guard of an action in the program of is a boolean expression involving variables of and its neighbors.The statement of an action of updates one or more variables of.An action can be executed only if its guard is satisﬁed.The state of a processor is deﬁned by the value of its variables. The state of a system is the product of the states of all processors.We will refer to the state of a processor and the system as a(local)state and(global)conﬁguration,respectively.We note the set of all possible conﬁguration of the system.Let and an action of().is said enabled at in if and only if the guard of is satisﬁed by in.Processor is said to be enabled in if and only if at least one action is enabled at in.When several actions are enabled simultaneously at a processor:only the priority enabled action can be activated.Let a distributed protocol be a collection of binary transition relations denoted by,on.A computation of a protocol is a maximal sequence of conﬁgurations,,...,,,...such that, ,(called a step)if exists,else is a terminal conﬁguration.Maximality means that the sequence is eitherﬁnite(and no action of is enabled in the terminal conﬁguration)or inﬁnite.All computations considered here are assumed to be maximal.is the set of all possible computations of.As we already said,each execution is decomposed into steps.Each step is shared into three sequential phases atomically executed:every processor evaluates its guards,a daemon(also called scheduler) chooses some enabled processors,each chosen processor executes its priority enabled action.When the three phases are done,the next step begins.A daemon can be deﬁned in terms of fairness and distributivity.In this paper,we use the notion of weakly fairness:if a daemon is weakly fair,then every continuously enabled processor is eventually chosen by the daemon to execute an action.We also use the notion of unfairness:the unfair daemon can forever prevent a processor to execute an action except if it is the only enabled processor.Concerning the distributivity,we assume that the daemon is distributed meaning that,at each step,if one or more processors are enabled,then the daemon chooses at least one of these processors to execute an action.We consider that any processor executed a disabling action in the computation step if was enabled in and not enabled in,but did not execute any protocol action in.The disabling action represents the following situation:at least one neighbor of changes its state in,and this change effectively made the guard of all actions of false in.To compute the time complexity,we use the deﬁnition of round[7].This deﬁnition captures the execution rate of the slowest processor in any computation.Given a computation(),theﬁrst round of(let us call it)is the minimal preﬁx of containing the execution of one action(an action of the protocol or a disabling action)of every enabled processor from the initial conﬁguration.Let be the sufﬁx of such that .The second round of is theﬁrst round of,and so on.Snap-Stabilization.Let be a set.means that satisﬁes the predicate deﬁned on.Deﬁnition1(Snap-stabilization)Let be a task,and the speciﬁcation of.The protocol is snap-stabilizing for the speciﬁcation if and only if the following condition holds:.The problem to be solved.Any processor can be an initiator in a PIF protocol and several PIF protocols may run simultaneously.In this paper,we consider the problem in a general setting of the PIF scheme wherewe assume that the PIF is initiated by the root only.Speciﬁcation1(PIF Wave)Aﬁnite computation is called a PIF Wave if and only if the following condition is true:If Processor r broadcasts a message m in the computation step,then:[PIF1]For each,there exists a unique such that receives m in,and[PIF2]In,r receives an acknowledgment of the receipt of m from every processor.Remark1So,in practice,to prove that a PIF protocol is snap-stabilizing we have to show that every execu-tion of the algorithm satisﬁes the following two conditions:if r has a message m to broadcast,then it will do in aﬁnite time,and starting from any conﬁguration where r is ready to broadcast,the system satisﬁes Speciﬁcation1.3AlgorithmWe now informally describe our snap-stabilizing PIF protocol(see Algorithms1and2for the formal descrip-tion).In the rest of the paper,we will refer to this protocol as Algorithm.Also,for sake of clarity,we divided Algorithm into three parts:1.The PIF Part.This is the main part of the protocol.Indeed,this part contains the actions correspondingto each of the three phases of the PIF wave:the broadcast phase,the feedback phase following the broadcast phase,and the cleaning phase which cleans the trace of the feedback phase so that the root is ready to broadcast a new message.2.The Question Part.This part ensures that each processor eventually receives the message sent bythe root during a broadcast phase.Especially when the system contains some erroneous behaviors (remember that the system can start from any conﬁguration).Actually,the question part controls that, after receiving a message sent by the root,a processor does not execute the feedback phase before all its neighbors received the message.3.The Correction Part.This part contains the actions dealing with the error correction,i.e.,the actionsthat clean the erroneous behaviors.We now more precisely describe the three parts of Algorithm.PIF Part.Consider a conﬁguration where,.We will refer to this conﬁguration as the normal starting conﬁguration.In,the root processor,r,is the only enabled processor and-is its only enabled action.So,r executes-in theﬁrst step:r broadcasts a message m,switches to the broadcast phase by,and initiates a question by(we will see later what the goal of this question is).When a processor waiting for a message(i.e.,)ﬁnds one of its neighbors in the broadcast phase(),receives the message from(-).Then,also switches to the broadcast phase(),initiates a question(),points out to using,andﬁnally sets its level to .Typically,contains the length of the path followed by the broadcast message from r to.(Since r never receives any broadcast message from any neighbor,Variables and are shown as constants in the algorithm.)Processor is now in the broadcast phase()and is supposed to broadcast the message to its neighbors except.So,step by step,a spanning tree rooted at r(w.r.t.the variables)is dynamically built during the broadcast phase.Let us call this tree r.Eventually,some processor in r cannot broadcast the message because all its neighbors have already received the message from some other neighbors(,).Then,(called a leaf of r)waits an authorization from the root to execute the feedback phase.This authorization corresponds to the reception by and its neighbors of an answer to the question previously asked by().So,after receiving this authorization, can switch to the feedback phase by-().The feedback phase is then propagated up into r as follows:a non-leaf processor switches to the feedback phase when it is authorized by rootInputs::set of(locally)ordered neighbors of;Constants:;;Variables:,,,;,,; ....................................................................................................................................... Macro:()()()[()(,)]; ....................................................................................................................................... General Predicates:()[()()]()[()()]()[()()]Guards:()()[()(,)]()(,)[()][[()(()(,))][()(()(()()))]](,)[()]()(,)[()()] ....................................................................................................................................... Actions:PIF Part:-;-;Inputs::set of(locally)ordered neighbors of;Variables:,,,,,;;;,,,; ....................................................................................................................................... Macros:()()()[()((,)())];,; ....................................................................................................................................... General Predicates:()[()()]()[()()]()[()()]()[()(()(,))]()()Guards:()[()(,)](,,)[()]()[()(,)]()()()()[()(,)]()(,)[()][[()(()(,))][(,)(()(()()))]](,)[()]()()(,)(()())(,)[()]()()(,)(()()) ....................................................................................................................................... Actions:Correction Part:-;min();;;-;-;-;Question Part:We now explain how this phase works.We already saw that a question is initiated at byeach time switches to a broadcast phase(-).This action forces all its neighbor satisfyingto execute(-).When every has reset,also executes-.The values are then propagated up in the trees of and every(and only these trees)following the variables.By this mechanism,all values possibly in the path from(resp.)to its root(w.r.t.the variable)are erased (in particular,the value present since the initial conﬁguration).So,from now on,when a value reaches a requesting processor or one of its neighbor,this value cannot come from any one but r and the processor obviously is in r.Then,as we have seen before,eventually,some processors in r,called leaves,detect that the broadcast phase cannot progress anymore because all their neighbors have received the broadcast message from some other processors(i.e.,and,).In this case,each executes (-)meaning that it is now waiting for an answer from the root.The value is then propagated up(by-)into the tree of(and only this tree)as follows:a non-leaf processor can execute-if all its children have set their variable to and no neighbor has still. When the values reaches all the children of r,r executes-:r broadcasts an answer into its tree and so on.So,,after initiating a question(i.e.,),if and its neigbors are in r, then they eventually receive a value.In this case,is sure that itself and all its neighbor are in r and is authorized to execute-(will satisfy).Otherwise,the processors in an abnormal tree receive no until they leave their trees(by the actions of the correction part)and hook on to the normaltree r(by-).In particular,if is in r,then its-will be enabled only after all its neighbors hook on to r.Correction Part.The actions of the correction part are used for erasing the erroneous behaviors from the system.Of course,the error correction only concerns processors such that and r,i.e., the abnormal processors.The abnormal processors are arranged into abnormal trees rooted at a processor satisfying,i.e.,an abnormal root.The abnormal trees can be deﬁned as follows:let such that ,,(the abnormal tree rooted at)if and only if there exists a sequence of processors(),...,,...,()such that,,(among the neighbors designating with only those satisfying are considered as children).So,the error correction consists in the removal of all these abnormal trees.To remove an abnormal tree,we cannot simply set to.Since some processor can be in.If we simply set to,then can participate again to the broadcast of the tree of which it was the root.Since we do not assume the knowledge of any bound on the values(we may assume that the maximum value of is any upper bound of),this scheme can progress inﬁnitely often,and the system may contain forever an abnormal tree which can prevent the progression of the normal tree r.We solve this problem by paralyzing the process of any abnormal tree before remove it.To that goal,these actions use two additional states in the variables:and (for Processor such that r only).If is an abnormal root,it sets its variable to and broadcasts this value into its tree and only its tree(-).When receives an acknowledgment(-)of all its children(value of variable),knows that all the processors of its tree satisfy and no processor can now receive the broadcast phase from any(indeed,,).Then can leave its tree (-)and it will try to receive the broadcast from one of the processors only when participates in another broadcast.By this process,all abnormal trees eventually disappear and r will be able to grow until it reaches all the processors of the network.4Proof of Correctness and Complexity AnalysisIn this section,we will prove that Algorithm is snap-stabilizing for Speciﬁcation1under an unfair daemon.To that goal,we propose the following scheme of proof:weﬁrst prove that Algorithm is snap-stabilizing assuming a weakly fair daemon;we then prove that each PIF wave is executed in aﬁnite number of steps.By these two assertions,it is clear that Algorithm is snap-stabilizing for Speciﬁcation 1with an unfair daemon.Indeed,by,we can claim that the unfair daemon cannot prevent forever any PIF wave to be completely executed and,by,we can claim that Algorithm satisﬁes Speciﬁcation1since theﬁrst wave.4.1Some DeﬁnitionsLet us deﬁne some items used in the proofs and prove some of their characteristics.Deﬁnition2The sequence of processors,,,,is called a path if,,. The processors and are termed as the extremities of.The length of()is noted.Deﬁnition3(PPath)such that,is the unique path() satisfying the following conditions:,,()(), (r).Deﬁnition4(Tree)such that(r),we deﬁne a set of processors as follows: ,if and only if and is theﬁrst extremity of.Remark2Let be a tree.Let and()its PPath.,,is the parent of in.Conversely,is a child of in.The height of in()is noted.Deﬁnition5(NormalTree)A tree containing only processors such that r is called a normal tree.Obviously,the system always contains one normal tree:the tree rooted at r.Any tree rooted at another processor than r is called an abnormal tree.Deﬁnition6(Alive)A tree satisﬁes(or is called)if and only if such that. Deﬁnition7(Dead)A tree satisﬁes(or is called)if and only if.Remark3No processor can hook on to a dead tree.Deﬁnition8(E-Dead)A tree satisﬁes-(or is called-)if and only if, ,.Remark4-.Deﬁnition9(S-Trace)Let be a tuple of processors(,,,).-is the sequence of the values of Variable on processors.By deﬁnition,,,,(see Algorithm1).So,if,then r by Deﬁnition4. Otherwise(,,),each child,,of r in r(if any)satisﬁes by Deﬁnition5.So,-,,,,,(r)and,by induction on the height of non-root processors in r,we can deduce the following result.Lemma1The normal tree,r,always satisﬁes one of the two following cases:r,or r,-.By deﬁnition,r,,,,,,(see Algorithm2).By Deﬁnitions4and5,each child,,of in(if any)satisﬁes r(in any abnormal tree,only the root satisﬁes).So,-,,,,,,,,,,, ()and,by induction on the height of processors different of in,we can deduce the following result.Lemma2Let be an abnormal tree.,-.4.2Proof assuming a Weakly Fair DaemonThe following theorem proves that any execution of Algorithm is deadlock-free.Theorem1,such that is enabled in.Proof.Assume,by the contradiction,that such that no action is enabled at in.Assume then that there exists at least one abnormal tree in.Among the abnormal trees in,we consider the one, ,having a root with the maximal value of.If such that,,,then by Lemma 2:Either,,,and-is enabled at,a contradiction.Or,such that,,and.In this case,-is enabled at,a contradiction.Hence,by the contradiction,,and,by Lemma2again,-.If ,then,.Also,such that()(),if,then otherwise satisﬁes(),a contradiction(remember that is an abnormal root with the maximal value of).Now,we already know that,.So,such that and we have()()((r)())and-is enabled at,a contradiction.So,by the contradiction,and we can deduce that such that ()(,)(in particular,if is a leaf,and the condition is trivially satisﬁed).Thus,by reasonning similar to the previous one,we can conclude that-is enabled at, a contradiction.Hence,we can conclude that there does not exist any abnormal tree in.Assume now that contains no abnormal tree.If in,then,and-is enabled at r,a contradiction.So,in.Assume that the normal tree(r)is dead in.Then,by Deﬁnition7and Lemma1,r,-.If r such that, then such that-is enabled at,a contradiction.So,r,.In this case,-is enabled at each leaf of r,a contradiction.Hence,r is alive and,Deﬁnition 6,r such that.By Lemma1,r,-with,in particular,.Also,r such that,also satisﬁes otherwisesuch that-is enabled at in(see Predicate).We now show that r, satisﬁes in(in particular,when).To that goal,we now focus on the Variables: -Assume,by the contradiction,that r such that.If such that ()(,),then,and-is enabled at,a contradiction (indeed,the system contains no abnormal tree,so,()(r)and we already know that r,-).Otherwise(,()(,)),as r,,and-is enabled at,a contradiction.Hence r,.-We now show that r,.Assumeﬁrst that some processors r have.If,-is enabled at(Remember that r,,).So,for all such that,we have,.Now,in this case,at least one of these processors satisﬁes,,(in particular,if is a leaf,and the condition is trivially satisﬁed).Moreover,if,we already know that satisﬁes.So, -is enabled at,a contradiction.Hence,r r,.Finally,assume that.Then,we already know that,,.Now,as and r satisﬁes r,-is enabled at r,a contradiction.-So,r,,with,in particular,(by deﬁnition,).In sucha conﬁguration,it is easy to see that if there exists some processors r such that,then at least one has its-enabled,a contradiction.Hence,r,in and also satisﬁes(because every neighbor of satisﬁes()(r)).Now,we already know that there exists some processors(at least one) r)satisfying.Among the processors,at least one,,satisﬁes(remember that and r,-).So,as and, -is enabled at,a contradiction.Lemmas3to6allow to show that the network contains no abnormal tree in rounds(Lemma7). Lemma3When-is enabled at,it remains enabled until executes it.Proof.Let be a step.Assume,by the contradiction,that-is enabled at in and not in but did not execute-in.First,-does not exist in the program of the root. So,r and let such that.Then,involves Variables and of and only.Also,-is the enabled action at which has the highest priority(-and-cannot be enabled at at the same time).So,did not move in,still satisﬁes,,and in and,by the contradiction,executes an action in which updates the value of and/or so that in.Finally,by Predicate,,,[()]in.So,we now study these two cases:-in.(,,),so in.Then,.Assume that in.As,,, ,and in(),in and,to that goal,must execute-in(-is the only action that updates).Now,as,, and in,satisﬁes and-is disabled at in,a contradiction.So,by the contradiction,in and in.In this case,-,,,,,,,,,,in(and,,)and-is the only action that may execute(in particular-is disable at because).Now,if executes-,then in and,as,,in(did not move in ),-is still enabled at in,a contradiction.-()in.By checking all actions of Algorithm,we can see that,as (),-is the only action that may execute in.Now,()()and(,,).So,-is disabled at in and did not execute any action in.Thus,is still enabled in,a contradiction.Lemma4When-is enabled at,it remains enabled until executes it.Proof.Let be a step.Assume,by the contradiction,that-is enabled at in and not in (i.e.,in)but did not execute-in.First,-does not exist in the program of the root.So,r.Then,as-is the enabled action at which has the highest priority(when-is enabled at,-and-are disabled at),did not move in and in.Now,()(,).So,there exists at least one neighbor,,of which executes an action in and which satisﬁes,in.Two cases are then possible: -satisﬁes()in but,after executing an action,satisﬁes(,)in.As in and-is the only action that updates Variables or,executes-in.By-,can only designate a processor such that in(see。

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uv (see Figure 1). (Note that a shortest restoration path does not guarantee a shortest path from source to destination.) Their method can restore loop-free routing after a link fault while propagating information about that failure to as few routers as possible and only to the ones along the shortest restoration path. This approach is also useful to divert tra c from a congested link. However, Narvaez' approach is ine cient when a link fault is bidirectional, because a restoration path is uni-directional and routing tables of nodes in the path are partially updated. In addition, two restoration paths may be generated for each bi-directional link fault.
1
This work was supported in part by NSF grant CCR 9900646 and ANI 0073736.
Abstract
Link-state routing protocols, such as OSPF and IS-IS, are widely used in the Internet today. In link-state routing protocols, global network topology information is rst collected at each node. A shortest path tree (SPT) is then constructed by applying the Dijkstra's shortest path algorithm at each node. Link-state protocols normally require the ooding of new information to the entire (sub)network after changes in any link state (including link faults). Narvaez et al. recently proposed a fault-tolerant link-state routing protocol without ooding. The idea is to construct a shortest restoration path for each uni-directional link fault. Faulty link information is distributed only to the nodes in the restoration path and only one restoration path is constructed. It is shown that this approach is loop-free. However, Narvaez' approach is ine cient when a link failure is bi-directional, because a restoration path is uni-directional and routing tables of nodes in the path are partially updated. In addition, two restoration paths may be generated for each bi-directional link fault. In this paper, we extend the Narvaez' protocol to e ciently handle a bi-directional link fault by making the restoration path bi-directional. Several desirable properties of the proposed extended routing protocol are also explored. A simulation study is conducted to compare the traditional link-state protocol, the source-tree protocol, the Narvaez' uni-directional restoration path protocol, and the proposed bi-directional restoration path protocol.
An Extended Fault-Tolerant Link-State Routing Protocol in the Internet 1
Jie Wu and Fei Dai Department of Computer Science and Engineering Florida Atlantic University Boca Raton, FL 33431 Xiaola Lin Department of Computer Science The University of Hong Kong Jiannong Cao Department of Computing The Hong Kong Polytechnic University Weijia Jia Department of Computer Engineering and Information Technology The City University of Hong Kong
Key words: Fault tolerance, Internet, link-state, loop-free, routing
1 ate routing protocols, such as OSPF 6, 7, 9, 12] and IS-IS 1, 11], are the dominant routing protocols in the Internet 2]. There are two major phases in such protocols: (1) each IP router rst collects the complete topological information of the underlying (sub)network (2) each router then computes the routes according to the collected topological information. The rst phase is performed distributively by all the routers in the network through exchanging link state information with its neighboring routers. In the second phase, each router can construct a routing table based on the shortest path tree (SPT) built using the topological information. Any SPT algorithm such as the Dijkstra's shortest path algorithm 3] can be used in building the SPT. Compared to other routing protocols such as distance-vector protocols, one of the major advantages of link-state protocols is that each router computes the routes independently using the same link-state information it does not depend on the computation done in other routers in the network. When link states are changed in the network, new information need only be sent once to each router for updating the routing table. Huitema 6] listed four good reasons why most network specialists favor link state protocols over the distance vector approach: (1) fast, loopless convergency (2) support of precise metrics and, if needed, multiple metrics (3) support of multiple paths to a destination and (4) separate representation of external routes. However, link-state protocols usually require ooding the network when any change occurs in the link states in the network. Flooding may be prohibitively expensive, especially when the link states change too frequently or when the number of links in the network is too large. Limiting the frequency of such updates can partially solve the problem when the e ect of the change of cost metric is minor in terms of transmission delay. However, this approach is ine cient in covering a link fault { because certain paths may be disconnected as a result of the link fault, delay in information update will lead to un-deliverable packets. In 10], Narvaez et al. presented a routing algorithm based on the link state method to limit routing information that needs to be delivered in a link-state protocol when a single link fails. Instead of using the ooding method, the proposed scheme restores all the paths traversing the failed link by performing only local updates on the a ected routers. Speci cally, a shortest restoration path is constructed that connects u to v for a faulty link 1

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