信号完整性的定义

Signal Integrity Definitions:
• V LOW: nominal output voltage in the low state
• V HIGH: nominal output in the low state
• V THRESHOLD: nominal input voltage where the devices switches from low to high or vice versa
• ∆V = V HIGH - V LOW: the nominal transition voltage in going from high to low
• Risetime (T r): the time that it takes for a signal to rise from V LOW + 0.1∆V to V HIGH - 0.1∆V
• Propagation time (T d): the time that it takes for a signal to travel from one point in a circuit to another, usually defined at V THRESHOLD
• R-C or L-R limiting: a capacitive or inductive load affects the risetime of a digital pulse. The pulse edge is slowed in proportion to RC or L/R
• L-C limiting: an LC load affects the risetime of a digital pulse. In an under-damped circuit, the risetime will increase, and overshoot and ringback occur. In an over-damped circuit, the
risetime will decrease.
• Overshoot: A digital pulse rises above its nominal high voltage level
• Undershoot: A digital pulse drops below its nominal low voltage level
• Ringback: the voltage, relative to low or high, that a waveform deviates towards V THRESHOLD after overshooting or undershooting
• Non-linear edge: edge has stepped appearance owing to midline inductance, midline capacitance, power droop, or ground bounce.
• Power droop: a temporary drop in V DD as a gate draws current through non-zero impedance • Ground bounce: a temporary increase in V SS (nominally zero) as a gate sinks current into a ground connection with non-zero impedance.
• Propagation (or flight) skew: difference in propagation time of two signals owing to different path lengths, or to edge deformations such as R-C, L-R, or L-C limiting, power droop, ground bounce.
Risetime Bandwidth Relationship:
• Bandwidth is determined by Risetime T r, not clock frequency f clk
• Bandwidth = 0.50/T r(multipole filter response, gaussian edge, raised cosine edge)
limited)
• Bandwidth = 0.35/T r (R-C
Lumped Circuits / Distributed Circuits:
• A signal traveling at u=2e8 m/s will travel 20cm in each nanosecond.
• A pulse with a 1ns edge occupies 20cm of physical line length (at above velocity)
• A 1cm trace will incur a 50ps delay (at above velocity)
• A circuit is considered lumped if its length is 1/6 of the edge length or smaller (33.3 mm or smaller in the above example)
• A circuit is considered distributed if its length is greater than 1/6 of the edge length
• Transmission line models are necessary when circuits are much longer than edge lengths.
Inductance and Second Order Circuits:
• The inductance of a square wire loop of dimensions x cm by y cm and wire diameter d cm given by L = 4xln{2y/d} +4yln{2x/d} (nH).
• An L-C circuit has a resonance at approximately ωo=1/sqrt{LC}
• As long as the knee frequency is well below fo=ωo/(2π), the resonant circuit will not affect the edge of a digital pulse.
• Q = sqrt{L/C}/Rs Rs is the resistance of the source feeding the circuit
• The rise-time of the step response of a second order circuit can be estimated from T r = T LC(1.08+0.56/Q2) where T LC= sqrt{LC}, Q is calculated knowing L,C, and R s.
Probes and Scopes:
• In practice inductance (and to a lesser extent skin effect) limit the bandwidth all probes • A 10:1 probe has an input impedance of (approximately) 10M ohm in parallel with 10pF • A 50 ohm source connected to a 10:1 probe with 30nH of ground inductance has a Q of 1.1 and a risetime of 847ps
• A 1kohm 21:1 probe has input impedance of 1050 ohms in parallel with 0.01pF of (stray) shunt capacitance
• A 50 ohm source connected to a 1kohm with 30nH of ground inductance has a Q of 1.65 and a risetime of 22ps (we calculate 65ps in class using an over-estimate).
• The rise time of a 500MHz scope is 0.35/500e6 = 700ps.
• The risetime of 3’ of RG174 is 32 ps (because of skin effect)
• Composite rise time T r = sqrt{T r12 + T r22 +T r32 +….}
Uncoupled Lossless Transmission Lines:
• l = inductance per unit length
(H/m) typically (nH/m) • c = capacitance per unit length
(F/m) typically (pF/m) • L=l x = total inductance of line
(H) • C=c x = total capacitance of line
(F) • v +(z,t)/ i +(z,t) = Z o , = sqrt{l /c} = sqrt{L/C}
(ohm) • u = 1/sqrt{l c} = = 1/(c Z o ) (m/s)
• T d = x/u = sqrt{LC}
(s) • Delay = 1/u = sqrt{l c
} (m/s) typically (ps/cm) • L= T d *Zo
(H) • C= T d /Zo (F) • General solution v(z,t) = v +(z-ut) + v -(z+ut)
• Γ = v -(z,t) / v +(z,t) = - i -(z,t) / i +(z,t)
• Γ = (R-Z o )/(R+Z o )
For a resistive termination • A P% variation in |R- Z o | results in a (P/2)% variation in Γ if |R- Z o | is small
• v +(0,t) = V s Z o /(Z o +R s ) t < 2T d • v(z,t) = v +(z,t) + v -(z,t) = v +(z,t)(1+Γ) t ≥ z/u, assuming no other reflections • V Thevenin = 2v +(z,t) R Thevenin = Z o .
Uncoupled Lossless Microstrip Formulae:
• Simplified microstrip analysis formulae: Zo = 87*ln{5.98h/(0.8w+t)}/sqrt{εr +1.41}
(εr is the permittivity of the medium, not effective permittivity εe )
εe = (εr +1)/2+(εr -1)/sqrt{1+12h/w}/2 if h/w ≥ 1 εe = (εr +1)/2+(εr -1)*(1/sqrt{1+12h/w}+0.04(1-w/h)2)/2 if h/w < 1
• Synthesis of height-width ratio: A=Zo*sqrt{(εr +1)/2}/60+(εr -1)*(0.23+0.11/εr )/( εr +1)
B=377π/(2Zo*sqrt{εr })
h/w = (exp{2A}-2)/(8exp{A}) if h/w ≥ 0.5
h/w = (π/2)/[B-1-log{2B-1}+(εr -1)*(log{B-1}+0.39-0.61/εr )/(2εr )] if h/w < 0.5
• T d (ps) = 33.33sqrt{εe }*length(cm) ≈ 33.46sqrt{0.475εr +0.67}*length(cm)
• 1-oz copper has a thickness of 34 um • FR4: 4.0 ≤ εr ≤ 4.7
(depending on frequency and resin content)
Uncoupled Lossless Stripline Formulae:
• Simplified Stripline analysis formula: Zo = 30*(h/(w e +0.441h)}/sqrt{εr }
where w e is the effective width given by w e = w if h/w < 2.86
w e = w – h(0.35-w/h)2 if h/w ≥ 2.886
• Synthesis of height-width ratio: A = 30π/(Zo*sqrt{εr })-0.441
h/w = 1/(0.85-sqrt{0.6-A}) if Zo*sqrt{εr } ≥ 120
h/w =
1/A if Zo*sqrt{εr } < 120
• T d (ps) = 33.33sqrt{εr }*length(cm)
Skin Effect and Conductor Resistance:
• High frequency currents flow close to the surface of a conduct nearest the return conductor. • Skin depth is defined as the depth where the current distribution has fall to exp(-1)=37% of its surface value
• SkinDepth = 1/sqrt{f πµσ} = 65/sqrt{f} (mm) for copper at room temp. • Rs = surface resistance = sqrt{πf µ/σ} Ohm/ = 0.257sqrt{f} µOhm/ (Cu@RT)
• Rac ≈ x*sqrt{ f πµ/σ}/w for flat signal conductors of width w and length x
• Rac ≈ x*sqrt{ f πµ/σ}/(6h) for flat ground conductors at height h below signal conductor • Rac = Rs*length/circumference for round conductors
• Rdc = length/(σ*Area) (any shaped conductor)
• R ≈ sqrt{Rac 2+Rdc 2}
Uncoupled Lossy Transmission Lines:
• Lossy lines model the effects of conductor resistance and dielectric loss
• Frequency domain techniques are used for lossy lines
• Z o = sqrt{(r+j ωl )/(g+j ω c )} is the complex characteristic impedance
• If j ωl >> r and jw c >> g, then Zo = sqrt(l /c )
• In RC lines, j ωl < r and j ωc< g, and the line has larger impedance and slower propagation. • γ = α +j β = sqrt{(r+j ωl )(g+j ωc )} is the complex propagation coeff.
• α has units of nepers / m
• β has units of radian / m
• r is calculated as a mixture of the DC and AC resistance (of which latter dominates in HSDD)
• g is calculated as g=tan(δ)*(ωc )
tan(δ) is the loss tangent • FR4: 0.010 ≤ tan(delta) ≤ 0.025
• The voltage drops in magnitude as exp{-α*z}
• Attenuation in dB/m is calculated from 20*log10{exp{α}} (assuming α in nepers/m) • At 100 MHz RG174 has an attenuation of about 0.28 dB/m (from catalog)
• A 50 ohm line is really only 50 ohms at a middle range of frequencies: a) above a lower limit below which RC propagation occurs b) below an upper limit where skin-effect and dielectric loss become dominant
• In this middle range of frequencies, both impedance and delay are independent of frequency • Outside this middle range of frequencies, impedance and delay are frequency dependent • A digital pulse contains a broad spectrum of frequencies from DC up to and including the knee frequency. However, since it is the edge that is propagating (not the steady levels), it is the knee frequency that determines the impedance that is seen by the pulse. Typically, f knee
falls in the middle range mentioned above, and therefore both impedance and delay are largely frequency independent.
Coupled Transmission Lines with T d >> T r (3-conductor lines)
• [L ] = [l 1 , l m ; l m , l 2] = [l 11 , l 12 ; l 21 , l 22]
l 1 = self inductance / unit length of line 1
(H/m) l 2 = self inductance / unit length of line 2
(H/m) l m = mutual inductance / unit length between line 1 and line 2
(H/m)
• [C ] = [c 1+c m , -c m ; -c m , c 2+c m ] = [c 11 , c 12 ; c 21 , c 22] c 1 = self inductance / unit length of line 1
(F/m) c 2 = self inductance / unit length of line 2
(F/m) c m = mutual inductance / unit length between line 1 and line 2
(F/m) •
CT = cross-talk = peak voltage induced in victim / excitation voltage (∆V) input to aggressor •
NEXT = near-end cross-talk: voltage induced in victim is at source •
FEXT = far-end cross-talk: voltage induced in victim is at load •
NEXT can be reflected toward the load (far-end) if the source is mismatched • FEXT can be reflected toward the source (near end) if the load is mismatched
•
In a ‘homogenous’ line (e.g. 2-line microstrip) l 11 = l 22 = l l 12 = l 21 = l m c 11 = c 22 = c c 12 = c 21 = c m • In a source-matched and load-matched lossless line with T d >> T r
NEXT = [c m /c + l m /l ]/4
NEXT waveform has a width (at 50% amplitude) of T r +2T d FEXT = T d [c m /c - l m /l ]/(2T r )
FEXT waveform has a width (at 50% amplitude) of T r and a delay of T d
Z o = sqrt{l /c } One line driving, the other line not driven
T d = x*sqrt{l c }
One line driving, the other line not driven Z o even = sqrt{(l + l m )/( c )} lines driven with same polarity
T d even = x*sqrt{(l + l m )( c )} lines driven with same polarity
Z o odd = sqrt{(l - l m )/(c + 2c m )} lines driven with opposite polarity
T d odd = x*sqrt{(l - l m )(c + 2c m )} lines driven with opposite polarity
• For a microstrip with line separation D and line height h above ground plane: CT ≈ k/(1+D/h)2
k < 1 for FEXT k ~ T d /T r
• In a ‘non-homogenous’ line (e.g. 2-line (3-conductor) ribbon cable)
l 11 ≠ l 22 l 12 = l 21 = l m c 11 ≠ c 22 c 12 = c 21 = c m
Crosstalk in coupled non-homogeneous lines must be evaluated computationally. One method (Brainin’s method) involves decoupling the transmission lines equations into so-called mode solutions by diagonalizing the [L ] and [C ] matrices so that [V (z,t)]=[A ][V m (z,t)] The elements of [A ], along with mode impedances and mode delays are used to form a spice model that utilizes EPOLY, FPOLY, and TLINE blocks.
Partial matching: Compute [Z c ] = u[L ] set R LOAD1 = Z c11 R LOAD2 = Z c22 Complete matching: Compute [Z c ] = u[L ] set R LOAD1 = Z c11 - Z c12 R LOAD2 = Z c22- Z c12 Terminate R LOAD1 and R LOAD2 through R LOAD3 = Z c12
Coupled Transmission Lines with T d >> T r (lumped circuits with resistive loads)
• max{dv/dt} ≈ ∆V/T r
∆V = voltage change from one state to another • v m = L m di A /dt
voltage across mutual inductance • V m = max{v m } ≈ L m ∆I/T r
max voltage across mutual inductance • ∆I = ∆V/R A
current change in aggressor • V ind ≈ V m
Induced voltage in victim • Inductive CT = V ind /∆V ≈ L m /(R A T r )
Aggressor circuit A is driving load R A • i m = C m dv A /dt
current through mutual capacitance • I m = max{i m } ≈ C m ∆V/T r
Max current through mutual capacitance • V ind ≈ I m R B Max voltage induced in victim
• Capacitive CT = V ind /∆V ≈ C m R B /T r Victim circuit B is has impedance R B • Ind CT / Cap CT = L m /C m / R 2
R A = R B = R • Ind CT > Cap CT ⇒ R < sqrt{L m /C m }
Short-line / Long-line Issues
• Question: when does a line look like Z o and when does it look like something else (such as an
inductance or a capacitance)?
• Answer: depends on how long the line is and what is terminating the line.
• A long line (T d >> T r ) terminated in Z o will always have an input impedance equal to Z o • A long line (T d >> T r ) terminated in something other than Z o will have an input impedance
equal to Z o until the first reflection arrives at the source.
• A short line (T d << T r ) will have an input impedance calculated as follows:
Zin = j ωk L + Z load /(1+j ωk CZ load )
where ωk = 2πf k = π/T r
• X L /X C = (πT d /T r )2
• In a short line (T d << T r ) with a high impedance load (Z load >> X C ) capacitive reactance dominates: line can be modeled as a capacitor (C) in parallel with load.
• In a short line (T d << T r ) with low impedance load (Z load << X C )
Inductive reactance dominates: line can be modeled as an inductor (L) in series with load.
Ground Planes and Power Delivery:
• The purpose of the power planes (or lines) and ground planes (or lines) is to:
a) provide a low impedance source of current at constant voltage to IC devices
b) provide a low impedance return path for signal currents
• As a signal current propagates along a signal trace to the desired receiver, a return current simultaneously propagates along a nearby ground plane or power plane (or both)
• The return current ‘chooses’ the path of least impedance
• At high speeds (fast edges), the path of least impedance is the path of least inductance
• As a general rule, the path of least inductance is close to the outgoing signal trace – return currents prefer to return the same way they went out.
• A stripline of height h will have lower power and ground inductance than a microstrip of the same height. Stripline is the best design for minimizing signal integrity effects.
• At lower edge frequencies, a cross-hatch power-ground system can be used. The intersection of each power finger and ground finger should be decoupled with a bypass capacitor.
• Wire-wrap and Breadboard prototyping will not provide reliable operation when edge frequencies are above a few megahertz: 8” wire loop has ~ 200nH ≡ 10ohm @ 8MHz
• When current is drawn through a power structure with non-zero impedance, the resulting voltage drop is called power droop. Power droop usually occurs as a gate switches high in order to source current to a capacitive load, and therefore corresponds to the leading edge of
a signal pulse. The droop occurs because current is drawn through the non-zero inductance
of the power line.
• When current returns through a ground structure with non-zero impedance, the resulting voltage increase is called ground bounce. Ground bounce usually occurs as a gate switches low in order to sink current from a capacitive load, and therefore corresponds to the trailing edge of a pulse. The bounce occurs because current is returned to the ground plane through the non-zero inductance of the chip package, or interconnects from the ground pin to the ground plane.
• Obstructions in the return path, such as slots, connectors, or other conductor discontinuities,
a) increase path inductance
c) degrade signal risetime
d) increase mutual inductance
e) increase inductive cross-talk
• A ground slot of width D (inch) will increase the inductance of a signal trace of width w (inch) by an amount L ≈ 5Dln{D/w} (nH), assuming the trace is centered over the slot.
• An inductor of inductance L in series with a long line will slow a pulse edge of rise time T r as
τL = L/Z o/2
follows: T r composite = sqrt{T r2 + (2.2τL)2} where
• An inductor of inductance L in series with a capacitively loaded short line will slow a pulse edge of rise time T r as follows: T r composite = sqrt{T r2 + LC(1.08+0.56/Q2)2}
Decoupling (or bypass) Capacitors
• Decoupling capacitors have two purposes:
a) To act as a temporary charge reservoir and thereby allow current to be drawn locally
rather than remotely from the central power supply
b) To provide a low impedance path between power and ground planes
• In both of the above cases, decoupling capacitors are bypassing the effects of power and ground plane inductance.
• Decoupling is usually done at three places on a circuit board:
a) with a large (typically electrolytic) capacitor at the point where the power supply enters
the board, or directly on the output of an on-board regulator
b) with a smaller (typically plastic) capacitor close to the IC body
c) incidentally with on-die capacitance and/or PCB capacitance between power and ground
• Use this strategy to calculate the IC bypass capacitor
a) determine the allowable peak voltage droop (δV)
b) estimate the peak current drawn by all gates (δI)
c) calculate the capacitance required to deliver current C min≈ T r δI/δV
d) If C < C die + C pcb = C local, then an external capacitor is required (usually the case)
e) Select a high Q (low loss) plastic capacitor with C d > C min, and place it as close to the
power and ground pins as possible. Typical values are 10 nF or 100nF or sometimes both (in parallel).
• Use this strategy to estimate the maximum allowable inductance in series with C d
a) L < T r δV/δI = (T r)2/C d
b) Note a larger decoupling capacitor implies less inductance. Strictly speaking, in order to
avoid exciting a resonance, need f knee = 0.5/T r < 1/(2πsqrt{LC d}) ⇒ L < (T r)2/C d/π2
c) Calculate interconnect inductance
L plane segment = 31.9 Dh/w (nH) D = length (in), w= width (in), h=board height (in)
L via = 5.08h[ln{4H/d}+1] (nH) d = diameter (in), H = via height (in)
L pin = 0.1 nH to 10 nH depending on package and bonding of die to package
d) L < L plane segment + L via(s) +L pin ?
• Use this strategy to estimate the effects of decoupling capacitor parasitics R ESR = Equivalent series resistance of capacitor
L cap = series inductance of capacitor
C = capacitance of capacitor
Xc = sqrt{(R ESR)2 + (πL cap/T r-T r/(πC))2 } << 1 ohm.
• Place decoupling capacitors in parallel to reduce series inductance and ESR.
• Do a complete frequency response of the power system and decoupling capacitors to identify intercapacitance resonances. Goal: total input impedance should be << 1 ohm up to and including the knee frequency.
Buffer Modeling
• Buffer modeling is based on an approximation or representation of transistor I-V curves
• Basically, three types of buffer models: a) Linear
b) Linear-behavioral c) Behavioral (IBIS)
• In linear modeling, the gate resistance is discrete and depends on V GS , or V GS and V DS
depending on the complexity of the model.
For simple linear modeling - the gate resistance has two discrete values:
R ON ~ ohms V GS > V T R OFF
~ Megohms V GS < V T More realistic linear modeling – the gate resistance has three discrete values: For an NMOS transistor:
R ON TRIODE ≈ 1/[V GS -V T ]/(2K) ~ ohms V DS << V GS -V T V GS > V T R ON SATURATION ≈ V A /I D ~ kohms V DS > V GS -V T V GS > V T R OFF ~ Megohms V GS < V T Where
V T is the threshold voltage ~ 2 volt V A is the early voltage ~ 20 – 200 volt V GS = gate source voltage
V DD or 0 volt K = 0.5µC ox (W/L)
~ 0.2 – 20 mA/V 2 • In linear-behavioral modeling, the gate resistance is a discrete function of time and varies according to a switch-time curve that follows the rise-time of the gate (this is the model we used in PSPICE). A simple linear-behavioral model for an NMOS transistor:
• In behavioral modeling, accurate I-V curves are used in conjunction with switch time curves.
• The industry standard for behavioral modeling is IBIS – IO Buffer Information Spec.
•
IBIS enables fast, accurate signal integrity simulation without disclosing proprietary information.
• IBIS data includes IV-curves, clamping diode curves, switch time curves, and package parasitics, arranged in an ASCII format, obtained from simulation or measurement.
R R
Source Synchronous Timing
• Method: Distribute and synchronize data clock (strobe) with data, rather than from a single source.
• Goal: to provide and optimize small hold and setup margins in order to protect against timing aberrations due to signal integrity issues.
• Definitions and relationships:
T vb = time data is valid at receiver latch D input before strobe signal is valid at clk input (< 0) T va = time data is valid at receiver latch D input after strobe signal is valid at clk input (> 0) T co = time data is valid at Q output of latch after clk is valid at input
T co skew = T co (data) – T co (strobe)
T prp = time it takes for signal to propagate from Q output of transmitter to D input of receiver
T flt = time it takes for data to be valid at D input of receiver latch compared to time it takes for Q output of transmitter latch to become valid while driving a reference load
T flt skew = T flt (data) - T flt (stobe)
T delay = additional delay that strobe clk is passed through (>T co skew)
T va= T co (data) – T co (strobe) + T delay = T co skew + T delay
T vb = T co (data) – T co (strobe) – T delay = T co skew - T delay
T va-T vb = 2T delay = T clk = 1/R clk R clk = data rate
T va+T vb = 2T co skew
T total delay = time it takes for signal at input of receiver latch to become valid after clk input to transmitter latch becomes valid
T total elay = T flt + T co (test) if latch is driving a reference load
T total delay = T prp + T co (sys) if latch is driving a real line
T skew = T delay (data) – T delay (strobe)
T skew = T flt skew + T co skew
T setup rgargin = T delay + T skew – T setup
T setup rgargin = -T vb – T setup – T flt skew (- T guard)
T hold rgargin = T delay + T skew – T hold
T hold rgargin = +T va – T hold – T flt skew (- T guard)
Signals are generally considered valid when the reach the nominal threshold of 50% Vdd (supply) Nominally |T va|=|T vb|= T clk/2 = T delay, so the strobe occurs roughly half way between data transitions – this is the whole point of source synchronous busing. However, T va + T vb =
|T va| - |T vb| = 2T co skew so the strobe triggers the data either before or after the midpoint T clk/2 depending on whether T co skew is positive or negative. Hence:
|T va| = T clk/2 + T co skew
|T vb| = T clk/2 - T co skew
|T va| - |T vb| = 2 T co skew
T hold rgargin - T setup rgargin = (T va + T vb) + (T setup - T hold) = (T setup - T hold) + 2T co skew
• The two margins will be equal if the setup and hold times are equal and the clock-output skew is small.
• Worst-case analysis: calculate T setup rgargin and T hold rgargin using worst-case value of T vb, T va, T setup, T hold, and T flt skew. Include an additional parameter T guard to reflect ambiguity in
measurement data.
• Worst-case analysis will yield small or negative margins when T flt skew≈ T clk/2 – {T setup or T hold} • T flt skew results from a) different path lengths and/or b) different switching characteristics • Statistical analysis: calculate T setup rgargin and T hold rgargin using means and variances of T vb, T va, T setup, T hold, and T flt skew. Set variance parameter to k=3.09 for 99.8% chance that margin will be smaller than calculation.。