CORE-Directed Self-Assembly at the 10 nm Scale by Using Capillary Force-Induced Nanocohesion

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ULPI_v1_1

ULPI_v1_1

UTMI+ Low Pin Interface (ULPI)SpecificationRevision 1.1October 20, 2004Revision HistoryDate CommentRevision Issue0.9 November 12, 2003 Pre-release.1.0rc1 January 3, 2004 Introduce PHY interface “modes”.Update interface timings. Clarify 4-bit data clocking.Clarify sending of RX CMD’s and interrupts.Introduce AutoResume feature.Route int pin to data(3) during 6-pin Serial Mode.Explain VBUS thresholds.Add T&MT diagram and updated text.Add new section to explain how PHY is aborted by Link.Various clarifications.1.0rc2 January 13, 2004 Add block diagram.Tighten interface timing.Modify suspend protocol to more closely resemble UTMI.Add SPKR_L and SPKR_MIC to signal list and T&MTconnector.Various clarifications.1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset.Link + PHY clock startup time of no more than 5.6ms for aperipheral is now mandatory.PHY output delay reduced from 10ns to 9ns.Added link decision time numbers for low speed.Various Clarifications.1.0 February 2, 2004 1.0rc3 adopted as 1.0 release.1.1rc1 September 1, 2004 Various clarifications and fixes to hold time numbers, sendingRXCMDs, FsLsSerialMode, Vbus control and monitoring,Test_J and Tesk_K signalling, Low Power Mode,Hostdisconnect, ID detection, HS SOF packets, interrupts,Carkit Mode, interface protection, No SYNC/EOP mode,linestate filtering, and AutoResume.1.1rc2 October 4, 2004 Re-arranged text in section 3.8.7.3. Updated contributors list.1.1 October 20, 2004 1.1rc2 adopted as 1.1 release.The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification.iiPromotersARC International Inc.Conexant Systems, Inc.Mentor Graphics CorporationPhilipsSMSCTransDimension, Inc.ContributorsVertenten PhilipsBartOkur PhilipsBatuhanBillAnderson MotorolaMcInerney TransDimensionBillBooker CypressBrianARCBelangerChrisKolb ARCChrisChrisSchell PhilipsChung Wing Yan PhilipsSrokaPhilipsDaveWang PhilipsDavidWooten TransDimensionDavidSMSCEricKawamotoPhilipsMackayFarranFrazier ConexantFrankFredRoberts SynopsysFarooqConexantHassanLee TransDimensionHyunParr MentorIanStandiford TransDimensionJayPhilipsTjiaJeromeMentorSaundersMarkMohamed Benromdhane ConexantSMSCMorganMonksISINabilTaklaTengstrand ARCPeterRamanand Mandayam ConexantDouglas MentorRobSaleemMohamed Synopsys(Author)ShaunReemeyer PhilipsCypressSimonNguyenSubramanyam Sankaran PhilipsTexasInstrumentsViningSueRemple QualcommTerryChen ConexantTimothyConexantChangVincentQuestions should be emailed to lpcwg@.iiiTable of Contents1.Introduction (1)1.1General (1)1.2Naming Convention (1)1.3Acronyms and Terms (1)1.4References (1)2.Generic Low Pin Interface (2)2.1General (2)2.2Signals (2)2.3Protocol (3)2.3.1Bus Ownership (3)2.3.2Transferring Data (3)2.3.3Aborting Data (4)3.UTMI+ Low Pin Interface (5)3.1General (5)3.2Signals (6)3.3Block Diagram (7)3.4Modes (9)3.5Power On and Reset (10)3.6Interrupt Event Notification (10)3.7Timing (11)3.7.1Clock (11)3.7.2Control and Data (13)3.8Synchronous Mode (15)3.8.1ULPI Command Bytes (15)3.8.2USB Packets (18)3.8.3Register Operations (30)3.8.4Aborting ULPI Transfers (37)3.8.5USB Operations (39)3.8.6Vbus Power Control (internal and external) (52)3.8.7OTG Operations (52)3.9Low Power Mode (55)3.9.1Data Line Definition For Low Power Mode (55)3.9.2Entering Low Power Mode (55)3.9.3Exiting Low Power Mode (56)3.9.4False Resume Rejection (57)3.10Full Speed / Low Speed Serial Mode (Optional) (58)3.10.1Data Line Definition For FsLsSerialMode (58)3.10.2Entering FsLsSerialMode (59)3.10.3Exiting FsLsSerialMode (60)3.11Carkit Mode (Optional) (61)3.12Safeguarding PHY Input Signals (62)4.Registers (65)4.1Register Map (65)4.2Immediate Register Set (67)4.2.1Vendor ID and Product ID (67)4.2.2Function Control (68)4.2.3Interface Control (69)4.2.4OTG Control (71)4.2.5USB Interrupt Enable Rising (72)4.2.6USB Interrupt Enable Falling (73)4.2.7USB Interrupt Status (74)4.2.8USB Interrupt Latch (75)4.2.9Debug (76)4.2.10Scratch Register (76)4.2.11Carkit Control (77)4.2.12Carkit Interrupt Delay (77)iv4.2.13Carkit Interrupt Enable (78)4.2.14Carkit Interrupt Status (78)4.2.15Carkit Interrupt Latch (79)4.2.16Carkit Pulse Control (79)4.2.17Transmit Positive Width (80)4.2.18Transmit Negative Width (80)4.2.19Receive Polarity Recovery (80)4.2.20Reserved (81)4.2.21Access Extended Register Set (81)4.2.22Vendor-specific (81)4.3Extended Register Set (81)4.4Register Settings for all Upstream and Downstream signalling modes (81)5.T&MT Connector (83)5.1General (83)5.2Daughter-card (UUT) Specification (83)vFiguresFigure 1 – LPI generic data bus ownership (3)Figure 2 – LPI generic data transmit followed by data receive (3)Figure 3 – Link asserts stp to halt receive data (4)Figure 4 – Creating a ULPI system using wrappers (5)Figure 5 – Block diagram of ULPI PHY (7)Figure 6 – Jitter measurement planes (12)Figure 7 – ULPI timing diagram (13)Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface (14)Figure 9 – Sending of RX CMD (17)Figure 10 – USB data transmit (NOPID) (18)Figure 11 – USB data transmit (PID) (19)Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale) (20)Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale) (21)Figure 14 – USB receive while dir was previously low (22)Figure 15 – USB receive while dir was previously high (23)Figure 16 – USB receive error detected mid-packet (24)Figure 17 – USB receive error during the last byte (25)Figure 18 – USB HS, FS, and LS bit lengths with respect to clock (26)Figure 19 – HS transmit-to-transmit packet timing (29)Figure 20 – HS receive-to-transmit packet timing (29)Figure 21 – Register write (30)Figure 22 – Register read (31)Figure 23 – Register read or write aborted by USB receive during TX CMD byte (31)Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive (32)Figure 25 – USB receive in same cycle as register read data. USB receive is delayed (33)Figure 26 – Register read followed immediately by a USB receive (33)Figure 27 – Register write followed immediately by a USB receive during stp assertion (34)Figure 28 – Register read followed by a USB receive (34)Figure 29 – Extended register write (35)Figure 30 – Extended register read (35)Figure 31 – Extended register read aborted by USB receive during extended address cycle (36)Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit (37)Figure 33 – PHY aborted by Link asserting stp. Link performs register read (38)Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir (38)Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) (40)Figure 36 – Preamble sequence (D+/D- timing not to scale) (41)Figure 37 – LS Suspend and Resume (timing not to scale) (43)Figure 38 – FS Suspend and Resume (timing not to scale) (44)Figure 39 – HS Suspend and Resume (timing not to scale) (46)Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) (47)Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) (48)Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) (49)Figure 43 – Automatic resume signalling (timing not to scale) (50)Figure 44 – USB packet transmit when OpMode is set to 11b (51)Figure 45 – RX CMD V A_VBUS_VLD ≤Vbus indication source (54)Figure 46 – Entering low power mode (55)Figure 47 – Exiting low power mode when PHY provides output clock (56)Figure 48 – Exiting low power mode when Link provides input clock (56)Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts (57)Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts (57)Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down (59)Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered (59)Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running (60)Figure 54 – Interface behaviour when exiting Serial Mode and clock is running (60)Figure 55 – PHY interface protected when the clock is running (62)Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected (63)Figure 57 – PHY automatically exits Low Power Mode with interface protected (63)Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running (64)viFigure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) (64)Figure 60 – Recommended daughter-card configuration (not to scale) (83)viiTablesTable 1 – LPI generic interface signals (2)Table 2 – PHY interface signals (6)Table 3 – Mode summary (9)Table 4 – Clock timing parameters (11)Table 5 – ULPI interface timing (13)Table 6 – Transmit Command (TX CMD) byte format (15)Table 7 – Receive Command (RX CMD) byte format (16)Table 8 – USB specification inter-packet timings (26)Table 9 – PHY pipeline delays (27)Table 10 – Link decision times (28)Table 11 – OTG Control Register power control bits (52)Table 12 – Vbus comparator thresholds (52)Table 13 – RX CMD VbusValid over-current conditions (53)Table 14 – Vbus indicators in the RX CMD required for typical applications (54)Table 15 – Interface signal mapping during Low Power Mode (55)Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode (58)Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode (58)Table 18 – Carkit signal mapping (61)Table 19 – Register map (66)Table 20 – Register access legend (67)Table 21 – Vendor ID and Product ID register description (67)Table 22 – Function Control register (68)Table 23 – Interface Control register (70)Table 24 – OTG Control register (71)Table 25 – USB Interrupt Enable Rising register (72)Table 26 – USB Interrupt Enable Falling register (73)Table 27 – USB Interrupt Status register (74)Table 28 – USB Interrupt Latch register (75)Table 29 – Rules for setting Interrupt Latch register bits (75)Table 30 – Debug register (76)Table 31 – Scratch register (76)Table 32 – Carkit Control Register (77)Table 33 – Carkit Interrupt Delay register (77)Table 34 – Carkit Interrupt Enable register (78)Table 35 – Carkit Interrupt Status Register (78)Table 36 – Carkit Interrupt Latch register (79)Table 37 – Carkit Pulse Control (79)Table 38 – Transmit Positive Width (80)Table 39 – Transmit Negative Width (80)Table 40 – Receive Polarity Recovery (81)Table 41 – Upstream and downstream signalling modes (82)Table 42 – T&MT connector pin view (84)Table 43 – T&MT connector pin allocation (84)Table 44 – T&MT pin description (85)viii1. Introduction1.1 GeneralThis specification defines a generic PHY interface in Chapter 2.In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB transceiver implementations supporting On-The-Go, host, and peripheral application spaces.Convention1.2 NamingEmphasis is placed on normal descriptive text using underlined Arial font, e.g. must.Signal names are represented using the lowercase bold Arial font, e.g. clk.Registers are represented using initial caps, bold Arial font, e.g. OTG Control.Register bits are represented using initial caps, bold italic Arial font, e.g. USB Interrupt Enable Falling. 1.3 Acronyms and TermsA-device Device with a Standard-A or Mini-A plug inserted into its receptacleB-device Device with a Standard-B or Mini-B plug inserted into its receptacleDeviceDRD Dual-RoleFPGA Field Programmable Gate ArraySpeedFS FullHNP Host Negotiation ProtocolHS Hi-SpeedLink ASIC, SIE, or FPGA that connects to an ULPI transceiverLPI Low Pin InterfaceSpeedLS LowOTG On-The-GoPHY Physical Layer (Transceiver)PLL Phase Locked LoopSE0 Single Ended ZeroSIE Serial Interface EngineSRP Session Request ProtocolT&MT Transceiver and Macrocell TesterULPI UTMI+ Low Pin InterfaceUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InteraceUUT Unit Under Test1.4 References[Ref 1] Universal Serial Bus Specification, Revision 2.0[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a[Ref 3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, v1.05[Ref 4] UTMI+ Specification, Revision 1.0[Ref 5] CEA-2011, OTG Transceiver Specification[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification[Ref 7] USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.212. Generic Low Pin Interface2.1 GeneralThis section describes a generic low pin interface (LPI) between a Link and a PHY. Interface signals are defined and the basic communication protocol is described. The generic interface can be used as a common starting point for defining multiple application-specific interfaces.Chapter 3 defines the UTMI+ Low Pin Interface (ULPI), which is based on the generic interface described here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2.2.2 SignalsThe LPI transceiver interface signals are described in Table 1. The interface described here is generic, and can be used to transport many different data types. Depending on the application, the data stream can be used to transmit and receive packets, access a register set, generate interrupts, and even redefine the interface itself. All interface signals are synchronous when clock is toggling, and asynchronous when clock is not toggling. Data stream definition is application-specific and should be explicitly defined for each application space for inter-operability.Control signals dir, stp, and nxt are specified with the assumption that the PHY is the master of the data bus. If required, an implementation can define the Link as the master. If the Link is the master of the interface, the control signal direction and protocol must be reversed.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. Both directions are allowed. All interface signals are synchronous to clock.data I/O Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.dir OUT Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.stp IN Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link.nxt OUT Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume.Table 1 – LPI generic interface signals22.3 ProtocolOwnership2.3.1 BusThe PHY is the master of the LPI bi-directional data bus. Ownership of the data bus is determined by the dir signal from the PHY, as shown in Figure 1. When dir is low, the Link can drive data on the bus. When dir is high, the PHY can drive data on the bus. A change in dir causes a turnaround cycle on the bus during which, neither Link nor PHY can drive the bus. Data during the turnaround cycle is undefined and must be ignored by both Link and PHY.The dir signal can be used to directly control the data output buffers of both PHY and Link.Figure 1 – LPI generic data bus ownershipData2.3.2 TransferringAs shown in the first half of Figure 2, the Link continuously drives the data bus to 00h during idle. The Link transmits data to the PHY by driving a non-zero value on the data bus. To signal the end of data transmission, the Link asserts stp in the cycle following the last data byte.In the second half of Figure 2, the Link receives data when the PHY asserts dir. The PHY asserts dir only when it has data to send to the Link, and keeps dir low at all other times. The PHY drives data to the Link after the turnaround cycle.The nxt signal can be used by the PHY to throttle the data during transmit and receive. During transmit, nxt may be asserted in the same cycle that the Link asserts stp.Figure 2 – LPI generic data transmit followed by data receive2.3.3 AbortingDataThe PHY can assert dir to interrupt any data being transmitted by the Link. If the Link needs to interrupt data being received from the PHY, it asserts stp for one clock cycle, as shown in Figure 3. This causes the PHY to unconditionally1 de-assert dir and accept a complete data transmit from the Link. The PHY may re-assert dir again only when the data transmit from the Link has completed.Figure 3 – Link asserts stp to halt receive data1 The PHY will not de-assert dir if the ULPI interface is not usable. For example, if the internal PLL is not stable.3. UTMI+ Low Pin Interface3.1 GeneralThis section describes how any UTMI+ core can be wrapped to convert it to the smaller LPI interface. The generic interface described in chapter 2 is used as a starting point. This section always over-rides anything stated in chapter 2. While this specification details support of UTMI+ Level 3, PHY implementers may choose to support any of the Levels defined in UTMI+.ULPI defines a PHY to Link interface of 8 or 12 signals that allows a lower pin count option for connecting to an external transceiver that may be based on the UTMI+ specification. The pin count reduction is achieved by having relatively static UTMI+ signals be accessed through registers and by providing a bi-directional data bus that carries USB data and provides a means of accessing register data on the ULPI transceiver.This specification relies on concepts and terminology that are defined in the UTMI+ specification [Ref 4]. Specifically, if a ULPI PHY design is based on an internal UTMI+ core, then that core must implement the following UTMI+ features.Linestate must accurately reflect D+/D- to within 2-3 clocks. It is up to individual Link designers to use Linestate to time bus events.Filtering to prevent spurious SE0/SE1 states appearing on Linestate due to skew between D+ and D-. Filtering of 14 clock cycles is required in Low Speed, and 2 clock cycles in Full Speed and Hi-Speed modes.The PHY must internally block the USB receive path during transmit. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.TxReady must be used for all types of data transmitted, including Chirp.Due to noise on the USB, it is possible that RxActive asserts and then de-asserts without any valid data being received, and RxValid will not assert. The Link should operate normally with these data-less RxActive assertions.As shown in Figure 4, a PHY or Link based on this specification can be implemented as an almost transparent wrapper around existing UTMI+ IP cores, preserving the original UTMI+ packet timing, while reducing pin count and leaving all functionality intact. This should not be taken to imply that other implementations are not possible.Figure 4 – Creating a ULPI system using wrappers3.2 SignalsTable 2 describes the ULPI interface on the PHY. The PHY is always the master of the ULPI bus. USB and Miscellaneous signals may vary with each implementation and are given only as a guide to PHY designers.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. The PHY must be capable of providing a 60MHz output clock. Support for an input 60MHz clock is optional. If the PHY supports both clock directions, it must not use the ULPI control and data signals for setting the clock direction.Data bus. Driven to 00h by the Link when the ULPI bus is idle. Two bus widths are allowed:• 8-bit data timed on rising edge of clock.data I/O• (Optional) 4-bit data timed on rising and falling edges of clock.dir OUT Controls the direction of the data bus2. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PLL is not stable. This applies whether Link or PHY is the clock source.stp IN The Link must assert stp to signal the end of a USB transmit packet or a register write operation, and optionally to stop any receive. The stp signal must be asserted in the cycle after the last data byte is presented on the bus.nxt OUT The PHY asserts nxt to throttle all data types, except register read data and the RX CMD. Identical to RxValid during USB receive, and TxReady during USB transmit. The PHY also asserts nxt and dir simultaneously to indicate USB receive activity (RxActive), if dir was previously low. The PHY is not allowed to assert nxt during the first cycle of the TX CMD driven by the Link.USB InterfaceD+ I/O D+ pin of the USB cable. Required.D- I/O D- pin of the USB cable. Required.ID IN ID pin of the USB cable. Required for OTG-capable PHY’s.VBUS I/O V BUS pin of the USB cable. Required for OTG-capable PHY’s. Required for driving V BUS and the V BUS comparators.MiscellaneousXI IN Crystal input pin. Vendors should specify supported crystal frequencies. XO OUT Crystal output pin.C+ I/O Positive terminal of charge pump capacitor.C- I/O Negative terminal of charge pump capacitor.SPKR_L IN Optional Carkit left/mono speaker input signal.SPKR_MIC I/O Optional Carkit right speaker input or microphone output signal.RBIAS I/O Bias current resistor.Table 2 – PHY interface signals2 UTMI+ wrapper developers should note that data bus control has been reversed from UTMI to ensure that USB data reception is not interrupted by the Link.3.3 BlockDiagramAn example block diagram of a ULPI PHY is shown in Figure 5. This example is based on an internal UTMI+ Level 3 core [Ref 4], which can interface to peripheral, host, and On-The-Go Link cores. A description of each major block is given below.ULPI InterfaceUSBCableChargePumpCapacitor Figure 5 – Block diagram of ULPI PHYUTMI+ Level 3 PHY coreThe ULPI PHY may contain a core that is compliant to any UTMI+ level [Ref 4]. Signals for 16-bit data buses are not supported in ULPI. While Figure 5 shows the typical blocks for a Level 3 UTMI+ core, the PHY vendor must specify the intended UTMI+ level, and provide the functionality necessary for compliance to that level.ULPI PHY WrapperThe ULPI PHY wrapper of Figure 5 reduces the UTMI+ interface to the Low Pin Interface described in this document. All signals shown on the UTMI+ Level 3 PHY core are reduced to the ULPI interface signals clock, data, dir, stp, and nxt. The Register Map stores the relatively static signals of the UTMI+ interface. Crystal Oscillator and PLLWhen a crystal is attached to the PHY, the internal clock(s) and the external 60MHz interface clock are generated from the internal PLL. When no crystal is attached, the PHY may optionally generate the internal clock(s) from an input 60MHz clock provided by the Link.General BiasingInternal analog circuits require an accurate bias current. This is typically generated using an external, accurate reference resistor.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external VBUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external VBUS source is provided the PHY may optionally provide for a VBUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.Power-On-ResetA power-on-reset circuit must be provided in the PHY. When power is first applied to the PHY, the power-on-reset will reset all circuitry and leave the ULPI interface in a usable state.Carkit OptionThe PHY may optionally support Carkit Mode [Ref 6]. While in Carkit Mode, the PHY routes speaker and microphone signals between the Link and the USB cable. In carkit mono mode, SPKR_L inputs a mono speaker signal and SPKR_MIC outputs the microphone signal, MIC. In carkit stereo mode, SPKR_L inputs the left speaker signal, and SPKR_MIC inputs the right speaker signal, SPKR_R.3.4 ModesThe ULPI interface can operate in one of five independent modes listed in Table 3. The interface is in Synchronous Mode by default. Other modes are enabled by bits in the Function Control and Interface Control registers. In Synchronous Mode, the data bus carries commands and data. In other modes, the data pins are redefined with different functionality. Synchronous Mode and Low Power Mode are mandatory.Mode Name Mode DescriptionSynchronous Mode This is the normal mode of operation. The clock is running and is stablewith the characteristics defined in section 3.6. The ULPI interface carriescommands and data that are synchronous to clock.Low Power Mode The PHY is powered down with the clock stopped. The PHY keeps dirasserted, and the data bus is redefined to carry LineState and interrupts.See section 3.9 for more information.6-pin FS/LS Serial Mode (optional) The data bus is redefined to 6-pin serial mode, including 6 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. This mode is valid only for implementations with an 8-bit data bus. See section 3.10 for more information.3-pin FS/LS Serial Mode (optional) The data bus is redefined to 3-pin serial mode, including 3 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. See section 3.10 for more information.Carkit Mode (optional) The data bus is redefined to Carkit mode [Ref 6], including 2 pins for serial UART data, and 1 pin to signal interrupt events. The clock may optionally be stopped. See section 3.11 for more information.Table 3 – Mode summary。

纳米颗粒自组装技术方案

纳米颗粒自组装技术方案

Langmuir, 2007, 23, 5757-5760.
无模板法
NPs的无模板定向自组 装(Template-free DLS): 通常采用刺激响应型分 子作为NPs的保护剂, 在受到环境刺激(如pH 、温度、光照、离子强 度等)时,修饰分子会作 出响应,带动NPs自组 装成相应的结构。
Fig 2. Schematic representation of template-free assemblies based on different stimuli-responsive
different aspect ratios.
Langmuir, 2008, 24:5233-5237.
然而在液相中,金属NPs的相互作用较弱且形式单一,难以定向自组装。所
以通常采用修饰法或施加外场,增强对金属NPs的定向调控能力。
分离是强化定向迁移和减小非定向扩散的过程
Table 1. Interactions potentials
of a region within the drop contact line, taken, for suspensions of spheres (a), ellipsoids (b), and
ellipsoids mixed with surfactant (SDS; 0.2 wt%) (c). Spheres pack closely at the contact line. Confocal
Adv. Funct. Mater., 2009, 19, 3271–3278.
其它物理组装法
• 自然沉降法:适用于300~550nm之间的纳米颗粒,不至于太轻太重。简单但不 可控,有序度不高;
• 旋涂法:利用离心力替代重力。离心力过大易出现裂痕,离心力太小容易多 层堆叠;

lbp3500维修手册

lbp3500维修手册
Indicates an item requiring care to avoid electric shocks.
Indicates an item requiring care to avoid combustion (fire).
Indicates an item prohibiting disassembly to avoid electric shocks or problems.
1.3 Product Specifications ................................................................................................................................1- 1 1.3.1 Specifications .......................................................................................................................................................... 1- 1
1.4 Name of Parts.............................................................................................................................................1- 3 1.4.1 External View........................................................................................................................................................... 1- 3 1.4.2 Cross Section .......................................................................................................................................................... 1- 4

浅析技术管理的重要性

浅析技术管理的重要性

浅析技术管理的重要性英国启航论文在现如今商业发展大环境下,技术管理是能够有效地提高工作效率的一种新的管理理念,一种新的技术。

现在的商业更需要技术驱动型的现代科技管理理念,也正因为这种管理理念的有效实践,为工作业绩做了很好的铺垫。

实际上,对于一家企业来说,管理技术是贯穿整个阶层和所有纪律最重要的部分。

因此,管理科技的原则对那些想要有效地处理应用,技术转移和集成整合的所有企业都很适合,而不仅仅是适应于传统的科学社会群体。

新的经营模式有助于企业创造更加优质的产品和服务,以及更加快捷和更高质量的商品,这一新技术在每一家企业中都占据着越来越重要得到地位。

有很多企业、政府部门、金融机构、建筑公司和医疗供应商都得在有效的技术型环境下运作,才能更有效的管理企业。

510转基因项目可以让我们更好的了解到管理技术的几个特点:Knowledge of modern technology management concepts and best practices provides the foundation for effective job performance in technology-driven business environments. Management of Technology discusses cutting-edge management concepts, tools, and techniques that effectively work in today's technology-intensive organizations.New management tools and techniques play an increasingly important role in every organization for creating quality products, services, and content faster, cheaper, and at a higher quality. Technology crosses virtually all levels and all disciplines of an enterprise. Therefore, the principles of managing technology are relevant not only to people in the traditional engineering-scientific community, but also apply to any organization and business that must effectively deal with the application, integration, and transfer of technology.Financial institutions, government agencies, architectural firms, and healthcare providers are just a few examples of the vast array of organizations that must function effectively in technology-based environments, and therefore be able to manage technology. Specifically, TMGT 510 course helps to understand following features:Methods for assessing the effectiveness and performance of the organization and its management processes.Insight into the functioning of contemporary work processes, such as concurrent engineering, design-build, integrated product development, and phase-gate processes.Special tools and techniques for effectively managing technology-based projects, including dealing with organizational interfaces from R&D to markets.Managerial Practices and ToolsTechnology-intensive projects are managed under a project management (PM) framework that includes a PM Plan, project organization, PM tools and techniques, and performance monitoring, and control. Thamhain (2009) suggested, “Tools such as the Project Maturity Model, the Six Sigma Project Management Process and focus groups, can serve as a framework for analyzing and fine-tuning the team development and management process” (p. 130, para. 1). The tools and techniques can be grouped in the categories based on their application as (1) Product Management, (2) Project Management, (3) General Management, (4) Strategic, (5) Quality Control. Organizational Behavior deals with the management of individuals, groups, organizations, processes and dynamic environments. Human Resources Management deals with the issues such as hiring, career management, management of hierarchical levels, management of competencies and training, remuneration, internal communication and evaluation of staff. HRM and OB have to deal with scientists, researchers, engineers, technicians and other technologists. Thamhain (2005) has stated, “Today’s business culture demands that project teams — in meeting and performing their project responsibilities —engage in multiple activities” (p. 35, para. 2). The work process in the technology-intensive enterprises is team-based, self-directed, and agile which are structured for parallel, concurrent execution of the work. They affect people issues, management style, and organizational culture and management tools such as scheduling, budgeting, and project performance analysis. Technology-intensive enterprises have a unique organizational culture with its own norms, value, and work ethics. These cultures are team-oriented in terms of decision-making, workflow, performance evaluation, and workgroup management.Project ManagementProject is a temporary task undertaken by a project manager and his team to produce a specific output and a product. Contemporary linear work processes and top-down controls are no longer adequate, but are steadily being switched with alternate organizational designs, new management methods and business processes, such as concurrent engineering (CE), design-build, and stage-gate protocols. CE is the consideration of the factors like product functionality, manufacturing, assembly, testing, maintenance, reliability, cost, and quality associated with the life cycle of the product during design phase. Thamhain (2005) explained the benefits of formal project management system so that managers can better respond to specific requirements, schedule management, short product life cycle, work culture differences, and diverse group dynamics (pp. 141-142). There are various practices of the PM and some of the best ones are described as to plan the work by utilizing a project definition document and to create a planning horizon. It is in the best interest to define PM procedures upfront and to look for warning signs ahead of time.Management should ensure that the sponsor approves scope-change requests and guard against the scope creep. It is very important to assess potential risk throughout the project and to work on a risk mitigation plan as necessary.Team managementThamhain (2005) has stated, “Today’s business culture demands that project teams — in meeting and performing their project responsibilities — engage in multiple activities” (p. 35, para. 2). Project teams are time limited and they produce one-time outputs, such as a new product or service. The tasks involved in the project teams are non-repetitive and require knowledge, judgment, and expertise. The project team consists of individuals from different functional unit. At the completion of the project, the individuals return to their respective units or move on to the next project. Not all projects may have the same members; however, they may have some common members. Staffing is also one of the most important elements for the success of the project. The team members of the project should possess just not only the pre-required skills, qualifications, and experience necessary for the job, but they must also possess those traits personality and ethics of work that are easily compatible with the values and the culture of the organization (Markopoulos et al., 2008, p. 366). The team should include people who understand the project thoroughly, who are technical experts, who can provide objectivity in the process and outcome, a nd suppliers. The knowledge workers of today’s modern world expect autonomy, a continuous level of learning, and innovation to be a vital part of the job. They are comparatively much better and educated as compared to their counterparts in the past. They function better in a self-directed and high performance groups and teams. Teams are an important asset when it comes to completing projects. When experiences teams are assigned tasks they come up with fruitful results for the organization; therefore, the design of the team is a much more important and significant managerial control. It also facilitates the better functioning and performance of self-directed teams and improvises the quality and worth of the member relationships and contentment.Decision making authoritiesThe Decision-making authority, accountabilities, and responsibilities of the team members should be defined in a very clear way to eliminate the role of any kind of ambiguity, uncertainty, or interdepartmental Conflicts. Once the project teams have been properly assembled and have settled down, then they should be supervised, coached, and supported at regular intervals to ensure that they are fulfilling their roles as expected (Markopoulos et al., 2008, p. 366). Motivation, empowerment, and mentoring are no doubt powerful and they exert indirect controls over the project in order to gain success by bringing out the best in an individual as well as project team performances. Evaluation of the project team and each individual involved in the team is important for the project manager and the organization. Evaluating teamproject performance is the key if the team needs to succeed and improve on future projects.The role of the organization in Project SuccessOrganizational design also plays a very vital role in controlling and supervising the technology intensive work in any organization. Organizational design contemplations consists of: the nature of the service or the product, the sequential as well as spatial distribution of the locations of the work, in-house in contrast to the outsourcing of the work, the convenience and flexibility given by virtual organizations, simultaneous engineering and incorporated product development, the extent of the use of technology, the availability and accessibility of core competencies and most important of all the strategic objectives of the company (Booth, 2011, pp. 111-113). The contemporary management practices indicate that the project management techniques and tools should be incapable of solving the complex problems, and at the same time, facilitating the effective and efficient control of deliverables of work, and eventually contributing to the continuous improvement.Tools & Control techniques for Project ManagementThe tools of project management should not only fulfill their aimed or intended purpose, but they should also be user friendly, easily compatible with the culture of the organization, and in alignment with the processes of the business (Markopoulos et al., 2008, p. 367). The new tools should be pre tested in the environment in which they will be used, and should ask for feedback from the users. Therefore, “fixing” incompatibilities eventually simplifies the introduction of the new tool in the organization or the workplace. PM control techniques are categorized into analytical management, people oriented and press oriented. The following discussions associate widely accepted PM techniques with the ‘monitoring and control’ feature of PMBOK as a source of knowledge (Markopoulos et al., 2008, p. 366). This is not an in-depth source as many other methods and means are present from which the Project Manager can have his pick. BenchmarkingBenchmarking is the comparison of tangible projects with comparable projects to spot the strong points of that project to come up with better ideas and serve as a standard to assess the performance. Institutions to assess their strong points and weak points as compared to the organization, which is considered the best, use benchmarking. It is the basis of controls, which stimulate the process of rectification. Benchmarking is a key method to verify estimates and schedules of a company by itself (Pinheiro, 2010, p. 7). Project Managers use benchmarks to compare and check on factors such as the time to market, major accomplishments, rates of accidents regarding safety, costs of production per unit, and satisfied customers. The selection of benchmarks is very specific and is relevant to the objectives of a company, which show great improvement. In order to choose a benchmark, theknowledge of how and what to benchmark, collection and analysis of data to pick out the ‘best in class’, assessing tactics, operations, and procedures alongside the benchmark, putting up targets of improvement, and rectification measures in case the result is below the benchmark (Pinheiro, 2010, p. 7).Change ManagementChange management is the process of shifting of technology, organization, person, processes, or political balance from current state to the next state. According to New man (2012), “a strong sense of imagination, creativity and patience is requiredif one is to persevere through the process” (p. 68). Change management can be either on the part of organization or on the part of an individual, it is about transforming and modifying in order to maintain or improve effectiveness. People resist and act conservative while undergoing a change. From organizational perspective, changes include mission/vision changes, strategic changes, operational changes, technological changes, and behavioral changes. According to Raineri (2011), “change management practices include a variety of organizational interventions that, when executed properly and in consistency with internal and external organizational events, facilitate the enactment of organizational change processes” (p. 266). Change affects entire organization both outside and inside the organization. Both the organization and the employees get under pressure while undergoing a change. Management requires some basic skills for managing changes that include:Skills to identify the problem.Skills to formulate techniques and strategies to solve those problems.Skills of implementing the processes leading towards change.Problem DiagnosisProblem diagnosis is the investigation to find out the root cause of any problem. Proper resource allocation is required to help diagnose forces and factors and resolve the problem. Technology facilitates rapid detection, diagnosis, and diffusion of problem by insuring systematic, detailed, clear, and reliable methods and techniques like rapid detection of problem, continuous monitoring, and correction from deviation ant it may include following steps: Is the problem recoverable?Does it need to be resolved?Are adequate resources available?How long will it take?Is this the appropriate time?MentoringA mentor is generally defined as a person with experience in an organization that has gained a certain rank or achievement and can support the professional development of people with less experience in that organizationInformal or traditional mentoring emphasize mainly on the protégé. Mentor and protégé work mutually to develop a plan that caters protégé’s career goals as well as private goals. The mentor and protégé pair together by their own internal forces that create the relationship. Generally, traditional mentoring lasts from several years to lifetime. This sort of mentoring usually takes place by spending time together and it flourish because both sides have a legitimate desire for each mutual interest (Kram, 1985, p. 22).Formal mentoring is based on a contract between a mentor and a protégé, a defined structure for mentoring and possibly a program of support. In a formal mentoring relation, there is expression of expectations, objectives, procedure going to be used the frequency, period of agreement and conditions are set first.Management of TechnologyTechnology Management is the set of management guidelines that enables an organization to maintain its technological essentials build a competitive advantage. The role of the Technology Management factor in an organization is to gasp the worth of certain technology for the firm. Steady technology development is valuable with the expectation that there is a value for the client and subsequently the Technology Management Function in an organization might as well have the ability to argue when to invest in technology infrastructure and when not to (Sabeel, Gopal and Rajashekhar, 2012, p. 2). Technology has empowered people to realize extraordinary change in the way they work by creating, advancing, utilizing and by progressing, upgrading technologyManagement confronts some running problems in Technology Management. The biggest around them is when the perfect time to finance technology. Most business fear to invest at present stage as they think that technology is adapting so quick that speculation made today will come to be basic soon and the investment may not ready to apprehend the sum cost brought about in it besides when and how to move to the next stage. Separated from running ahead with putting resources into technology outside of the norm, the firm needs to graph a point-by-point move toward how it will eliminate the present technology level to move to next level.Slow transformation over the period keeps the crux in managing technology both on the shop floor and in its financial accounts. Technology is not just modifyingstandard of how to work but it likewise taking it to the next level where most industry player should not just check out technology actually to cut expenses but in addition to drive technological enhancements and efficiencies (Dolinsek and Strukelj, 2012, p. 30).英国启航论文。

萨福铝焊机说明书

萨福铝焊机说明书

B - 安装调试 ............................................................................................................10 1. 拆除包装 .......................................................................................................10 2. 送丝机连接...................................................................................................10 3. 主电源的电路连接 .....................................................................................10 4. 焊枪的连接...................................................................................................10
中文
目录
安全说明 .....................................................................................................................2
A - 总体介绍 ...............................................................................................................7 1. 装置简介 .........................................................................................................7 2. 焊接设备组成 ................................................................................................7 3. 前面板描述.....................................................................................................8 4. 选配件..............................................................................................................8 5. OPTIPULS i / i W技术规格 .............................................................................8 6. 尺寸和重量.....................................................................................................9 7. 冷却装置的技术规格......................................................................................9

杨梦苏教授1984年毕业于厦门大学,1988年获得加拿大

杨梦苏教授1984年毕业于厦门大学,1988年获得加拿大

简介杨梦甦教授1984年毕业于厦门大学化学系,1993年获得加拿大多伦多大学博士学位,1993-1994期间在美国加州生物医学机构Scripps Research Institute从事研究工作。

1994年底加入香港城市大学,现任香港城市大学生物及化学系讲座教授和香港城市大学深圳生物医药中心主任,并兼任英国中兰开夏大学、浙江大学、解放军第三军医大学、沈阳药科大学、及解放军总医院客座教授。

在行政工作方面担任香港城市大学校董会荣誉学位委员会、大学顾问委员会、大学教务会、研究生院理事会等多个委员会成员。

杨教授主要研究领域为生物芯片技术的开发与应用和纳米生物领域的基础与应用研究, 1995年迄今成功获得包括国家高科技发展计划(863计划)、香港特区政府创新科技基金和研究资助局、及香港赛马会基金等逾6千万港元研究基金的资助,负责管理多个大型科研项目,亦是香港特区政府大学资助委员会之“药物发现与合成分子技术研究”、“中药基础研究与开发”、“海洋环境研究与创新技术”三个卓越学科的主要成员之一。

迄今在国际权威杂志共发表论文160余篇,专著章节17篇,在国内核心杂志发表论文50余篇,在大型国际会议共发表论文80余篇,应邀在各大学和研究机构做过逾70场学术报告,在相关领域申请/获得20多项中国及美国专利。

杨教授实验室已培训18名博士、8名硕士及16名博士后。

杨教授为香港特区政府创新科技基金评审委员会和健康防护基金评审委员会成员,及香港特区政府创新科技署纳米技术和先进材料研究院(NAMI)技术顾问,并兼任英国皇家化学会专业杂志《The Analyst》和中国化学会专业杂志《生命科学仪器》编辑委员会成员,德国《Microchimica Acta》国际顾问委员会成员,以及国际生物芯片大会学术委员会和世界华人高科技化学大会学术委员会成员。

杨教授从2002年主持筹建香港城市大学深圳生物医药中心,领导该中心成功获得包括国家高科技发展计划(863)课题及广东省科技重点攻关项目的资助,并得到深圳市/广东省政府的多次奖励,被授予深圳市生物芯片重点实验室的称号。

TD信息元素详解

TD信息元素详解

信息元素功能性定义作者:李欣目录目录 (1)信息元素功能性定义 (11)1 核心网信息元素 (11)1.1 CN Information elements (11)1.2 CN Domain System Information (11)1.3 CN Information info (11)1.4 IMEI (11)1.5 IMSI (GSM-MAP) (11)1.6 Intra Domain NAS Node Selector (11)1.7 Location Area Identification (12)1.8 NAS message (12)1.9 NAS system information (GSM-MAP) (12)1.10 Paging record type identifier (12)1.11 PLMN identity (12)1.12 PLMN Type (12)1.13 P-TMSI (GSM-MAP) (12)1.14 RAB identity (12)1.15 Routing Area Code (12)1.16 Routing Area Identification (13)1.17 TMSI (GSM-MAP) (13)2 UTRAN 移动信息元素 (13)2.1 Cell Access Restriction (13)2.2 Cell identity (13)2.3 Cell selection and re-selection info for SIB3/4 (13)2.4 Cell selection and re-selection info for SIB11/12 (13)2.5 Mapping Info (14)2.6 URA identity (14)3 UE 信息元素 (14)3.1 Activation time (14)3.2 Capability Update Requirement (14)3.3 Cell update cause (15)3.4 Ciphering Algorithm (15)3.5 Ciphering mode info (15)3.6 CN domain specific DRX cycle length coefficient (15)3.7 CPCH Parameters (15)3.8 C-RNTI (15)3.9 DRAC system information (15)3.10 Void (16)3.11 Establishment cause (16)3.12 Expiration Time Factor (16)3.13 Failure cause (16)3.14 Failure cause and error information (16)3.15 Initial UE identity (16)3.16 Integrity check info (16)3.17 Integrity protection activation info (17)3.18 Integrity protection Algorithm (17)3.19 Integrity protection mode info (17)3.20 Maximum bit rate (17)3.21 Measurement capability (17)3.22 Paging cause (17)3.23 Paging record (17)3.24 PDCP capability (17)3.25 Physical channel capability (18)3.26 Protocol error cause (18)3.27 Protocol error indicator (18)3.28 RB timer indicator (18)3.29 Redirection info (18)3.30 Re-establishment timer (18)3.31 Rejection cause (18)3.32 Release cause (18)3.33 RF capability FDD (19)3.34 RLC capability (19)3.35 RLC re-establish indicator (19)3.36 RRC transaction identifier (19)3.37 Security capability (19)3.38 START (19)3.39 Transmission probability (19)3.40 Transport channel capability (20)3.41 UE multi-mode/multi-RAT capability (20)3.42 UE radio access capability (20)3.43 UE Timers and Constants in connected mode (21)3.44 UE Timers and Constants in idle mode (21)3.45 UE positioning capability (21)3.46 URA update cause (21)3.47 U-RNTI (21)3.48 U-RNTI Short (21)3.49 UTRAN DRX cycle length coefficient (21)3.50 Wait time (21)3.51 UE Specific Behavior Information 1 idle (21)3.52 UE Specific Behavior Information 1 interRAT (22)4 无线承载信息元素 (22)4.0 Default configuration identity (22)4.1 Downlink RLC STATUS info (22)4.2 PDCP info (22)4.3 PDCP SN info (22)4.4 Polling info (22)4.5 Predefined configuration identity (23)4.6 Predefined configuration value tag (23)4.7 Predefined RB configuration (23)4.8 RAB info (23)4.9 RAB info Post (23)4.10 RAB information for setup (23)4.11 RAB information to reconfigure (24)4.12 NAS Synchronization indicator (24)4.13 RB activation time info (24)4.14 RB COUNT-C MSB information (24)4.15 RB COUNT-C information (24)4.16 RB identity (24)4.17 RB information to be affected (24)4.18 RB information to reconfigure (25)4.19 RB information to release (25)4.20 RB information to setup (25)4.21 RB mapping info (25)4.22 RB with PDCP information (25)4.23 RLC info (25)4.24 Signaling RB information to setup (26)4.25 Transmission RLC Discard (26)5 传输信道信息元素 (26)5.1 Added or Reconfigured DL TrCH information (26)5.2 Added or Reconfigured UL TrCH information (27)5.3 CPCH set ID (27)5.4 Deleted DL TrCH information (27)5.5 Deleted UL TrCH information (27)5.6 DL Transport channel information common for all transport channels (27)5.7 DRAC Static Information (27)5.8 Power Offset Information (28)5.9 Predefined TrCH configuration (28)5.10 Quality Target (28)5.11 Semi-static Transport Format Information (28)5.12 TFCI Field 2 Information (28)5.13 TFCS Explicit Configuration (28)5.14 TFCS Information for DSCH (TFCI range method) (29)5.15 TFCS Reconfiguration/Addition Information (29)5.16 TFCS Removal Information (29)5.17 Void (29)5.18 Transport channel identity (29)5.19 Transport Format Combination (TFC) (29)5.20 Transport Format Combination Set (29)5.21 Transport Format Combination Set Identity (29)5.22 Transport Format Combination Subset (29)5.23 Transport Format Set (29)5.24 UL Transport channel information common for all transport channels (30)6 物理信道信息元素 (30)6.1 AC-to-ASC mapping (30)6.2 AICH Info (30)6.3 AICH Power offset (30)6.4 Allocation period info (30)6.5 Alpha (30)6.6 ASC Setting (30)6.7 Void (31)6.8 CCTrCH power control info (31)6.9 Cell parameters Id (31)6.10 Common timeslot info (31)6.11 Constant value (31)6.12 CPCH persistence levels (31)6.13 CPCH set info (31)6.14 CPCH Status Indication mode (31)6.15 CSICH Power offset (32)6.16 Default DPCH Offset Value (32)6.17 Downlink channelisation codes (32)6.18 Downlink DPCH info common for all RL (32)6.19 Downlink DPCH info common for all RL Post (32)6.20 Downlink DPCH info common for all RL Pre (32)6.21 Downlink DPCH info for each RL (32)6.22 Downlink DPCH info for each RL Post (33)6.23 Downlink DPCH power control information (33)6.24 Downlink information common for all radio links (33)6.25 Downlink information common for all radio links Post (33)6.26 Downlink information common for all radio links Pre (33)6.27 Downlink information for each radio link (33)6.28 Downlink information for each radio link Post (33)6.29 Void (33)6.30 Downlink PDSCH information (33)6.31 Downlink rate matching restriction information (34)6.32 Downlink Timeslots and Codes (34)6.33 DPCH compressed mode info (34)6.34 DPCH Compressed Mode Status Info (34)6.35 Dynamic persistence level (34)6.36 Frequency info (34)6.37 Individual timeslot info (35)6.38 Individual Timeslot interference (35)6.39 Maximum allowed UL TX power (35)6.40 Void (35)6.41 Midamble shift and burst type (35)6.42 PDSCH Capacity Allocation info (35)6.43 PDSCH code mapping (36)6.44 PDSCH info (36)6.45 PDSCH Power Control info (36)6.46 PDSCH system information (36)6.47 PDSCH with SHO DCH Info (36)6.48 Persistence scaling factors (36)6.49 PICH Info (36)6.50 PICH Power offset (37)6.51 PRACH Channelisation Code List (37)6.52 PRACH info (for RACH) (37)6.53 PRACH partitioning (37)6.54 PRACH power offset (37)6.55 PRACH system information list (37)6.56 Predefined PhyCH configuration (38)6.57 Primary CCPCH info (38)6.58 Primary CCPCH info post (38)6.59 Primary CCPCH TX Power (38)6.60 Primary CPICH info (38)6.61 Primary CPICH Tx power (38)6.62 Primary CPICH usage for channel estimation (38)6.63 PUSCH info (38)6.64 PUSCH Capacity Allocation info (38)6.65 PUSCH power control info (39)6.66 PUSCH system information (39)6.67 RACH transmission parameters (39)6.68 Radio link addition information (39)6.69 Radio link removal information (39)6.70 SCCPCH Information for FACH (39)6.71 Secondary CCPCH info (39)6.72 Secondary CCPCH system information (40)6.73 Secondary CPICH info (40)6.74 Secondary scrambling code (40)6.75 SFN Time info (40)6.76 SSDT cell identity (40)6.77 SSDT information (40)6.78 STTD indicator (40)6.79 TDD open loop power control (41)6.80 TFC Control duration (41)6.81 TFCI Combining Indicator (41)6.82 TGPSI (41)6.83 Time info (41)6.84 Timeslot number (41)6.85 TPC combination index (41)6.86 TSTD indicator (41)6.87 TX Diversity Mode (41)6.88 Uplink DPCH info (41)6.89 Uplink DPCH info Post (42)6.90 Uplink DPCH info Pre (42)6.91 Uplink DPCH power control info (42)6.92 Uplink DPCH power control info Post (42)6.93 Uplink DPCH power control info Pre (42)6.94 Uplink Timeslots and Codes (42)6.95 Uplink Timing Advance (42)6.96 Uplink Timing Advance Control (43)7 测量信息元素 (43)7.1 Additional measurements list (43)7.2 Cell info (43)7.3 Cell measured results (43)7.4 Cell measurement event results (44)7.5 Cell reporting quantities (44)7.6 Cell synchronization information (44)7.7 Event results (44)7.8 FACH measurement occasion info (45)7.9 Filter coefficient (45)7.10 HCS Cell re-selection information (45)7.11 HCS neighboring cell information (45)7.12 HCS Serving cell information (45)7.13 Inter-frequency cell info list (46)7.14 Inter-frequency event identity (46)7.15 Inter-frequency measured results list (46)7.16 Inter-frequency measurement (46)7.17 Inter-frequency measurement event results (47)7.18 Inter-frequency measurement quantity (47)7.19 Inter-frequency measurement reporting criteria (47)7.20 Inter-frequency measurement system information (47)7.21 Inter-frequency reporting quantity (47)7.22 Inter-frequency SET UPDATE (48)7.23 Inter-RAT cell info list (48)7.24 Inter-RAT event identity (48)7.25 Inter-RAT info (48)7.26 Inter-RAT measured results list (48)7.27 Inter-RAT measurement (49)7.28 Inter-RAT measurement event results (49)7.29 Inter-RAT measurement quantity (49)7.30 Inter-RAT measurement reporting criteria (49)7.31 Inter-RAT measurement system information (50)7.32 Inter-RAT reporting quantity (50)7.33 Intra-frequency cell info list (50)7.34 Intra-frequency event identity (50)7.35 Intra-frequency measured results list (50)7.36 Intra-frequency measurement (50)7.37 Intra-frequency measurement event results (51)7.38 Intra-frequency measurement quantity (51)7.39 Intra-frequency measurement reporting criteria (51)7.40 Intra-frequency measurement system information (51)7.41 Intra-frequency reporting quantity (52)7.42 Intra-frequency reporting quantity for RACH reporting (52)7.43 Maximum number of reported cells on RACH (52)7.44 Measured results (52)7.45 Measured results on RACH (52)7.46 Measurement Command (52)7.47 Measurement control system information (53)7.48 Measurement Identity (53)7.49 Measurement reporting mode (53)7.50 Measurement Type (53)7.51 Measurement validity (53)7.52 Observed time difference to GSM cell (53)7.53 Periodical reporting criteria (53)7.54 Primary CCPCH RSCP info (54)7.55 Quality measured results list (54)7.56 Quality measurement (54)7.57 Quality measurement event results (54)7.58 Quality measurement reporting criteria (54)7.59 Quality reporting quantity (54)7.60 Reference time difference to cell (54)7.61 Reporting Cell Status (55)7.62 Reporting information for state CELL_DCH (55)7.63 SFN-SFN observed time difference (55)7.64 Time to trigger (55)7.65 Timeslot ISCP info (55)7.66 Traffic volume event identity (55)7.67 Traffic volume measured results list (55)7.68 Traffic volume measurement (55)7.69 Traffic volume measurement event results (56)7.70 Traffic volume measurement object (56)7.71 Traffic volume measurement quantity (56)7.72 Traffic volume measurement reporting criteria (56)7.73 Traffic volume measurement system information (56)7.74 Traffic volume reporting quantity (56)7.75 UE internal event identity (56)7.76 UE internal measured results (57)7.77 UE internal measurement (57)7.78 UE internal measurement event results (57)7.79 UE internal measurement quantity (57)7.80 UE internal measurement reporting criteria (57)7.81 Void (58)7.82 UE Internal reporting quantity (58)7.83 UE Rx-Tx time difference type 1 (58)7.84 UE Rx-Tx time difference type 2 (58)7.85 UE Transmitted Power info (58)7.86 UE positioning Ciphering info (58)7.87 UE positioning Error (58)7.88 UE positioning GPS acquisition assistance (59)7.89 UE positioning GPS almanac (59)7.90 UE positioning GPS assistance data (59)7.91 UE positioning GPS DGPS corrections (59)7.92 UE positioning GPS ionospheric model (59)7.93 UE positioning GPS measured results (59)7.94 UE positioning GPS navigation model (60)7.95 UE positioning GPS real-time integrity (60)7.96 UE positioning GPS reference time (60)7.97 UE positioning GPS UTC model (61)7.98 UE positioning IPDL parameters (61)7.99 UE positioning measured results (61)7.100 UE positioning measurement (61)7.101 UE positioning measurement event results (61)7.102 Void (62)7.103 UE positioning OTDOA assistance data for UE-assisted (62)7.104 Void (62)7.105 UE positioning OTDOA measured results (62)7.106 UE positioning OTDOA neighbor cell info (62)7.107 UE positioning OTDOA quality (63)7.108 UE positioning OTDOA reference cell info (63)7.109 UE positioning position estimate info (64)7.110 UE positioning reporting criteria (64)7.111 UE positioning reporting quantity (64)7.112 T ADV info (65)8 其它信息元素 (65)8.1 BCCH modification info (65)8.2 BSIC (65)8.3 CBS DRX Level 1 information (65)8.4 Cell Value tag (65)8.5 Inter-RAT change failure (65)8.6 Inter-RAT handover failure (66)8.7 Inter-RAT UE radio access capability (66)8.8 Void (66)8.9 MIB Value tag (66)8.10 PLMN Value tag (66)8.11 Predefined configuration identity and value tag (66)8.12 Protocol error information (66)8.13 References to other system information blocks (66)8.14 References to other system information blocks and scheduling blocks (67)8.15 Rplmn information (67)8.16 Scheduling information (67)8.17 SEG COUNT (67)8.18 Segment index (67)8.19 SIB data fixed (67)8.20 SIB data variable (67)8.21 SIB type (67)8.22 SIB type SIBs only (67)9 ANSI-41 Information elements (68)10 Multiplicity values and type constraint values (68)信息元素功能性定义消息是由多个信息元素组合而成,信息元素根据其功能的不同划分为:核心网域信息元素、UTRAN 移动信息元素、UE 信息元素、无线承载信息元素、传输信道信息元素、物理信道信息元素和测量信息元素。

自组装工艺)

自组装工艺)

π-π相互作用驱动
基于π-π相互作用而自组装形成的磁性Fe3O4 纳米粒子。
Fig.2 (a) TEM image of self-assembled microspheres prepared by dropping the as-prepared TTP-COOH-coated Fe3O4 solution. (b) Structure model proposed for the self-assembly process of individual nanoparticles to form microspheres through π-πinteractions.
影响因子:溶液浓度, 周围温度,相对湿度以及 旋转速度。
垂直沉积法
将基片垂直浸入单分散微球的悬浮液中,当溶剂蒸发时,毛细管力驱 动弯月面中的微球在基片表面自组装为周期排列结构,形成胶体晶体。
优点:晶体厚度可精确控制 。
近年来相继出现了有温 度梯度的垂直沉积法、基片 提拉法、流速控制法、倾斜 基片法以及双基片垂直沉积
的表面。
自组装技术的分类
目前,自组装技术主要分定向自组装 (Directed Self-assembly)和分子自组装 (Molecular Self-assembly)。
图(1)定向自组装
图(2)分子自组装
定向自组装如图1所示,是采用流体、电磁场 等介质,通过外形识别或自选性胶体(如 DNA)等来实现微元件在相应基板位置上的定向和定位,进而完成微元件的组装。
驱动力在自组装中的应用举例
氢键驱动
最典型的代表是在金或银纳米粒子的表面用硫醇进行单分子层的修饰, 通过硫醇分子间氢键来诱导自组装。 以四齿硫醚小分子化合物修饰的金纳米粒子自组装为球状聚集体的模型图 。

self-assembly

self-assembly
Self-Assembly
• Definition
• Common Features • Types of Self-Assembly
• Drive mode
• Influence factors • Present and Future Applications
Self-Assembly at All Scales George M. Whitesides and Bartosz Grzybowski Science 295, 2418 (2002)
F ig. 2 The schem atic drawing of molecular self-assem bly
Static self-assembly (S) involves systems that are at global or local equilibrium and do not dissipate energy. For example, molecular crystals are formed by static self-assembly; so are most folded, globular proteins. In static self-assembly, formation of the ordered structure may require energy (for example in the form of stirring), but once it is formed, it is stable. Most research in self-assembly has focused on this static type
Definition
Self-assembly is the autonomous organization of components into patterns or structures without human intervention. Self-assembling processes are common throughout nature and technology. They involve components from the molecular (crystals) to the planetary (weather systems) scale and many different kinds of interactions. The concept of selfassembly is used increasingly in many disciplines, with a different favor and emphasis in each.

纳米材料自组装技术

纳米材料自组装技术

纳米粒子的自组装
纳米粒子所具有的优异性质可以通过简单的操纵或调节其尺 度和几何外观来得到调节。因此, 功能性纳米粒子的可控分 级有序自组装是目前乃至将来很长一段时间里纳米科技发展 的重要方向。
将纳米粒子自组装为一维、二维或三维有序结构后可以获得 新颖的整体协同特性, 并且可以通过控制纳米粒子间的相互 作用来调节它们的性质 。
自组装的特点
• 自组装材料的多样性——通过自组装可以形成单 分子层、膜、囊泡、胶束、微管、小棒及更复杂 的有机/金属、有机/无机、生物/非生物的复合物 等
• 可以广泛应用在光电子、生物制药、化工等领域
自组装过程中分子在界面的识别至 关重要
自组装能否实现取决于基本结构单元的特性,如表面形貌 、形状、表面功能团和表面电势等,组装完成后最终的结 构具有最低的自由能。
模板诱导一维纳米材料的自组装
• 模板诱导自组装是得到理想结构一种十分 有效的方法。例如,单壁碳纳米管在氧化 硅凝胶表面进行的自组装。
(a) Self-Assembling Processes, (b) SEM image taken after the first cycle adsorption of SWNTs using amine-functionalized silica spheres
自组装法
• 自组装过程一旦开始,将自动进行到某个预期终点, 分子等结构单元将自动排列成有序的图形,即使是形 成复杂的功能体系也不需要外力的作用。
• 自组装过程并不是大量原子、离子、分子之间弱作用 力的简单叠加,而是若干个体之间同时自发的发生关 联并集合在一起形成一个紧密而又有序的整体,是4 纳米粒子自组装
Fig. (a) Schematic illustration of processes of preparing colloidosomes based on self-assembly of Fe3O4 NPs (golden dots) at interfaces of toluene and water, (b) confocal microscopy image of colloidosomes, water-in-toluene droplets stabilized with 8 nm Fe3O4 NPs

嵌段共聚物薄膜自组装热退火技术进展

嵌段共聚物薄膜自组装热退火技术进展

嵌段共聚物薄膜自组装热退火技术进展刘冬梅;李海英;雷良才【摘要】大分子自组装能使嵌段共聚物薄膜中微相结构进行自发地有序排列,形成高度图案化的微观形貌,继而赋予薄膜特殊的物理与化学功能.热退火诱导技术是制备嵌段共聚物自组装薄膜的一种主要手段,具有操作简单和实验条件易于控制的优点.综述了多种新型热退火诱导技术以及制备高取向、低缺陷密度自组装薄膜的方法,并对多种新型技术的特点进行了总结.【期刊名称】《应用化工》【年(卷),期】2016(045)004【总页数】4页(P751-754)【关键词】嵌段共聚物;自组装;薄膜;热退火;相分离【作者】刘冬梅;李海英;雷良才【作者单位】辽宁石油化工大学化学化工与环境学部,辽宁抚顺113001;辽宁石油化工大学化学化工与环境学部,辽宁抚顺113001;辽宁石油化工大学化学化工与环境学部,辽宁抚顺113001【正文语种】中文【中图分类】O631.1+3;O631.1+2嵌段共聚物薄膜自组装(Thin Film Self-Assembly of Block Copolymer)是嵌段共聚物(BCP)自组装研究的一个重要分支,其实质是调控多种实验条件,诱导BCP薄膜(膜厚一般<200 nm)内高分子链发生可控微相分离,形成结构明确的、高度有序的超分子结构[1,3-5]。

薄膜自组装微相结构包括棒状、层状、球状和双螺旋及其它复杂几何结构,其特征尺寸一般介于几纳米至数百纳米之间[2]。

BCP自组装薄膜的有序微相结构赋予了高分子薄膜材料特殊的物理与化学性能,因此有望在有机光电材料、分离膜材料、介孔材料和新型传感器等领域得到广泛的应用[3]。

热退火技术是一种重要的BCP 薄膜自组装诱导技术,即将BCP薄膜置于其玻璃态转变温度(Tg)甚至黏流温度以上,在无溶剂状态下,使高分子链的排布最大程度接近热力学平衡[6],形成长程有序的微观相分离形貌。

目前,关于热退火技术已有大量的文献报道[7-9],然而经典热退火技术制备的薄膜往往含有大量的结构缺陷,尚不能直接获得大面积微相结构长程有序的薄膜[10]。

CPCI PSB System Subrack 10 U 用户手册说明书

CPCI PSB System Subrack 10 U 用户手册说明书

CPCI PSB System Subrack 10 UUser ManualProduct Number:24579-028Revision: R1.1, October 30, 2009 Doc-No: 63972-163Rev.Date updated ChangeR1.0November 21, 2007Initial releaseR1.1October 30, 2009Second CMM slot removedImpressum:Schroff GmbHD-75334 Straubenhardt, GermanyThe details in this manual have been carefully compiled and checked - supported by certified Quality Management System to EN ISO 9001/2000The company cannot accept any liability for errors or misprints. The company reserves the right to amendments of technical specifications due to further development and improvement of products.Copyright © 2007All rights and technical modifications reserved.Table of Contents1Safety (1)1.1Intended Application (1)1.2Safety Instructions (2)1.3Safety Symbols used in this document (2)1.4General Safety Precautions (2)1.5References and Architecture Specifications (3)2Product Definition (4)2.1Mechanical Overview (5)2.2Subrack (5)2.3CPCI PSB Backplane (6)2.4Power Supply (7)2.4.1Grounding (8)2.4.2Power Supply (9)2.5Thermals (11)2.6Fan Control Module (FCM) (12)2.7Chassis Monitoring Module (CMM) -optional- (13)3Installation (14)3.1Unpacking (14)3.1.1Ensuring Proper Airflow (14)3.2Rack-Mounting (15)3.3Initial Operation (16)4Service (17)4.1Technical support and Return for Service Assistance (17)4.2Declaration of Conformity (17)4.3Scope of delivery (18)4.4Accessories (18)4.5Spare Parts (18)5Technical Data (19)1 Safety1.1 Intended ApplicationThe CompactPCI (CPCI) system subrack, described in this manual, is intendedas a platform for a microcomputer system based on the CompactPCI StandardPICMG 2.0 Rev.3 and PICMG 2.16.The CPCI system subracks are designed for protection class IP 20 and can beused only in the resp. environments.For higher protection requirements, a.e. IP 54/55 you must install the systemsubrack in a protective case.CPCI system subracks are not end-products, so there is no valid approval forthis unit. In order to enable stand-alone functionality, additional elements arerequired. An operational system is achieved only by way of appropriate CPCIboards.The completion and final testing of the units have been carried out, or at leastsupervised, by qualified technicians. These instructions are directed exclusivelyto these qualified technicians i.e.engineers, trained and qualified electriciansetc.Make sure that:•the assembled unit complies with the safety regulations currently applicable in the country it is going to be used.•the overall unit complies with all other regulations and specifications at the place and country of use, e.g. interference limits, approval by the telecom-munications authorities.1.2 Safety InstructionsThe intended audience of this User’s Manual is system integrators andhardware/software engineers.1.3 Safety Symbols used in this document1.4 General Safety Precautions•Service personnel must know the necessary electrical safety, wiring and connection practices for installing this equipment in a telecommunicationenvironment.•Install this equipment only in compliance with local and national electrical codes.1.5 References and Architecture Specifications•User Manual CPCI Backplane 23006-610Order no.: 73972-089•User Manual CPCI BackplanesOrder no.: 73972-101•User Manual Fan Control Module (FCM)Order no.: 73972-083•User Manual Power SupplyOrder no.: 73972-077•User Manual Chassis Monitoring Module (CMM)Order no.: 73972-084For more information see the catalogue …Electronic Packaging“ and at2 Product DefinitionThe Schroff CPCI system subrack consists of:• A shielded 19“ subrack with front assembly area for6 U front boards according to CompactPCI Standard PICMG 2.0 Rev.3 andPICMG 2.16• A 6 U CPCI PSP Backplane (PICMG 2.16)2/14 slot (2 Fabric (Switch) and 14 Node Slots)•Two 19“ plug-in power supply with wide range input•Speed controlled fans for cooling the boards•Fan Control Module (FCM) for fan monitoring/controlling•Display module•Mains/line switch•Rear assembly area for 6 U, 4 HP Rear I/O Modules2.1 Mechanical OverviewFigure 1: Mechanical Overview100068131DC Switch6Power Supply #22Power Supply #17Chassis Monitoring Module (CMM)(optional)3Front card cage with guide rails8Power Supply #4 (optional)4Power Supply #3 (optional)9Front panel 3 U / 1 HP5Drawer with Fans10Bottom-hinged front panel,perforated2.2 SubrackThe 10 U 19“ system based on the Schroff europacPro System with EMCshielding. The front card cage provides space for the installation of 14 CPCI(Node) boards and 2 Switch boards.The lower guide rails are fitted with ESD clips.2.3 CPCI PSB Backplane12307811The 6 U Backplane provides:• 2 Fabric Slots placed left to the Node Slots including optional Link between both•14 Node Slots• 1 slot for a Chassis Monitoring Module (CMM)• 4 PSU Slots acc. to PICMG 2.11 for 4 x 3 U PSUs•CompactPCI bus (PICMG2.0 R.3.0) is implemented at Node Slots;two independent segments with System Slot left and rightApplicable Specifications:PICMG 2.16 R1.0 Packed Switched BackplanePICMG 2.0 R3.0 CPCI Core SpecificationPICMG 2.01 R2.0 Hot SwapPICMG 2.09 R1.0 System Management BusPICMG 2.10 R1.0 KeyingPICMG 2.11 R1.0 Power Interface SpecificationFor more information see the Backplane’s User Manual, Order No.: 73972-089/-101, in the catalogue and at 2.4 Power SupplyThe subrack system has 19“ AC power supplies with wide range input.The power supplies are plugged-in in two dedicated slots at the left and rightside of the backplane. The power supplies contact via a P47 connectors to thebackplane.The power input is provided by a AC mains/line module with IEC 320-C14connector, integrated mains/line fuses and line filter.With a DC switch at the front side you can switch the power supply to standbymode, i.e. the supply voltages to the backplane are shut off.Maximum fuse value is 10 A.2.4.1 GroundingThe subrack provides two M5 studs to connect a double-lug ground terminal cable. These M5 studs are only for equipotential bonding. Grounding is achieved through the protective earth conductor of the power cable!Figure 3: AC Terminal - Grounding100068121Ground terminal3Fuses2AC Connector (IEC320-C14)2.4.2 Power SupplyFigure 4: Power SupplyTable 1: Data AC Power Supply10006814Input voltage nominal100 - 240 VAC Mains Frequency50 / 60 Hz Output (max.)250 W Output voltages 3.35.012.0-12.0V V V V ----40405.52A A A A Ripple < 1 %Dynamic response < 1 % or 60 mVRecovery time to within 1%< 300 µsecOvervoltage protection for all voltages120 – 130 % U > 5 VOvercurrent protection 105 – 130 % of rated output currentHold-up time>= 20 msFigure 5: Block Diagram123078132.5 ThermalsThe front boards are cooled by forced air convection through 3 speed controlled24 VDC axial fans (290 m³/h (170 cfm) each.The fans are assembled on a drawer behind the perforated front panel at thebottom of the system.The air enters the subrack at the lower front into the bottom air plenum turns 90°upward and passes an air filter. As the air passes across the hot components onthe Front Boards, heat is carried away by forced convection. The air exits theSubrack at the top, is drawn into the upper plenum, turns 90°, and is exhaustedout the rear of the subrack.The fan speed is controlled by the Fan Control Module (FCM) depending on theexhaust temperature. 3 NTC temperature sensors are located above the cardcage.Figure 6: Airflow123078142.6 Fan Control Module (FCM)The Fan Control Module (FCM):•Monitors and controls up to four fans•Monitors the signals from up to four temperature sensors•Speed up the fans in case of a failure of one fan•Is able to communicate with the optional Chassis Monitoring Module (CMM)Up to four NTC temperature sensors can be connected to the FCM. The highesttemperature level is the reference for the fan speed. If one ore more sensorsexceed 60° C the output for the temperature fail LED and a digital output areactivated. Since the fan speed is temperature controlled by the FCM, the fansrotate with the lowest speed possible. Lower speeds reduce acoustic noise andincrease the longevity of the fans.Figure 7: Diagram fan speed/temperature10006807 For more information see the FCM’s User Manual, Order No.: 73972-083 and at2.7 Chassis Monitoring Module (CMM) -optional-The Chassis Monitoring Module (CMM)•monitors the three VME voltages•can monitor two additional voltages with a range of ±24 V DC•can monitor up to seven NTC temperature sensors•can communicate with the Fan Control Module (FCM)•provides 16 digital inputs•provides 10 digital outputsThe CMM is an optional assembly and not included with the subrack by default.The CMM is a pluggable unit in the 3 U euroboard format with a3 U/1 HP front panel and can be assembled at the front side.The CMM allows communication and remote monitoring via RS-232 or Ethernetinterface. The front panel provides a RJ45 connector (Ethernet) an a D-Sub9connector (RS-232).A user interface via HTML page is available.The CMM can monitor the 4 CPCI voltages and two additional voltages (up to±24 V DC). The error status can be displayed by LEDs, through the RS-232 serialinterface or via ethernet as a HTML page.Up to 7 NTC temperature sensors can be connected to the CMM.Two alarmthresholds between 20° C and 70° C can be set.The CMM provides 16 digital inputs and 10 digital outputs for custom specificapplications. Four digital outputs are open collector outputs, isolated by opto-couplers, six digital outputs are TTL-compatible non-isolated.The CMM is connected to the FCM. The temperature values and the fan speedsare transferred to the CMM.For more information see the CMM’s User Manual, Order No.: 73972-084 andat 3 Installation3.1 UnpackingConsider the following when unpacking and storing the system:•Leave the system packed until it is needed for immediate installation.•After unpacking the system, save and store the packaging material in case the system must be returned.If the packaging is damaged and possible system damage is present, report tothe shipper and analyze the damage.3.1.1 Ensuring Proper Airflow•Install the system in an open rack whenever possible. If installation in an enclosed rack is unavoidable, ensure that the rack has adequate ventilation.•Maintain ambient airflow to ensure normal operation. If the airflow is blocked or restricted, or if the intake air is too warm, an over temperature conditioncan occur.•Ensure that cables from other equipment do not obstruct the airflow through the systems.•Use filler panels to cover all empty chassis slots. The filler panel prevents fan air from escaping out of the front of an open slot.3.2 Rack-MountingThis subrack system can be installed in 19“ equipment racks. The rack must beaccessible from the front and rear for equipment installation.Mounting brackets and a rack mount kit come with the system. Allow sufficientclearance around the rack for system maintenance.Mounting Instructions:•Ensure that the rack is constructed to support the weight and dimensions of the Shelf.•Install any stabilizers that came with your equipment rack before mounting or servicing the system in the rack.•Load the rack from the bottom to the top, with the heaviest system at the bottom, avoid uneven mechanical loading of the rack.•We recommend to use also chassis support brackets.3.3 Initial OperationBefore starting the system with CPCI boards the following tests have to be done:•Ensure that the unit does not get damaged during transport.•Check the Protective Earth (PE) resistance, should be < 0,1 Ohm.•Switch on the system and check all CPCI voltages on the Backplaneconnectors before you plug in the CPCI boards.•Plug in the CPCI boards.•Cover all open Slots with filler panels.•Tighten the rear panel mounting screws.•Power-on the system and determine the actual current consumption.•Replace the mains fuses suitable to the actual current.The fuse value has been determined in factory for the maximum powerdelivered by the power supply. The fuse value must be adjusted to the actualcurrent consumption of the completed system.Maximum value is 10 A slow blow.4 Service4.1 Technical support and Return for Service AssistanceFor all product returns and support issues, please contact your Schroff salesdistributor or .We recommend that you save the packing material. Shipping without the originalpacking material might void the warranty.4.2 Declaration of ConformitySCHROFF CompactPCI systems are developed and manufactured accordingto EN 60950-1.SCHROFF CompactPCI systems are not end-products with independentfunctionality as described in the definition of the EMC regulations, and thereforea CE marking is not required. However, when CPCI cards are assembledaccording to specification, the systems fulfill the requirements in accordancewith EMC Directive 2004/108/EG and Low-voltage Directive 2006/95/EG.Interference resistance and interference emissions are factors which are heavilyinfluenced by the type and quantity of CPCI cards used in the system assembly.Through the use of high quality line filters and EMC optimized enclosure design,SCHROFF offers CPCI systems which serve as an ideal base for systemintegrators, which comply with the prescribed limits of EN 6100-6-3 and EN61000-6-2The systems are generally equipped with power supplies which possess CEmarkings in accordance with EN 60950-1, EN 61000-6-3, EN 61000-6-2).Before delivery a high-voltage, protective earth and functionality test is carriedout on each individual system.4.3 Scope of deliveryQuantity Description119" subrack, shielded. (front handles: RAL 7016; 19"-brackets, top and base covers: Al (1CPCI PSB Backplane 6U14 Node Slots, 2 Fabric Slots. Fabric Slots placed left to the Node Slots including optional Linkbetween both4 PSU Slots acc. to PICMG 2.11 for 4 x 3 U PSUsCompactPCI bus (PICMG2.0 R.3.0) is implemented at Node Slots;two independent segments with System Slot left and right1Front assembly area for max. 16 Boards 6 U 160mm deepguide rails incl. ESD-Clips (ESD-Clips assembled at front bottom)1Rear assembly area for the installation of max. 16 Rear I/0 Boards 6 U, 4 HP.1AC mains/line module with IEC 320-C14 connector, mains fuses and line filter219“ plug-in power supplies each 250 W(with 4 voltages: 3.3 V / 40 A; 5 V / 40 A; 12 V / 5.5 A, -12 V / 2 A)1Complete AC/DC wiring3Speed controlled fans, assembled on front accessible drawer1FCM-Module for fan monitoring and controlling4.4 AccessoriesParts-No.Description23207-022Chassis Monitoring Module (CMM)20848-7xx Filler panel with EMC front plate for empty Slots, dimensions see catalogue34562-8xx Filler panel for empty Slots, dimensions see catalogue24579-03x Printed Circuit Board covers, dimensions see catalogue4.5 Spare PartsOn request.5 Technical DataTable 2: Technical DataDimensionsHeight 443.70 mm (10 U)Width 482.60 mm (19“)Depth 276.75 mmDepth with handles 333.20 mmWeight18 KgPower supplyInput voltage 100 VAC to 240 VACMains frequency 50 / 60 HzPower consumption up to 500/1000 WCooling3 x 24 VDC Fans Each 290 m³/h (170 cfm)Ambient TemperatureOperating 0 °C to +40 °CStorage -40 °C to +85 °CHumiditypermissible Humidity 30 % to 80 %, non condensingEMC, the system meets therequirements for:Emitted Interference EN 55022Interference Resistance EN 55024SafetyTest voltage according to EN 60950 Input - Output:Input- PE:Output - PE:Output - Output: 4,3 kVDC 2,2 kVDC 0,7 kVDC 0,7 kVDCShock and Vibration:EN 60068-2-6 and EN 60068-2-27 Electromagnetic ShieldingShielding attenuation typ. 40 dB at 1 GHz if shielded frontpanels are used.SCHROFF GMBH Langenalberstr. 96-100Tel.: + 49 (0) 7082 794-0Fax: +49 (0) 7082 794-200 D-75334 Straubenhardt。

ABAQUS常见问题汇总

ABAQUS常见问题汇总
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ABAQUS 常见问题汇总 - 2.0 版
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0. ABAQUS 入门资料.......................................................................................................................... 4
6.1 ABAQUS 安装方法 ................................................................................................................. 12 6.2 ABAQUS 显示异常(无法显示栅格、显卡冲突、更改界面颜色).......................................... 21 6.3 Document 无法搜索................................................................................................................. 21 6.4 磁盘空间不足 ........................................................................................................................... 22 6.5 Linux 系统................................................................................................................................ 22 6.6 死机后恢复模型 ....................................................................................................................... 23

C8051F060_07中文资料

C8051F060_07中文资料

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Directed Self-Assembly at the10nm Scale by Using Capillary Force-Induced Nanocohesion Huigao Duan,†,‡and Karl K.Berggren†,*†Department of Electrical Engineering and Computer Science,Massachusetts Institute of Technology, Cambridge,Massachusetts02139and‡School of Physical Science and Technology,Lanzhou University, Lanzhou,Gansu730000,People’s Republic of ChinaABSTRACT We demonstrated a new nanoassembly strategy based on capillary force-induced cohesion of high-aspect ratio nanostructures made by electron-beam ing this strategy,ordered complex pattern were fabricated from individual nanostructures at the10nm length scale.This method enables the formation of complex designed networks from a sparse array of nanostructures,suggesting a number of potential applications in fabrication of nanodevices,nanopatterning,andfluid-flow investigations.KEYWORDS Capillary force,self-assembly,nanocohesion,electron-beam lithography,10-nm-scaleC apillary force plays a dominant role in a large rangeof natural phenomena1-8and has been widely usedas a driving force for the self-assembly of nanoscale to mesoscale objects.9-18However,these self-assembly processes based on capillary forces were limited to the microscale and mesoscale and have never been used in patterning sub-100nm length-scale structures.Furthermore, local control of self-assembly on this length scale had not been achieved.In this report,we demonstrate a directed-assembly process based on controllable capillary force-induced nanocohesion that can precisely assemble indi-vidual high-aspect ratio structures at10nm length scales into complex hierarchical structures.The basic idea of this nanoassembly process is shown in Figure1a,where straight high-aspect ratio nanopillars are first defined as latent features in resist and then developed in a liquid developing agent.In the subsequent drying process,capillary force exists between the nanopillars on the nanopillar liquid-air interface.2,19When the capillary force is larger than a critical force,19,20the nanopillars will collapse, potentially resulting in nanocohesion.If the adhesion force between the cohered pillars(or between the pillars and the substrate)is larger than the elastic force acting to restore the pillars to their original shape,the cohesion would be sus-tained after drying.By adjusting the spatial distribution of nanopillars,this cohesion can be used to form complex two-dimensional structures at the10nm length scale.An example of this process is shown in Figure1b,c where we fabricated two arrays of uniformly distributed high-aspect ratio negative poly(methyl methacrylate)(PMMA)nanopil-lars21using the same parameters but dried one of them by using a supercritical-point carbon dioxide dryer(for Figure 1b)and the other by using a spin dryer(for Figure1c).The diameter of the pillars was∼15nm,the height was∼80nm, and the pitch was50nm.In Figure1b,all of the high-aspect ratio nanopillars remained standing because the supercriti-cal-point drying process eliminated the surface tension and resultant capillary force;while in Figure1c,all of the pillars collapsed and cohered into various assemblies because of the capillary force induced in the liquid-evaporation process.Similar capillary force-induced collapse effects have been widely reported as unwanted random behaviors in many high-aspect ratio structures such as carbon nanotubes,22 ZnO nanowires,23silicon nanorods,24polymer micropil-lars,25and general resist structures.8,26In these cases,the random collapse is thought to result from the combination of many factors27such as capillarity,self-weight,28aniso-tropic geometry,29and even a domino effect.18,30To direct the collapse,we must use one of these factors as the main driving force.Recently,domino effect-based,30gel-as-sisted,31and asymmetric geometry-based29self-organiza-tions of nanopillars or microneedles have been reported. However,these self-organization processes still cannot be well controlled or designed to achieve arbitrary two-or three-dimensional nanostructures.In this work,we used intentionally asymmetric capillary forces to reproducibly direct the self-assembly of nanopillars to form ordered,designable paring to previous work,our study focused on how to deterministically control the capillary force-induced self-assembly of high-aspect ratio structures at10-nm-length scales.By locally varying the initial relative positions in the top-down nano-fabrication process and by tuning the critical minimum cohesion force of structures by using electron-exposure dose,complex,predesigned and defect-free hierarchical patterns were deterministically self-assembled from sparse individual posts.*To whom correspondence should be addressed.E-mail:berggren@. Received for review:06/28/2010Published on Web:08/12/2010The capillary force between two pillars i and j is given bywhere S ij is the effective surface area contributing to capillary force,γis the surface tension of liquid,R is the contact angle between liquid and the pillars,and p ij is the distance between pillars i and j prior to collapse.32The net force on an individual pillar i in a pillar array is the sum of capillary forces from all other pillars.To simplify the description,we consider the situation shown in Figure 1d (I)of a one-dimensional uniform sym-metric series of 2N pillars (for odd numbers of pillars,the capillary force for the middle pillar is zero due to symmetry).In this case,the total capillary force for the pillar i is given bywhere p is the pitch of this pillar array (because the pillars are generally much smaller in diameter than the spacing between them,we assumed that the diameter of the pillar can be neglected when determining the distance of pillars for the calculation of capillary force),S ij can be considered as the effective surface area contributing to capillaryforceFIGURE 1.Schematics of controllable capillary force-induced nanocohesion process.(a)Schematic of nanoassembly by capillary force-induced cohesion of high-aspect ratio nanostructures in the drying process.(b)Scanning-electron microscopy (SEM)image of 50nm pitch nanopillars with diameter ∼15nm fabricated by electron beam lithography using PMMA as a negative resist.The thickness of PMMA was ∼90nm,the lithographic electron dose for each individual pillar was 300fC,and the resultant height of nanopillars was ∼80nm.The sample was developed by 1:2methyl isobutyl ketone -IPA for 1min at 20°C,rinsed by pure IPA,and then dried in a supercritical point dryer.(c)SEM image of negative PMMA nanopillars dried in a spin dryer in air at room temperature in which pattern collapse was induced by capillary forces in the liquid-evaporation process.The nanopillars were fabricated by using the same parameters as those in (b).(d)Schematic of (I)a one-dimensional uniform 2N -nanopillar array,(II)3-pillar array,and (III)a two-dimensional nanopillar array with designed capillary force to direct the pattern collapse.In (III),p 1is the pitch of nanopillars in the same cell and p 2is defined as the intercell spacing of two adjacent cells.When p 2*p 1,asymmetric capillary forces will be introduced.(e -h)SEM images of cohered nanopillars with p 2)p 1(e),p 2-p 1)2nm (f),p 2-p 1)4nm (g),p 2-p 1)8nm (h),demonstrating that the yield of deterministic cohesion increased when increasing intercell spacing p 2.The diameter of nanopillars was ∼20nm,the pitch of pillars in the cell p 1was 50nm,and the lithographic electron dose for each individual pillar was 400fC.(i)Quantitative yield as a function of the value of intercell spacing variation (p 2-p 1),which shows high yield of deterministic cohesion when (p 2-p 1)was large enough.All SEM images show the full extent of the patterned region,and their scale bars are 200nm.f ij )2πS ij γcos α/p ij(1)f i )2πγcos α∑j )1,*i2NS ij1(j -i )p(1e i e N,1e j e 2N )(2)between pillars i and j,which decreases when increasing thedistance between pillars i and j.Because of the symmetry of the system,many termscancel out and we can simplify eq2to get the asymmetriccapillary force for each pillarFrom this equation,we know that,for afixed pillar-number2N,boundary pillars(i)1)have the largest asym-metric capillary force,and the asymmetric capillary forceapplied on the pillar i decreases when it is closer to themiddle(i.e.,increasing i to N),while the central pillars havethe smallest asymmetric capillary force(i)N).There existsa critical minimum lateral force f min to collapse a pillar.19,20When f i>f min,the pillar i will collapse in the direction of the capillary force;when f i<f min,the pillar i will remain vertical. Thus the pillars closer to the boundary prefer to collapsetoward the center,while the pillars closer to the middleprefer to stand.In an ideal infinitely uniform pillar array,nopillar will collapse because the capillary forces for any pillarequilibrate to zero.In reality,there exist other random factssuch as pillar displacement,intrinsic imperfections of pillars,and the dynamics of dewetting,which could introducerandom deformation or collapse of some pillars.In particu-lar,these initial random deformations or collapses couldbreak the symmetry of the surroundings and induce dy-namic effects.The scenario shown in Figure1c can thus be understoodto be determined by the combined effects described above,in which boundary pillars had enough asymmetric capillaryforce toward the center of the array,so they collapsed tothe center,but inner pillars collapsed randomly because thedirected capillary forces were insufficient and thus theircollapse was determined by random effects.To direct collapse of all pillars,the asymmetric capillaryforce f i of all the pillars must be larger than f min.There aretwo possible ways to achieve this result:(1)by increasingasymmetric capillary force for all pillars;and(2)by decreas-ing the minimum critical collapse force f min.We will discusseach of these possible approaches.To demonstrate control and strengthening of the asym-metric capillary force,we introduced asymmetric design ina pillar array to achieve designed force on all pillars.Theschematic of our simplest method is shown in Figure1d(II),where the capillary force of the center pillar isWhen the pitch difference of p2-p1is much smaller than p1p2,f j∝(p2-p1),implying that the asymmetric capillary force increases with increasing the pitch difference.When the designed asymmetric capillary force f j is large enough to overcome all other random effects,the collapse is directed.This concept can be extended to a two-dimensional array of pillars.We designed a periodic two-dimensional4-pillar-unitcell array of nanopillars,as shown in Figure1d(III).We fixed the intracell pitch p1and varied the intercell spacing p2.When p2was greater than p1,the asymmetric capillary force of each pillar pointed to the center of its cell.We patterned an array of nanopillars in PMMA using a negative-tone electron-beam lithography(EBL)process.After devel-opment in developer and rinsing in isopropyl alcohol(IPA), the negative PMMA nanopillars were spin-dried.The intracell pitch p1was50nm,the pillars were∼80nm tall,and the diameter was∼20nm.The intercell spacing p2varied from 50to90nm.In the case of p2)p1shown in Figure1e,the pillars collapsed randomly and formed different assemblies con-sisting of between2and9elements.As p2increased,the yield of the intended intracell4-pillar collapse increased correspondingly(Figure1f,g),indicating that the collapse of the pillars were more directed and controllable.Once p2was large enough,the yield reached100%,as shown in Figure 1h,where(p2-p1)was8nm,that is,a16%increase relative to the intracell pitch p1.The yield as a function of(p2-p1)is shown in Figure1i from which we can see a clear systematic trend.To further demonstrate the reliability of this strategy,we designed a series of multielement cells with different cell geometries.Figure2a,f shows that assemblies with2,3,4, 6,7,and9elements in each cell nanocohered as designed, where the intercell spacing p2was∼2times that of the intracell pitch p1,and all other parameters were the same as those in Figure1e,h.In these assemblies,we can see that all boundary pillars in any single cell cohered to the center of the cell rigidly,while the middle pillars(in7-and9-ele-ment cell,shown in Figure2e,f,respectively)remained vertical because of symmetry within the cell.No imperfec-tions were found across∼16µm2patterns(400cells,our largest test area for this sample).Figure2g shows a new type of example in which9-pillar-cell arrays with4different rotations were self-assembled, from which we can see robustly ordered assemblies were achieved by capillary force-induced nanocohesion.This nanocohesion-based self-assembly could also be achieved across a range of length scales with different materials and geometries(Supporting Information Figure S1-S3).Though we could get robust ordered assemblies for small-element number cells because the asymmetric capillary force was large enough to direct cohesion for all pillars,the assembly of larger-element number(>25)uniform cells was more difficult(Figure1c and Supporting Information Figure S4)because the lower asymmetric capillary force for innerf i)2πγcosα∑j)2i2N S ij1(j-i)p(1e i e N,1e j e2N)(3)f j)f ij-f jk)2πSγcosα/p1-2πSγcosα/p2∼(1/p1-1/p2))(p2-p1)/p1p2(4)pillars permitted random collapse.For this case,we describe here that directed self-assembly could still be realized by controlling the critical minimum cohesion force f min through varying the dot exposure dose during the lithography pro-cess (and thus varying the pillar diameter and perhaps also slightly varying its intrinsic strength).For a pillar in an array with a given pitch,the critical minimum cohesion force 33is given bywhere E is Young’s modulus,d is the diameter of the pillar,h is the height of the pillar,and A is the aspect ratio of the pillar defined by A )h /d .This formula implies that to decrease f min ,we can increase the elasticity (i.e.,decrease E ),decrease the diameter d ,or increase the height h .When elasticity variation is negligible,increasing aspect ratio A is the most effective way to decrease f min .To engineer f min ,we fabricated a uniform 171-element array of hexagonal high-aspect ratio negative PMMA nano-pillars.The height of the pillars h was ∼550nm,and the pitch p was 200nm.The diameter d of pillars was controlled by changing the exposure dose of each pillar,which allowed us to achieve varying aspect ratios.Figure 3a -d shows the evolution of nanocohesion of this 171-element nanopillar array as the aspect ratio was increased by decreasing lithographic electron exposure.From these figures,we can see that with decreasing pillar diameter,pillars tended to cohere toward the pattern center.We can use the theoretical picture described above to give a qualitative explanation of the dynamic process of each scenario.To illustrate the process,we consider a uniformly spaced one-dimensional 8-nanopillar array,shown sche-matically in Figure 3a ′-d ′,in which the initial asymmetric capillary forces for each nanopillar are f 1,f 2,f 3,and f 4,andf 1>f 2>f 3>f 4according to our model.Suppose the critical minimum lateral cohesion forces for each of the pillars in Figure 3a -d were f a to f d .With decreasing the diameter,from formula 5,we know f a >f b >f c >f d .In the first case (Figure 3a),we believe the initial condition was f 1>f a >f 2>f 3>f 4,so pillar 1collapsed first.During the collapse of pillar 1,the distance between pillar 1and pillar 2decreased and the capillary force between them increased dramatically (f ∼1/p 12),which made f 2reverse in directions and increase in magnitude so that it induced pillar 2to collapse toward pillar 1(we describe this dynamic interaction as a “domino effect”);after pillar 2collapsed,the asymmetric capillary forces for pillar 3and pillar 4increased but were still smaller than the critical force f a required to induce the collapse (Figure 3a ′).In the second case (Figure 3b),the initial condition was also f 1>f b >f 2>f 3>f 4,so that pillar 1collapsed and induced pillar 2collapse toward pillar 1as in the first case.However,in contrast to the first case,during the collapse process of pillar 2,the asymmetric capillary force for pillar 3was now sufficient to collapse pillar 3toward pillar 4,and another domino effect took place for the remaining pillars (Figure 3b ′).In the third case (Figure 3c),we understand f 1>f 2>f 3>f c >f 4,so pillar 1,2,and 3initially collapsed to the center and induced pillar 4to collapse to pillar 3(Figure 3c ′).In the last case (Figure 3d),the initial asymmetric capillary force of all pillars was such that f 1>f 2>f 3>f 4>f d ,so that all of them collapsed to the center (Figure 3d ′).The above-mentioned dynamic processes were also found in nonuniform pillar arrays,shown in Supporting Information Figure S5.More symmetric assemblies could be obtained from smaller arrays,as shown in Figure 3e and Supporting Information Figure S6,where hexagonal nanopillar arrarys were assembled into symmetric nanohills.This symmetry was possible because the asymmetric capillary force for the pillar nearest to the middle should be f N ∼1/NpaccordingFIGURE 2.SEM images of ordered multielement assemblies fabricated by capillary force-induced nanocohesion.(a)A 2-element-cell with two different rotations;(b)3-element-cell with three different rotations;(c)4-element-cell with two different rotations;(d)6-element-cell with three different rotations;(e)7-element-cell with three different rotations;(f)9-element-cell with two different rotations;and (g)large area 9-element-cell with four different rotations.The diameter of nanopillars was ∼20nm,the pitch of pillars in the cell was 50nm,and the intercell spacing between adjacent cells was ∼100nm.The thickness of PMMA was ∼90nm and the resultant negative PMMA nanopillars were ∼80nm tall.All scale bars are 200nm.f min ∼Ed 4/h 3)Ed /A 3)Eh /A 4(5)to eq 3,so for fewer-element pillar arrays,pillars closer to the middle should be more easily directed compared to larger arrays.We also noticed that although increasing the aspect ratio could increase the fidelity of self-assembly,the collapse of nanopillars would be partly determined by random effects when the aspect ratio was too high,resulting in random collapse of some pillars (see Supporting Informa-tion Figure S7).In this case,we believe that the critical lateral collapse force f min was so small that it was comparable with random forces induced by imperfections and self-weight of pillars,so random forces partly affected the collapse.As described above,the action of nanocohesion was determined by the relationship of designed asymmetric capillary force and the critical collapse force f min of nanopil-lars.By deliberately setting this relationship for all the nanopillars in a pattern,we also showed that complex hierarchical nanostructures could be fabricated by nanoco-hesion as is evident in Figure 4.Figure 4a shows some hierarchical designs where the basic concept was to deliberately vary the local position (by ∼10%,relative to a uniform distribution)of some pillars in a larger cell to create controlled substructures.Thus,while boundary pillars in the cell had the largest capillary force,the pillars in the designed substructures also had sufficient capillary forces to induce directed collapse,as shown sche-matically by the arrows in Figure 4a.Figure 4b shows complex hierarchical networks fabricated on the basis of the designs in Figure 4a,from which we can see that the pillarscollapsed and self-assembled in the expected directions to form the desired patterns.Though the yield decreased when increasing the total element-number in these tests,we believe this technique could be further improved by optimiz-ing the pillar placement and geometry.The central result of this report is the demonstration of a new nanoassembly strategy based on capillary force-induced cohesion of high-aspect ratio nanostructures during the postdevelopment drying process.By using this strategy,robust ordered complex networks of nanostructures were fabricated.Though we focused here on patterning with electron beam lithography,we believe that this technique can be also applied to other high-aspect ratio nanostructures,including functional vertically aligned semiconductor nano-wires or nanorods,carbon nanotubes,or metal nanopillars to perhaps permit functional self-assembled structures.On the other hand,from a lithographer’s point of view,this self-assembly technique suggests a number of potential applica-tions in electron-beam lithography,including (1)increasing the throughput by patterning only a portion of the final structures,then increasing the pattern area by inducing controlled collapse;(2)reducing proximity effect 34by reduc-ing the total dose needed to make patterns in a given area (again by patterning only pillars,then inducing collapse to make linear structures);and (3)reducing electron exposure in radiation-sensitive devices by using induced collapse across sensitive device material to define a device feature.One limitation of this method is that accuratepatternFIGURE 3.SEM images of large-element-number assemblies fabricated by capillary force-induced nanocohesion.(a -d)SEM images of the evolution of a 171-pillar array with increasing the aspect ratio by decreasing lithographic electron exposure dose:(a)5.7,(b)4.0,(c)2.8,and (d)2.0pC/pillar,showing how asymmetric capillary force determined nanocohesion of a large array with different aspect ratios.The pitch of the pillars was 200nm.The scale bars are 500nm.(a ′-d ′)Cross-sectional schematic diagrams of different scenarios for (a -d).(e)SEM image of a symmetric nanohill collapsed from a 91-pillar array (smaller than in cases a -d)with a pitch of 160nm by nanocohesion.Scale bar is 200nm.The PMMA thickness was ∼600nm and resultant height of nanopillars was ∼550nm.transfer of collapsed structures to functional layers may be challenging because the sidewall profile of collapsed struc-tures is not vertical,and the diameter of electron beam lithography-defined high-aspect ratio structures may not be perfectly uniform along their length (due to forward scatter-ing of exposing electrons).More work should be done in the future to apply this method for fabricating functional devices.Finally,because the process can take place at sub-20nm scale,this technique could also serve as a platform for scientific investigation of fluid flow near the molecular scale to study the mechanism of evaporation,dewetting phenom-ena,and the mechanical behaviors of structures on the 10-nm length scale.Acknowledgment.This work was supported by Office of Naval Research and Nanoelectronics Research Initiative.Patterning was done at MIT’s shared scanning-electron-beam-lithography facility in the Research Laboratory of Electronics.We thank M.Mondol and J.Daley for technical assistance and Dr.Joel Yang for helpful discussion.H.G.Duan was supported by a fellowship from the China Scholar-ship Council.Supporting Information Available.Methods,additional figures,and additional references.This material is available free of charge via the Internet at .REFERENCES AND NOTES(1)de Gennes,P.G.;Brochard-Wyard,F.;Quere,D.Capillarity and Wetting Phenomena:Drops,Bubbles,Pearls,Waves ;Springer:New York,2003.(2)Bico,J.;Roman,B.;Moulin,L.;Boudaoud,A.Nature 2004,432,690.(3)Kim,H.Y.;Mahadevan,L.J.Fluid Mech.2006,548,141–150.(4)Gao,X.F.;Jiang,L.Nature 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