BA-2RV219-D68;中文规格书,Datasheet资料

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LTC2460CDD#PBF;LTC2460IMS#PBF;LTC2462IMS#PBF;LTC2462CMS#PBF;中文规格书,Datasheet资料

124602fa–50–1010–3050703090TEMPERATURE (°C)R E F E R E N C E O U T P U T V O L T A G E (V )1.25201.25151.25101.25051.250024602 TA01b1.24801.24851.24901.2495Typical applicaTionFeaTuresapplicaTionsDescripTionwith 10ppm/°C Max Precision ReferenceThe L TC ®2460/L TC2462 are ultra tiny, 16-Bit analog-to-digital converters with an integrated precision reference. They use a single 2.7V to 5.5V supply and communicate through an SPI Interface. The L TC2460 is single-ended with a 0V to V REF input range and the L TC2462 is dif-ferential with a ±V REF input range. Both ADC’s include a 1.25V integrated reference with 2ppm/°C drift per-formance and 0.1% initial accuracy. The converters are available in a 12-pin DFN 3mm × 3mm package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The L TC2460/L TC2462 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters.Following a single conversion, the L TC2460/L TC2462 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA.The L TC2460/L TC2462 can sample at 60 conversions per second, and due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. Both include continuous internal offset and fullscale calibration algorithms which are transparent to the user , ensuring accuracy over time and the operating temperature range.V REF vs Temperaturen16-Bit Resolution, No Missing Codesn Internal Reference, High Accuracy 10ppm/°C (Max)n Single-Ended (L TC2460) or Differential (L TC2462)n 2LSB Offset Error n 0.01% Gain Errorn 60 Conversions Per SecondnSingle Conversion Settling Time for Multiplexed ApplicationsnSingle-Cycle Operation with Auto Shutdown n 1.5mA Supply Current n 2µA (Max) Sleep Currentn Internal Oscillator—No External Components Required n SPI InterfacenUltra-Tiny 12-Lead 3mm × 3mm DFN and MSOP PackagesnSystem Monitoringn Environmental Monitoringn Direct Temperature Measurements n Instrumentationn Industrial Process Control n Data Acquisitionn Embedded ADC UpgradesL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and No Latency ∆∑ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6208279, 6411242, 7088280, 7164378./224602fapin conFiguraTionabsoluTe MaxiMuM raTingsSupply Voltage (V CC ) ...................................–0.3V to 6V Analog Input Voltage (IN +, IN –, IN, REF –,COMP, REFOUT) ...........................–0.3V to (V CC + 0.3V)Digital Voltage(V SDI , V SDO , V SCK , V CS ) ................–0.3V to (V CC + 0.3V)(Notes 1, 2)orDer inForMaTionStorage Temperature Range ..................–65°C to 150°C Operating Temperature RangeLTC2460C/LTC2462C ...............................0°C to 70°C LTC2460I/LTC2462I .............................–40°C to 85°CL TC2462L TC2462TOP VIEWDD PACKAGE12-LEAD (3mm × 3mm) PLASTIC DFN 1211891045321V CC GND IN –IN +REF –GNDREFOUT COMP CS SDI SCK SDO67T JMAX = 125°C, θJA = 43°C/WEXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL123456REFOUT COMP CS SDI SCK SDO121110987V CC GND IN –IN +REF –GNDTOP VIEWMS PACKAGE12-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 120°C/WL TC2460L TC2460TOP VIEWDD PACKAGE12-LEAD (3mm × 3mm) PLASTIC DFN 1211891045321V CC GND GND IN REF –GNDREFOUT COMP CS SDI SCK SDO67T JMAX = 125°C, θJA = 43°C/WEXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL123456REFOUT COMP CS SDI SCK SDO121110987V CC GND GND IN REF –GNDTOP VIEWMS PACKAGE12-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 120°C/WLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2460CDD#PBF L TC2460CDD#TRPBF LFDQ 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C L TC2460IDD#PBF L TC2460IDD#TRPBF LFDQ 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C L TC2460CMS#PBF L TC2460CMS#TRPBF 246012-Lead Plastic MSOP-120°C to 70°C L TC2460IMS#PBF L TC2460IMS#TRPBF 246012-Lead Plastic MSOP-12–40°C to 85°C L TC2462CDD#PBF L TC2462CDD#TRPBF LDXM 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C L TC2462IDD#PBF L TC2462IDD#TRPBF LDXM 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C L TC2462CMS#PBF L TC2462CMS#TRPBF 246212-Lead Plastic MSOP-120°C to 70°C L TC2462IMS#PBFL TC2462IMS#TRPBF246212-Lead Plastic MSOP-12–40°C to 85°CConsult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel//324602faelecTrical characTerisTics PARAMETERCONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes)(Note 3)l 16Bits Integral Nonlinearity (Note 4)l 110LSB Offset Error l215LSB Offset Error Drift 0.02LSB/°C Gain Error Includes Contributions of ADC and Internal Reference l ±0.01±0.25% of FS Gain Error DriftIncludes Contributions of ADC and Internal Reference C-Grade I-Gradel l±2 ±5 ±10ppm/°C ppm/°C T ransition Noise2.2µV RMSPower Supply Rejection DC80dBThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. (Note 2)analog inpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Supply Voltage l 2.75.5V I CCSupply Current Conversion Nap Sleepl l l1.5 800 0.22.5 1500 2mA µA µAThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C.SYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSV IN +Positive Input Voltage Range L TC2462l 0V REF V V IN –Negative Input Voltage Range L TC2462l 0V REF V V IN Input Voltage RangeL TC2460lV REFV V OR +, V UR +Overrange/Underrange Voltage, IN +V IN – = 0.625V (See Figure 3)8LSB V OR –, V UR –Overrange/Underrange Voltage, IN–V IN + = 0.625V (See Figure 3)8LSB C ININ +, IN –, IN Sampling Capacitance0.35pFI DC_LEAK(IN +, IN –, IN)IN +, IN – DC Leakage Current (L TC2462) IN DC Leakage Current (L TC2460)V IN = GND (Note 8)V IN = V CC (Note 8)ll –10 –10 1 11010nA nA I DC_LEAK(IN –)IN – DC Leakage Current V IN = GND (Note 8) V IN = V CC (Note 8)l l–10 –10 1 110 10nA nA I CONV Input Sampling Current (Note 5)50nA V REFReference Output Voltage l1.2471.25 1.253V Reference Voltage Coefficient(Note 11) C-Grade I-Grade l±2 ±5 ±10ppm/°C ppm/°CReference Line Regulation 2.7V ≤ V CC ≤ 5.5V–90dB Reference Short Circuit Current V CC = 5.5, Forcing Output to GND l 35mA COMP Pin Short Circuit Current V CC = 5.5, Forcing Output to GND l200µA Reference Load Regulation 2.7V ≤ V CC ≤ 5.5V , I OUT = 100μA Sourcing 3.5mV/mA Reference Output Noise DensityC COMP = 0.1μF, C REFOUT = 0.1μF , At f = 1kHz 30nV/√Hzpower requireMenTs/424602faThe l denotes the specifications which apply over the full operating temperaturerange,otherwise specifications are at T A = 25°C.SYMBOLPARAMETER CONDITIONSMIN TYP MAX UNITS t CONV Conversion Time l 1316.623ms f SCK SCK Frequency Range l 2MHz t lSCK SCK Low Period l 250ns t hSCK SCK High Periodl 250nst 1CS Falling Edge to SDO Low Z (Notes 7, 8)l 0100ns t 2CS Rising Edge to SDO High Z (Notes 7, 8)l 0100ns t 3CS Falling Edge to SCK Falling Edge l 100ns t KQ SCK Falling Edge to SDO Valid (Note 7)l 0100ns t 4SDI Setup Before SCK ↑(Note 3)l 100ns t 5SDI Hold After SCK ↑(Note 3)l100nsNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2. All voltage values are with respect to GND. V CC = 2.7V to 5.5V unless otherwise specified. V REFCM = V REF /2, FS = V REFV IN = V IN + – V IN –, –V REF ≤ V IN ≤ V REF ; V INCM = (V IN + + V IN –)/2.Note 3. Guaranteed by design, not subject to test.Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation.Note 5: CS = V CC . A positive current is flowing into the DUT pin.Note 6: SCK = V CC or GND. SDO is high impedance.Note 7: See Figure 4.Note 8: See Figure 5.Note 9: Input sampling current is the average input current drawn from the input sampling network while the L TC2460/L TC2462 is actively sampling the input.Note 10: A positive current is flowing into the DUT pin.Note 11: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at T A = 25°C. (Note 2)SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNITSV IH High Level Input Voltage l V CC – 0.3V V IL Low Level Input Voltage l 0.3V I IN Digital Input Current l–1010µA C IN Digital Input Capacitance 10pF V OH High Level Output Voltage I O = –800µA l V CC – 0.5VV OL Low Level Output Voltage I O = 1.6mAl 0.4V I OZHi-Z Output Leakage Currentl–1010µADigiTal inpuTs anD DigiTal ouTpuTs/524602faTypical perForMance characTerisTicsOffset Error vs TemperatureADC Gain Error vs TemperatureT ransition Noise vs TemperatureConversion Mode Power Supply Current vs TemperatureSleep Mode Power Supply Current vs TemperatureV REF vs Temperature(T A = 25°C, unless otherwise noted)TEMPERATURE (°C)O F F S E T E R R O R (L S B )1524602 G04–10234–2–3–4–5TEMPERATURE (°C)A D C G A I N E R R O R (L SB )25524602 G050151020TEMPERATURE (°C)T R A N S IT I O N N O I S E R M S (µV )61024602 G06457893210–50–1010–3050703090TEMPERATURE (°C)C O N V E R S I O N C U R R E N T (m A )2.01.924602 G071.41.51.61.71.81.31.21.11.0–50–1010–3050703090TEMPERATURE (°C)S L E E P C U R R E N T (n A )35024602 G08150300250200100500–50–1010–3050703090TEMPERATURE (°C)R E F E R E N C E O U T P U T V O L T A G E (V )1.250824602 G091.25021.25031.25041.25051.25061.2507Integral NonlinearityIntegral NonlinearityMaximum INL vs TemperatureDIFFERENTIAL INPUT VOL TAGE (V)–1.25–0.75–0.25I N L (L S B )1324602 G02–102–2–30.250.751.25TEMPERATURE (°C)–55I N L (L S B )1324602 G03–102–2–3–35–15254565855125105DIFFERENTIAL INPUT VOL TAGE (V)–1.25–0.75–0.25I N L (L S B )1324602 G01–102–2–30.250.75 1.25/624602fapin FuncTionsREFOUT (Pin 1): Reference Output Pin. Nominally 1.25V , this voltage sets the fullscale input range of the ADC. For noise and reference stability connect to a 0.1µF capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT cannot be overdriven by an external reference. For applications that require an input range greater than 0V to 1.25V , please refer to the L TC2450/ L TC2452.COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1μF capacitor to GND.CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO output. A HIGH on this pin places the SDO output pin in a high impedance state and any inputs on SDI and SCK will be ignored.SDI (Pin 4): Serial Data Input Pin. This pin is used to pro-gram the sleep mode and 30Hz/60Hz output rate (L TC2460).SCK (Pin 5): Serial Clock Input. SCK synchronizes the serial data input/output. Once the conversion is complete, a new data bit is produced at the SDO pin following each SCK falling edge. Data is shifted into the SDI pin on each rising edge of SCK.SDO (Pin 6): Three-State Serial Data Output. SDO is used for serial data output during the DATA INPUT/OUTPUT state and can be used to monitor the conversion status.GND (Pins 7, 11): Ground. Connect directly to the ground plane through a low impedance connection.REF – (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor .IN + (L TC2462), IN (L TC2460) (Pin 9): Positive input volt-age for the L TC2462 differential device. ADC input for the L TC2460 single-ended device.IN – (L TC2462), GND (L TC2460) (Pin 10): Negative input voltage for the L TC2462 differential device. GND for the L TC2460 single-ended device.V CC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the device as possible.Exposed Pad (Pin 13 – DFN Package): Ground. Connect directly to the ground plane through a low impedance connection.Typical perForMance characTerisTics(T A = 25°C, unless otherwise noted)Power Supply Rejection vs Frequency at V CCConversion Time vs TemperatureFREQUENCY AT V CC (Hz)1R E J E C T I O N (d B )024602 G10–20–40–60–80–100–120101k 10k 100k 1M10010MTEMPERATURE (°C)C O N V E R S I O N T I M E (m s )2124602 G1120161718191514V REF vs V CCV CC (V)V R E F (V )1.248921.2489124602 G121.248841.248851.248861.248871.248881.248891.24890/724602faapplicaTions inForMaTionCONVERTER OPERATION Converter Operation CycleThe L TC2460/L TC2462 are low power , delta sigma, ana-log to digital converters with a simple SPI interface (see Figure 1). The L TC2462 has a fully differential input while the L TC2460 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT , SLEEP/NAP , and DATA INPUT/OUTPUT . The operation begins with the CONVERT state (see Fig-ure 2). Once the conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read or an abort is initiated the device begins a new conversion.The CONVE RT state duration is determined by the L TC2460/L TC2462 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (V CC < 2.1V) which generates an internal power-on reset signal.After the completion of a conversion, the L TC2460/L TC2462 enters the SLEEP/NAP state and remains there until the chip select is LOW (CS = LOW). Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state.Figure 2. L TC2460/L TC2462 State T ransition DiagramWhile in the SLEEP/NAP state, when chip select input is HIGH (CS = HIGH), the L TC2460/L TC2462’s converters are powered down. This reduces the supply current by approximately 50%. While in the Nap state the reference remains powered up. In order to power down the reference in addition to the converter , the user can select the SLEEPblock DiagraMFigure 1. Functional Block Diagram( ) PARENTHESIS INDICATE L TC2460/824602faapplicaTions inForMaTionmode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, the SLEEP state is entered and power is reduced to less than 2μA. The reference is powered up once CS is brought low. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF).Upon entering the DATA INPUT/OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin.During the DATA INPUT/OUTPUT state, the L TC2460/L TC2462 can be programmed to SLEEP or NAP (default) following the next conversion cycle. Data is shifted into the device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second bit EN2 = 0 the device is enabled for programming. The following two bits (SPD and SLP) will be written into the device. SPD (only used for the L TC2460) to select the 60Hz output rate, no offset calibration mode (SPD = 0, default). Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the L TC2462. The next bit (SLP) enables the sleep or nap mode. If SLP = 0 (default) the reference remains powered up at the end of the next conversioncycle. If SLP = 1, the reference powers down following the next conversion cycle. The remaining 12 SDI input bits are ignored (don’t care).SDI may also be tied directly to GND or V DD in order to simplify the user interface. In the case of the L TC2460, the 60Hz output rate is selected if SDI is tied low and the 30Hz output rate is selected if SDI is tied to V DD . The L TC2462 output rate is always 60Hz independent of SDI or SPD. The reference sleep mode is disabled for both the L TC2460 and L TC2462 if SDI is tied to GND or V DD .The DATA INPUT/OUTPUT state concludes in one of two different ways. First, the DATA INPUT/OUTPUT state opera-tion is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA INPUT/OUT-PUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the L TC2460/L TC2462 will enter the CONVE RT state and initiate a new conversion cycle.Power-Up SequenceWhen the power supply voltage (V CC ) applied to the con-verter is below approximately 2.1V , the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result.When V CC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the L TC2460/L TC2462 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (C COMP = C REFOUT = 0.1μF). The first conver-sion following powerup will be invalid since the reference voltage has not completely settled. The first conversion following power up can be discarded using the data abort command or simply read and ignored. The following con-versions are accurate to the device specifications.Ease of UseThe L TC2460/L TC2462 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondenceFigure 3. Output Code vs V IN + with V IN – = 0 (L TC2462)V IN +/V REF +O U T P U T C O D E4122024602 F03–4–120816–8–16–20/924602fabetween the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions.The L TC2460/L TC2462 perform offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature.The L TC2460/L TC2462 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the L TC2460/L TC2462. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1µF results in <1LSB additional error . Additionally, there is negligible leakage current between IN + and IN –.Input Voltage Range (L TC2460)Ignoring offset and full-scale errors, the L TC2460 will theoretically output an “all zero” digital result when the input is at ground (a zero scale input) and an “all one” digital result when the input is at V REF (V REFOUT = 1.25V). In an under-range condition, for all input voltages below zero scale, the converter will generate the output code 0. In an over-range condition, for all input voltages greater than V REF , the converter will generate the output code 65535. For applications that require an input range greater than 0V to 1.25V , please refer to the L TC2450.Input Voltage Range (L TC2462)As mentioned in the Output Data Format section, the output code is given as 32768 • (V IN + – V IN –)/V REF + 32768. For (V IN + – V IN –) ≥ V REF , the output code is clamped at 65535 (all ones). For (V IN + – V IN –) ≤ –V REF , the output code is clamped at 0 (all zeroes).The L TC2462 includes a proprietary architecture that can, typically, digitize each input up to 8 LSBs above V REF and below GND, if the differential input is within ±V REF . As an example (Figure 3), if the user desires to measure a signal slightly below ground, the user could set V IN – = GND, and V REF = 1.25V . If V IN + = GND, the output code would be approximately 32768. If V IN + = GND – 8LSB = –0.305mV , the output code would be approximately 32760. For applications that require an input range greater than ±1.25V , please refer to the L TC2452.Output Data FormatThe L TC2460/L TC2462 generates a 16-bit direct binary encoded result. It is provided as a 16-bit serial stream through the SDO output pin under the control of the SCK input pin (see Figure 4).The L TC2462 (differential input) output code is given by 32768 • (V IN + – V IN –)/V REF + 32768. The first bit output by the L TC2462, D15, is the MSB, which is 1 for V IN + ≥ V IN – and 0 for V IN + < V IN –. This bit is followed by succes-sively less significant bits (D14, D13, …) until the LSB is output by the L TC2462, see Table 1.KQ lSCK hSCKapplicaTions inForMaTionFigure 4. Data Input/Output Timing/applicaTions inForMaTionThe L TC2460 (single-ended input) output code is a direct binary encoded result, see Table 1.During the data output operation the CS input pin must be pulled low (CS = LOW). The data output process starts with the most significant bit of the result being present at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin after each falling edge detected at the SCK input pin. The output data can be reliably latched on the rising edge of SCK.Data Input FormatThe data input word is 4 bits long and consists of two en-able bits (EN1 and EN2) and two programming bits (SPD and SLP). EN1 is applied to the first rising edge of SCK after the conversion is complete. Programming is enabled by setting EN1 = 1 and EN2 = 0.The speed bit (SPD) is only used by the L TC2460. In the default mode, SPD = 0, the output rate is 60Hz and con-tinuous background offset calibration is not performed. By changing the SPD bit to 1, background offset calibration is performed and the output rate is reduced to 30Hz. Alterna-tively, SDI can be tied directly to ground (SPD = 0) or V CC (SPD = 1), eliminating the need to program the device. The L TC2462 data output rate is always 60Hz and background offset calibration is performed (SPD = don’t care).The sleep bit (SLP) is used to power down the on chip reference. In the default mode, the reference remains powered up even when the ADC is powered down. If the SLP bit is set HIGH, the reference will power down after the next conversion is complete. It will remain powered down until CS is pulled low. The reference startup time is approximately 12ms. In order to ensure a stable refer-ence for the following conversions, either the data input/ output time should be delayed 12ms after CS goes low or the first conversion following a reference start up should be discarded. If SDI is tied HIGH (L TC2460 operating in 30Hz mode) the SLP mode is disabled. Conversion Status MonitorFor certain applications, the user may wish to monitor the L TC2460/L TC2462 conversion status. This can be achieved by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low (CS = LOW), the SDO output pin will provide an indication of the conversion status. SDO = HIGH is an indication of a conversion cycle in progress while SDO = LOW is an indication of a completed conversion cycle. An example of such a sequence is shown in Figure 5. Conversion status monitoring, while possible, is not re-quired for the L TC2460/L TC2462 as its conversion time is fixed and typically 16.6ms (23ms maximum). Therefore, external timing can be used to determine the completion of a conversion cycle.SERIAL INTERFACEThe L TC2460/L TC2462 transmit the conversion result and receive the start of conversion command through a syn-chronous 2-, 3- or 4-wire interface. This interface can beTable 1. L TC2460/L TC2462 Output Data FormatSINGLE ENDED INPUT V IN(L TC2460)DIFFERENTIAL INPUT VOL TAGEV IN+ – V IN– (L TC2462)D15(MSB)D14D13D12...D2D1D0(LSB)CORRESPONDINGDECIMAL VALUE≥V REF≥V REF11111165535V REF – 1LSB V REF – 1LSB111110655340.75 • V REF0.5 • V REF110000491520.75 • V REF – 1LSB0.5 • V REF – 1LSB101111491510.5 • V REF010*********0.5 • V REF – 1LSB–1LSB011111327670.25 • V REF–0.5 • V REF010********0.25 • V REF – 1LSB–0.5 • V REF – 1LSB001111163830≤ –V REF0000000/1024602fa分销商库存信息:LINEAR-TECHNOLOGYLTC2460CDD#PBF LTC2460IMS#PBF LTC2462IMS#PBF LTC2462CMS#PBF LTC2460CDD#TRPBF LTC2460CMS#TRPBF LTC2462CDD#TRPBF LTC2462CMS#TRPBF LTC2460IDD#PBF LTC2462IDD#PBF LTC2460IDD#TRPBF LTC2460IMS#TRPBF LTC2462IDD#TRPBF LTC2462IMS#TRPBF LTC2462CDD#PBF LTC2460CMS#PBF DC1490A DC1492A。

BB182LX,315;中文规格书,Datasheet资料

1.Product proﬁle1.1General descriptionThe BB182LX is a planar technology variable capacitance diode in a SOD882T ultra small leadless plastic SMD package.The excellent matching performance is achieved by gliding matching and a Direct Matching Assembly (DMA) procedure.1.2FeaturesI High linearityI Excellent matching to 2 % DMA I Ultra small leadless SMD packageI C d(28V):2.7pF; C d(1V) to C d(28V) ratio: 22ILow series resistance1.3ApplicationsI Voltage Controlled Oscillators (VCO)I Electronic tuning in VHF television tuners, Band A up to 160MHz2.Pinning information[1]The marking bar indicates the cathode.3.Ordering informationBB182LXVHF variable capacitance diodeRev. 01 — 29 January 2009Product data sheetTable 1.PinningPin Description Simpliﬁed outlineGraphic symbol1cathode [1]2anodeTransparenttop view21sym008Table 2.Ordering informationType numberPackage NameDescriptionVersion BB182LX-leadless ultra small plastic package; 2 terminals;body 1.0×0.6×0.4mmSOD882T4.Marking5.Limiting values6.CharacteristicsTable 3.Marking codesType numberMarking code BB182LXL7Table 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter ConditionsMin Max Unit V R reverse voltage -32V I F forward current -20mA T stg storage temperature −55+150°C T jjunction temperature−55+125°CTable 5.CharacteristicsSymbol Parameter Conditions MinTypMaxUnitI Rreverse currentsee Figure 3V R =30V--10nA V R =30V; T j =85°C--200nA r s diode series resistance f =100MHz at C d =30pF;see Figure 2- 1.0-ΩC ddiode capacitancef =1MHz; see Figure 1 and Figure 4V R =1V 52-62pF V R =28V2.48 2.7 2.89pFC d(1V)/C d(2V)diode capacitance ratio (1V to 2V) f = 1 MHz - 1.31-C d(1V)/C d(28V)diode capacitance ratio (1V to 28V) f = 1 MHz 20.622-C d(25V)/C d(28V)diode capacitance ratio (25V to 28V)f = 1 MHz- 1.05-∆C d /C ddiode capacitance matchingV R =1V to 28V;in sequence of 5 diodes (gliding)--2%f =1MHz; T j =25°C.f =100MHz; T j =25°C.Fig 1.Diode capacitance as a function of reverse voltage; typical valuesFig 2.Diode serial resistance as a function of reverse voltage; typical valuesT j =0°C to 85°C.Fig 3.Reverse current as a function of junction temperature; maximum valuesFig 4.Temperature coefﬁcient of diode capacitance as a function of reverse voltage; typical values001aaj47540206080C d (pF)0V R (V)10−1102101001aaj4760.40.81.2r s (Ω)0V R (V)10−1102101001aaj47710210103I R (nA)1T j (°C)010080406020V R (V)10−1102101001aaj47810−310−410−2TC Cd (K −1)10−57.Package outlineFig 5.Package outline SOD882TREFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDECJEITASOD882TSOD882T04-12-1406-04-12Note1. The marking bar indicates the cathodeUNIT A mm0.400.360.550.450.650.551.050.950.300.22A 1max DIMENSIONS (mm are the original dimensions)Leadless ultra small plastic package; 2 terminals; body 1 x 0.6 x 0.4 mmABye 1wBML 1 (2×)A 1A b (2×)(2×)(2×)DE (1)0.5 1 mmscale0.04b D E e 10.65L 1w 0.1y 0.0321wAM8.AbbreviationsTable 6.AbbreviationsAcronym DescriptionSMD Surface Mounted DeviceVHF Very High Frequency9.Revision historyTable 7.Revision historyDocument ID Release date Data sheet status Change notice Supersedes BB182LX_120090129Product data sheet--10.Legal information10.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Deﬁnitions”.[3]The product status of device(s)described in this document may have changed since this document was published and may differ in case of multiple devices.The latest product status information is available on the Internet at URL .10.2DeﬁnitionsDraft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s)and title.A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.10.3DisclaimersGeneral —Information in this document is believed to be accurate andreliable.However,NXP Semiconductors does not give any representations or warranties,expressed or implied,as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation speciﬁcations and product descriptions, at any time and without notice.This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134)may cause permanent damage to the device.Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale,as published at /proﬁle/terms , including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant,conveyance or implication of any license under any copyrights,patents or other industrial or intellectual property rights.Quick reference data —The Quick reference data is an extract of theproduct data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.10.4TrademarksNotice:All referenced brands,product names,service names and trademarks are the property of their respective owners.11.Contact informationFor more information, please visit:For sales ofﬁce addresses, please send an email to:salesaddresses@Document status [1][2]Product status [3]DeﬁnitionObjective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.Product [short] data sheetProductionThis document contains the product speciﬁcation.12.Contents1Product proﬁle. . . . . . . . . . . . . . . . . . . . . . . . . . 11.1General description. . . . . . . . . . . . . . . . . . . . . . 11.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Pinning information. . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 14Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 26Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 48Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 59Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 510Legal information. . . . . . . . . . . . . . . . . . . . . . . . 610.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 610.2Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 610.4T rademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Contact information. . . . . . . . . . . . . . . . . . . . . . 612Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2009.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@Date of release: 29 January 2009分销商库存信息: NXPBB182LX,315。

MMF1WSFRF10R;MMF1WSFRF100K;MMF1WSFRF100R;MMF1WSFRF10K;MMF1WSFRF120R;中文规格书,Datasheet资料

Note: Special value is available on request
ENVIRONMENTAL CHARACTERISTICS
PERFORMANCE TEST Short Time Overload Voltage Proof Temperature Coefficient Insulation Resistance Solderability Solvent Resistance of Marking Periodic-pulse Overload Damp Heat Steady State Endurance at 70°C Temperature Cycling Resistance to Soldering Heat TEST METHOD IEC 60115-1 4.13 IEC 60115-1 4.7 IEC 60115-1 4.8 IEC 60115-1 4.6 IEC 60115-1 4.17 IEC 60115-1 4.30 IEC 60115-1 4.39 IEC 60115-1 4.24 IEC 60115-1 4.25 IEC 60115-1 4.19 IEC 60115-1 4.18 2.5 times RCWV for 5 Sec. in V-block for 60 Sec., test voltage by type -55°C to +155°C in V-block for 60 Sec. 235±5°C for 3±0.5 Sec. IPA for 5±0.5 Min. with ultrasonic 4 times RCWV 10,000 cycles (1 Sec. on, 25 Sec. off) 40±2°C, 90-95% RH for 56 days, loaded with 0.1 times RCWV 70±2°C at RCWV for 1,000 Hr. (1.5 Hr. on, 0.5 Hr. off) -55°C Room Temp. +155°C Room Temp. (5 cycles) 260±3°C for 10±1 Sec., immersed to a point 3±0.5mm from the body APPRAISE ±0.5%+0.05 Ω By type By type >10,000M Ω 95% Min. coverage No deterioration of coatings and markings ±1.0%+0.05 Ω ±2.0%+0.1 Ω ±2.0%+0.1 Ω ±0.75%+0.05 Ω ±0.5%+0.05 Ω

BAR18FILM;中文规格书,Datasheet资料

Min.
Typ.
Max.
2 100
Unit
pF ps
* Effective carrier life time.
Fig. 1-1: Forward voltage drop versus forward current (low level).
IFM(A) 2.0E-2 1.8E-2 1.6E-2 1.4E-2 1.2E-2 1.0E-2 8.0E-3 6.0E-3 4.0E-3 2.0E-3 0.0E+0 0.0
Epoxy meets UL94,V0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

3700S-1-103L;3700S-1-202L;3700S-1-203L;3700S-1-104L;3701H-1-103L;中文规格书,Datasheet资料

Total Resistance Tolerance.................. ±5 % ...........................................±10 %
Independent Linearity .......................... ±0.25 % ......................................±0.25 %
Total Resistance Shift ...................... ±2 % maximum ..........................±5 % maximum Rotational Life (No Load)..................... 1,000,000 shaft revolutions2 .....4,000,000 shaft revolutions2
Effective Electrical Angle ..................... 3600 ° +10 °, -0 ° .......................3600 ° +10 °, -2 °
Absolute Minimum Resistance/ ........... 1 ohm or 0.1 % maximum ..........Minimum voltage
Mechanical Characteristics1
Stop Strength.......................................................................................... 14 N-cm (20 oz-in.) minimum Mechanical Angle ......................................................................................................3600 ° +20 °, -0 ° Torque (Starting & Running) .....................................................................0.45 N-cm (0.6 oz.-in.) max.

BAV99,215;BAV99,235;BAV99W,115;BAV99W,135;BAV99S,135;中文规格书,Datasheet资料

IFRM
repetitive peak forward
-
current
IFSM
non-repetitive peak
forward current
Ptot Per device
total power dissipation BAV99 BAV99S BAV99W
square wave tp = 1 μs tp = 1 ms tp = 1 s
Simplified outline Graphic symbol
3
3
1
2
006aaa144
1
2
006aaa763
654
654
123
123 006aab101
3. Ordering information
Table 4. Ordering information
Type number Package
IF = 50 mA
IF = 150 mA
IR
reverse current
VR = 25 V
VR = 80 V
VR = 25 V; Tj = 150 °C
VR = 80 V; Tj = 150 °C
Cd
diode capacitance
f = 1 MHz; VR = 0 V
trr
reverse recovery time
Min Typ
-
-
-
-
[1] -
-
[1] When switched from IF = 10 mA to IR = 10 mA; RL = 100 Ω; measured at IR = 1 mA.
Max
0.5 100 4

W9412G6JH-5I;中文规格书,Datasheet资料

Read Operation............................................................................................................. 12 Write Operation ............................................................................................................. 13 Precharge ..................................................................................................................... 13 Burst Termination ......................................................................................................... 13 Refresh Operation ........................................................................................................ 13 Power Down Mode ....................................................................................................... 14 Input Clock Frequency Change during Precharge Power Down Mode ........................ 14 Mode Register Operation .............................................................................................. 14 Publication Release Date: Nov. 29, 2011 Revision A03

DS1603;中文规格书,Datasheet资料

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: /errata .FEATURES§ Two 32-bit counters keep track of real -time and elapsed time§ Counters keep track of seconds for over 125 years§ Battery powered counter counts seconds from the time battery is attached until V BAT is less than 2.5V§ V CC powered counter counts seconds while V CC is above V TP and retains the count in the absence of V CC under battery backup power § Clear function resets selected counter to 0 § Read/write serial port affords low pin count § Powered internally by a lithium energy cell that provides over 10 years of operation§ One-byte protocol defines read/write, counter address and software clear function§ Self-contained crystal provides an accuracy of ±2 min per month§ Operating temperature range of 0°C to +70°C § Low-profile SIP module§ Underwriters Laboratory (UL) recognized PIN ASSIGNMENTPIN DESCRIPTIONRST- Reset CLK - ClockDQ - Data Input/Output GND - Ground V CC - +5VOSC - 1Hz Oscillator Output NC- No ConnectDESCRIPTIONThe DS1603 is a real -time clock/elapsed time counter designed to count seconds when V CC power is applied and continually count seconds under battery backup power with an additional counter regardless of the condition of V CC . The continuous counter can be used to derive time of day, week, month, and year by using a software algorithm. The V CC powered counter will automatically record the amount of time that V CC power is applied. This function is particularly useful in determining the operational time of equipment in which the DS1603 is used. Alternatively, this counter can also be used under software control to record real -time events. Communication to and from the DS1603 takes place via a 3-wire serial port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. The device contains a 32.768kHz crystal that will keep track of time to within ±2 min/mo. An internal lithium energy source contains enough energy to power the continuous seconds counter for over 10 years.OPERATIONThe main elements of the DS1603 are shown in Figure 1. As shown, communications to and from the elapsed time counter occur over a 3-wire serial port. The port is activated by driving RST to a high state.V CC RST DQ NC CLK OSC GND DS1603Elapsed Time Counter Moduleselect, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol additional clocks will output data for a read or input data for a w rite. V CC must be present to access the DS1603. If V CC < V TP, the DS1603 will switch to internal power and disable the serial port to conserve energy. When running off of the internal power supply, only the continuous counter will continue to count and the counter powered by V CC will stop, but retain the count, which had accumulated when V CC power was lost. The 32-bit V CC counter is gated by V CC and the internal 1Hz signal.PROTOCOL REGISTERThe protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical 1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or write this counter. If the counter is being read, the contents will be latched into a different register at the end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the rising edge of the 32nd clock. The next bit (bit 6 which is designated AVC) selects the 32–bit V CC active counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond the protocol are ignored and bit 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3 (011) will give a clock accuracy of ±120 seconds per month at +25°C. Increasing the binary number towards 7 will cause the real-time clock to run faster. Conversely, lowering the binary number towards 0 will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used to conserve battery life during storage. In this mode the internal power supply current is reduced to 100 nA maximum. In applications where oscillator trimming is not practical or not needed, a default setting of 011 is recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When set to logic 1, the continuous counter will reset to 0 when RST is taken low. Bit 1 of protocol (designated CVC) is used to clear the V CC active counter. When set to logical 1, the V CC active counter will reset to 0 when RST is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a logical 1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow w ill write a counter or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a logical 1 a read action will follow. When sending the protocol, 8 bits should always be sent. Sending less than 8 bits can produce erroneous results. If clearing the counters or trimming the oscillator, the data transfer can be terminated after the 8-bit protocol is sent. However, when reading or writing the counters, 32 clock cycles should always follow the protocol.RESET AND CLOCK CONTROLAll data transfers are initiated by driving the RST input high. The RST input has two functions. First, RST turns on the serial port logic, which allows access to the protocol register for the protocol data entry. Second, the RST signal provides a method of terminating the protocol transfer or the 32-bit counter transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For write inputs, data must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock when data is being read. All data transfers terminate if the RST input is transitioned low and the DQ pin goes to a high-impedance state. RST should only be transitioned low while the clock is high to avoid disturbing the last bit of data. All data transfers must consist of 8 bits when transferring protocol only or 8 + 32 bits when reading or writing either counter. Data tran sfer is illustrated in Figure 3.DATA INPUTFollowing the 8-bit protocol that inputs write mode, 32 bits of data are written to the selected counter on the rising edge of the next 32 CLK cycles. After 32 bits have been entered any additional CLK cycles will be ignored until RST is transitioned low to end data transfer and then high again to begin new data transfer.DATA OUTPUTFollowing the eight CLK cycles that input read mode protocol, 32 bits of data will be output from the selected counter on the next 32 CLK cycles. The first data bit to be transmitted from the selected 32-bit counter occurs on the falling edge after the last bit of protocol is written. When transmitting data from the selected 32-bit counter, RST must remain at high level as a transition to low level will terminate data transfer. Data is driven out the DQ pin as long as CLK is low. When CLK is high the DQ pin is tristated. OSCILLATOR OUTPUTPin 6 of the DS1603 module is a 1Hz output signal. This signal is present only when V CC is applied and greater than the internal power supply. However, the output is guaranteed to meet TTL requirement only while V CC is within normal limits. This output can be used as a 1-second interrupt or time tick needed in some applications.INTERNAL POWERThe internal battery of the DS1603 module provides 35mAh and will run the elapsed time counter for over 10 years in the absence of power.PIN DESCRIPTIONSV CC, GND – DC power is provided to the device on these pins. V CC is the +5V input. When 5V is applied within normal limits, the device is fully accessible and data can be written and read. When a 3V battery is connected to the device and V CC is below 1.25 x V BAT, reads and writes are inhibited. As V CC falls below V BAT the continuous counter is switched over to the internal battery.CLK (Serial Clock Input) – CLK is used to synchronize data movement on the serial interface.DQ (Data Input/Output) – The DQ pin is the bi-directional data pin for the 3-wire interface.RST (Reset) – The reset signal must be asserted high during a read or a write.OSC (One Hertz Output Signal) – This signal is only present when Vcc is at a valid level and the oscillator is enabled.Figure 1. ELAPSED TIME COUNTER BLOCK DIAGRAMFigure 2. PROTOCOL BIT MAP7 6 5 4 3 2 1 0ACC AVC OSC2 OSC1 OSC0 CCC CVC RDTable 1. VALID PROTOCOLSPROTOCOLACTIONACC AVC OSC2 OSC1 OSC0 CCC CVC RDFUNCTION ReadContinuous Counter 1 0 X X X X X 1Output continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.WriteContinuous Counter 1 0 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.Read V CCActive Counter 0 1 X X X X X 1Output V CC activecounter on the 32 clocksfollowing protocol,oscillator trim registeris not updated. Countersare not reset.Write V CCActive Counter 0 1 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.ClearContinuous Counter 0 0 X X X 1 X XResets the continuouscounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Clear V CCActive Counter 0 0 X X X X 1 XResets the V CC activecounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Set Oscillator Trim Bits 1 1 A B C X X 0Sets the oscillator trimregister to a value ofABC. Counters areunaffected.X = Don’t CareFigure 3. DATA TRANSFERTIMING DIAGRAM: READ/WRITE DATA TRANSFERNote: t CL, t CH, t R, and t F apply to both read and write data transfer.ABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground -0.3V to +7.0VOperating Temperature Range 0°C to +70°CStorage Temperature Range -40°C to +70°CSoldering Temperature Range See IPC/JEDEC J-STD-020A (See Note 11)This is a stress rating only and functional operation of the device at these or any other conditions beyond t h ose indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.RECOMMENDED DC OPERATING CONDITIONS (0°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage V CC 4.5 5.0 5.5 V 1 Logic 1 Input V IH 2.0 V CC + 0.3 V 1 Logic 0 Input V IL-0.3 0.8 V 1DC ELECTRICAL CHARACTERISTICS (0°C to +70°C; V CC = 5V ±10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage I LI-1 +1 µAI/O Leakage I LO-1 +1 µALogic 1 Output V OH 2.4 V 2 Logic 0 Output V OL0.4 V 3 Active Supply Current I CC 1 mA 4 Timekeeping Current I CC150 µA 5 Battery Trip Point V TP 3.0 4.5 V 9 CAPACITANCE (T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C I 5 pFI/O Capacitance C I/O10 pF(T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Datat DR10 years 10 Retention TimeNOTES:1) All voltages are referenced to ground.2) Logic 1 voltages are specified at a source current of 1mA.3) Logic 0 voltages are specified at a sink current of 4mA.4) I CC is specified with the DQ pin open.5) I CC1 is specified with V CC at 5.0V and RST = GND.6) Measured at V IH= 2.0V or V IL = 0.8V.7) Measured at V OH = 2.4V or V OL - 0.4V.8) Load capacitance = 50pF.9) Battery trip point is the point at which the V CC powered counter and the serial port stops operation.The battery trip point drops below the minimum once the internal lithium energy cell is exhausted. 10) The expected t D R is defined as accumulative time in the absence of V CC with the clock oscillatorrunning.11) Real-time clock modules can be successfully processed through conventional wave-solderingtechniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used.DS1603DS1603 7-PIN MODULEPKG7-PIN DIM MIN MAX A IN. MM 0.830 21.08 0.850 21.59 B IN. MM 0.650 16.51 0.670 17.02 C IN. MM 0.310 7.87 0.330 8.38 D IN. MM 0.015 0.38 0.030 0.76 E IN. MM 0.110 2.79 0.140 3.56 F IN. MM 0.015 0.38 0.021 0.53 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.105 2.67 0.135 3.43 J IN. MM 0.360 9.14 0.390 9.91分销商库存信息: MAXIMDS1603。

LTC2191IUKG#PBF;LTC2192CUKG#PBF;LTC2192IUKG#PBF;LTC2190CUKG#PBF;中文规格书,Datasheet资料

1219210fAPPLICATIONSnCommunications n Cellular Base Stations n Software-Defined Radios n Portable Medical Imagingn Multi-Channel Data Acquisition n Nondestructive TestingTYPICAL APPLICATIONDESCRIPTION25Msps Low PowerDual ADCsThe L TC ®2192/L TC2191/L TC2190 are 2-channel, simul-taneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07ps RMS allows undersampling of IF frequencies with excellent noise performance.DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.3LSB RMS .To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.The ENC + and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.FEATURESn2-Channel Simultaneous Sampling ADCn Serial LVDS Outputs: 1, 2 or 4 Bits per Channel n 77dB SNR n 90dB SFDRn Low Power: 198mW/146mW/104mW Total n 99mW/73mW/52mW per Channel n Single 1.8V Supplyn Selectable Input Ranges: 1V P-P to 2V P-P n 550MHz Full-Power Bandwidth S/H n Shutdown and Nap Modesn Serial SPI Port for Configuration n52-Pin (7mm × 8mm) QFN Package2-Tone FFT , f IN = 70MHz and 69MHzCH1ANALOG INPUT CH2ANALOG INPUT ENCODEINPUTSERIALIZED LVDS OUTPUTSL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100102030219210 G07/2219210fSupply VoltagesV DD , OV DD ................................................–0.3V to 2V Analog Input VoltageA IN +, A IN –, PAR/SER , SENSE(Note 3) ....................................–0.3V to (V DD + 0.2V)Digital Input Voltage E NC +, ENC –, CS , SDI, SCK (Note 4) ......–0.3V to 3.9V SDO (Note 4) ............................................–0.3V to 3.9V Digital Output Voltage ................–0.3V to (OV DD + 0.3V)Operating Temperature RangeL TC2192C, L TC2191C, L TC2190C.............0°C to 70°C L TC2192I, L TC2191I, L TC2190I ............–40°C to 85°C Storage Temperature Range ...................–65°C to 150°C(Notes 1, 2)1615171819TOP VIEW53GNDUKG PACKAGE52-LEAD (7mm × 8mm) PLASTIC QFN20212223242526515250494847464544434241333435363738394087654321V CM1GND A IN1+A IN1–GND REFH REFL REFH REFL PAR/SER A IN2+A IN2–GND V CM2OUT1C +OUT1C –OUT1D +OUT1D –DCO +DCO –OV DD OGND FR +FR–OUT2A +OUT2A –OUT2B +OUT2B –V D DV D DS E N S EG N DV R E FG N DS D OG N DO U T 1A +O U T 1A –O U T 1B +O U T 1B –V D DV D DE N C +E N C –C SS C KS D IG N DO U T 2D–O U T 2D +O U T 2C –O U T 2C +32313029282791011121314T JMAX = 150°C, θJA = 29°C/WEXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2192CUKG#PBF L TC2192CUKG#TRPBF L TC2192UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2192IUKG#PBF L TC2192IUKG#TRPBF L TC2192UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C L TC2191CUKG#PBF L TC2191CUKG#TRPBF L TC2191UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2191IUKG#PBF L TC2191IUKG#TRPBF L TC2191UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C L TC2190CUKG#PBF L TC2190CUKG#TRPBF L TC2190UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2190IUKG#PBFL TC2190IUKG#TRPBFL TC2190UKG52-Lead (7mm × 8mm) Plastic QFN–40°C to 85°CConsult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container .Consult L TC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS/CONVERTER CHARACTERISTICSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)PARAMETER CONDITIONSL TC2192L TC2191L TC2190UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXResolution (No Missing Codes)l161616Bits Integral Linearity Error Differential Analog Input(Note 6)l–6±26–6±26–6±26LSB Differential Linearity Error Differential Analog Input l–0.9±0.50.9–0.9 ±0.50.9–0.9±0.50.9LSB Offset Error(Note 7)l–7±1.57–7±1.57–7±1.57mVGain Error Internal ReferenceExternal Reference l–1.7±1.5–0.40.9–1.7±1.5–0.40.9–1.7±1.5–0.40.9%FS%FSOffset Drift±10±10±10µV/°CFull-Scale Drift Internal ReferenceExternal Reference ±30±10±30±10±30±10ppm/°Cppm/°CGain Matching±0.3±0.3±0.3%FS Offset Matching±1.5±1.5±1.5mV T ransition Noise 3.3 3.3 3.2LSB RMSANALOG INPUTThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN+ – A IN–) 1.7V < V DD < 1.9V l 1 to 2V P-P V IN(CM)Analog Input Common Mode (A IN+ + A IN–)/2Differential Analog Input (Note 8)l0.7V CM 1.25V V SENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300VI INCM Analog Input Common Mode Current Per Pin, 65MspsPer Pin, 40MspsPer Pin, 25Msps 1046440µAµAµAI IN1Analog Input Leakage Current (No Encode)0 < A IN+, A IN– < V DD l–11µA I IN2PAR/SER Input Leakage Current0 < PAR/SER < V DD l–33µA I IN3SENSE Input Leakage Current0.625V < SENSE < 1.3V l–66µA t AP Sample-and-Hold Acquisition Delay Time0nst JITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended EncodeDifferential Encode 0.070.09ps RMSps RMSCMRR Analog Input Common Mode Rejection Ratio80dB BW–3B Full-Power Bandwidth Figure 6 Test Circuit550MHz/3219210fDYNAMIC ACCURACYThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 5)SYMBOL PARAMETER CONDITIONSL TC2192L TC2191L TC2190UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXSNR Signal-to-Noise Ratio5MHz Input30MHz Input 70MHz Input 140MHz Input l75.37776.976.876.375.276.976.876.776.275.677.17776.976.4dBFSdBFSdBFSdBFSSFDR Spurious Free Dynamic Range2nd Harmonic 5MHz Input30MHz Input70MHz Input140MHz Inputl839090898483909089848390908984dBFSdBFSdBFSdBFSSpurious Free Dynamic Range 3rd Harmonic 5MHz Input30MHz Input70MHz Input140MHz Inputl849090898484909089848490908984dBFSdBFSdBFSdBFSSpurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input30MHz Input70MHz Input140MHz Inputl899595959589959595958995959595dBFSdBFSdBFSdBFSS/(N+D)Signal-to-Noise PlusDistortion Ratio 5MHz Input30MHz Input70MHz Input140MHz Inputl74.876.876.776.476.374.876.776.676.375.27576.976.876.576.4dBFSdBFSdBFSdBFSCrosstalk10MHz Input–110–110–110dBcINTERNAL REFERENCE CHARACTERISTICSThel denotes the specifications which apply over the fulloperating temperature range, otherwise specifications are at T A = 25°C. (Note 5)PARAMETER CONDITIONS MIN TYP MAX UNITSV CM Output Voltage I OUT = 00.5 • V DD – 25mV0.5 • V DD0.5 • V DD + 25mV VV CM Output Temperature Drift±25ppm/°CV CM Output Resistance–600µA < I OUT < 1mA4ΩV REF Output Voltage I OUT = 0 1.225 1.250 1.275VV REF Output Temperature Drift±25ppm/°CV REF Output Resistance–400µA < I OUT < 1mA7ΩV REF Line Regulation 1.7V < V DD < 1.9V0.6mV/VDIGITAL INPUTS AND OUTPUTSThel denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSENCODE INPUTS (ENC+, ENC–)Differential Encode Mode (ENC– Not Tied to GND)V ID Differential Input Voltage(Note 8)l0.2VV ICM Common Mode Input Voltage Internally SetExternally Set (Note 8)l 1.11.21.6VVV IN Input Voltage Range ENC+, ENC– to GND (Note 8)l0.2 3.6V R IN Input Resistance See Figure 1010kΩC IN Input Capacitance(Note 8) 3.5pF /4219210fDIGITAL INPUTS AND OUTPUTSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND)V IH High Level Input Voltage V DD =1.8V l 1.2V V IL Low Level Input Voltage V DD =1.8V l0.6V V IN Input Voltage Range ENC+ to GND l0 3.6V R IN Input Resistance See Figure 1130kΩC IN Input Capacitance(Note 8) 3.5pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)V IH High Level Input Voltage V DD =1.8V l 1.3V V IL Low Level Input Voltage V DD =1.8V l0.6V I IN Input Current V IN = 0V to 3.6V l–1010µA C IN Input Capacitance(Note 8)3pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)R OL Logic Low Output Resistance to GND V DD =1.8V, SDO = 0V200ΩI OH Logic High Output Leakage Current SDO = 0V to 3.6V l–1010µA C OUT Output Capacitance(Note 8)3pF DIGITAL DATA OUTPUTSV OD Differential Output Voltage100Ω Differential Load, 3.5mA Mode100Ω Differential Load, 1.75mA Mode ll247125350175454250mVmVV OS Common Mode Output Voltage100Ω Differential Load, 3.5mA Mode100Ω Differential Load, 1.75mA Mode ll1.1251.1251.2501.2501.3751.375VVR TERM On-Chip Termination Resistance Termination Enabled, OV DD = 1.8V100ΩPOWER REQUIREMENTSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 9)SYMBOL PARAMETER CONDITIONSL TC2192L TC2191L TC2190UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXV DD Analog Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V OV DD Output Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V I VDD Analog Supply Current Sine Wave Input l9910972804956mA I OVDD Digital Supply Current1-Lane Mode, 1.75mA Mode1-Lane Mode, 3.5mA Mode2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode llll10.217.613.624.721.139.6173025479.216.612.823.920.338.8162925478.716.112.323.419.938.416292547mAmAmAmAmAmAP DISS Power Dissipation1-Lane Mode, 1.75mA Mode1-Lane Mode, 3.5mA Mode2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode llll198211203223217250227251242281146159152172166199173197189229104118111131124158130153146186mWmWmWmWmWmWP SLEEP Sleep Mode Power111mW P NAP Nap Mode Power505050mW P DIFFCLK Power Increase with Diffential Encode Mode Enabled(No Increase for Sleep Mode)202020mW /5219210fTIMING CHARACTERISTICSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONSL TC2192L TC2191L TC2190UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXf S Sampling Frequency(Notes 10, 11)l565540525MHzt ENCL ENC Low Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll7.327.697.6910010011.88212.512.51001001922020100100nsnst ENCH ENC High Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll7.327.697.6910010011.88212.512.51001001922020100100nsnst AP Sample-and-HoldAcquistion Delay Time000ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (R TERM = 100Ω Differential, C L = 2pF to GND On Each Output)t SER Serial Data Bit Period4-Lane Output Mode2-Lane Output Mode1-Lane Output Mode 1/(4 • f S)1/(8 • f S)1/(16 • f S)Sect FRAME FR to DCO Delay(Note 8)l0.35 • t SER0.5 • t SER0.65 • t SER Sec t DATA Data to DCO Delay(Note 8)l0.35 • t SER0.5 • t SER0.65 • t SER Sec t PD Propagation Delay(Note 8)l0.7n + 2 • t SER 1.1n + 2 • t SER 1.5n + 2 • t SER Sec t r Output Rise Time Data, DCO, FR, 20% to 80%0.17ns t f Output Fall Time Data, DCO, FR, 20% to 80%0.17ns DCO Cycle-Cycle Jitter t SER = 1ns60ps P-P Pipeline Latency7Cycles SPI Port Timing (Note 8)t SCK SCK Period Write ModeReadback Mode,C SDO = 20pF, R PULLUP = 2k ll40250nsnst S CS-to-SCK Setup Time l5ns t H SCK-to-CS Setup Time l5ns t DS SDI Setup Time l5ns t DH SDI Hold Time l5nst DO SCK Falling to SDOValid Readback Mode,C SDO = 20pF, R PULLUP = 2kl125nsNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.Note 5: V DD = OV DD = 1.8V, f SAMPLE = 65MHz (L TC2192), 40MHz(L TC2191), or 25MHz (L TC2190), 2-lane output mode, differential ENC+/ENC– = 2V P-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted.Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band.Note 7: Offset error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode.Note 8: Guaranteed by design, not subject to test.Note 9: V DD = OV DD=1.8V, f SAMPLE = 65MHz (L TC2192),40MHz (L TC2191), or 25MHz (L TC2190), 2-lane output mode,ENC+ = single-ended 1.8V square wave, ENC– = 0V, input range = 2V P-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel.Note 10: Recommended operating conditions.Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps, so t SER must be greater than or equal to 1ns./6219210f7219210fTIMING DIAGRAMS4-Lane Output ModeANALOG INPUT ENC–ENC +DCO –FR –OUT#A –OUT#A +OUT#B –OUT#B +OUT#C –OUT#C +OUT#D –OUT#D+219210 TD01DCO +FR +2-Lane Output ModeANALOG INPUT ENC –ENC +DCO –FR +OUT#A –OUT#A +OUT#B –OUT#B +DCO +FR –OUT#C +, OUT#C –, OUT#D +, OUT#D – ARE DISABLED/8219210fTIMING DIAGRAMS1-Lane Output ModeANALOG INPUT ENC –ENC +DCO –FR +OUT#A –OUT#A +DCO +FR –OUT#B +, OUT#B –, OUT#C +, OUT#C –, OUT#D +, OUT#D –ARE DISABLEDCS SCKSDI SDOSPI Port Timing (Readback Mode)SPI Port Timing (Write Mode)219210 TD04CS SCKSDI SDOHIGH IMPEDANCE/9219210fTYPICAL PERFORMANCE CHARACTERISTICSL TC2192: 64k Point FFT ,f IN = 30MHz, –1dBFS, 65MspsL TC2192: 64k Point FFT ,f IN = 70MHz, –1dBFS, 65MspsL TC2192: 64k Point FFT ,f IN = 140MHz, –1dBFS, 65MspsL TC2192: 64k Point 2-Tone FFT , f IN = 69MHz, 70MHz, –7dBFS, 65MspsL TC2192: Shorted Input HistogramL TC2192: SNR vs Input Frequency, –1dBFS, 65Msps, 2V RangeL TC2192: Integral Nonlinearity (INL)L TC2192: Differential Nonlinearity (DNL)L TC2192: 64k Point FFT , f IN = 5MHz, –1dBFS, 65MspsOUTPUT CODE–4.0–3.0–2.0–1.0I N L E R R O R (L S B )01.04.03.02.016384327684915265536219210 G01OUTPUT CODE–1.0–0.4–0.2–0.6–0.8D N L E R R O R (L S B )00.40.20.60.81.0219210 G0216384327684915265536FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100219210 G03102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100219210 G04102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100219210 G05102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100219210 G06102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100102030219210G07OUTPUT CODE328311000030002000C O U N T4000500010000900080007000600032837328433284932855219210 G08INPUT FREQUENCY (MHz)0727170787776757473S N R (d B F S )50100150200250300219210 G09SINGLE-ENDED ENCODEDIFFERENTIAL ENCODE/10219210fTYPICAL PERFORMANCE CHARACTERISTICSL TC2192: I VDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each ChannelL TC2192: I OVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each InputL TC2192: SNR vs SENSE, f IN = 5MHz, –1dBFSL TC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 2V RangeL TC2192: SFDR vs Input Level, f IN = 70MHz, 65Msps, 2V RangeL TC2191: Integral Nonlinearity (INL)L TC2191: Differential Nonlinearity (DNL)L TC2191: 64k Point FFT , f IN = 5MHz, –1dBFS, 40MspsL TC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 1V RangeINPUT FREQUENCY (MHz)908580757065100952N D A N D 3R D H A R M O N I C (d B F S )219210 G10INPUT FREQUENCY (MHz)908580757065100952N D A N D 3R D H A R M O N I C (d B F S )219210 G11INPUT LEVEL (dBFS)–8060504030208070S F D R (d B c A N D d B F S )90100130120110–70–60–50–40–30–20–10219210 G12dBFSdBcSAMPLE RATE (Msps)060I V D D (m A )70809010011010203040219210 G135060SAMPLE RATE (Msps)5I O V D D (m A )25153545219210 G14SENSE PIN (V)0.6717072737877767574S N R (d B F S)0.70.80.9 1.1 1.2 1.31219210 G15OUTPUT CODE–4.0–3.0–2.0–1.0I N L E R R O R (L S B )01.04.03.02.016384327684915265536219210 G16–1.0–0.4–0.2–0.6–0.8D N L E R R O R (L S B )00.40.20.60.81.0219210 G17OUTPUT CODE16384327684915265536FREQUENCY (MHz)0–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–1001051520219210 G18/分销商库存信息:LINEAR-TECHNOLOGYLTC2191IUKG#PBF LTC2192CUKG#PBF LTC2192IUKG#PBF LTC2190CUKG#PBF LTC2190IUKG#PBF LTC2191CUKG#PBF LTC2190CUKG#TRPBF LTC2190IUKG#TRPBF LTC2191CUKG#TRPBF LTC2191IUKG#TRPBF LTC2192IUKG#TRPBF LTC2192CUKG#TRPBF DC1763A-D DC1763A-E DC1763A-F。

M16B开发板实验指导书v1.0

安全需知
为防止损坏您的 AVR 相关工具，避免您或他人受伤，在使用本开发套装前请仔细阅读下面的安全需知，并妥善保管以便所有本产品设备的使用者都可随时参阅。
请遵守本节中所列举的用以下符号所标注的各项预防措施，否则可能对产品造成损害。
该标记表示警告，提醒您应该在使用本产品前阅读这些信息，以防止可能发生的损害。
警告
请勿在易燃气体环境中使用电子设备，以避免发生爆炸或火灾。请勿在潮湿的环境中使用电子设备，以避免设备损坏。发生故障时立即拔下所有线缆。当您发现产品冒烟或发生异味时，请立刻拔下所有与其连接的线缆，切断电源，以避免燃烧。若在这种情况下还继续使用，可能会导致产品的进一步损坏，并使您受伤。请与我们联系后，将产品寄回给我们维修。请勿自行拆卸本产品触动产品内部的零件可能会导致受伤。遇到故障时，请及时联系我们。自行拆卸可能会导致其他意外事故发生。使用合适的电缆线若要将线缆连接到本设备的插座上，请使用本产品提供的线缆，以保证产品的规格的兼容性。请勿在儿童伸手可及之处保管本产品请特别注意防止婴幼儿玩耍或将产品的小部件放入口中。
M16B 开发板实验指导书
V1.0 – 2008-10-29
本资料由北京百纳信达科技有限公司编写、版权所有商标咨询 ATMEL 与 AVR 分别是 ATMEL CORPORATION 的注册商标和商标百纳信达、、分别是北京百纳信达科技有限公司的商标与域名
实验二 Mega16 IO 口作为输入使用 ................................................................................................... 3
【实验目的】 .............................................................................................................................................. 3 【实验设备】 .............................................................................................................................................. 3 【实验要求】 .............................................................................................................................................. 3 【实验原理】 .............................................................................................................................................. 3 【实验步骤】 .............................................................................................................................................. 4 【范例路径】 .............................................................................................................................................. 4 【思考练习】 .............................................................................................................................................. 5

DAP222MT2L;中文规格书,Datasheet资料

1.75±0.07
3.5±0.05
1.35±0.05 0
φ0.5±0.05 1.3±0.05 0 (4.0±0.1) 2.0±0.05
Absolute maximum ratings (Ta=25°C) Parameter Symbol Reverse voltage (repetitive peak) VRM VR Reverse voltage (DC) IFM Forward voltage (Single) Average rectified forward current (Single) Io Isurge Surge current (t=1us) Power dissipation Pd Junction temperature Tj Storage temperature Tstg
Data Sheet
Switching Diode
DAP222M
Applications Ultra high speed switching Dimensions (Unit : mm) Land size figure (Unit : mm)
0.8
0.32±0.05 0.13±0.05 (3)
ROHM Customer Support System
/contact/
© 2011 ROHM Co., Ltd. All 20A
/
分销商库存信息:
ROHM DAP222MT2L
0～0.1
5.5±0.2
Conditions
1/2
2011.06 - Rev.B
/
8.0±0.1
1.15
DAP222M
Data Sheet
100
Ta=75℃

PIC16F72T-IML;中文规格书,Datasheet资料

SSP MODULEThe PIC® microcontrollers you have received all exhibit anomalous behavior in their Synchronous Serial Port (SSP) modules, as described in this document. They otherwise conform functionally to the descriptions pro-vided in their respective Device Data Sheets and Ref-erence Manuals, as amended by silicon release errata for particular devices.Users are encouraged to review the latest device data sheets and errata available for additional information concerning an individual device. These documents may be obtained directly from the Microchip corporate web site, at .Silicon ErrataThese issues are expected to be resolved in future silicon revisions of the designated parts.The silicon issues identified in this “Silicon Errata” section affect all silicon revisions of the following devices:1.Module:I2C™ (Slave Mode)In its current implementation, the module may fail to correctly recognize certain Repeated Start conditions. For this discussion, a Repeated Start is defined as a Start condition presented to the bus after an initial valid Start condition has been recog-nized and the Start status bit (SSPSTAT<3>) has been set and before a valid Stop condition is received.I f a Repeated Start is not recognized, a loss ofsynchronization between the Master and Slave may occur; the condition may continue until the module is reset. A NACK condition, generated by the Slave for any reason, will not reset the module.This failure has been observed only under two circumstances:• A Repeated Start occurs within the frame of adata or address byte. The unexpected Startcondition may be erroneously interpreted as adata bit, provided that the required conditionsfor setup and hold times are met.• A Repeated Start condition occurs between twoback-to-back slave address matches in the1)in both cases. (This circumstance is regardedas being unlikely in normal operation.)Work aroundA time-out routine should be used to monitor themodule’s operation. The timer is enabled upon the receipt of a valid Start condition; if a time-out occurs, the module is reset. The length of the time-out period will vary from application to application and will need to be determined by the user.Two methods are suggested to reset the module:1.Change the mode of the module to somethingother than the desired mode by changing the set-tings of bits, SSPM3:SSPM0 (SSPCON<3:0>);then, change the bits back to the desiredconfiguration.2.Disable the module by clearing the SSPEN bit(SSPCON<5>); then, re-enable the module bysetting the bit.Other methods may be available.•PIC14000•PIC16C923•PIC16C62•PIC16C924•PIC16C62A•PIC16C925•PIC16C62B•PIC16C926•PIC16C63•PIC16CR62•PIC16C63A•PIC16CR63•PIC16C64•PIC16CR64•PIC16C64A•PIC16CR65•PIC16C65•PIC16CR72•PIC16C65A•PIC16CR72A•PIC16C65B•PIC16F72•PIC16C66•PIC16F73•PIC16C67•PIC16F74•PIC16C717•PIC16F76•PIC16C72•PIC16F77•PIC16C72A•PIC16F87•PIC16C73•PIC16F88•PIC16C73A•PIC16F818•PIC16C73B•PIC16F819•PIC16C74•PIC18F2331•PIC16C74A•PIC18F2431•PIC16C74B•PIC18F4331•PIC16C76•PIC18F4431•PIC16C77SSP Module Silicon/Data Sheet Errata© 2007 Microchip Technology Inc.DS80132F-page 1SSP MODULEDS80132F-page 2© 2007 Microchip Technology Inc.Clarifications/Corrections to the Data Sheets1.Module:SSP (SPI Mode)The description of the operation of the CKE bit (SSPSTAT<6>) is clarified. Please substitute the description in Register 1, below, for all occurrences of the existing text for the SSPSTAT register, bit 6 (new text in bold ). 2.Module:SSP (SPI Slave Mode)The description of the operation of SPI Slave mode is clarified as follows:Before enabling the module in SPI Slave mode, the state of the clock line (SCK) must match the polarity selected for the dle state. The clock line can be observed by reading the SCK pin. The polarity of the Idle state is determined by the CKP bit (SSPCON<4>).This foregoing text should be added to the appropriate subsections of the “SSP Module” chapter, entitled “SPI Mode” and read in context with any discussions of SPI Slave mode.n the case of DS30234D, the text applies to both implementations of SP I mode, as described in Sections 11.2 and 11.3.REGISTER 1:SSPSTAT: SSP STATUS REGISTER (EXCERPT)Note:This correction applies to the Data Sheets for the following devices:•PIC16C62B/72A (DS35008B)•PIC16C63A/65B/73B/74B (DS30605C)•PIC16C923/924 (DS30444E)•PIC16C925/926 (DS39544A)•PIC16F72 (DS39597B)•PIC16F73/74/76/77 (DS30325B)•PIC18F2331/2431/4331/4431 (DS39616B)In addition, this clarification applies only to the following devices in the P C16C6X Data Sheet (DS30234D):•PIC16C66•PIC16C67In addition, this clarification applies only to the following devices in the P C16C7X Data Sheet (DS30390E):•PIC16C76•PIC16C77Any devices not explicitly listed in this section do not implement SPI mode and are not affected by this clarification.Note:This text refers only to the operation of the CKE bit in SPI mode; its operation in I 2C mode is unchanged.Note:This correction applies to the Data Sheets for the following devices:•PIC16C6X (DS30234D), except PIC16C61 (does not implement the SSP module)•PIC16C62B/72A (DS35008B)•PIC16C63A/65B/73B/74B (DS30605C)•PIC16C72/73/73A/74/74A/76/77 (DS30390E)•PIC16C923/924 (DS30444E)•PIC16C925/926 (DS39544A)•PIC16F72 (DS39597B)•PIC16F73/74/76/77 (DS30325B)•PIC18F2331/2431/4331/4431 (DS39616B)Any other devices not explicitly listed in this section do not implement SPI mode and are not affected by this clarification.bit 6CKE: SPI Clock Edge Select bit1 =Transmit occurs on transition from active to Idle clock state 0 =Transmit occurs on transition from Idle to active clock state Note:Polarity of clock state is set by the CKP bit (SSPCON<4>).© 2007 Microchip Technology Inc.DS80132F-page 3SSP MODULE3.Module:SSP (I 2C Mode)The description of the I 2C pins related to the TRIS bits is clarified. To ensure proper communication of the I 2C Slave mode, the TRIS bits (TRISx [SDA,SCL]) corresponding to the I 2C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>) of the port con-taining the 2C pins (PORTx [SDA, SCL]) are changed in software during I 2C communication using a Read-Modify-Write instruction (BSF , BCF ),then the I 2C mode may stop functioning properly and 2C communication may suspend. Do not change any of the TRISx bits (TRIS bits of the port containing the I 2C pins) using the instruction BSF or BCF during I 2C communication. If it is absolutely necessary to change the TR I Sx bits during communication, the following method can be used:Note:This correction applies to the Data Sheets for the following devices:•PIC14000 (DS40122B)•PIC16C6X (DS30234D) exceptPIC16C61 (does not implement SSP module)•PIC16C62B/72A (DS35008B)•PIC16C63A/65B/73B/74B (DS30605C)•PIC16C72/73/73A/74/74A/76/77 (DS30390E)•PIC16C923/924 (DS30444E)•PIC16C925/926 (DS39544A)•PIC16F72 (DS39597B)•PIC16F73/74/76/77 (DS30325B)MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F73IORLW 0x18; Ensures <4:3> bits are ‘11’ANDLW B’11111001’; Sets <2:1> as output, but will not alter other bits; User can use their own logic here, such as IORLW, XORLW and ANDLWMOVWFTRISCSSP MODULEREVISION HISTORYRevision A Document (7/2002):Original version (I2C Slave Issue).Revision B Document (1/2003):Clarification of original issue to include Restartconditions. Addition of data sheet clarification 1 (SPIMode, CKE bit).Revision C Document (3/2003):Addition of data sheet clarification 2 (SPI Slave Mode,operation).Revision D Document (9/2004):Updated list of affected devices for silicon issue 1 (I2C– Slave Mode) and 2 (SSP – SP, Slave Mode),removed silicon issue 3 (I2C – Slave Mode). Updatedlist of affected devices for data sheet clarification 1(SSP – SPI Mode) and 2 (SSP – SPI Slave Mode).Added data sheet clarification 3 (SSP – I2C Mode).Revision E Document (7/2006):Removed silicon issue 2 (SSP – SPI Slave Mode).Revision F Document (2/2007):Added four devices to list of devices affected by thesilicon errata and clarified the related language.DS80132F-page 4© 2007 Microchip Technology Inc.© 2007 Microchip Technology Inc.DS80132F-page 5I nformation contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.M I CROCH I P MAKES NO REPRESENTAT I ONS OR WARRANT ES OF ANY K ND WHETHER EXPRESS OR I MPL I ED, WR I TTEN OR ORAL, STATUTORY OR OTHERW I SE, RELATED TO THE I NFORMAT I ON,I NCLUD I NG BUT NOT L I M I TED TO I TS COND I T I ON,QUAL I TY , PERFORMANCE, MERCHANTAB I L I TY OR F TNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron,dsPIC, K EE L OQ , K EE L OQ logo, micro ID , MPLAB, PIC,PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company areregistered trademarks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, , dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,In-Circuit Serial Programming, ICSP , ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, , PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, TotalEndurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC ® DSCs, K EE L OQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analogproducts. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.AMERICASCorporate Office2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200Fax: 480-792-7277 Technical Support: Web Address: AtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088 ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260 KokomoKokomo, INTel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Santa ClaraSanta Clara, CATel: 408-961-6444Fax: 408-961-6445 TorontoMississauga, Ontario, CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHabour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - FuzhouTel: 86-591-8750-3506Fax: 86-591-8750-3521China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - ShundeTel: 86-757-2839-5507Fax: 86-757-2839-5571China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XianTel: 86-29-8833-7250Fax: 86-29-8833-7256ASIA/PACIFICIndia - BangaloreTel: 91-80-4182-8400Fax: 91-80-4182-8422India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - GumiTel: 82-54-473-4301Fax: 82-54-473-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - PenangTel: 60-4-646-8870Fax: 60-4-646-5086Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-572-9526Fax: 886-3-572-6459Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820 W ORLDWIDE S ALES AND S ERVICE12/08/06DS80132F-page 6© 2007 Microchip Technology Inc.分销商库存信息: MICROCHIPPIC16F72T-I/ML。

RPI-222;中文规格书,Datasheet资料

Electrical and optical characteristics (T a =25°C )Electrical and optical characteristics curvesExternal dimensions (Unit : mm)Fig.1 Relative output current vs.distance ( )R E L A T I V E C O L L E C T O R C U R R E N T : I c (%)DISTANCE : d (mm)Fig.4 Relative output current vs.distance ( )R E L A T I V E C O L L E C T O R C U R R E N T : I c (%)DISTANCE : d (mm)Fig.2 Forward current falloffF O R W A R D C U R R E N T : I F (m A )AMBIENT TEMPERATURE : Ta (°C)10504030200Fig.10 Output characteristics C O L L E C T O R C U R R E N T : I c (m A )COLLECTOR TO EMITTER VOLTAGE : V CE (V)t d : Delay timet r : Rise time (time for output current to risefrom 10% to 90% of peak current)t f : Fall time (time for output current to fallfrom 90% to 10% of peak current)Fig.11 Response time measurement circuitFig.8 Response time vs.collector currentR E S P O N S E T I M E : t (µs )COLLECTOR CURRENT : Ic (mA)Fig.9 Dark current vs.ambient temperatureD A R K C U R RE N T : I D (n A )AMBIENT TEMPERATURE : Ta (°C)Fig.6 Relative output vs. ambienttemperatureR E L A T I V E C O L L E C T O R C U R R E N T : I c (%)AMBIENT TEMPERATURE : Ta (°C)020406080100120160140Fig.7 Collector current vs.forward currentC O L L E C T O R C U R R E N T : I c (m A )FORWARD CURRENT : I F (mA )0102030405001.02.0FORWARD VOLTAGE : V F (V ) F O R W A R D C U R R E N T : I F (m A )Fig.3 Forward current vs. forwardvoltage P O W E R D I S S I P A T I O N / C O L L E C T O R P O W E R D I S S I P A T I O N : P D / P c (m W )AMBIENT TEMPERATURE : Ta (°C)Fig.5 Power dissipation / collector powerdissipation vs. ambient temperature −20020P D P C40608010020406080100120AppendixAbout Export Control Order in JapanProducts described herein are the objects of controlled goods in Annex 1 (Item 16) of Export T rade ControlOrder in Japan.In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.Appendix1-Rev1.1 /分销商库存信息: ROHMRPI-222。

LTC3577EUFF-4#PBF;LTC3577EUFF-3#TRPBF;LTC3577EUFF-4#TRPBF;LTC3577EUFF-3#PBF;中文规格书,Datasheet资料

1357734fbT YPICAL APPLICATIONF EATURESA PPLICATIONS DESCRIPTION Portable Product PMIC nFull Featured Li-Ion/Polymer Charger/PowerPath™ Controller with Instant-On Operation n T riple Adjustable High Efﬁ ciency Step-DownSwitching Regulators (800mA, 500mA, 500mA I OUT ) n I 2C Adjustable SW Slew Rates for EMI Reduction n High Temperature Battery Voltage Reduction Improves Safety and Reliabilityn Overvoltage Protection Controller for USB (V BUS )/Wall Inputs Provide Protection to 30Vn Integrated 40V Series LED Back Light Driver with 60dB Brightness Control and Gradation via I 2Cn 1.5A Maximum Charge Current with Thermal Limiting n Battery Float Voltage: 4.2V (L TC3577-3) 4.1V (L TC3577-4)n Pushbutton ON/OFF Control with System Reset n Dual 150mA Current Limited LDOsn Start-Up Timing Compatible with SiRF Atlas IV Processor n Small 4mm × 7mm 44-Pin QFN PackagenPNDs, DMB/DVB-H, Digital/Satellite Radio, Media Playersn Portable Industrial/Medical Products n Other USB-Based Handheld ProductsThe L TC ®3577-3/L TC3577-4 are highly integrated power management ICs for single cell Li-Ion/Polymer battery ap-plications. It includes a PowerPath manager with automatic load prioritization, a battery charger , an ideal diode, input overvoltage protection and numerous other internal pro-tection features. The L TC3577-3/L TC3577-4 are designed to accurately charge from current limited supplies such as USB by automatically reducing charge current such that the sum of the load current and the charge current does not exceed the programmed input current limit (100mA or 500mA modes). The L TC3577-3/L TC3577-4 reduce the bat-tery voltage at elevated temperatures to improve safety and reliability. The three step-down switching regulators and two LDOs provide a wide range of available supplies. The L TC3577-3/L TC3577-4 also include a pushbutton input to control power sequencing and system reset. The onboard LED backlight boost circuitry can drive up to 10 series LEDs and includes versatile digital dimming via the I 2C input. The L TC3577-3/L TC3577-4 are designed to support the SiRF Atlas IV processor and has pushbutton timing and sequencing different from other L TC3577 versions. The L TC3577-3/L TC3577-4 are available in a low proﬁ le 4mm × 7mm × 0.75mm 44-pin QFN package.L , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6522118, 6700364, 7511390, 5481178, 6580258. Other patents pending.LED Driver Efﬁ ciency (10 LEDs)5V ADAPTERLED CURRENT (mA)20E F F I C I E N C Y (%)305060809010001001010.10.01357734 TA01b1070400/TABLE OF CONTENTSFeatures (1)Applications (1)Typical Application (1)Description (1)Absolute Maximum Ratings (3)Order Information (3)Pin Conﬁ guration (3)Electrical Characteristics (4)Typical Performance Characteristics (10)Pin Functions (16)Block Diagram (19)Operation (20)PowerPath OPERATION (20)Low Dropout Linear Regulator Operation (28)Step-Down Switching Regulator Operation (29)LED Backlight/Boost Operation (33)I2C Operation (37)Pushbutton Interface Operation (42)Layout and Thermal Considerations (46)Typical Applications (48)Package Description (50)Related Parts (51)2357734fb/3357734fbP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS V SW ............................................................–0.3V to 45V V BUS , V OUT , V IN12, V IN3, V INLDO1, V INLDO2, WALL t < 1ms and Duty Cycle < 1% ...................–0.3V to 7V Steady State ............................................–0.3V to 6V CHRG , BAT, LED_FS, LED_OV,PWR_ON, EXTPWR , PBSTAT, PGOOD, FB1, FB2, FB3, LDO1, LDO1_FB, LDO2,LDO2_FB, DV CC , SCL, SDA, EN3 .................–0.3V to 6V NTC, PROG, CLPROG, ON , I LIM0, I LIM1 (Note 4) ...........................................–0.3V to V CC + 0.3V I VBUS , I VOUT , I BAT , Continuous (Note 16) .....................2AI SW3, Continuous (Note 16).................................850mA I SW2, I SW1, Continuous (Note 16)........................600mA I LDO1, I LDO2, Continuous (Note 16) .....................200mA I CHRG , I ACPR , I EXTPWR , I PBSTAT , I PGOOD ...................75mA I OVSENS ..................................................................10mA I CLPROG , I PROG , I LED_FS , I LED_OV ..............................2mA Maximum Junction Temperature ...........................110°C Operating Temperature Range .................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C(Notes 1, 2, 3)TOP VIEW 45GNDUFF PACKAGE44-LEAD (7mm s 4mm) PLASTIC QFNI LIM01I LIM1 2LED_FS 3WALL 4SW3 5V IN3 6FB3 7OVSENS 8LED_OV 9DV CC 10SDA 11SCL 12OVGATE 13PWR_ON 14ON 1537 IDGATE 36 PROG 35 NTC 34 NTCBIAS 33 SW132 V IN1231 SW230 V INLD0229 LDO228 LDO127 V INLDO126 FB125 FB224 LDO2_FB 23 LDO1_FBP B S T A T 16E N 317S W 18S W 19S W 20P G O O D 21I L E D 2244C H R G43 C L P R O G 42E X T P W R 41A C P R 40 V B U S39 V O U T 38 B A TT JMAX = 110°C, θJA = 45°C/WEXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC3577EUFF-3#PBF L TC3577EUFF-3#TRPBF 3577344-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C L TC3577EUFF-4#PBFL TC3577EUFF-4#TRPBF3577444-Lead (4mm × 7mm) Plastic QFN–40°C to 85°CConsult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based ﬁ nish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel//E LECTRICAL CHARACTERISTICS Power Manager. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V BUS = 5V, V BAT = 3.8V, I LIM0 = I LIM1 = 5V, WALL = 0V,V INLDO2 = V INLOD1 = V IN12 = V IN3 = V OUT, R PROG = 2k, R CLPROG = 2.1k, unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Power SupplyV BUS Input Supply Voltage 4.35 5.5VI BUS_LIM Total Input Current (Note 5)I LIM0 = 5V, I LIM1 = 5V (1x Mode)I LIM0 = 0V, I LIM1 = 0V (5x Mode)I LIM0 = 0V, I LIM1 = 5V (10x Mode)lll80450900904759501005001000mAmAmAI BUSQ Input Quiescent Current, POFF State1x, 5x, 10x ModesI LIM0 = 5V, I LIM1 = 0V (Suspend Mode)0.420.050.1mAmAh CLPROG Ratio of Measured V BUS Current toCLPROG Program Current1000mA/mAV CLPROG CLPROG Servo Voltage in CurrentLimit 1x Mode5x Mode10x Mode0.21.02.0VVVV UVLO V BUS Undervoltage Lockout Rising ThresholdFalling Threshold 3.53.83.73.9VVV DUVLO V BUS to V OUT Differential UndervoltageLockout Rising ThresholdFalling Threshold50–50100mVmVR ON_ILIM Input Current Limit Power FET On-Resistance (Between V BUS and V OUT)200mΩBattery ChargerV FLOAT V BAT Regulated Output Voltage L TC3577-3L TC3577-3, 0 ≤ T A≤ 85°C 4.1794.1654.2004.2004.2214.235VVL TC3577-4L TC3577-4, 0 ≤ T A≤ 85°C 4.0794.0654.14.14.1214.135VVI CHG Constant-Current Mode Charge CurrentIC Not in Thermal Limit R PROG = 1k, Input Current Limit = 2AR PROG = 2k, Input Current Limit = 1AR PROG = 5k, Input Current Limit = 0.4Alll95046518010005002001050535220mAmAmAI BATQ_OFF Battery Drain Current, POFF State,Buck3 Disabled, No Load (Note 15)V BAT = 4.3V, Charger Time OutV BUS = 0V65527100μAμAI BATQ_ON Battery Drain Current, PON State,Buck3 Enabled (Notes 10, 15)V BUS = 0V, I OUT = 0μA, No Load OnSupplies, Burst Mode Operation130200μAV PROG,CHG PROG Pin Servo Voltage V BAT > V TRKL 1.000V V PROG,TRKL PROG Pin Servo Voltage in T rickleChargeV BAT < V TRKL0.100V h PROG Ratio of I BAT to PROG Pin Current1000mA/mA I TRKL T rickle Charge Current V BAT < V TRKL405060mAV TRKL T rickle Charge Rising ThresholdT rickle Charge Falling Threshold V BAT RisingV BAT Falling 2.52.92.753.0VVΔV RECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to V FLOAT–75–100–125mV t TERM Safety Timer Termination Period Timer Starts when V BAT = V FLOAT – 50mV 3.24 4.8Hour t BADBAT Bad Battery Termination Time V BAT < V TRKL0.40.50.6Hourh C/10End-of-Charge Indication Current Ratio(Note 6)0.0850.10.11mA/mAR ON_CHG Battery Charger Power FET On-Resistance (Between V OUT and BAT)200mΩT LIM Junction Temperature in ConstantTemperature Mode110°C /4357734fbPower Manager. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V BUS = 5V, V BAT = 3.8V, I LIM0 = I LIM1 = 5V, WALL = 0V,V INLDO2 = V INLOD1 = V IN12 = V IN3 = V OUT, R PROG = 2k, R CLPROG = 2.1k, unless otherwise noted.E LECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NTC, Battery Discharge ProtectionV COLD Cold Temperature Fault ThresholdVoltage Rising NTC VoltageHysteresis75761.377%V NTCBIAS%V NTCBIASV HOT Hot Temperature Fault ThresholdVoltage Falling NTC VoltageHysteresis34351.336%V NTCBIAS%V NTCBIASV TOO_HOT NTC Discharge Threshold Voltage Falling NTC VoltageHysteresis 24.525.55026.5%V NTCBIASmVI NTC NTC Leakage Current V NTC = V BUS = 5V–5050nA I BAT2HOT BAT Discharge Current V BAT = 4.1V, NTC < V TOO_HOT170mA V BAT2HOT BAT Discharge Threshold I BAT < 0.1mA, NTC < V TOO_HOT 3.9V Ideal DiodeV FWD Forward Voltage Detection I OUT = 10mA51525mV R DROPOUT Diode On-Resistance, Dropout I OUT = 200mA200mΩI MAX Diode Current Limit(Note 7) 3.6A Overvoltage ProtectionV OVCUTOFF Overvoltage Protection Threshold Rising Threshold, R OVSENS = 6.2k 6.10 6.35 6.70VV OVGATE OVGATE Output Voltage Input Below V OVCUTOFFInput Above V OVCUTOFF 1.88 • V OVSENS 12VVI OVSENSQ OVSENS Quiescent Current V OVSENS = 5V40μA t RISE OVGATE Time to Reach Regulation C OVGATE = 1nF 2.5ms Wall Adapter and High Voltage Buck Output ControlV ACPR ACPR Pin Output High VoltageACPR Pin Output Low Voltage I ACPR = 0.1mAI ACPR = 1mAV OUT – 0.3 V OUT00.3VVV W Absolute Wall Input Threshold Voltage V WALL RisingV WALL Falling 3.14.33.24.45VVΔV W Differential Wall Input ThresholdVoltage V WALL – V BAT FallingV WALL – V BAT Rising02575100mVmVI QWALL Wall Operating Quiescent Current I WALL + I VOUT , I BAT = 0mA,WALL = V OUT = 5V440μA Logic (I LIM0, I LIM1 and CHRG)V IL Input Low Voltage I LIM0, I LIM10.4V V IH Input High Voltage I LIM0, I LIM1 1.2VI PD Static Pull-Down Current I LIM0, I LIM1; V PIN = 1V2μAV CHRG CHRG Pin Output Low Voltage I CHRG = 10mA0.150.4VI CHRG CHRG Pin Input Current V BAT = 4.5V, V CHRG = 5V01μA /5357734fbE LECTRICAL CHARACTERISTICS I2C Interface. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. DV CC = 3.3V, V OUT = 3.8V, unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DV CC Input Supply Voltage 1.6 5.5VI DVCC DV CC Supply Current SCL = 400kHzSCL = SDA = 0kHz 101μAμAV DVCC,UVLO DV CC UVLO 1.0V V IH Input HIGH Voltage5070%DV CC V IL Input LOW Voltage3050%DV CC I IH Input HIGH Leakage Current SDA = SCL = DV CC = 5.5V–11μA I IL Input LOW Leakage Current SDA = SCL = 0V, DV CC = 5.5V–11μA V OL SDA Output LOW Voltage I SDA = 3mA0.4V Timing Characteristics (Note 8) (All Values are Referenced to V IH and V IL)f SCL SCL Clock Frequency400kHz t LOW LOW Period of the SCL Clock 1.3μs t HIGH HIGH Period of the SCL Clock0.6μs t BUF Bus Free Time Between Stop and Start Condition 1.3μs t HD,STA Hold Time After (Repeated) Start Condition0.6μs t SU,STA Setup Time for a Repeated Start Condition0.6μs t SU,STO Stop Condition Setup Time0.6μs t HD,DATO Output Data Hold Time 0900ns t HD,DATI Input Data Hold Time0ns t SU,DAT Data Setup Time100ns t SP Input Spike Suppression Pulse Width50nsLED Boost Switching Regulator. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN3 = V OUT = 3.8V, R OV = 10M, R LED_FS = 20k, boost regulator disabled unlessotherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN3, V OUT Operating Supply Range(Note 9)l 2.7 5.5VI VOUT_LED Operating Quiescent CurrentShutdown Quiescent Current (Notes 10, 14)5600.01μAμAV LED_OV LED Overvoltage Threshold LED_OV RisingLED_OV Falling0.61.00.851.25VVI LIM Peak NMOS Switch Current80010001200mAI LED(FS)I LED Pin Full-Scale Operating Current182022mAI LED(DIM)I LED Pin Full-Scale Dimming Range64 Steps60dBR NSWON R DS(ON) of NMOS Switch240mΩI NSWOFF NMOS Switch Off Leakage Current V SW = 5.5V0.011μAf OSC Oscillator Frequency0.95 1.125 1.3MHzV LED_FS LED_FS Pin Voltage l780800820mVI LED_OV LED_OV Pin Current l 3.84 4.2μAD BOOST Maximum Duty Cycle I LED = 097%V BOOSTFB Boost Mode Feedback Voltage l775800825mV /6357734fbE LECTRICAL CHARACTERISTICS Step-Down Switching Regulators. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V OUT = V IN12 = V IN3 = 3.8V, all regulators enabled unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Step-Down Switching Regulators (Buck1, Buck2 and Buck3)V IN12, V IN3Input Supply Voltage(Note 9)l 2.7 5.5VV OUT UVLO V OUT FallingV OUT Rising V IN12 and V IN3 Connected to V OUT ThroughLow Impedance. Switching Regulators areDisabled Below V OUT UVLO2.5 2.72.8 2.9VVf OSC Oscillator Frequency 1.91 2.25 2.59MHz 800mA Step-Down Switching Regulator 3 (Buck3-Enabled via EN3, Disabled in PON and POFF States)I VIN3Q Pulse-Skipping Mode Input Current (Note 10)100μABurst Mode Operation Input Current(Note 10)2035μAShutdown Input Current EN3 = 00.011μA I LIM3Peak PMOS Current Limit(Note 7)100014001700mAV FB3Feedback Voltage Pulse-Skipping ModeBurst Mode Operation ll0.780.780.80.80.820.824VVI FB3FB3 Input Current(Note 10)–0.050.05μA D3Max Duty Cycle FB3 = 0V100% R P3R DS(ON) of PMOS0.3ΩR N3R DS(ON) of NMOS0.4ΩR SW3_PD SW3 Pull-Down in Shutdown EN3 = 010kΩV IL,EN3EN3 Input Low Voltage0.4V V IH,EN3EN3 Input High Voltage 1.2V 500mA Step-Down Switching Regulator 2 (Buck2-Pushbutton Enabled, Third in Sequence)I VIN12Q Pulse-Skipping Mode Input Current (Note 10)100μABurst Mode Operation Input Current(Note 10)20μAShutdown Input Current POFF State0.011μA I LIM2Peak PMOS Current Limit(Note 7)6509001200mAV FB2Feedback Voltage Pulse-Skipping ModeBurst Mode Operation ll0.780.780.80.80.820.824VVI FB2FB2 Input Current(Note 10)–0.050.05μA D2Max Duty Cycle FB2 = 0V100% R P2R DS(ON) of PMOS I SW2 = 100mA 0.6ΩR N2R DS(ON) of NMOS I SW2 = –100mA0.6ΩR SW2_PD SW2 Pull-Down in Shutdown POFF State10kΩ500mA Step-Down Switching Regulator 1 (Buck1-Pushbutton Enabled, Second in Sequence)I VIN12Q Pulse-Skipping Mode Input Current (Note 10)100μABurst Mode Operation Input Current(Note 10)20μAShutdown Input Current0.011μA I LIM1Peak PMOS Current Limit(Note 7)6509001200mAV FB1Feedback Voltage Pulse-Skipping ModeBurst Mode Operation ll0.780.780.80.80.820.824VVI FB1FB1 Input Current(Note 10)–0.050.05μAD1Max Duty Cycle FB1 = 0V100% R P1R DS(ON) of PMOS I SW1 = 100mA 0.6ΩR N1R DS(ON) of NMOS I SW1 = –100mA0.6ΩR SW1_PD SW1 Pull-Down in Shutdown POFF State10kΩ/7357734fbE LECTRICAL CHARACTERISTICS LDO Regulators. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V INLDO1 = V INLDO2 = V OUT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LDO Regulator 1 (LDO1-Always On)V INLDO1Input Voltage Range V INLDO1 ≤ V OUT + 0.3V l 1.65 5.5VV OUT_UVLO V OUT FallingV OUT Rising LDO1 is Disabled Below V OUT UVLO 2.5 2.72.8 2.9VVV LDO1_FB LDO1_FB Regulated Feedback Voltage I LDO1 = 1mA l0.780.80.82V LDO1_FB Line Regulation (Note 11)I LDO1 = 1mA, V IN = 1.65V to 5.5V0.4mV/V LDO1_FB Load Regulation (Note 11)I LDO1 = 1mA to 150mA5μV/mA I LDO1_OC Available Output Current l150mA I LDO1_SC Short-Circuit Output Current270mAV DROP1Dropout Voltage (Note 12)I LDO1 = 150mA, V INLDO1 = 3.6VI LDO1 = 150mA, V INLDO1 = 2.5VI LDO1 = 75mA, V INLDO1 = 1.8V 160200170260320280mVmVmVR LDO1_PD Output Pull-Down Resistance in Shutdown LDO1 Disabled10kΩI LDO_FB1LDO_FB1 Input Current–5050nA LDO Regulator 2 (LDO2-Pushbutton Enabled, First in Sequence)V INLDO2Input Voltage Range V INLDO2 ≤ V OUT + 0.3V l 1.65 5.5VV OUT_UVLO V OUT FallingV OUT Rising LDO2 is Disabled Below V OUT UVLO 2.5 2.72.8 2.9VVV LDO2_FB LDO2_FB Regulated Output Voltage I LDO2 = 1mA l0.780.80.82V LDO2_FB Line Regulation (Note 11)I LDO2 = 1mA, V IN = 1.65V to 5.5V0.4mV/V LDO2_FB Load Regulation (Note 11)I LDO2 = 1mA to 150mA5μV/mA I LDO2_OC Available Output Current l150mA I LDO2_SC Short-Circuit Output Current270mAV DROP2Dropout Voltage (Note 12)I LDO2 = 150mA, V INLDO2 = 3.6VI LDO2 = 150mA, V INLDO2 = 2.5VI LDO1 = 75mA, V INLDO1 = 1.8V 160200170260320280mVmVmVR LDO2_PD Output Pull-Down Resistance in Shutdown LDO2 Disabled14kΩI LDO_FB2LDO_FB2 Input Current–5050nA /8357734fbE LECTRICAL CHARACTERISTICS Pushbutton Controller. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V OUT = 3.8V, unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Pushbutton Pin (ON)V OUT Pushbutton Operating Supply Range(Note 9)l 2.7 5.5VV OUT UVLO V OUT FallingV OUT Rising Pushbutton is Disabled Below V OUT UVLO 2.5 2.72.8 2.9VVV ON_TH ON Threshold RisingON Threshold Falling0.40.80.71.2VVI ON ON Input Current V ON = V OUTV ON = 0V –1–4–91–14μAμAPower-On Input Pin (PWR_ON)V PWR_ON PWR_ON Threshold RisingPWR_ON Threshold Falling0.40.80.71.2VVI PWR_ON PWR_ON Input Current V PWR_ON = 3V–11μA Status Output Pins (PBSTAT, EXTPWR, PGOOD)I PBSTAT PBSTAT Output High Leakage Current V PBSTAT = 3V–11μA V PBSTAT PBSTAT Output Low Voltage I PBSTAT = 3mA0.10.4V I EXTPWR EXTPWR Pin Input Current V EXTPWR = 3V01μA V EXTPWR EXTPWR Pin Output Low Voltage I EXTPWR = 2mA0.150.4V I PGOOD PGOOD Output High Leakage Current V PGOOD = 3V–11μA V PGOOD PGOOD Output Low Voltage I PGOOD = 3mA0.10.4V V THPGOOD PGOOD Threshold Voltage(Note 13)–8% Pushbutton Timing Parameterst ON_PBSTAT1ON Low Time to PBSTAT Low 50ms t ON_PBSTAT2ON High to PBSTAT High PBSTAT Low > t PBSTAT_PW900μs t PBSTAT_PW PBSTAT Minimum Pulse Width4050ms t ON_PUP ON Low Time for Power-Up50ms t ON_RST ON Low to PGOOD Reset Low121416.5Seconds t ON_RST_PW PGOOD Reset Low Pulse Width 1.8ms t PUP_PDN Minimum Time from Power Up to Down1Seconds t PDN_PUP Minimum Time from Power Down to Up1Seconds t PWR_ONH PWR_ON High to Power-Up50ms t PWR_ONL PWR_ON Low to Power-Down50ms t PWR_ONBK1PWR_ON Power-Up Blanking PWR_ON Low Recognized from Power-Up1Seconds t PWR_ONBK2PWR_ON Power-Down Blanking PWR_ON High Recognized from Power-Down1Seconds t PGOODH From Regulation to PGOOD High Buck1, 2 and LDO1 Within PGOOD Threshold230ms t PGOODL Bucks Disabled to PGOOD Low Bucks Disabled44μs t LDO2_BK1LDO2 Enable to Buck Enable12.514.517.5msNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L TC3577-3/L TC3577-4 are guaranteed to meet performance speciﬁ cations from 0°C to 85°C. Speciﬁ cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 3: This IC includes over temperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 110°C when over temperature protection is active. Continuous operation above the speciﬁ ed maximum operating junction temperature may result in device degradation or failure. Note 4: V CC is the greater of V BUS, V OUT or BAT.Note 5: Total input current is the sum of quiescent current, I BUSQ, and measured current given by V CLPROG/R CLPROG • (h CLPROG + 1)./9357734fb10357734fbT YPICAL PERFORMANCE CHARACTERISTICS Input Supply Currentvs TemperatureInput Supply Currentvs Temperature (Suspend Mode)Battery Drain Current vs TemperatureInput Current Limit vs TemperatureInput R ON vs TemperatureCharge Current vs Temperature (Thermal Regulation)E LECTRICAL CHARACTERISTICS Note 6: h C/10 is expressed as a fraction of measured full charge current with indicated PROG resistor .Note 7: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions. Continuous operation above the maximum speciﬁ ed pin current rating may result in device degradation or failure.Note 8: The serial port is tested at rated operating frequency. Timing parameters are tested and/or guaranteed by design.Note 9: V OUT not in UVLO.Note 10: Buck FB high, not switching.Note 11: Measured with the LDO running unity gain with output tied to feedback pin.Note 12: Dropout voltage is the minimum input to output voltage differential needed for an LDO to maintain regulation at a speciﬁ ed output current. When an LDO is in dropout, its output voltage will be equal to V IN – V DROP .Note 13: PGOOD threshold is expressed as a percentage difference from the Buck1, Buck2 and LDO1 regulation voltages. The threshold is measured from Buck1, Buck2 and LDO1 output rising.Note 14: I VOUT_LED is the sum of V OUT and V IN3 current due to LED driver .Note 15: The I BATQ speciﬁ cations represent the total battery load assuming V INLDO1, V INLDO2, V IN12 and V IN3 are tied directly to V OUT .Note 16: Long-term current density rating for the part.TEMPERATURE (°C)–50I V B U S (m A )0.725357734 G010.40.2–25500.100.80.60.50.375100125T A = 25°C unless otherwise speciﬁ ed TEMPERATURE (°C)–50–250I V B U S (m A )0.040.1005075357734 G020.020.080.0625100125TEMPERATURE (°C)–50I V B U S (m A )40010001100120005075357734 G042001008006003009000700500–2525100125TEMPERATURE (°C)–500R O N (m Ω)10014016018030024005075357734 G05120260280220–2525100125TEMPERATURE (°C)–50I B A T (m A )4005006002575357734 G06300200–2550100125100TEMPERATURE (°C)–500I B A T (μA )5015020025045035005075357734 G03100400300–2525100125/分销商库存信息:LINEAR-TECHNOLOGYLTC3577EUFF-4#PBF LTC3577EUFF-3#TRPBF LTC3577EUFF-4#TRPBF LTC3577EUFF-3#PBF。

FTE-120-01-G-DV-ES-A-P-TR;FTE-113-01-G-DV-A;FTE-136-01-G-DV-A;中文规格书,Datasheet资料

Choiceof post heightsSurfaceMount FTE–155–01–G–DVFTE–130–01–G–DV–ESOptional分销商库存信息:SAMTECFTE-190-01-G-DH FTE-107-02-G-DV FTE-120-01-G-DV-ES-A-P-TRFTE-113-01-G-DV-A FTE-136-01-G-DV-A FTE-136-03-G-DV-AFTE-190-01-G-DV FTE-103-01-G-DV FTE-101-01-G-DHFTE-102-01-G-DH FTE-105-01-G-DV FTE-106-01-G-DVFTE-103-01-G-DH FTE-107-01-G-DV FTE-104-01-G-DHFTE-108-01-G-DV FTE-105-01-G-DH FTE-109-01-G-DVFTE-106-01-G-DH FTE-110-01-G-DV FTE-111-01-G-DVFTE-107-01-G-DH FTE-112-01-G-DV FTE-108-01-G-DHFTE-113-01-G-DV FTE-109-01-G-DH FTE-114-01-G-DVFTE-115-01-G-DV FTE-110-01-G-DH FTE-116-01-G-DVFTE-111-01-G-DH FTE-117-01-G-DV FTE-112-01-G-DHFTE-118-01-G-DV FTE-119-01-G-DV FTE-113-01-G-DHFTE-120-01-G-DV FTE-114-01-G-DH FTE-121-01-G-DVFTE-115-01-G-DH FTE-122-01-G-DV FTE-123-01-G-DVFTE-116-01-G-DH FTE-124-01-G-DV FTE-117-01-G-DHFTE-125-01-G-DV FTE-118-01-G-DH FTE-126-01-G-DVFTE-127-01-G-DV FTE-119-01-G-DH FTE-128-01-G-DVFTE-120-01-G-DH FTE-129-01-G-DV FTE-121-01-G-DHFTE-130-01-G-DV FTE-131-01-G-DV FTE-122-01-G-DHFTE-132-01-G-DV FTE-123-01-G-DH FTE-133-01-G-DVFTE-124-01-G-DH FTE-134-01-G-DV FTE-135-01-G-DVFTE-125-01-G-DH FTE-136-01-G-DV FTE-126-01-G-DHFTE-137-01-G-DV FTE-127-01-G-DH FTE-138-01-G-DVFTE-139-01-G-DV FTE-128-01-G-DH FTE-140-01-G-DVFTE-129-01-G-DH FTE-141-01-G-DV FTE-130-01-G-DHFTE-142-01-G-DV FTE-143-01-G-DV FTE-131-01-G-DHFTE-144-01-G-DV FTE-132-01-G-DH FTE-145-01-G-DVFTE-133-01-G-DH FTE-146-01-G-DV FTE-147-01-G-DVFTE-134-01-G-DH FTE-148-01-G-DV FTE-135-01-G-DHFTE-149-01-G-DV FTE-136-01-G-DH FTE-150-01-G-DVFTE-151-01-G-DV FTE-137-01-G-DH FTE-152-01-G-DVFTE-138-01-G-DH FTE-153-01-G-DV FTE-139-01-G-DHFTE-154-01-G-DV FTE-140-01-G-DH FTE-155-01-G-DVFTE-156-01-G-DV FTE-141-01-G-DH FTE-157-01-G-DVFTE-142-01-G-DH FTE-158-01-G-DV FTE-143-01-G-DHFTE-159-01-G-DV FTE-160-01-G-DV FTE-144-01-G-DHFTE-161-01-G-DV FTE-145-01-G-DH FTE-162-01-G-DVFTE-146-01-G-DH FTE-163-01-G-DV FTE-164-01-G-DVFTE-147-01-G-DH FTE-165-01-G-DV FTE-148-01-G-DHFTE-166-01-G-DV FTE-149-01-G-DH FTE-167-01-G-DVFTE-168-01-G-DV FTE-150-01-G-DH FTE-169-01-G-DV。

BA2和BPA板的技术参数参见表

4.21.6 技术参数BA2和BPA板的技术参数参见表4-69。

表4-69 BA2和BPA板的技术参数注意：BPA前置放大做环回时，注意输入光功率的范围，避免损伤光模块。

12.2 BPA本节介绍BPA（1路功率放大和1路前置放大板）的版本、功能、原理、面板及技术指标等。

∙12.2.1 版本描述BPA单板的功能版本为N1。

∙12.2.2 功能和特性光信号进行长距离传输时，信号衰耗较多，为使光接收机接收到正常的光信号，需要加光功率放大板（BA）和前置放大板（PA）。

∙12.2.3 工作原理和信号流BPA单板由光学部分、驱动与检测部分、数据处理与通信部分构成。

∙12.2.4 面板BPA单板的面板上有单板指示灯和接口。

∙12.2.5 可插放槽位BPA单板可以插在子架的slot 1～8、11～18、26～31。

∙12.2.6 单板特性码单板特性码即单板条形码中位于单板名称后面的编码。

BPA的单板特性码用于描述光接口的输出光功率。

∙12.2.7 技术指标BPA单板指标包含光接口指标、单板尺寸、重量和功耗。

父主题：12 光放大单板和色散补偿单板12.2.1 版本描述BPA单板的功能版本为N1。

父主题：12.2 BPA12.2.2 功能和特性光信号进行长距离传输时，信号衰耗较多，为使光接收机接收到正常的光信号，需要加光功率放大板（BA）和前置放大板（PA）。

BA和PA在光传输系统中的位置如图12-4所示。

BPA单板的具体功能和特性如表12-5所示。

4.23 DCUDCU板是色散补偿板，可补偿10Gbit/s系统中光信号在光纤传输中积累的色散，压缩光信号，使光信号得到恢复，配合光放大板可实现长距离光中继传输。

DCU板可以插在子架的slot 1～8、11～18、26～31槽位。

4.23.1 功能●DCU板采用啁啾光栅对光纤传输中的色散进行补偿，压缩脉冲信号，使光信号得到恢复。

●最多支持两路光信号同时进行色散补偿。

可提供的色散补偿量为1020ps/nm（对应60km G.652光纤产生的色散）或1360ps/nm（对应80km G.652光纤产生的色散），或者两者的任意组合。