ADS8364的VHDL程序

关于ADS8364高精度多通道的A/D转换器，只要照着芯片资料时序写程序就可以了library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ad8364 is
port(
clk:in std_logic;
eoc:in std_logic;
coe:out std_logic;
clkd :out std_logic;
a2,a1,a0:out std_logic;
adin:in std_logic_vector(15 downto 0);
holda,holdb,holdc:out std_logic;
rd,wr:out std_logic;
ada0,ada1,adb0,adb1,adc0,adc1:out std_logic_vector(15 downto 0));
end;
architecture a of ad8364 is
signal clk1:std_logic:='0';
type states is ( st0,st1, st2, st3);
signal csn:states:=st0;
constant q1:std_logic_vector(7 downto 0):="00000011";
constant q2:std_logic_vector(7 downto 0):="11100011";
constant q3:std_logic_vector(7 downto 0):="11100001";
constant q4:std_logic_vector(7 downto 0):="11100101";
constant q5:std_logic_vector(7 downto 0):="11101001";
constant q6:std_logic_vector(7 downto 0):="11101101";
constant q7:std_logic_vector(7 downto 0):="11110001";
constant q8:std_logic_vector(7 downto 0):="11110101";
signal q:std_logic_vector(7 downto 0);
signal cn :integer range 0 to 5000;
begin
process(clk)
variable cnt:integer range 0 to 25;
begin
if clk='1' and clk'event then
if cnt=25 then
cnt:=0;clk1<=not clk1;
else cnt:=cnt+1;end if;
end if;
end process;
clkd<=clk1;
process(clk1)
variable td:integer range 0 to 6;
begin
if clk1'event and clk1='1' then
case csn is
when st0=> q<=q1;
if (cn<100) then
csn<=st0;cn<=cn+1;
else cn<=0; csn<=st1;
end if;
when st1 =>q<=q2;
if (cn<60) then
csn<=st1;cn<=cn+1;
else csn<=st2;cn<=0;end if;
when st2=>
if td=0 then q<=q3;
elsif td=1 then q<=q4;
elsif td=2 then q<=q5;
elsif td=3 then q<=q6;
elsif td=4 then q<=q7;
elsif td=5 then q<=q8;end if;
if (cn<60) then
csn<=st2;cn<=cn+1;
else csn<=st3;cn<=0;td:=td+1;
end if;
when st3=>q<=q1;
if td=1 then ada0<=adin;
elsif td=2 then ada1<=adin;
elsif td=3 then adb0<=adin;
elsif td=4 then adb1<=adin;
elsif td=5 then adc0<=adin;
elsif td=6 then adc1<=adin; end if;
if cn<30 then csn<=st3;cn<=cn+1;
else csn<=st0;cn<=0;td:=0;end if;
when others =>csn<=st0;td:=0;
end case;
end if;
end process;
holda<=q(7);
holdb<=q(6);
holdc<=q(5);
a2<=q(4);
a1<=q(3);
a0<=q(2);
rd<=q(1);
wr<=q(0);
coe<=not eoc; end architecture;。