FPGA可编程逻辑器件芯片XC3S100E-5FGG484C中文规格书

Chapter 9
Programmable Logic
The programmable logic (PL) is a scalable structure that provides the ability to create many
possible functions. The PL logic regions include DSP engines, configurable logic blocks, and two types of RAM arrays. These are configured together to create almost any type of hardware
functionality including accelerators, processors, functional pipeline units, and peripherals. The PL includes connections for the integrated hardware and peripherals, ports to the NoC interconnect,access to CMOS and gigabit high-speed I/O, and interface channels to the PS.
The PL complements the functionality of the PS, AI Engine, and other integrated hardware to improve application performance. The PL instantiates system functionality and provides connectivity between the system and integrated hardware and peripherals.
The PMC and PS have many signal connections and bus interfaces to the PL. These are
summarized in the Boundary Interface Signals chapter.
PL Configuration
The connections and configuration of the PL elements are captured in the Vivado ® design suite and the Vitis ™ unified software platform tool chain using a programmable device image (PDI).The PDI contains PL configuration frames (CFRAME), which are sent by the PLM to the
configuration frame unit (CFU) for processing. The CFU interfaces to the PL via the configuration frame interface (CFI). The PL can be configured during the boot process and can be re-configured during normal system operation. The PL configuration can be read-back for debug and functional safety applications. The CFU is described in Configuration Frame Unit and the CFI is described in Configuration Frame Interface .
Building Blocks
The PL includes building blocks and provides several types of connections to many parts of the device including several subsystems and I/O. The PL has AXI interfaces to the PS, CPM, AI Engine, and the integrated controllers. The PL also has port interface signals and parameter configuration inputs to the PS, PMC, and other parts of the system.
The PL building blocks include the DSP Engine, configurable logic block (CLB), Block RAM, and UltraRAM integrated components. These components are surrounded by clocking structures and wiring pathways. The PL makes connection between PS, CPM, PMC, NoC, AI Engine, GTs, XPIO banks, high-density I/O (HDIO) buffers, and components instantiated within the PL.
The PL building blocks include:
Section II: Hardware Architecture
Chapter 9: Programmable Logic
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○ULPI is routed via the PMC MIO (not LPD MIO or EMIO)
For more information, see Section XII: I/O Peripheral Controllers .
Flash Memory Controllers
The flash memory controllers are located in the PMC and include:
•Quad SPI Controller
•Octal SPI Controller
•SD/eMMC Controller (two in PMC)
Flash memory controllers can serve as primary boot devices. The options are listed in Boot Modes .
Section II: Hardware Architecture
Chapter 8: PS and PMC I/O Peripherals
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•DSP Engine (intelligent)
•CLB (adaptable)
•Block RAM and UltraRAM (adaptable)
Additional Features
The PL also contains clocking structures and PLL-enabled clocks for the PL fabric and I/O. The PL also includes connections to the Arm CoreSight™ debug hardware for data monitoring and collection.
Tool Support
The Vivado tools provide a large library of complex functional components (microprocessors,peripherals, filters, etc.) that can be instantiated and connected to create a design. Additionally, a hardware description language can be used to describe specific functions in the design. The Vivado tools then translate the design into the building blocks of the PL. The PL can be partially or fully programmed during the boot start-up and as a service operation when the system is operating.Block Diagram
The PL building blocks and clock structures provide the foundation for instantiating functionality.The PL is provided with port interface signals attached to nearly every part of the device.The high-level PL perspective of the system is shown in the following figure.
Section II: Hardware Architecture
Chapter 9: Programmable Logic
AM011 (v1.1) November 30, 2020Versal ACAP TRM。