FPGA可编程逻辑器件芯片XCZU19EG-L1FFVC1760I中文规格书

HD IOB Supported Standards Table 106: HD IOB Supported Single-Ended Standards
IOSTANDARD Required V CCO
Level for Input
and Output
INTERNAL _VREF Level for
Input DRIVE and Termination Options
LVTTL 3.3V N/A DRIVE: 4, 8, 12
LVCMOS33 3.3V N/A DRIVE: 4, 8, 12
LVCMOS25 2.5V N/A DRIVE: 4, 8, 12
LVCMOS18 1.8V N/A DRIVE: 4, 8, 12
SSTL18_I 1.8V0.9V SPLIT
HSTL_I_18 1.8V0.9V SPLIT
Table 107: HD IOB Supported Differential Standards
IOSTANDARD V CCO Level1Drive and Termination Options LVDS_25 (input only) 2.5V
LVPECL (input only) 3.3V
SLVS_400_25 (input only) 2.5V
SUB_LVDS (input only) 1.8V
DIFF_HSTL_I_18 1.8V SPLIT
DIFF_SSTL18_I 1.8V SPLIT
Notes:
1.When on-die input termination is used (ODT is set to a value other than RTT_NONE) or when PULLTYPE leverages
V CCO (KEEPER or PULLUP), the V CCO input voltage is as specified. When ODT = RTT_NONE and PULLTYPE is unused,
NONE, or PULLDOWN, the V CCO input voltage is any allowed voltage higher than the highest signal level applied to
the pin.
HD IOB Primitives
The Vivado Design Suite library includes an extensive list of primitives supporting many I/O
primitives. The generic primitives can each support most of the single-ended I/O standards:
•IBUF: Input buffer
•IOBUF: Bidirectional buffer
•IOBUF_INTERMDISABLE: Bidirectional buffer with input buffer disable and on-die input termination disable control
•OBUF: Output buffer
•OBUFT: Tristate output buffer
Chapter 7: HD IOB Resources
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
Chapter 1: Overview
Differences from Previous Generations Versal™ ACAPs have several important feature enhancements as well as updates to existing
features.
XP XPHY
The following table summarizes the key differences between the UltraScale™ architecture PHY and the Versal™ architecture XPHY.
Table 1: UltraScale Architecture PHY and Versal Architecture XPHY Key Differences
Function Versal Architecture XPHY UltraScale Architecture PHY NIBBLESLICEs per nibble6 6 or 7
Nibbles per bank9 (54 pins)8 (52 pins)
Serialization8:1, 4:1, 2:18:1, 4:1
Deserialization1:8, 1:4, 1:21:8, 1:4
Wizard required to access interface Yes No
Input and output delays625 ps (512 taps)UltraScale devices: 1250 ps (512 taps)
UltraScale+ devices: 1100 ps (512 taps) Some of the other differences between the PHY architectures of UltraScale™ and Versal devices include the following:
•Receive FIFO bypass support for low-latency applications
•No NIBBLESLICE 0 (formerly called BITSLICE 0) instantiation requirements
•The IDELAYCTRL, ISERDES, OSERDES, RXTX_BITSLICE, RX_BITSLICE, TX_BITSLICE, BITSLICE_CONTROL, and RIU_OR UNISIM primitives are not supported
•The XP IOL resources are independent of the XPHY. Only one or the other can be used at a time.
•Programmable logic control ports are shared between input and output delays through a delay select port
•Some XPIO banks (typically located on the corner of the device) have pins that have limited function and can only be used for DDR memory controller functionality. See the Versal ACAP
Packaging and Pinouts Architecture Manual (AM013) for specific pin information. Also see the
Versal Architecture and Product Data Sheet: Overview (DS950).
•QBC and DBC functionality has been split into two parts: Strobes now enter on XCC pins, while inter-nibble and inter-byte clocking capabilities are determined by the nibble.
•The PHY can only be constructed by using the Advanced IO Wizard together with the Advanced I/O Planner (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)).
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual。