lm5122

V OUT
V IN
LM5122/LM5122-Q1
SNVS954C–APRIL2013–REVISED MAY2013 Wide Input Synchronous Boost Controller with Multiple Phase Capability
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FEATURES APPLICATIONS
•Available in AEC-Q100(LM5122-Q1)•12V,24V,and48V Power Systems •Maximum Input Voltage:65V•Automotive Start-Stop
•Min Input Voltage:3.0V(4.5V for startup)•Audio Power Supply
•Output Voltage up to100V•High Current Boost Power Supply
•Bypass(V OUT=V IN)Operation
DESCRIPTION
• 1.2V Reference with±1.0%Accuracy
The LM5122is a multiphase capable synchronous •Free-Run/Synchronizable Switching to1MHz boost controller intended for high-efficiency
•Peak Current Mode Control synchronous boost regulator applications.The control
method is based upon peak current mode control.•Robust3A Integrated Gate Drivers
Current mode control provides inherent line feed-•Adaptive Dead-Time Control
forward,cycle-by-cycle current limiting and ease of •Optional Diode Emulation Mode loop compensation.
•Programmable Cycle-by-Cycle Current Limit The switching frequency is programmable up to1•Hiccup Mode Overload Protection MHz.Higher efficiency is achieved by two robust N-
channel MOSFET gate drivers with adaptive dead-•Programmable Line UVLO
time control.A user-selectable diode emulation mode •Programmable Soft-Start
also enables discontinuous mode operation for •Thermal Shutdown Protection improved efficiency at light load conditions.
•Low Shutdown Quiescent Current:9μA An internal charge pump allows100%duty cycle for •Programmable Slope Compensation high-side synchronous switch(Bypass operation).A
180ºphase shifted clock output enables easy multi-•Programmable Skip Cycle Mode Reduces
phase interleaved configuration.Additional features Standby Power
include thermal shutdown,frequency synchronization,•Allows External VCC Supply hiccup mode current limit and adjustable line
•Inductor DCR Current Sensing Capability undervoltage lockout.
•Multiphase Capability
•Thermally Enhanced20-Pin HTSSOP
SIMPLIFIED APPLICATION DIAGRAM
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright©2013,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
LM5122/LM5122-Q1
SNVS954C–APRIL2013–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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LM5122/LM5122-Q1 SNVS954C–APRIL2013–REVISED MAY2013
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range(unless otherwise noted)
VALUE
UNIT
MIN MAX
Input VIN,CSP,CSN–0.375V BST to SW,FB,MODE,UVLO,OPT,VCC(2)–0.315V
SW–5.0105V
BST–0.3115V
SS,SLOPE,SYNCIN/RT–0.37V
CSP to CSN,PGND–0.30.3V
HO to SW–0.3BST to SW+0.3V Output(3)LO–0.3VCC+0.3V COMP,RES,SYNCOUT–0.37V
Human-Body Model(HBM)JESD22-A1142kV ESD Rating
Charged-Device Model(CDM)JESD22-C1011kV
Storage Temperature–55150ºC Thermal
Junction Temperature–40150ºC (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Unless otherwise specified,all voltages are referenced to AGND pin.
(2)See Application Information when input supply voltage is less than the VCC voltage.
(3)All output pins are not specified to have an external voltage applied.
THERMAL CHARACTERISTICS
THERMAL METRIC UNIT
θJA Junction-to-ambient thermal resistance(Typ.)40ºC/W
θJC Junction-to-case thermal resistance(Typ.)4ºC/W RECOMMENDED OPERATING CONDITIONS(1)
Over operating free-air temperature range(unless otherwise noted)
MIN MAX UNIT Input supply voltage(2)VIN 4.565V
Low-side driver bias voltage VCC14V High-side driver bias voltage BST to SW 3.814V Current sense common mode range(2)CSP,CSN 3.065V Switch node voltage SW100V Junction temperature T J–40125ºC (1)Recommended Operating Conditions are conditions under which operation of the device is intended to be functional,but does not
guarantee specific performance limits.
(2)Minimum VIN operating voltage is always4.5V.The minimum input power supply voltage can be3.0V after start-up,assuming VIN
voltage is supplied from an available external source.
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SNVS954C–APRIL2013–REVISED
ELECTRICAL CHARACTERISTICS
Unless otherwise specified,these specifications apply for-40°C≤T J≤+125°C,V VIN=12V,V VCC=8.3V,R T=20kΩ,no load on LO and HO.Typical values represent the most likely parametric norm at T J=25°C,and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY
I SHUTDOWN VIN shutdown current V UVLO=0V917µA
I BIAS VIN operating current(exclude V UVLO=2V,non-switching
45mA the current into RT resistor)
VCC REGULATOR
V CC(REG)VCC regulation No load 6.97.68.3V
V VIN=4.5V,no external load0.25V VCC dropout(VIN to VCC)
V VIN=4.5V,I VCC=25mA0.280.5V VCC sourcing current limit V VCC=0V5062mA
V VCC=8.3V 3.55mA VCC operating current(exclude
I VCC
the current into RT resistor)V
=12V 4.58mA
VCC
VCC rising,V VIN=4.5V 3.9 4.0 4.1V VCC undervoltage threshold
VCC falling,V VIN=4.5V 3.7V VCC undervoltage hysteresis0.385V UNDERVOLTAGE LOCKOUT
UVLO threshold UVLO rising 1.17 1.20 1.23V
UVLO hysteresis current V UVLO=1.4V71013µA
UVLO standby enable threshold UVLO rising0.30.40.5V
UVLO standby enable hysteresis0.10.125V MODE
Diode emulation mode threshold MODE rising 1.20 1.24 1.28V
Diode emulation mode hysteresis0.1V
Default MODE voltage145155170mV
COMP rising,measured at COMP 1.290V Default skip cycle threshold
COMP falling,measured at COMP 1.245V Skip cycle hysteresis Measured at COMP40mV ERROR AMPLIFIER
V REF FB reference voltage Measured at FB,V FB=V COMP 1.188 1.200 1.212V FB input bias current V FB=V REF5nA
I SOURCE=2mA,V VCC=4.5V 2.75V
V OH COMP output high voltage
I SOURCE=2mA,V VCC=12V 3.40V
V OL COMP output low voltage I SINK=2mA0.25V
A OL DC gain80dB
f BW Unity gain bandwidth3MHz
Slave mode threshold FB rising 2.7 3.4V OSCILLATOR
f SW1Switchin
g frequency1R T=20kΩ400450500kHz
f SW2Switchin
g frequency2R T=10kΩ775875975kHz
RT output voltage 1.2V
RT sync rising threshold RT rising 2.5 2.9V
RT sync falling threshold RT falling 1.6 2.0V
Minimum sync pulse width100ns SYNCOUT
SYNCOUT high-state voltage I SYNCOUT=–1mA 3.3 4.3V
SYNCOUT low-state voltage I SYNCOUT=1mA0.150.25V
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LM5122/LM5122-Q1 SNVS954C–APRIL2013–REVISED MAY2013
ELECTRICAL CHARACTERISTICS(continued)
Unless otherwise specified,these specifications apply for-40°C≤T J≤+125°C,V VIN=12V,V VCC=8.3V,R T=20kΩ,no load on LO and HO.Typical values represent the most likely parametric norm at T J=25°C,and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPT
Synchronization selection OPT rising
2.0
3.0
4.0V
threshold
SLOPE COMPENSATION
SLOPE output voltage 1.17 1.20 1.23V
R SLOPE=20kΩ,f SW=100kHz,50%
1.375 1.650 1.925V
duty cycle,T J=–40ºC to+125ºC
V SLOPE Slope compensation amplitude
R SLOPE=20kΩ,f SW=100kHz,50%duty
1.400 1.650 1.900V
cycle,T J=25ºC
SOFT-START
I SS-SOURCE SS current source V SS=0V7.51012µA
SS discharge switch R DS-ON13Ω
PWM COMPARATOR
V VCC=5.5V330400ns t LO-OFF Forced LO off-time
V VCC=4.5V560750ns
R SLOPE=5kΩ150ns t ON-MIN Minimum LO on-time
R SLOPE=200kΩ300ns
T J=–40ºC to+125ºC0.95 1.10 1.25V COMP to PWM voltage drop
T J=25ºC 1.00 1.10 1.20V CURRENT SENSE/CYCLE-BY-CYCLE CURRENT LIMIT
CSP to CSN,T J=–40ºC to+125ºC65.575.087.5mV Cycle-by-cycle current limit
V CS-TH1
threshold CSP to CSN,T
=25ºC67.075.086.0mV
J
CSP to CSN,rising7mV V CS-ZCD Zero cross detection threshold
CSP to CSN,falling0.5612mV Current sense amplifier gain10V/V
I CSP CSP input bias current12µA
I CSN CSN input bias current11µA
Bias current matching I CSP-I CSN–1.751 3.75µA
CS to LO delay Current sense/current limit delay150ns HICCUP MODE RESTART
V RES Restart threshold RES rising 1.15 1.20 1.25V
RES rising 4.2V V HCP-
Hiccup counter upper threshold RES rising,
UPPER 3.6V
V VIN=V VCC=4.5V
RES falling 2.15V V HCP-
Hiccup counter lower threshold RES falling,
LOWER 1.85V
V VIN=V VCC=4.5V
I RES-RES current source1Fault-state charging current
203040µA SOURCE1
I RES-SINK1RES current sink1Normal-state discharging current5µA
I RES-RES current source2Hiccup mode off-time charging current
10µA SOURCE2
I RES-SINK2RES current sink2Hiccup mode off-time discharging current5µA
Hiccup cycle8Cycles
RES discharge switch R DS-ON40Ω
Ratio of hiccup mode off-time to
122
restart delay time
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LM5122/LM5122-Q1
SNVS954C–APRIL2013–REVISED
ELECTRICAL CHARACTERISTICS(continued)
Unless otherwise specified,these specifications apply for-40°C≤T J≤+125°C,V VIN=12V,V VCC=8.3V,R T=20kΩ,no load on LO and HO.Typical values represent the most likely parametric norm at T J=25°C,and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HO GATE DRIVER
V OHH HO high-state voltage drop I HO=–100mA,V OHH=V BST–V HO0.150.24V V OLH HO low-state voltage drop I HO=100mA,V OLH=V HO–V SW0.10.18V HO rise time(10%to90%)C LOAD=4700pF,V BST=12V25ns
HO fall time(90%to10%)C LOAD=4700pF,V BST=12V20ns
V HO=0V,V SW=0V,V BST=4.5V0.8A
I OHH Peak HO source current
V HO=0V,V SW=0V,V BST=7.6V 1.9A
V HO=V BST=4.5V 1.9A
I OLH Peak HO sink current
V HO=V BST=7.6V 3.2A
I BST BST charge pump sourcing V VIN=V SW=9.0V,V BST-V SW=5.0V
100200µA current
B ST to SW,I BST=–70μA,
5.3
6.2 6.75V
V VIN=V SW=9.0V
BST charge pump regulation
B ST to SW,I BST=–70μA,
78.59V
V VIN=V SW=12V
BST to SW undervoltage 2.0 3.0 3.5V
BST DC bias current V BST-V SW=12V,V SW=0V3045µA
LO GATE DRIVER
V OHL LO high-state voltage drop I LO=–100mA,V OHL=V VCC–V LO0.150.25V V OLL LO low-state voltage drop I LO=100mA,V OLL=V LO0.10.17V LO rise time(10%to90%)C LOAD=4700pF25ns
LO fall time(90%to10%)C LOAD=4700pF20ns
V LO=0V,V VCC=4.5V0.8A
I OHL Peak LO source current
V LO=0V 2.0A
V LO=V VCC=4.5V 1.8A
I OLL Peak LO sink current
V LO=V VCC 3.2A SWITCHING CHARACTERISTICS
t DLH LO fall to HO rise delay No load,50%to50%5080115ns t DHL HO fall to LO rise delay No load,50%to50%6080105ns THERMAL
T SD Thermal shutdown Temperature rising165ºC Thermal shutdown hysteresis25ºC
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LM5122/LM5122-Q1 SNVS954C–APRIL2013–REVISED MAY2013
TYPICAL CHARACTERISTICS
BST SW VCC
VCC
SW SHUTDOWN
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SNVS954C–APRIL2013–REVISED
TYPICAL CHARACTERISTICS(continued)
VCC VCC VCC VIN
CSP CSN
BST-SW SW BST
CS-TH1VIN CS-TH1
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LM5122/LM5122-Q1 SNVS954C–APRIL2013–REVISED MAY2013
TYPICAL CHARACTERISTICS(continued)
BST-SW
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VCC UVLO CSP OPT CSN VIN SLOPE SYNCIN/RT
BST COMP
RES SW LO
HO AGND
SS
PGND MODE FB
SYNCOUT
LM5122/LM5122-Q1
SNVS954C –APRIL 2013–REVISED MAY 2013
DEVICE INFORMATION
HTSSOP-20(TOP VIEW)
PIN FUNCTIONS
PIN
I/O (1)DESCRIPTION
NAME NO.AGND 9G Analog ground connection.Return for the internal voltage reference and analog circuits.
High-side driver supply for bootstrap gate drive.Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor.The bootstrap capacitor supplies current to charge the high-BST
20
P/I
side N-channel MOSFET gate and should be placed as close to controller as possible.An internal BST charge pump will supply 200µA current into bootstrap capacitor for bypass operation.
Output of the internal error amplifier.The loop compensation network should be connected between COMP 11O this pin and the FB pin.
CSN 3I Inverting input of current sense amplifier.Connect to the negative-side of the current sense resistor.Non-inverting input of current sense amplifier.Connect to the positive-side of the current sense CSP 4I resistor.
Exposed pad of the package.No internal electrical connections.Should be soldered to the large EP EP N/A ground plane to reduce thermal resistance.
Feedback.Inverting input of the internal error amplifier.A resistor divider from the output to this pin FB 10I sets the output voltage level.The regulation threshold at the FB pin is 1.2V.The controller is configured as slave mode if the FB pin voltage is above 2.7V at initial power-on.
High-side N-channel MOSFET gate drive output.Connect to the gate of the high-side synchronous HO 19O N-channel MOSFET switch through a short,low inductance path.
Low-side N-channel MOSFET gate drive output.Connect to the gate of the low-side N-channel LO
16
O
MOSFET switch through a short,low inductance path.
Switching mode selection pin.700k Ωpull-up and 100k Ωpull-down resistor internal hold MODE pin to 0.15V as a default.By adding external pull-up or pull-down resistor,MODE pin voltage can be programmed.When MODE pin voltage is greater than 1.2V diode emulation mode threshold,forced PWM mode is enabled,allowing current to flow in either direction through the high-side N-MODE 13I
channel MOSFET switch.When MODE pin voltage is less than 1.2V,the controller works in diode emulation mode.Skip cycle comparator is activated as a default.If MODE pin is grounded,the controller still operates in diode emulation mode,but the skip cycle comparator will not be triggered in normal operation,this enables pulse skipping operation at light load.
Clock synchronization selection pin.This pin also enables/disables SYNCOUT related with OPT 2I master/slave configuration.The OPT pin should not be left floating.
Power ground connection pin for low-side N-channel MOSFET gate driver.Connect directly to the PGND
15
G
source terminal of the low-side N-channel MOSFET switch.
(1)G =Ground,I =Input,O =Output,P =Power
10
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PIN
I/O(1)DESCRIPTION
NAME NO.
The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay RES14O during over load conditions.Connect directly to the AGND when hiccup mode operation is not
required.
SLOPE12I Slope compensation is programmed by a single resistor between SLOPE and the AGND.
Soft-start programming pin.An external capacitor and an internal10μA current source set the ramp SS7I
rate of the internal error amplifier reference during soft-start.
Switching node of the boost regulator.Connect to the bootstrap capacitor,the source terminal of the SW18I/O high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET
switch through short,low inductance paths.
The internal oscillator frequency is programmed by a single resistor between RT and the AGND.
The internal oscillator can be synchronized to an external clock by applying a positive pulse signal SYNCIN/RT8I
into this SYNCIN pin.The recommended maximum internal oscillator frequency in master
configuration is2MHz which leads to1MHz maximum switching frequency.
Clock output pin.SYNCOUT provides180ºshifted clock output for an interleaved operation. SYNCOUT1O
SYNCOUT pin can be left floating when it is not used.See Slave Mode and SYNCOUT section.
Undervoltage lockout programming pin.If the UVLO pin is below0.4V,the regulator is in the
shutdown mode with all functions disabled.If the UVLO pin voltage is greater than0.4V and below
1.2V,the regulator is in standby mode with the VCC regulator operational and no switching at the
UVLO6I
HO and LO outputs.If the UVLO pin voltage is above1.2V,the startup sequence begins.A10μA
current source at UVLO pin is enabled when UVLO exceeds1.2V and flows through the external
UVLO resistors to provide hysteresis.The UVLO pin should not be left floating.
VCC bias supply pin.Locally decouple to PGND using a low ESR/ESL capacitor located as close to VCC17P/O/I
controller as possible.
Supply voltage input source for the VCC regulator.Connect to input capacitor and source power VIN5P/I
supply connection with short,low impedance paths.
FUNCTIONAL BLOCK DIAGRAM
V
Functional Description
The LM5122wide input range synchronous boost controller features all of the functions necessary to implement a highly efficient synchronous boost regulator.The regulator control method is based upon peak current mode control.Peak current mode control provides inherent line feed-forward and ease of loop compensation.This highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive dead-time control.The switching frequency is user programmable up to1MHz set by a single resistor or synchronized to an external clock.The LM5122’s180ºshifted clock output enables easy multi-phase configuration.
The control mode of high-side synchronous switch can be configured as either forced PWM(FPWM)or diode emulation mode.Fault protection features include cycle-by-cycle current limiting,hiccup mode over load protection,thermal shutdown and remote shutdown capability by pulling down the UVLO pin.The UVLO input enables the controller when the input voltage reaches a user selected threshold,and provides a tiny9μA shutdown quiescent current when pulled low.The device is available in20-pin HTSSOP package featuring an exposed pad to aid in thermal dissipation.
IN(SHUTDOWN)IN(STARTUP)HYS V V V [V]
UV2
UV1IN(STARTUP)1.2V R R V 1.2V u ªº
¬¼ :HYS UV2V
R 10 $: ªº
¬¼
Undervoltage Lockout (UVLO)
The LM5122features a dual level UVLO circuit.When the UVLO pin voltage is less than the 0.4V UVLO standby enable threshold,the LM5122is in the shutdown mode with all functions disabled.The shutdown comparator provides 0.1V of hysteresis to avoid chatter during transition.If the UVLO pin voltage is greater than 0.4V and below 1.2V during power up,the controller is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs.This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO pin down below the UVLO standby enable threshold with an external open collector or open drain device.
Figure 16.UVLO Remote Standby and Shutdown Control
If the UVLO pin voltage is above the 1.2V UVLO threshold and VCC voltage exceeds the VCC UV threshold,a startup sequence begins.UVLO hysteresis is accomplished with an internal 10μA current source that is switched on or off into the impedance of the UVLO setpoint divider.When the UVLO pin voltage exceeds 1.2V,the current source is enabled to quickly raise the voltage at the UVLO pin.When the UVLO pin voltage falls below the 1.2V UVLO threshold,the current source is disabled causing the voltage at the UVLO pin to quickly fall.In addition to the UVLO hysteresis current source,a 5μs deglitch filter on both rising and falling edge of UVLO toggling helps preventing chatter upon power up or down.
An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input operating voltage of the regulator.The divider must be designed such that the voltage at the UVLO pin is greater than 1.2V when the input voltage is in the desired operating range.The maximum voltage rating of the UVLO pin is 15V.If necessary,the UVLO pin can be clamped with an external zener diode.The UVLO pin should not be left floating.The values of R UV1and R UV2can be determined from Equation 1and Equation 2.
(1)
(2)where
•
V HYS is the desired UVLO hysteresis
•
V IN(STARTUP)is the desired startup voltage of the regulator during turn-on.
Typical shutdown voltage during turn-off can be calculated as follows:
(3)
High Voltage VCC Regulator
The LM5122contains an internal high voltage regulator that provides typical 7.6V VCC bias supply for the controller and N-channel MOSFET drivers.The input of VCC regulator,VIN,can be connected to an input voltage source as high as 65V.The VCC regulator turns on when the UVLO pin voltage is greater than 0.4V.When the input voltage is below the VCC setpoint level,the VCC output tracks VIN with a small dropout voltage.The output of the VCC regulator is current limited at 50mA minimum.
Upon power-up,the VCC regulator sources current into the capacitor connected to the VCC pin.The recommended capacitance range for the VCC capacitor is 1.0μF to 47μF and is recommended to be at least 10times greater than C BST value.When operating with a VIN voltage less than 6V,the value of VCC capacitor should be 4.7µF or greater.
V External
VCC Supply
VCC
n u V External VCC Supply
The internal power dissipation of the LM5122device can be reduced by supplying VCC from an external supply.If an external VCC bias supply exists and the voltage is greater than 9V and below 14.5V.The external VCC bias supply can be applied to the VCC pin directly through a diode,as shown in Figure 17.
Figure 17.External Bias Supply when 9V<V EXT <14.5V
Shown in Figure 18is a method to derive the VCC bias voltage with an additional winding on the boost inductor.This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC regulator.
Figure 18.External Bias Supply using Transformer
The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be fully forward biased in normal operation,as shown in Figure 19.If the voltage of the external VCC bias supply is greater than the VIN pin voltage,an external blocking diode is required from the input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply through VCC.The need for the blocking diode should be evaluated for all applications when the VCC is supplied by the external bias supply.Especially,when the input power supply voltage is less than 4.5V,the external VCC supply should be provided and the external blocking diode is required.
Figure 19.VIN Configuration when V VIN <V VCC
IN
OUT
V 'D V 9
'IN S SLOPE IN L 610K 1D V R 10R §·u u
u ¨¸¨¸u u u ©¹
9
IN SLOPE OUT IN(MIN)S L 610R K V V R 10u u ªº¬¼ªºu u u ¬:¼
IN OUT
V D 1V
9
SLOPE SW SLOPE
6x10V xD [V]
f x R
9
T SW f 910R u
¼
:ªº¬ Oscillator
The LM5122switching frequency is programmable by a single external resistor connected between the RT pin and the AGND pin.The resistor should be located very close to the device and connected directly to the RT pin and AGND pin.To set a desired switching frequency (f SW ),the resistor value can be calculated from Equation 4.
(4)
Slope Compensation
For duty cycles greater than 50%,peak current mode regulators are subject to sub-harmonic oscillation.Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles.This sub-harmonic oscillation can be eliminated by a technique,which adds an artificial ramp,known as slope compensation,to the sensed inductor current.
Figure 20.Slope Compensation
The amount of slope compensation is programmable by a single resistor connected between the SLOPE pin and the AGND pin.The amount of slope compensation can be calculated as follows:
where
•
(5)
R SLOPE value can be determined from the following equation at minimum input voltage:
where
•
K=0.82~1as a default
(6)
From the above equation,K can be calculated over the input range as follows:
where
•
(7)
In any case,K should be greater than at least 0.5.At higher switching frequency over 500kHz,K factor is recommended to be greater than or equal to 1because the minimum on-time affects the amount of slope compensation due to internal delays.
FB2
FB1
P _EA COMP
HF
COMP COMP HF
1
Hz C C C f 2R C ªº¬¼
§·u S u u ¨¸ ©¹
Z _EA COMP COMP 1
f Hz
2R C ªº¬¼S u u 9
SLOPE SW 810R f :u !ªº
¬¼
9IN MIN SLOPE SW OUT V 5.710R 1.2V f §
·u ¨¸!u
:ªº¬¼¨¸©
¹
The sum of sensed inductor current and slope compensation should be less than COMP output high voltage (V OH )for proper startup with load and proper current limit operation.This limits the minimum value of R SLOPE to be:
•
This equation can be used in most cases
•
This conservative selection should be considered when V IN(MIN)<5.5V
The SLOPE pin cannot be left floating.
Error Amplifier
The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin voltage and the internal precision 1.2V reference.The output of the error amplifier is connected to the COMP pin allowing the user to provide a Type 2loop compensation network.
R COMP ,C COMP and C HF configure the error amplifier gain and phase characteristics to achieve a stable voltage loop.This network creates a pole at DC,a mid-band zero (f Z_EA )for phase boost,and a high frequency pole (f P_EA ).The minimum recommended value of R COMP is 2k Ω.See Feedback Compensation section.
(9)
(10)
PWM Comparator
The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the
voltage at the COMP pin through a 1.2V internal COMP to PWM voltage drop,and terminates the present cycle when the sum of sensed inductor current and slope compensation ramp is greater than V COMP –1.2V.
Figure 21.Feedback Configuration and PWM Comparator。