limits(完成)

32
16
8
4
13
How to Exceed ILP Limits of this study?
These are not laws of physics; just practical limits for today, and perhaps overcome via research
Compiler & ISA advances can change results WAR and WAW hazards through memory: eliminated
Memory Alias
Perfect
Perfect ??
8
More Realistic HW: Branch Impact
Change from Infinite window to 2048 and maximum issue of 64 instructions per clock cycle
Cache Memory Alias Analysis
Infinite 48 integer + 40 Floating-point Perfect 2% to 6% misprediction
(Tournament Branch Predictor) Perfect 64KI, 32KD, 1.92M L2, 36M L3 Perfect ??
(Tournament Branch Predictor)
Perfect
Perfect 64KI, 32KD, 1.92B L2, 36M L3
Memory Alias
HW dis-
Perfect ??
ambiguation
12
Realistic HW: Window Impact
Instruction issuesIperPcycleC
Perfect
Cache Memory Alias
Perfect Perfect
Perfect Model Infinite 4
Infinite 200
Power 5
Infinite 48 integer + 40 Floating-point
Perfect 2% to 6% misprediction (Tournament Branch Predictor)
Branch Prediction
Perfect, 8K Tournament, 512 2-bit, profile, none
Perfect
2% to 6% misprediction
(Tournament Branch Predictor)
Cache
Perfect
Perfect 64KI, 32KD, 1.92B L2, 36M L3
Perfect 64KI, 32KD, 1.92B L2, 36M L3 Perfect ??
6
More Realistic HW: Window Impact
Instructions Per Clock
160
150
FP: 9 - 150
140
119
120
100
Integer: 8 - 63
80
63
The above two assumptions eliminate all but RAW
Branch prediction – perfect; no mispredictions Jump prediction – all jump/returns perfectly predicted
WAW and WAR hazards through register renaming, but not in memory usage
Can get conflicts via allocation of stack frames as a called procedure reuses the memory addresses of a previous frame on the stack
Infinite 48 integer + 40 Floating-point
Perfect 2% to 6% misprediction (Tournameቤተ መጻሕፍቲ ባይዱt Branch Predictor)
Perfect 64KI, 32KD, 1.92B L2, 36M L3
Memory Alias
Perfect Perfect ??
Limits on Instruction-Level Parallelism
Introduction
Thread Level Parallelism
Multithreading
Simultaneous Multithreading
Power 4 vs. Power 5
VLIW vs. Superscalar vs. SMT
How close a real dynamically scheduled, speculative processor come to the ideal one?
Look arbitrarily far ahead predicting all branches Rename all register uses to avoid WAR/WAW Determine data dependencies Determine memory dependencies Enough parallel unis
Conclusion
CDA 5155 – Fall 2012
Copyright © 2012 Prabhat Mishra
1
Limits to ILP
Assumptions for ideal/perfect machine to start:
Register renaming – infinite virtual registers
60 55
41
40
36
75 61 49 35
20
10 10 8
15 13 8
18 15 12 11 9
14
0
gcc
espresso
li
f pppp
59
16 15 9
60 45 34
14
doduc
tomcatv
Window Sizes: Infinite 2048 512 128 32
7
Limits to ILP HW Model Comparison
2
Limits to ILP HW Model Comparison
Perfect Model Instructions Issued per clock Infinite 4
Instruction Window Size
Infinite 200
Power 5
Renaming Registers Branch Prediction
Unnecessary dependencies e.g., loop variable can be removed by loop unrolling
10
Renaming Register Impact (N int + N fp)
Change 2048 instr window, 64 instr issue, 8K 2 level prediction FP: 5 - 49
Integer: 5 - 15
IPC
Infinite 256 128 64 32 None
Perfect disambiguation (HW), 1K Selective Prediction, 16 entry return, 64 registers, issue as many as window
60
56
52
FP: 3 - 47
50
47
45
40
35
Integer: 2 - 12
30
140
120
Integer: 18 - 63
100
80
62.6
60
54.8
FP: 75 - 150 150.1
118.7 75.2
40
17.9 20
0
gcc
espresso
li
fpppp
Programs
doducd tomcatv
4
Practical Check: Max. Issue Count
Paper: Limits of Instruction-Level Parallelism, David Wall, 1990
3
Upper Limit to ILP: Ideal Machine
Instructions Per Clock
Instruction Issues per cycle
160
All register WAW & WAR hazards are avoided
Memory-address alias analysis – addresses known and a load can be moved before a store provided addresses are not equal
FP: 13 - 48
Integer: 6 - 12
IPC
Perfect Tournament
BHT (512) Profile
No prediction 9
Limits to ILP HW Model Comparison
New Model
Instructions Issued 64 per clock