sram芯片的使用标准协议

256K x 16 Static RAMCY7C1041BV33Features•High speed —t AA = 12 ns •Low active power —612 mW (max.)•Low CMOS standby power (Commercial L version)—1.8 mW (max.)•2.0V Data Retention (600 µW at 2.0V retention)•Automatic power-down when deselected •TTL-compatible inputs and outputs•Easy memory expansion with CE and OE featuresFunctional DescriptionThe CY7C1041BV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits.Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O 7), iswritten into the location specified on the address pins (A 0through A 17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O 15) is written into the location specified on the address pins (A 0 through A 17).Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O 15. See the truth table at the back of this data sheet for a complete description of read and write modes.The input/output pins (I/O 0 through I/O 15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).The CY7C1041BV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout.1415Logic Block DiagramPin ConfigurationA 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODERR O W D E C O D E RS E N S E A M P SINPUT BUFFER256K x 16ARRAY A 0A 11A 13A 12A A A 16A 17A 9A 101024 x 4096I/O 0 – I/O 7OE I/O 8 – I/O 15CE WE BLEBHE Top ViewSOJ TSOP II WE 1234567891011143132363534333740393812134144434216152930V CC A 5A 6A 7A 8A 0A 1OE V SS A 17I/O 15A 2CE I/O 2I/O 0I/O 1BHE A 3A 418172019I/O 32728252622212324V SS I/O 6I/O 4I/O 5I/O 7A 16A 15BLE V CC I/O 14I/O 13I/O 12I/O 11I/O 10I/O 9I/O 8A 14A 13A 12A 11A 9A 10NC Selection Guide-12-15-17-20-25Maximum Access Time (ns)1215172025Maximum Operating Current (mA)Comm ’l190170160150130Ind ’l-190180170150Maximum CMOS Standby Current (mA)Com ’l/Ind ’l 88888Com ’lL0.50.50.50.50.5Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[1]....–0.5V to +4.6V DC Voltage Applied to Outputsin High Z State[1]....................................–0.5V to V CC + 0.5V DC Input Voltage[1]................................–0.5V to V CC + 0.5V Current into Outputs (LOW)........................................20 mAOperating RangeRangeAmbientTemperature[2]V CC Commercial0°C to +70°C 3.3V ± 0.3V Industrial–40°C to +85°CElectrical Characteristics Over the Operating RangeParameter Description Test Conditions-12-15Min.Max.Min.Max.Unit V OH Output HIGH Voltage V CC = Min.,I OH = –4.0 mA2.4 2.4VV OL Output LOW Voltage V CC = Min.,I OL = 8.0 mA0.40.4VV IH Input HIGH Voltage 2.2V CC+ 0.52.2V CC+ 0.5VV IL Input LOW Voltage[1]–0.50.8–0.50.8V I IX Input Load Current GND < V I < V CC–1+1–1+1µA I OZ Output Leakage Current GND < V OUT < V CC, Output Disabled–1+1–1+1µAI CC V CC OperatingSupply Current V CC = Max., f = f MAX =1/t RCComm’l190170mAInd’l-190mAI SB1Automatic CEPower-Down Current—TTL Inputs Max. V CC, CE > V IHV IN > V IH orV IN < V IL, f = f MAX4040mAI SB2Automatic CEPower-Down Current—CMOS Inputs Max. V CC,CE > V CC– 0.3V,V IN > V CC– 0.3V,or V IN < 0.3V, f = 0Com’l/Ind’l88mACom’l L0.50.5mANotes:1.V IL (min.) = –2.0V for pulse durations of less than 20 ns.2.T A is the “Instant On” case temperature.Electrical Characteristics Over the Operating Range (continued)Test Conditions-17-20-25Parameter Description Min.Max.Min.Max.Min.Max.Unit V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.42.42.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.40.40.4V V IH Input HIGH Voltage 2.2V CC +0.5 2.2V CC + 0.5 2.2V CC + 0.5V V IL Input LOW Voltage [1]–0.50.8–0.50.8–0.50.8V I IX Input Load Current GND < V I < V CC –1+1–1+1–1+1µA I OZ Output Leakage Current GND < V OUT < V CC ,Output Disabled –1+1–1+1–1+1µA I CC V CC Operating Supply Current V CC = Max., f = f MAX = 1/t RC Comm ’l 160150130mAInd ’l180170150I SB1Automatic CEPower-Down Current —TTL Inputs Max. V CC , CE > V IH V IN > V IH orV IN < V IL , f = f MAX 404040mAI SB2Automatic CEPower-Down Current —CMOS InputsMax. V CC ,CE > V CC – 0.3V,V IN > V CC – 0.3V,or V IN < 0.3V, f=0Com ’l/Ind ’l 888mA Com ’lL0.50.50.5mACapacitance [3]Parameter DescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V8pF C OUTI/O Capacitance8pFNote:3.Tested initially and after any design or process changes that may affect these parameters.AC Test Loads and Waveforms90%10%3.3VGND 90%10%ALL INPUT PULSES3.3V OUTPUT30 pFINCLUDING JIG AND SCOPE OUTPUT(a)(b)R1 317Ω167ΩR2351ΩVENIN EQUIVALENT TH É 1.73VRise time: 1 V/nsFall time:1 V/nsSwitching Characteristics[4]Over the Operating Range-12-15-17Parameter Description Min.Max.Min.Max.Min.Max.Unit READ CYCLEt RC Read Cycle Time121517nst AA Address to Data Valid121517nst OHA Data Hold from Address Change333nst ACE CE LOW to Data Valid121517nst DOE OE LOW to Data Valid678nst LZOE OE LOW to Low Z000nst HZOE OE HIGH to High Z[5, 6]677nst LZCE CE LOW to Low Z[6]333nst HZCE CE HIGH to High Z[5, 6]677nst PU CE LOW to Power-Up000nst PD CE HIGH to Power-Down121517nst DBE Byte Enable to Data Valid677nst LZBE Byte Enable to Low Z000nst HZBE Byte Disable to High Z678ns WRITE CYCLE[7, 8]t WC Write Cycle Time121517nst SCE CE LOW to Write End101212nst AW Address Set-Up to Write End101212nst HA Address Hold from Write End000nst SA Address Set-Up to Write Start000nst PWE WE Pulse Width101212nst SD Data Set-Up to Write End789nst HD Data Hold from Write End000nst LZWE WE HIGH to Low Z[6]333nst HZWE WE LOW to High Z[5, 6]678nst BW Byte Enable to End of Write101212ns Notes:4.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specifiedI OL/I OH and 30-pF load capacitance.5.t HZOE, t HZCE, and t HZWE are specified with a load capacitance of 5 pF as in part (b) of AC T est Loads. Transition is measured ±500 mV from steady-state voltage.6.At any given temperature and voltage condition, t HZCE is less than t LZCE, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for any given device.7.The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either ofthese signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.8.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD.Switching Characteristics[4]Over the Operating Range (continued)Parameter Description-20-25Unit Min.Max.Min.Max.READ CYCLEt RC Read Cycle Time2025ns t AA Address to Data Valid2025ns t OHA Data Hold from Address Change35ns t ACE CE LOW to Data Valid2025ns t DOE OE LOW to Data Valid810ns t LZOE OE LOW to Low Z00ns t HZOE OE HIGH to High Z[5, 6]810ns t LZCE CE LOW to Low Z[6]35ns t HZCE CE HIGH to High Z[5, 6]810ns t PU CE LOW to Power-Up00ns t PD CE HIGH to Power-Down2025ns t DBE Byte Enable to Data Valid810ns t LZBE Byte Enable to Low Z00ns t HZBE Byte Disable to High Z810ns WRITE CYCLE[7, 8]t WC Write Cycle Time2025ns t SCE CE LOW to Write End1315ns t AW Address Set-Up to Write End1315ns t HA Address Hold from Write End00ns t SA Address Set-Up to Write Start00ns t PWE WE Pulse Width1315ns t SD Data Set-Up to Write End910ns t HD Data Hold from Write End00ns t LZWE WE HIGH to Low Z[6]35ns t HZWE WE LOW to High Z[5, 6]810ns t BW Byte Enable to End of Write1315nsData Retention Characteristics Over the Operating Range (For L version only)Parameter Description Conditions[10]Min.Max.Unit V DR V CC for Data Retention 2.0VI CCDR Data Retention Current V CC = V DR = 2.0V,CE > V CC– 0.3V,V IN > V CC– 0.3V or V IN < 0.3V 330µAt CDR[3]Chip Deselect to DataRetention Time0ns t R[9]Operation Recovery Time t RC nsNotes:9.t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 and slower speeds.10.No input may exceed V CC + 0.5V.Data Retention Waveform1041BV33–3.0V 3.0V t CDRV DR >2VDATA RETENTION MODEt RCEV CC Switching WaveformsNotes:11.Device is continuously selected. OE, CE, BHE and/or BHE = V IL .12.WE is HIGH for read cycle.13.Address valid prior to or coincident with CE transition LOW.Read Cycle No. 1PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHA1041BV33-6ADDRESSDATA OUT[11, 12]Read Cycle No. 2(OE Controlled)1041BV33-750%50%DATA VALIDt RCt ACEt DOE t LZOE t LZCE t PUHIGH IMPEDANCEt HZOEt HZBEt PDHIGHOE CEICC ISB IMPEDANCEADDRESSDATA OUT V CC SUPPLY t DBE t LZBEt HZCE BHE,BLE[12, 13]CURRENTI CCI SBNotes:14.Data I/O is high-impedance if OE or BHE and/or BLE= V IH .15.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high –impedance state.Switching Waveforms (continued)Write Cycle No. 1(CE Controlled)1041BV33-8t HDt SDt SCEt SA t HAt AWt PWEt WCBWDATAI/OADDRESSCEWEBHE,BLE[14, 15]t Write Cycle No. 2(BLE or BHE Controlled)t HDt SDt BWt SA t HAt AWt PWEt WCt SCEDATAI/OADDRESSBHE,BLEWECE1041BV33-9Truth TableCE OE WE BLE BHE I/O 0–I/O 7I/O 8–I/O 15ModePower H X X X X High Z High Z Power Down Standby (I SB )L L H L L Data Out Data Out Read All Bits Active (I CC )L L H L H Data Out High Z Read Lower Bits Only Active (I CC )L L H H L High Z Data Out Read Upper Bits Only Active (I CC )L X L L L Data In Data In Write All Bits Active (I CC )L X L L H Data In High Z Write Lower Bits Only Active (I CC )L X L H L High Z Data In Write Upper Bits Only Active (I CC )LHHXXHigh ZHigh ZSelected, Outputs DisabledActive (I CC )Switching Waveforms (continued)Write Cycle No.3(WE Controlled ,OE LOW)1041BV33-10t HDt SDt SCEt HAt AWt PWEt WCt BWDATA I/OADDRESSCEWEBHE,BLEt SAt LZWEt HZWEOrdering InformationSpeed(ns)Ordering Code PackageName Package TypeOperatingRange12CY7C1041BV33-12VC V3444-Lead (400-Mil) Molded SOJ Commercial CY7C1041BV33L-12VC V3444-Lead (400-Mil) Molded SOJCY7C1041BV33-12ZC Z4444-Pin TSOP II Z44CY7C1041BV33L-12ZC Z4444-Pin TSOP II Z4415CY7C1041BV33-15VC V3444-Lead (400-Mil) Molded SOJ Commercial CY7C1041BV33L-15VC V3444-Lead (400-Mil) Molded SOJCY7C1041BV33-15ZC Z4444-Pin TSOP II Z44CY7C1041BV33L-15ZC Z4444-Pin TSOP II Z44CY7C1041BV33-15VI V3444-Lead (400-Mil) Molded SOJ Industrial CY7C1041BV33-15ZI Z4444-Pin TSOP II Z4417CY7C1041BV33-17VC V3444-Lead (400-Mil) Molded SOJ Commercial CY7C1041BV33L-17VC V3444-Lead (400-Mil) Molded SOJCY7C1041BV33-17ZC Z4444-Pin TSOP II Z44CY7C1041BV33L-17ZC Z4444-Pin TSOP II Z44CY7C1041BV33-17VI V3444-Lead (400-Mil) Molded SOJ Industrial CY7C1041BV33-17ZI Z4444-Pin TSOP II Z4420CY7C1041BV33-20VC V3444-Lead (400-Mil) Molded SOJ Commercial CY7C1041BV33L-20VC V3444-Lead (400-Mil) Molded SOJCY7C1041BV33-20ZC Z4444-Pin TSOP II Z44CY7C1041BV33L-20ZC Z4444-Pin TSOP II Z44CY7C1041BV33-20VI V3444-Lead (400-Mil) Molded SOJ Industrial CY7C1041BV33-20ZI Z4444-Pin TSOP II Z4425CY7C1041BV33-25VC V3444-Lead (400-Mil) Molded SOJ Commercial CY7C1041BV33L-25VC V3444-Lead (400-Mil) Molded SOJCY7C1041BV33-25ZC Z4444-Pin TSOP II Z44CY7C1041BV33L-25ZC Z4444-Pin TSOP II Z44CY7C1041BV33-25VI V3444-Lead (400-Mil) Molded SOJ Industrial CY7C1041BV33-25ZI Z4444-Pin TSOP II Z44Package Diagrams44-Lead (400-Mil) Molded SOJ V3451-85082-B44-Pin TSOP II Z4451-85087-ADocument #: 38-05168 Rev. **Page 11 of 11Document Title: CY7C1041BV33 256K x 16 SRAM Document Number: 38-05168REV.ECN NO.Issue Date Orig. of Change Description of Change **11184011/17/01DSGChange from Spec number: 38-00932 to 38-05168。