Design and Optimization of CMOS

Design and Optimization of CMOS

RF Power Amplifiers

Ravi Gupta,Associate Member,IEEE,Brian M.Ballweber,Member,IEEE,and David J.Allstot,Fellow,IEEE Abstract—A CMOS radio-frequency power amplifier including

on-chip matching networks has been designed in a0.6-

and power-added efficiency(PAE)

as

is the RF output

power,is the dc power drawn

from

otherwise

(5)

and

,the product of this

load

resistance,,and the peak instantaneous value of the

fundamental component of the drain current,should equal the

desired maximum voltage swing.

Hence,can be obtained

from

.With the optimum load impedance presented to the

PA output,the maximum RF voltage swing

of

]to

the

(a)

(b)

Fig.2.PA drain efficiency versus conduction angle.(a)R

fixed.

dc power[the product of the supply voltage and average current

given by(5)]is easily derived

as

decreases.Also evident is the

Class A efficiency of50%and Class B efficiency of78.5%

(neglecting

and

180

)for all values

of

.Thus,this curve does not represent how a PA with a fixed

load resistance behaves if the conduction angle of the driver

transistor is varied.It does give an upper limit for the drain

efficiency achievable for a fixed optimum load resistance value.

This efficiency is realized for a particular conduction angle for

which the output voltage swing is maximum.An important

implication for a PA with a fixed matching network optimized

for a particular output power level is that its efficiency will

degrade when operated at a reduced power level[Fig.2(b)].

Fig.3.PA output power (normalized to Class A)versus conduction

angle.

Fig.4.PA normalized fundamental to third harmonic component ratio versus

conduction angle.

The increased efficiency at a reduced conduction angle is achieved at the expense of decreased maximum power output.In the limit,one can design a Class C PA to achieve a drain effi-ciency approaching 100%,but the corresponding output power approaches zero.The output power is expressed

as

,again assuming that

the output voltage swing is maximum

(

is achieved at the expense of

reduced output power.Thus,there is a direct trade-off between drain efficiency and power output.As the conduction angle de-creases,the harmonic content of the output signal also increases,illustrating a linearity-output power-efficiency trade-off.Fig.4shows a plot of the normalized ratio of the fundamental and the third harmonic components versus conduction angle.This plot indicates the behavior of IP3as a function of conduction angle.A reduced conduction angle causes the fundamental component to decrease more rapidly than the third harmonic,resulting

in

Fig.5.Measured one-port s -parameter values for a metal3square spiral inductor,7.25turns and 12.4nH.

a more nonlinear power amplifier.Depending upon the peak to average power ratio of the signal being amplified,the adja-cent channel power performance also degrades as the conduc-tion angle is reduced beyond a certain limit.

III.I NTEGRATED I NDUCTOR M ODEL FOR CAD O PTIMIZATION Shown in Fig.5is measured

one-port

m triple-metal CMOS process.The 29-segment (7.25turns)inductor

formed on the metal3layer was

15-m interturn spacing,and a

100-