ADCS7476芯片资料
AD7476ABKS-500RL7中文资料
REV.CaAD7476A/AD7477A/AD7478A *2.35 V to 5.25 V, 1 MSPS,12-/10-/8-Bit ADCs in 6-Lead SC70Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESFast Throughput Rate: 1 MSPSSpecified for V DD of 2.35V to 5.25V Low Power:3.6 mW Typ at 1 MSPS with 3 V Supplies 12.5 mW Typ at 1 MSPS with 5 V Supplies Wide Input Bandwidth:71 dB SNR at 100 kHz Input FrequencyFlexible Power/Serial Clock Speed Management No Pipeline DelaysHigh Speed Serial InterfaceSPI ®/QSPI™/MICROWIRE™/DSP Compatible Standby Mode: 1 A Max 6-Lead SC70 Package 8-Lead MSOP PackageAPPLICATIONSBattery-Powered Systems Personal Digital Assistants Medical Instruments Mobile CommunicationsInstrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical SensorsFUNCTIONAL BLOCK DIAGRAMV V T A GENERAL DESCRIPTION The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit high speed, low power, successive-approximation ADCs, respec-tively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz.The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS , and the conversion is also initiated at this point.There are no pipeline delays associated with the parts.The AD7476A/AD7477A/AD7478A use advanced design tech-niques to achieve low power dissipation at high throughput rates.The reference for the part is taken internally from V DD , which allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 to V DD . The conversion rate is determined by the SCLK.PRODUCT HIGHLIGHTS1.First 8-/10-/12-bit ADCs in an SC70 package.2.High throughput with low power consumption.3.Flexible power/serial clock speed management. The conversionrate is determined by the serial clock, allowing the conver-sion time to be reduced through the serial clock speed increase.This allows the average power consumption to be reduced when a power-down mode is used while not converting. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1µA max and 50 nA typically when in power-down mode.4.Reference derived from the power supply.5.No pipeline delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.*Protected by U.S.Patent No. 6,681,332.AD7476A/AD7477A/AD7478AAD7476A–SPECIFICATIONS1(V DD = 2.35 V to 5.25 V, f SCLK = 20 MHz, f SAMPLE = 1 MSPS, unless otherwise noted;T A = T MIN to T MAX, unless otherwise noted.)Parameter A Grade2 B Grade2Y Grade2Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 100 kHz Sine WaveSignal-to-Noise + Distortion (SINAD)3707070dB min V DD = 2.35 V to 3.6 V, T A = 25؇C696969dB min V DD = 2.4 V to 3.6 V71.571.571.5dB typ V DD = 2.35 V to 3.6 V696969dB min V DD = 4.75 V to 5.25 V, T A = 25؇C686868dB min V DD = 4.75 V to 5.25 VSignal-to-Noise Ratio (SNR)3717171dB min V DD = 2.35 V to 3.6 V, T A = 25؇C707070dB min V DD = 2.4 V to 3.6 V707070dB min V DD = 4.75 V to 5.25 V, T A = 25؇C696969dB min V DD = 4.75 V to 5.25 VTotal Harmonic Distortion (THD)3–80–80–80dB typPeak Harmonic or Spurious Noise (SFDR)3–82–82–82dB typIntermodulation Distortion (IMD)3Second-Order Terms–84–84–84dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Terms–84–84–84dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay101010ns typAperture Jitter303030ps typFull Power Bandwidth13.513.513.5MHz typ@ 3 dB222MHz typ@ 0.1 dBDC ACCURACY B and Y Grades4Resolution121212BitsIntegral Nonlinearity3±1.5±1.5LSB max±0.75LSB typDifferential Nonlinearity–0.9/+1.5–0.9/+1.5LSB max Guaranteed No Missed Codes to 12 Bits±0.75LSB typOffset Error3,5±1.5±1.5LSB max±1.5±0.2±0.2LSB typGain Error3,5±1.5±1.5LSB max±1.5±0.5±0.5LSB typTotal Unadjusted Error (TUE)3, 5±2±2LSB maxANALOG INPUTInput Voltage Range0 to V DD0 to V DD0 to V DD VDC Leakage Current±0.5±0.5±0.5µA maxInput Capacitance202020pF typ Track-and-Hold in Track; 6 pF typ whenin HoldLOGIC INPUTSInput High Voltage, V INH 2.4 2.4 2.4V min1.8 1.8 1.8V min V DD =2.35 VInput Low Voltage, V INL0.80.80.8V max V DD = 5 V0.40.40.4V max V DD = 3 VInput Current, I IN, SCLK Pin±0.5±0.5±0.5µA max Typically 10 nA, V IN = 0 V or V DD Input Current, I IN, CS Pin±10±10±10nA typmaxInput Capacitance, C IN6555pFLOGIC OUTPUTSOutput High Voltage, V OH V DD – 0.2V DD – 0.2V DD – 0.2V min I SOURCE = 200 µA; V DD = 2.35 V to 5.25 V Output Low Voltage, V OL0.40.40.4V max I SINK = 200 µAFloating-State Leakage Current±1±1±1µA maxmaxFloating-State Output Capacitance6555pFOutput Coding Straight (Natural) BinaryCONVERSION RATEConversion Time800800800ns max16 SCLK CyclesTrack-and-Hold Acquisition Time3250250250ns maxThroughput Rate111MSPS max See Serial Interface Section–2–REV. CREV. C AD7476A/AD7477A/AD7478A–3–AD7477A–SPECIFICATIONS1(V DD = 2.35 V to 5.25 V, f SCLK = 20 MHz, f SAMPLE = 1 MSPS, unless otherwise noted;T A = T MIN to T MAX , unless otherwise noted.)ParameterA Grade 2B Grade 2Y Grade 2Unit Test Conditions/CommentsPOWER REQUIREMENTS V DD 2.35/5.252.35/5.25 2.35/5.25V min/max I DDDigital I/Ps = 0 V or V DDNormal Mode (Static)2.5 2.5 2.5mA typ V DD = 4.75 V to 5.25 V, SCLK ON or OFF 1.21.2 1.2mA typ V DD =2.35 V to3.6 V, SCLK ON or OFF Normal Mode (Operational) 3.53.5 3.5mA max V DD =4.75 V to5.25 V, f SAMPLE = 1 MSPS 1.71.7 1.7mA max V DD =2.35 V to3.6 V, f SAMPLE = 1 MSPS Full Power-Down Mode (Static)111µA max Typically 50 nAFull Power-Down Mode (Dynamic)0.60.60.6mA typ V DD = 5 V, f SAMPLE = 100 kSPS 0.30.30.3mA typ V DD = 3 V, f SAMPLE = 100 kSPS Power Dissipation7Normal Mode (Operational)17.517.517.5mW max V DD = 5 V, f SAMPLE = 1 MSPS 5.15.1 5.1mW max V DD = 3 V, f SAMPLE = 1 MSPS Full Power-Down Mode 555µW max V DD = 5 V 333µW maxV DD = 3 VNOTES 1Temperature ranges as follows: A, B Grades: –40°C to +85°C, Y Grade: –40°C to +125°C.2Operational from V DD = 2.0 V, with input low voltage (V INL ) 0.35 V max.3See Terminology section.4B and Y Grades, maximum specifications apply as typical figures when V DD = 4.75 V to 5.25 V.5SC70 values guaranteed by characterization.6Guaranteed by characterization.7See Power vs. Throughput Rate section.Specifications subject to change without notice.ParameterA Grade 2Unit Test Conditions/Comments DYNAMIC PERFORMANCEf IN = 100 kHz Sine WaveSignal-to-Noise + Distortion (SINAD)361dB min Total Harmonic Distortion (THD)3–72dB max Peak Harmonic or Spurious Noise (SFDR)3–73dB max Intermodulation Distortion (IMD)3Second-Order Terms –82dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms –82dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10ns typ Aperture Jitter30ps typ Full Power Bandwidth13.5MHz typ @ 3 dB 2MHz typ @ 0.1 dBDC ACCURACY Resolution10BitsIntegral Nonlinearity ±0.5LSB max Differential Nonlinearity ±0.5LSB max Guaranteed No Missed Codes to 10 BitsOffset Error 3, 4±1LSB max Gain Error 3, 4±1LSB max Total Unadjusted Error (TUE)3, 4±1.2LSB max ANALOG INPUT Input Voltage Range 0 to V DD VDC Leakage Current ±0.5µA max Input Capacitance20pF typTrack-and-Hold in Track; 6 pF typ when in HoldAD7476A/AD7477A/AD7478A–4–REV. CREV. C AD7476A/AD7477A/AD7478A–5–NOTES 1Temperature range from –40°C to +85°C.2Operational from V DD = 2.0 V, with input high voltage (V INH ) 1.8 V min.3See Terminology section.4SC70 values guaranteed by characterization.5Guaranteed by characterization.6See Power vs. Throughput Rate section.Specifications subject to change without notice.REV. C–6–AD7476A/AD7477A/AD7478ATIMING SPECIFICATIONS1(V DD = 2.35 V to 5.25 V; T A = T MIN to T MAX , unless otherwise noted.)Limit at T MIN , T MAXParameter AD7476A/AD7477A/AD7478AUnit Description f SCLK 210kHz min 3A, B Grades 20kHz min 3Y Grade20MHz maxt CONVERT 16 ϫ t SCLK AD7476A 14 ϫ t SCLK AD7477A 12 ϫ t SCLK AD7478At QUIET 50ns min Minimum Quiet Time Required between Bus Relinquish and Start of Next Conversion t 110ns min Minimum CS Pulse Width t 210ns min CS to SCLK Setup Timet 3422ns max Delay from CS until SDATA Three-State Disabled t 4440ns max Data Access Time after SCLK Falling Edge t 50.4 t SCLK ns min SCLK Low Pulse Width t 60.4 t SCLK ns min SCLK High Pulse Widtht 75SCLK to Data Valid Hold Time 10ns min V DD ≤ 3.3 V9.5ns min 3.3 V < V DD ≤ 3.6 V 7ns min V DD > 3.6 Vt 8636ns max SCLK Falling Edge to SDATA High Impedance See Note 7ns min SCLK Falling Edge to SDATA High Impedance t POWER-UP 81µs maxPower-Up Time from Full Power-DownNOTES 1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD ) and timed from a voltage level of 1.6 V.2Mark/space ratio for the SCLK input is 40/60 to 60/40.3Minimum f SCLK at which specifications are guaranteed.4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V DD = 2.35 V and 0.8 V or 2.0 V for V DD > 2.35 V.5Measured with 50 pF load capacitor.6t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.7t 7 values also apply to t 8 minimum values.8See Power-Up Time section.Specifications subject to change without notice.Figure 1.Load Circuit for Digital Output Timing SpecificationsREV. CAD7476A/AD7477A/AD7478A–7–Timing Example 1Having f SCLK = 20 MHz and a throughput of 1 MSPS gives a cycle time of t 2 + 12.5 (1/f SCLK ) + t ACQ = 1 µs. With t 2 = 10 ns min,this leaves t ACQ to be 365ns. This 365 ns satisfies the requirement of 250 ns for t ACQ . From Figure 3, t ACQ is comprised of 2.5 (1/f SCLK )+ t 8 + t QUIET , where t 8 = 36 ns max. This allows a value of 204ns for t QUIET , satisfying the minimum requirement of 50ns.CSSCLKSDA T AFigure 2.AD7476A Serial Interface Timing DiagramCSSCLKFigure 3.Serial Interface Timing ExampleTiming Example 2Having f SCLK = 5 MHz and a throughput of 315 kSPS gives a cycle time of t 2 + 12.5 (1/f SCLK ) + t ACQ = 3.174 µs. With t 2 =10ns min, this leaves t ACQ to be 664 ns. This 664 ns satisfies the requirement of 250 ns for t ACQ . From Figure 3, t ACQ is comprised of 2.5(1/f SCLK ) + t 8 + t QUIET , t 8 = 36 ns max. This allows a value of 128ns for t QUIET , satisfying the minimum requirement of 50ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50ns minimum t QUIET between conversions. In Example 2, the signal should be fully acquired at approximately Point C in Figure 3.REV. C–8–AD7476A/AD7477A/AD7478AABSOLUTE MAXIMUM RATINGS 1(T A = 25°C, unless otherwise noted.)V DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to GND . . . . . . . –0.3 V to V DD + 0.3 V Digital Input Voltage to GND . . . . . . . . . . . . –0.3 V to +7 V Digital Output Voltage to GND . . . . . –0.3 V to V DD + 0.3 V Input Current to Any Pin except Supplies 2 . . . . . . . . ±10 mA Operating Temperature RangeCommercial (A and B Grades) . . . . . . . . . –40°C to +85°C Industrial (Y Grade) . . . . . . . . . . . . . . . .–40°C to +125°C Storage Temperature Range . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C MSOP PackageJA Thermal Impedance . . . . . . . . . . . . . . . . . . 205.9°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . 43.74°C/WCAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment, and can discharge without detection. Although the AD7476A/AD7477A/AD7478A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.SC70 PackageJA Thermal Impedance . . . . . . . . . . . . . . . . . . 340.2°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . 228.9°C/W Lead Temperature, SolderingReflow (10 sec to 30 sec) . . . . . . . . . . . . . . . .235 (0/+5)°C Pb-free Temperature SolderingReflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 (0/+5)°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kVNOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2Transient currents of up to 100 mA will not cause SCR latch-up.REV. CAD7476A/AD7477A/AD7478A–9–ORDERING GUIDETemperature Linearity Package ModelRangeError (LSB)1Option 2Branding AD7476AAKS-500RL7–40°C to +85°C ±0.75 typ KS-6CEZ AD7476AAKS-REEL –40°C to +85°C ±0.75 typ KS-6CEZ AD7476AAKS-REEL7–40°C to +85°C ±0.75 typ KS-6CEZ AD7476ABKS-500RL7–40°C to +85°C ±1.5 max KS-6CEY AD7476ABKS-REEL –40°C to +85°C ±1.5 max KS-6CEY AD7476ABKS-REEL7–40°C to +85°C ±1.5 max KS-6CEY AD7476ABKSZ-REEL 3–40°C to +85°C ±1.5 max KS-6CEY AD7476ABKSZ-REEL73–40°C to +85°C ±1.5 max KS-6CEY AD7476ABRM–40°C to +85°C ±1.5 max RM-8CEY AD7476ABRM-REEL –40°C to +85°C ±1.5 max RM-8CEY AD7476ABRM-REEL7–40°C to +85°C ±1.5 max RM-8CEY AD7476AYKS-500RL7–40°C to +125°C ±1.5 max KS-6CEW AD7476AYKS-REEL7–40°C to +125°C ±1.5 max KS-6CEW AD7476AYKSZ-500RL73–40°C to +125°C ±1.5 max KS-6CEW AD7476AYKSZ-REEL73–40°C to +125°C ±1.5 max KS-6CEW AD7476AYRM–40°C to +125°C ±1.5 max RM-8CEW AD7476AYRM-REEL7–40°C to +125°C ±1.5 max RM-8CEW EVAL-AD7476ACB 4Evaluation Board AD7477AAKS-500RL7–40°C to +85°C ±0.5 max KS-6CFZ AD7477AAKS-REEL –40°C to +85°C ±0.5 max KS-6CFZ AD7477AAKS-REEL7–40°C to +85°C ±0.5 max KS-6CFZ AD7477AAKSZ-REEL 3–40°C to +85°C ±0.5 max KS-6CFZ AD7477AAKSZ-REEL73–40°C to +85°C ±0.5 max KS-6CFZ AD7477AARM–40°C to +85°C ±0.5 max RM-8CFZ AD7477AARM-REEL –40°C to +85°C ±0.5 max RM-8CFZ AD7477AARM-REEL7–40°C to +85°C ±0.5 max RM-8CFZ EVAL-AD7477ACB 4Evaluation Board AD7478AAKS-500RL7–40°C to +85°C ±0.3 max KS-6CJZ AD7478AAKS-REEL –40°C to +85°C ±0.3 max KS-6CJZ AD7478AAKS-REEL7–40°C to +85°C ±0.3 max KS-6CJZ AD7478AAKSZ-500RL73–40°C to +85°C ±0.3 max KS-6CJZ AD7478AAKSZ-REEL 3–40°C to +85°C ±0.3 max KS-6CJZ AD7478AAKSZ-REEL73–40°C to +85°C ±0.3 max KS-6CJZ AD7478AARM–40°C to +85°C ±0.3 max RM-8CJZ AD7478AARM-REEL –40°C to +85°C ±0.3 max RM-8CJZ AD7478AARM-REEL7–40°C to +85°C±0.3 maxRM-8CJZEVAL-CONTROL BRD25Evaluation Control BoardNOTES 1Linearity error here refers to integral nonlinearity.2KS = SC70; RM = MSOP.3Z = Pb-free part.4This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.5This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7476ACB, the EVAL-CONTROLBRD2, and a 12 V ac transformer. See relevant evaluation board application note for more information.REV. C–10–AD7476A/AD7477A/AD7478APIN CONFIGURATIONSPIN FUNCTION DESCRIPTIONSMnemonic FunctionCS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7476A/AD7477A/AD7478A and also frames the serial data transfer.V DD Power Supply Input. The V DD range for the AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V.GND Analog Ground. Ground reference point for all circuitry on the AD7476A/AD7477A/AD7478A. All analog input signals should be referred to this GND voltage.V IN Analog Input. Single-ended analog input channel. The input range is 0 V to V DD .SDATAData Out. Logic output. The conversion result from the AD7476A/AD7477A/AD7478A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first. The data stream from the AD7477A consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream from the AD7478A consists of four leading zeros followed by the 8 bits of conversion data followed by four trailing zeros, which are provided MSB first.SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7476A/AD7477A/AD7478A ’s conversion process.NCNo Connect.8-Lead MSOPV DD SDA T A CS V IN NC 6-Lead SC70V V CS SDA T ASCLKAD7476A/AD7477A/AD7478ATERMINOLOGYIntegral NonlinearityThis is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476A/ AD7477A/AD7478A, the endpoints of the transfer function are zero scale, a point 1LSB below the first code transition, and full scale, a point 1LSB above the last code transition.Differential NonlinearityThis is the difference between the measured and the ideal 1LSB change between any two adjacent codes in the ADC.Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.Gain ErrorThis is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e., V REF– 1 LSB after the offset error has been adjusted out.Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after the end of conversion. See the Serial Interface section for more details.Signal-to-(Noise + Distortion) Ratio (SINAD)This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digiti-zation process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, it is 74dB for a 12-bit converter, 62 dB for a 10-bit con-verter, and 50 dB for an 8-bit converter.Total Unadjusted Error (TUE)This is a comprehensive specification that includes the gain, linearity, and offset errors.Total Harmonic Distortion (THD)Total harmonic distortion is the ratio of the rms sum of har-monics to the fundamental. It is defined asTHDV V V V VV22324252621dB()=++++20logwhere V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.Peak Harmonic or Spurious Noise (SFDR)Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter-mined by the largest harmonic in the spectrum. But for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.Intermodulation Distortion (IMD)With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb, where m andn= 0, 1, 2, 3, and so on.Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).The AD7476A/AD7477A/AD7478A are tested using the CCIF standard where two input frequencies are used (see fa and fb on the specification pages). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation dis-tortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.AD7476A/AD7477A/AD7478AFREQUENCY – kHz5–55–11550050S N R – d B100150200250300350400450–15–35–75–95TPC 1.AD7476A Dynamic Performance at 1 MSPS FREQUENCY – kHzS N R – d BTPC 2.AD7477A Dynamic Performance at 1 MSPS FREQUENCY – kHzS N R – d BTPC 3.AD7478A Dynamic Performance at 1 MSPSFREQUENCY – kHz–66–69–72101000S I N A D – d B100–67–68–70–71–73–74TPC 4.AD7476A SINAD vs. Input Frequency at 1 MSPSTPC 1, TPC 2, and TPC 3 each show a typical FFT plot for the AD7476A, AD7477A, and AD7478A, respectively, at a 1 MSPS sample rate and 100 kHz input frequency.TPC 4 shows the signal-to-(noise + distortion) ratio performance versus the input frequency for various supply voltages while sampling at 1MSPS with an SCLK frequency of 20 MHz for the AD7476A.TPC 5 and TPC 6 show INL and DNL performance for the AD7476A.TPC 7 shows a graph of the total harmonic distortion versus the analog input frequency for different source impedances when using a supply voltage of 3.6V and sampling at a rate of 1MSPS (see Analog Input section).TPC 8 shows a graph of the total harmonic distortion versus the analog input signal frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 20 MHz.–Typical Performance CharacteristicsAD7476A/AD7477A/AD7478ACODE1.00.4–0.201024I N L E R R O R – L S B5120.80.60.20–0.4–0.6–0.8–1.0153620482560307235844096TPC 5.AD7476A INL PerformanceCODE1.00.4–0.201024D N LE R R O R – L S B5120.80.60.20–0.4–0.6–0.8–1.0153620482560307235844096TPC 6.AD7476A DNL PerformanceINPUT FREQUENCY – kHz0–30–60101000T H D – d B100–10–20–40–50–70–80–90TPC 7.THD vs. Analog Input Frequency for Various Source ImpedancesINPUT FREQUENCY – kHz–60–75–90101000T H D –d B100–65–70–80–85TPC 8.THD vs. Analog Input Frequency for Various Supply VoltagesAD7476A/AD7477A/AD7478ACIRCUIT INFORMATIONThe AD7476A/AD7477A/AD7478A are fast, micropower,12-/10-/8-bit, single-supply A/D converters, respectively. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7476A/ AD7477A/AD7478A are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock.The AD7476A/AD7477A/AD7478A provide the user with an on-chip, track-and-hold A/D converter and a serial interface housed in a tiny 6-lead SC70 or 8-lead MSOP package, which offer the user considerable space-saving advantages over alterna-tive solutions. The serial clock input accesses data from the part but also provides the clock source for the successive-approximation A/D converter. The analog input range is 0 V to V DD. The ADC does not require an external reference or an on-chip reference. The reference for the AD7476A/AD7477A/AD7478A is derived from the power supply and thus gives the widest dynamic input range.The AD7476A/AD7477A/AD7478A also feature a power-down option to allow power saving between conversions. The power-down feature is implemented across the standard serial interface, as described in the Modes of Operation section. CONVERTER OPERATIONThe AD7476A/AD7477A/AD7478A is a successive-approximation, analog-to-digital converter based around a charge redistribution DAC. Figures 4 and 5 show simplified schematics of the ADC. Figure 4 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on V IN.V INFigure 4.ADC Acquisition Phase When the ADC starts a conversion, see Figure 5, SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADCoutput code. Figure 6 shows the ADC transfer function.V INFigure 5.ADC Conversion PhaseADC TRANSFER FUNCTIONThe output coding of the AD7476A/AD7477A/AD7478A is straight binary.The designed code transitions occur at the successive integer LSB values, i.e., 1 LSB, 2 LSB, and so on. The LSB size isV DD/4096 for the AD7476A, V DD/1024 for the AD7477A, and V DD/256 for the AD7478A. The ideal transfer characteristic for the AD7476A/AD7477A/AD7478A is shown in Figure 6.000 (000)ADCCODEANALOG INPUT111 (111)000 (001)111 (000)011 (111)Figure 6.AD7476A/AD7477A/AD7478ATransfer Characteristic。
铂电阻 采样芯片
铂电阻采样芯片
常见的铂电阻采样芯片有Maxim MAX31865和AD7476。
Maxim MAX31865是简单易用的热敏电阻至数字输出转换器，优化用于铂电阻温度检测器（RTD）。
其输入具有高达±45V的过压保护，提供可配置的RTD及电缆开路、短路条件检测。
AD7476是12位低功耗逐次逼近型ADC，采用单电源工作，电源电压为2.35V至5.25V，最高吞吐速率可达1MSPS，完全满足系统的采样精度和速度的要求。
该芯片内置一个低噪声、宽带宽采样保持放大器，可处理6MHz以上的输入频率。
AD转换过程和数据采集过程通过CS和串行时钟SCLK进行控制，从而为器件与FPGA接口创造了条件。
74系列芯片简介——功能与描述
7400、74H00、74L00、74LS00、74S00、74HC00、74C00、74F00、74ALS00四2输入与非门Y=\AB。
7401、74LS01、74HC01、74ALS01四2输入与非门（OC）Y=\AB。
7402、74L02、74LS02、74S02、74HC02、74C02、74ALS02、74F02四2输入或非门。
Y=/A+B。
7403、74L03、74LS03、74ALS03、74S03、74HC037404、74H04、74L04、74S04、74HC04、74C04、74F04、74ALS04六反相器Y=/A。
7405、74H05、74LS05、74S05、74HC05、74F05、74ALS05六反相器（OC）Y=/A。
7406、74LS06六反相缓冲器/驱动器（OC、高压输出）Y=/A;是7405高耐压输出型，耐压30V。
7407、74LS07、74HC07六缓冲器/驱动器（OC、高压输出）Y=A; 30V耐高压输出。
7408、74LS08、74F08、74ALS08、74S08、74HC08、74C08四2输入与门Y=AB。
7409、74LS09、74F09、74ALS09、74S09、74HC09四2输入与门（OC）Y=AB。
7410、74H10、74L10、74LS10、74ALS10、74S10、74HC10、74C1074H11、74LS11、74S11、74F11、74ALS11、74HC11三3输入与门Y=ABC。
7412、74LS12、74ALS12三3输入与非门（OC）Y=\ABC。
7413、74LS13双4输入与非门Y=\ABCD。
7414、74LS14、74HC14、74C1474H15、74LS15、74ALS15、74S15三3输入与门（OC）Y=ABC。
7416、74LS16六反相缓冲器/驱动器Y=/A；7417、74LS17六缓冲器/驱动器（OC、高压输出）Y=A；15V耐压输出。
7476芯片资料
Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.1POST OFFICE BOX 655303 • DALLAS, TEXAS 752652POST OFFICE BOX 655303 • DALLAS, TEXAS 752653 POST OFFICE BOX 655303 • DALLAS, TEXAS 752654POST OFFICE BOX 655303 • DALLAS, TEXAS 752655 POST OFFICE BOX 655303 • DALLAS, TEXAS 752656POST OFFICE BOX 655303 • DALLAS, TEXAS 75265IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。
4046芯片
4046芯片4046芯片是一种多功能模拟数字转换器（ADC）和数字模拟转换器（DAC）芯片。
它由一组数字逻辑门和放大器组成，用于实现信号的模拟和数字转换。
4046芯片可用于多种应用，例如锁相环（PLL）电路、频率合成器、频率跟踪器、数码相位锁定环路（DPLL）等。
它能够将模拟信号转换为数字信号，并将数字信号转换为模拟信号。
以下是关于4046芯片的详细介绍。
1. 锁相环（PLL）电路：4046芯片可用作PLL电路的核心部件。
它可以实现频率合成、频率跟踪和相位锁定等功能。
通过调整输入信号和参考信号之间的相位差，4046芯片可以将输入信号锁定到参考信号的相位和频率。
2. 频率合成器：4046芯片可以生成稳定的高频信号。
它可以将低频信号调制到高频，并通过调整振荡器的控制电压来实现频率的调节。
这使得4046芯片非常适合用于射频电路、电视和广播设备等领域。
3. 频率跟踪器：4046芯片可以实现信号的频率跟踪和锁定。
它可以将一个输入信号的频率转换为数字信号，并通过反馈机制来调整输入信号的频率，使其与参考信号的频率保持同步。
4. 数码相位锁定环路（DPLL）：4046芯片可以用作数码相位锁定环路的核心元件。
数码相位锁定环路是一种常用的时钟恢复和时钟提取技术，可用于数据通信设备和数字音视频设备中。
4046芯片可以将失真的时钟信号转换为稳定的时钟信号，并通过反馈机制来实现时钟的同步和提取。
除了以上应用，4046芯片还具有以下特点：1. 高精度：4046芯片具有很高的精度和稳定性，可以实现精确的模拟和数字信号转换。
2. 宽电压范围：4046芯片的工作电压范围通常为3V至15V，使其能够适应不同的应用需求。
3. 多功能性：4046芯片支持多种功能，如锁相环、频率合成和频率跟踪等。
这使得它成为设计各种电子设备的理想选择。
总结而言，4046芯片是一种功能强大的模拟数字转换器和数字模拟转换器芯片。
它可以应用于锁相环电路、频率合成器、频率跟踪器和数码相位锁定环路等多种应用领域。
SN7476N3中文资料
Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-9557501QEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 5962-9557501QFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 5962-9557501QFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7601301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC7601301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC JM38510/00204BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC JM38510/00204BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN5476J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCSN5476J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS76AJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS76AJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCSN7476N OBSOLETE PDIP N16TBD Call TI Call TISN7476N OBSOLETE PDIP N16TBD Call TI Call TISN7476N3OBSOLETE PDIP N16TBD Call TI Call TISN7476N3OBSOLETE PDIP N16TBD Call TI Call TISN74LS76AD OBSOLETE SOIC D16TBD Call TI Call TISN74LS76AD OBSOLETE SOIC D16TBD Call TI Call TISN74LS76ADR OBSOLETE SOIC D16TBD Call TI Call TISN74LS76ADR OBSOLETE SOIC D16TBD Call TI Call TISN74LS76AN OBSOLETE PDIP N16TBD Call TI Call TISN74LS76AN OBSOLETE PDIP N16TBD Call TI Call TISN74LS76AN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS76AN3OBSOLETE PDIP N16TBD Call TI Call TI SNJ5476J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCSNJ5476J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCSNJ5476W ACTIVE CFP W161TBD Call TI Level-NC-NC-NCSNJ5476W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS76AJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS76AJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS76AW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS76AW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. 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中微爱芯逻辑芯片AIP74LV AIP74LVC系列
概述：AiP74LVC1G18是2选1的同相多路分解器，具有3态输出。
设备根据输入的状态是否缓冲输入A上的数据并将其传递给输出1Y或2Y 输入（引脚S）为LOW或HIGH。
可以从3.3或5V设备驱动输入。
这些功能允许在3.3V和5V混合环境中使用这些设备。
该设备完全指定用于使用IOFF的部分掉电应用。
IOFF电路会禁用输出，以防止在断电时通过设备的有害回流电流。
特点：宽电源电压范围为1.65V至5.5V 5V耐压输入，可与5V逻辑±24mA 输出驱动器接口（VCC = 3.0V）CMOS低功耗锁存性能超过250mA 具有TTL电平的直接接口在-40℃至+ 85℃包装信息：SOT-23-6 / SOT-363AiP74LVC2G04概述：AiP74LVC2G04提供了双反相缓冲器。
输入可以由3.3V或5V器件驱动。
这些功能允许在3.3V和5V混合环境中使用这些器件。
该器件完全指定用于使用IOFF的部分掉电应用。
IOFF电路禁用输出，以防止在断电时流经该器件的有害回流电流。
宽电源电压范围为1.65V至5.5V5V耐压输入，用于与5V逻辑接口高抗扰度±24mA输出驱动（VCC = 3.0V）CMOS低功耗闩锁性能超过250mA与TTL电平直接接口输入可接受高达5V的电压多种包装选择规定温度为-40℃至+ 85℃包装信息：SOT23-6 / SOT36374系列产品AiP74HC/HCT/LVC系列:拥有74HC/HCT/LVC等系列品种上百款，可完全替换进口TI/NXP/ON等公司逻辑产品。
74系列产品广泛应用各种电子产品中，如家电、数码产品、仪器仪表、工业设备、电信及网络设备等，用于数据放大、运算、锁存、移位等处理，工作温度范围-40℃到85℃。
74HCXXX、74HCTXXX、74LVCXXX等是指对应的芯片系列，“XXX”表示芯片具体型号。
>> 有批量现货产品如下：•门电路AiP74HC00，AiP74HCT00，AiP74HC02，AiP74HC05，AiP74HC08，AiP74HCT08，AiP74HC20，AiP74HC32，AiP74HC86，AiP74HCT86•反相器/缓冲器/驱动器/收发器AiP74HC04，AiP74HCT04，AiP74HC07，AiP74HC14，AiP74HC125，AiP74HC126，AiP74HC244，AiP74HCT244，AiP74HC245，AiP74HCT245•编码器/译码器AiP74HC138，AiP74HCT138，AiP74HCT139，AiP74HC148，AiP74HC238•数字复用器AiP74HC157•触发器AiP74HC74，AiP74HC273，AiP74HC374，AiP74HC574•锁存器AiP74HC373，AiP74HC563，AiP74HC573，AiP74HCT573•移位寄存器AiP74HC164，AiP74HC165，AiP74HC595•计数器AiP74HC191，AiP74HC192，AiP74HC193•多频振荡器74HC123>> 可接受提前一个月订货产品如下：•门电路AiP74HCT02，AiP74HC03，AiP74HCT03，AiP74HC10，AiP74HCT10，AiP74HC11，AiP74HCT11，AiP74HCT20，AiP74HC21，AiP74HCT21，AiP74HC27，AiP74HCT27，AiP74HC30，AiP74HCT30，AiP74HCT32，AiP74HC58，AiP74HCT58，AiP74HC132，AiP74HCT132，AiP74HC4002，AiP74HCT4002，AiP74HC4075，AiP74HCT4075，AiP74HC7266，AiP74HCT7266•反相器/缓冲器/驱动器/收发器AiP74HCT05，AiP74HCT14，AiP74HCT125，AiP74HCT126，AiP74HC240，AiP74HCT240，AiP74HC241，AiP74HCT241，AiP74HC243，AiP74HCT243，AiP74HC365，AiP74HCT365，AiP74HC366，AiP74HCT366，AiP74HC367，AiP74HCT367，AiP74HC368，AiP74HCT368，AiP74HC540，AiP74HCT540，AiP74HC541，AiP74HCT541，AiP74HC640，AiP74HCT640，AiP74HC4049，AiP74HCT4049，AiP74HC4050，AiP74HCT4050，AiP74HC7014•编码器/译码器AiP74HC42，AiP74HCT42，AiP74HC47，AiP74HC48，AiP74HC137，AiP74HCT137，AiP74HCT139，AiP74HC147，AiP74HCT147，AiP74HCT148，AiP74HC237，AiP74HCT237，AiP74HC238，AiP74HCT238•数字复用器AiP74HC151，AiP74HCT151，AiP74HC153，AiP74HCT153，AiP74HCT157，AiP74HC158，AiP74HCT158，AiP74HC251，AiP74HCT251，AiP74HC253，AiP74HCT253，AiP74HC257，AiP74HCT257，AiP74HC258，AiP74HCT258•触发器AiP74HCT74，AiP74HCT273，AiP74HCT374，AiP74HC534，AiP74HCT534，AiP74HC564，AiP74HCT564，AiP74HCT574•锁存器AiP74HCT373，AiP74HCT563•计数器AiP74HC160，AiP74HCT160，AiP74HC161，AiP74HCT161，AiP74HC162，AiP74HC162，AiP74HC163，AiP74HCT163，AiP74HC190，AiP74HCT190，AiP74HCT191，AiP74HCT192，AiP74HCT193•数字比较器/多频振荡器/奇偶校验器/全加器AiP74HC85，AiP74HCT85，AiP74HCT123，AiP74HC280，AiP74HCT280，AiP74HC283，AiP74HCT283>> 有现货产品如下：•门电路AiP74LVC00，AiP74LVC08，AiP74LVC32，AiP74LVC1G00，AiP74LVC1G08，AiP74LVC1G27，AiP74LVC1G32，AiP74LVC1G38，AiP74LVC1G86，AiP74LVC2G08 •反相器/缓冲器/驱动器/收发器AiP74LVC04，AiP74LVC1G04，AiP74LVC1G07，AiP74LVC1G14，AiP74LVC1G17，AiP74LVC1G125，AiP74LVC1G126，AiP74LVC2G04，AiP74LVC2GU04，AiP74LVC2G14，AiP74LVC2G34•编码器/译码器AiP74LVC138，AiP74LVC1G18•数字复用器AiP74LVC157，AiP74LVC1G157•触发器AiP74LVC74，AiP74LVC1G74>> 可接受提前一个月订货产品如下：•门电路AiP74LVC02，AiP74LVC03，AiP74LVC10，AiP74LVC11，AiP74LVC20，AiP74LVC27，AiP74LVC30，AiP74LVC86，AiP74LVC132，AiP74LVC1G02，AiP74LVC1G10，AiP74LVC1G11，AiP74LVC1G57，AiP74LVC1G58，AiP74LVC1G97，AiP74LVC1G98，AiP74LVC1G99，AiP74LVC1G332，AiP74LVC1G386，AiPLVC2G00，AiPLVC2G02，AiPLVC2G32，AiPLVC2G38，AiPLVC2G86•反相器/缓冲器/驱动器/收发器AiP74LVCU04，AiP74LVC05，AiP74LVC06，AiP74LVC07，AiP74LVC14，AiP74LVC17，AiP74LVC125，AiP74LVC126，AiP74LVC240，AiP74LVC244，AiP74LVC245，AiP74LVC365，AiP74LVC367，AiP74LVC541，AiP74LVC623，AiP74LVC1GU04，AiP74LVC1G06，AiP74LVC1G34，AiP74LVC2G06，AiP74LVC2G07，AiP74LVC2G16，AiP74LVC2G17，AiPLVC2G125，AiPLVC2G126，AiPLVC2G240，AiPLVC2G241•编码器/译码器AiP74LVC139，AiP74LVC1G16，AiPLVC1G19•数字复用器AiP74LVC153，AiP74LVC251，AiP74LVC257•触发器AiP74LVC273，AiP74LVC374，AiP74LVC377，AiP74LVC574AiPLVC1G79，AiPLVC1G80，AiPLVC1G175•锁存器AiP74LVC373，AiP74LVC573•移位寄存器AiP74LVC594，AiP74LVC595以上是“奥伟斯科技”分享的产品信息，如果您需要订购此款物料，请查看我们的官网与我们联系，非常感谢您的关注与支持！奥伟斯科技提供专业的智能电子锁触摸解决方案,并提供电子锁整套的芯片配套:低功耗触摸芯片、低功耗单片机、马达驱动芯片、显示驱动芯片、刷卡芯片、时针芯片、存储芯片、语音芯片、低压MOS管、TVS二极管；中微爱芯LCD显示驱动IC：AiP31107 AiP31107E AiP31108、AiP31108U、AiP31108E、AiP31066 AiP31066LC AiP31068 AiP31065 AiP31065L AiP31063 AiP31086U AiP31020 AiP31021 AiP31520 CS1621 AIP31621D AIP31621E CS1622 CS75823优势产品未尽详细，欢迎查询！。
半导体传感器AD7477ARTZ-REEL中文规格书
REV.–2–AD744–SPECIFICATIONS(@ +25؇C and ؎15 V dc, unless otherwise noted)AD744J/A/S AD744K/B/T ModelConditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE 1Initial Offset0.3 1.00.250.5mV OffsetT MIN to T MAX 2 1.0mV vs. Temp.520510µV/°C vs. Supply 2829588100dB vs. SupplyT MIN to T MAX 8288dB Long-Term Stability1515µV/month INPUT BIAS CURRENT 3Either InputV CM = 0 V 3010030100pA Either Input @ T MAX =V CM = 0 V J, K70°C 0.7 2.30.7 2.3nA A, B, C85°C 1.9 6.4 1.9 6.4nA S, T125°C 3110231102nA Either InputV CM = +10 V 4015040150pA Offset CurrentV CM = 0 V 20501050pA Offset Current @ T MAX =V CM = 0 V J, K70°C 0.4 1.10.2 1.1nA A, B, C85°C 1.3 3.20.6 3.2nA S, T125°C 20521052nA FREQUENCY RESPONSEGain BW, Small SignalG = –1813913MHz Full Power ResponseV O = 20 V p-p 1.2 1.2MHz Slew Rate, Unity GainG = –145755075V/µs Settling Time to 0.01%4G = –10.50.750.50.75µs Total Harmonicf = 1 kHz DistortionR1 ≥ 2 k ΩV O = 3 V rms 0.00030.0003%INPUT IMPEDANCEDifferential3 ϫ 1012||5.5 3 ϫ 1012||5.5Ω||pF Common Mode3 ϫ 1012||5.5 3 ϫ 1012||5.5Ω||pF INPUT VOLTAGE RANGEDifferential 5±20±20V Common-Mode Voltage+14.5, –11.5+14.5, –11.5V Over Max Operating Range 6–11+13–11+13V Common-ModeRejection Ratio V CM = ±10 V 78888288dB T MIN to T MAX 76848084dB V CM = ±11 V 72847884dB T MIN to T MAX 70807480dB INPUT VOLTAGE NOISE 0.1 to 10 Hz 22µV p-p f = 10 Hz 4545nV/√Hz f = 100 Hz 2222nV/√Hz f = 1 kHz 1818nV/√Hz f = 10 kHz 1616nV/√Hz INPUT CURRENT NOISE f = 1 kHz 0.010.01pA/√Hz OPEN LOOP GAIN 7V O = ±10 V R LOAD ≥ 2 k Ω200400250400V/mV T MIN to T MAX 100100V/mV OUTPUT CHARACTERISTICS Voltage R LOAD ≥ 2 k Ω+13, –12.5+13.9, –13.3+13, –12.5+13.9, –13.3V T MIN to T MAX ±12+13.8, –13.1±12+13.8, –13.1V Current Short Circuit 2525mA Capacitive Load 8Gain = –110001000pF POWER SUPPLY Rated Performance ±15±15V Operating Range ±4.5±18±4.5±18V Quiescent Current 3.5 5.0 3.5 4.0mA NOTES1Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.2PSRR test conditions: +V S = 15 V, –V S = –12 V to –18 V and +V S = +12 V to +18 V, –V S = –15 V.3Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperature, the current doubles every 10°C.4Gain = –1, R L = 2 k, C L = 10 pF, refer to Figure 25.5Defined as voltage between inputs, such that neither exceeds ±10 V from ground.6Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.7Open-Loop Gain is specified with V OS both nulled and unnulled.8Capacitive load drive specified for C COMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/µs and 0.01% settling time = 1.5 µs typical.Refer to Table II for optimum compensation while driving a capacitive load.Specifications subject to change without notice. All min and max specifications are guaranteed.DREV. AD744–4––Typical Characteristics Figure 1.Input Voltage Swing vs. Supply VoltageFigure 4.Quiescent Current vs.Supply VoltageFigure 7.Input Bias Current mon-Mode Voltage Figure 2.Output Voltage Swing vs. Supply Voltage Figure 5.Input Bias Current vs.Temperature Figure 8.Short Circuit Current Limit vs. Temperature Figure 3.Output Voltage Swing vs.Load Resistance Figure 6.Output Impedance vs.Frequency Figure 9.Gain Bandwidth Product vs. TemperatureD。
半导体传感器AD7472ARUZ中文规格书
AD7476/AD7477/AD7478Rev. F | Page 12 of 24TERMINOLOGYIntegral NonlinearityThis is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476/AD7477, the endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. For the AD7478, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (such as AGND + 0.5 LSB). For the AD7478, this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (such as AGND + 1 LSB).Gain ErrorFor the AD7476/AD7477, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as V REF – 1.5 LSB) after the offset error has been adjusted out. For the AD7478, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as V REF – 1 LSB) after the offset error has been adjusted. Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns into track mode after the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after the end of conversion. See the Serial Interface section for more details. Signal-to-(Noise + Distortion) RatioThis is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S /2), excluding dc.The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given bySignal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB; for a 10-bit converter it is 62 dB; and for an 8-bit converter it is 50 dB. Total Unadjusted Error This is a comprehensive specification that includes gain error, linearity error, and offset error. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7476/ AD7477/AD7478, it is defined as: ()12625242322log 20dB V V V V V V THD ++++=where V 1 is the rms amplitude of the fundamental and V 2, V 3, V 4, V 5, and V 6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S /2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7476/AD7477/AD7478 are tested using the CCIF standard where two input frequencies are used (fa = 498.7 kHz and fb = 508.7 kHz). In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB.AD7476/AD7477/AD7478Rev. F | Page 18 of 24SERIAL INTERFACESixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/ AD7477/AD7478. Figure 23, Figure 24, and Figure 25 show the detailed timing diagrams for serial interfacing to the AD7476, AD7477, and AD7478, respectively. The serial clock provides the conversion clock and controls the transfer of information from the part during conversion. CS going low provides the first leading zero to be read by the microcontroller or DSP . The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge, although the first leading zero has to be read on the first SCLK falling edge after the CS falling edge. Therefore, the first rising edge of SCLK after the CS falling edge provides the second leading zero. The 15th rising SCLK edge has DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input at this point. The conversion initiates and requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold goes back into track on the next SCLK rising edge as shown at Point B in , , and . On the sixteenth SCLK falling edge, the SDATA line will go back into three-state. If the rising edge of Figure 23Figure 24Figure 25CS occurs before 16 SCLKs have elapsed, the conversion terminates and the SDATA line goes back into three-state; otherwise, SDATAreturns to three-state on the 16th SCLK falling edge as shown in , , and .Figure 23Figure 24Figure 2501Figure 23. AD7476 Serial Interface Timing Diagram01Figure 24. AD7477 Serial Interface Timing Diagram010Figure 25. AD7478 Serial Interface Timing Diagram。
7406芯片
Hitachi CodeJEDECEIAJWeight (reference value)DP-14ConformsConforms0.97 gUnit: mmHitachi CodeJEDECEIAJWeight (reference value)FP-14DA—Conforms0.23 gUnit: mm*Dimension including the plating thickness Base material dimension° – 8°Hitachi Code JEDEC EIAJ Weight (reference value)FP-14DN Conforms Conforms0.13 gUnit: mm°– 8°*Pd platingCautions 1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you havereceived the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularlyfor maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document withoutwritten approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.Hitachi Asia Pte. Ltd.16 Collyer Quay #20-00Hitachi Tower Singapore 049318Tel: 535-2100Fax: 535-1533URL NorthAmerica : http:/Europe : /hel/ecg Asia (Singapore): .sg/grp3/sicd/index.htm Asia (Taiwan): /E/Product/SICD_Frame.htm Asia (HongKong): /eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105)Tel: <886> (2) 2718-3666Fax: <886> (2) 2718-8180Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components)7/F., North Tower, World Finance Centre,Harbour City, Canton Road, Tsim Sha Tsui,Kowloon, Hong Kong Tel: <852> (2) 735 9218Fax: <852> (2) 730 0281 Telex: 40815 HITEC HXHitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham RoadMaidenheadBerkshire SL6 8YA, United KingdomTel: <44> (1628) 585000Fax: <44> (1628) 778322Hitachi Europe GmbH Electronic components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor(America) Inc.179 East Tasman Drive,San Jose,CA 95134Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:。
ADCS7478AIMFNOPB;ADCS7478AIMFENOPB;ADCS7476AIMFNOPB;ADCS7477AIMFNOPB;中文规格书,Datasheet资料
Supply Voltage VDD Voltage on Any Analog Pin to GND
Voltage on Any Digital Pin to GND Input Current at Any Pin (Note 3) ESD Susceptibility
Human Body Model Machine Model Soldering Temperature, Infrared,
The ADCS7476/77/78 uses the supply voltage as a reference, enabling the devices to operate with a full-scale input range of 0 to VDD. The conversioial clock (SCLK) speed. These converters offer a shutdown mode, which can be used to trade throughput for power consumption. The ADCS7476/77/78 is operated with a single supply that can range from +2.7V to +5.25V. Normal power consumption during continuous conversion, using a +3V or +5V supply, is 2 mW or 10 mW respectively. The power down feature, which is enabled by a chip select (CS) pin, reduces the power consumption to under 5 µW using a +5V supply. All three converters are available in a 6-lead, SOT-23 package and in a 6-lead LLP, both of which provide an extremely small footprint for applications where space is a critical consideration. These products are designed for operation over the automotive/extended industrial temperature range of −40°C to +125°C.
7474芯片
7474芯片7474芯片是一种双触发D触发器，由Texas Instruments（德州仪器）公司研发与生产。
它是一款十分常用的数字电路元件，广泛应用于逻辑电路设计中，特别是时序电路的设计。
在本文中，我将介绍7474芯片的内部结构、工作原理以及应用场景。
首先，让我们来看一下7474芯片的内部结构。
7474芯片由两个D触发器组成，每个D触发器包含一个数据输入（D）和一个时钟输入（CLK）。
其中，D触发器的输出（Q）被馈送到下一个D触发器的数据输入，形成了一个级联的结构。
除此之外，每个D触发器还有一个使能端（EN），可以控制数据输入在时钟脉冲到来时是否有效，从而实现数据的存储或传输。
接下来，我们来探讨一下7474芯片的工作原理。
当时钟脉冲到来时，如果使能端为高电平，则数据输入会被写入到D触发器中，并在下一时钟脉冲到来时保持不变。
如果使能端为低电平，则数据输入不会被写入，而是保持上一次时钟脉冲到来时的状态。
这样，通过控制使能端的电平，可以实现数据的存储或传输。
在实际应用中，7474芯片常常用于时序电路设计。
例如，它可以用来实现寄存器、计数器、移位寄存器等功能。
在这些应用中，通过将多个7474芯片级联起来，可以实现更复杂的功能。
另外，7474芯片还可以用于时钟信号的整形和分频。
通过利用其存储和传输功能，可以实现对时钟信号的控制和分频操作，从而满足各种特定的时序要求。
综上所述，7474芯片是一款十分常用的数字电路元件。
它的内部结构简单，工作原理清晰。
通过合理配置使能端和时钟脉冲，可以实现数据的存储或传输，并在时序电路设计中发挥重要作用。
7474芯片在计算机硬件、通信系统等领域有着广泛的应用，为实现复杂的数字逻辑功能提供了可靠的解决方案。
芯片手册
74系列74ls48 BCD—7段译码器-内部上拉输出驱动 1 7473 TTL 带清除负触发双J-K触发器 1 7474 TTL 带置位复位正触发双D触发器 2 7476 TTL 带预置清除双J-K触发器 2 7483 TTL 四位二进制快速进位全加器 3 7485 TTL 四位数字比较器 4 7486 TTL 2输入端四异或门 5 7490 TTL 可二-五分频十进制计数器 5 7495 TTL 四位并行输入-输出移位寄存器7 74107 TTL 带清除主从双J-K触发器8 74109 TTL 带预置清除正触发双J-K触发器8 74122 TTL 可再触发单稳态多谐振荡器9 74126 TTL 三态输出低有效四总线缓冲门9 74138 TTL 3-8线译码器-复工器10 74139 TTL 双2-4线译码器-复工器11 74150 TTL 16选1数据选择-多路开关12 74154 TTL 4线—16线译码器13 74157 TTL 同相输出四2选1数据选择器14 74160 TTL 可预置BCD异步清除计数器15 74165 TTL 八位并行入-串行输出移位寄存器16 74166 TTL 八位并入-串出移位寄存器16 74169 TTL 二进制四位加-减同步计数器17 74173 TTL 三态输出四位D型寄存器18 74174 TTL 带公共时钟和复位六D触发器18 74175 TTL 带公共时钟和复位四D触发器19 74180 TTL 9位奇数-偶数发生器-校验器20 74185 TTL 二进制—BCD代码转换器21 74192 TTL 可预置BCD双时钟可逆计数器22 74194 TTL 四位双向通用移位寄存器22 74197 TTL 二进制可预置锁存器-计数器23 74245 TTL 八同相三态总线收发器23 74247 TTL BCD—7段15V输出译码-驱动器23 74248 TTL BCD—7段译码-升压输出驱动器24 74273 TTL 带公共时钟复位八D触发器24 74299 TTL 三态输出八位通用移位寄存器25 74323 TTL 三态输出八位双向移位-存贮寄存器25CD系列4008 CMOS 4位二进制并行进位全加器26 4013 CMOS 带置位-复位的双D触发器28 4014 CMOS 8级同步并入串入-串出移位寄存器294015 CMOS 双4位串入-并出移位寄存器29 4021 CMOS 异步8位并入同步串入-串出寄存器30 4027 CMOS 带置位复位双J-K主从触发器32 4028 CMOS BCD- 十进制译码器32 4030 CMOS 四异或门33 4042 CMOS 四时钟控制D 锁存器34 4043 CMOS 四三态或非R-S 锁存器36 4051 CMOS 8选1双向模拟开关36 4052 CMOS 双4选1双向模拟开关37 4056 CMOS BCD—7段译码-驱动器39 4070 CMOS 四异或门40 4077 CMOS 四异或非门41 4094 CMOS 8级移位存储总线寄存器42 4099 CMOS 八位可寻址锁存器42 4502 CMOS 可选通六反相缓冲器43 4503 CMOS 六三态同相缓冲器44 4506 CMOS 双二组2输入可扩展与或非门45 4511 CMOS BCD-7段锁存-译码-LED驱动47 4512 CMOS 8通道数据选择器48 4513 CMOS BCD-7段译码-锁存-驱动器49 4514 CMOS 四位锁存-4-16高有效译码器50 4515 CMOS 四位锁存-4-16低有效译码器51 4528 CMOS 双单稳态多谐振荡器52 4529 CMOS 双四路或单八路模拟开关53 4531 CMOS 12位奇偶校验电路54 4538 CMOS 双精密单稳多谐振荡器55 4539 CMOS 双四路数据选择器-多路开关56 4541 CMOS 可编程振荡器-计时器57 4543 CMOS BCD-7段译码-锁存-液晶驱动器58 4544 CMOS BCD-7段译码-消隐-驱动器59 4547 CMOS BCD-7段译码-大电流驱动器60 4549 CMOS 逐级近似寄存器61 4553 CMOS 3位数BCD计数器62 4557 CMOS 1-64位可变字长移位寄存器62 4558 CMOS BCD-7段译码器63 4559 CMOS 逐级近似寄存器64 4560 CMOS BCD全加器65 4561 CMOS “9”补码电路66 4568 CMOS 相位比较器-可编辑计数器66 4583 CMOS 双多能施密特触发器67 4585 CMOS 4位数字比较器68 40110 CMOS 十进制加减计数-译码-锁存-驱动69 40117 CMOS 10线—4线BCD优先编码器70 40174 CMOS 六D触发器7140175 CMOS 四D触发器71 40181 CMOS 4位算术逻辑单元72 40257 CMOS 四2线-1线数据选择器-多路传输73光电耦合4n35-36-37光电藕合器（达林顿输出）74 4n25 26 74 6n137光电藕合器74 std4nb25 光电藕合器75 6n136 75 Tlp521光电藕合器76 4n25光电藕合器76模拟集成电路Ua741高增益运放77 Ua725高精度运算放大器77 ICL7650斩波稳零运放78 LM358双运放78 CMOS集成四运放79 LM324四运放7974系列74ls48 BCD—7段译码器-内部上拉输出驱动7473 TTL 带清除负触发双J-K触发器7474 TTL 带置位复位正触发双D触发器7476 TTL 带预置清除双J-K触发器7483 TTL 四位二进制快速进位全加器7485 TTL 四位数字比较器7486 TTL 2输入端四异或门7490 TTL 可二-五分频十进制计数器7495 TTL 四位并行输入-输出移位寄存器74107 TTL 带清除主从双J-K触发器74109 TTL 带预置清除正触发双J-K触发器74122 TTL 可再触发单稳态多谐振荡器74126 TTL 三态输出低有效四总线缓冲门74138 TTL 3-8线译码器-复工器74139 TTL 双2-4线译码器-复工器74150 TTL 16选1数据选择-多路开关74153 TTL 双4选1数据选择器74154 TTL 4线—16线译码器74157 TTL 同相输出四2选1数据选择器74160 TTL 可预置BCD异步清除计数器十进制同步计数器（异步清除）74165 TTL 八位并行入-串行输出移位寄存器74166 TTL 八位并入-串出移位寄存器74169 TTL 二进制四位加-减同步计数器74173 TTL 三态输出四位D型寄存器74174 TTL 带公共时钟和复位六D触发器74175 TTL 带公共时钟和复位四D触发器74180 TTL 9位奇数-偶数发生器-校验器74185 TTL 二进制—BCD代码转换器74192 TTL 可预置BCD双时钟可逆计数器74194 TTL 四位双向通用移位寄存器74197 TTL 二进制可预置锁存器-计数器74245 TTL 八同相三态总线收发器74247 TTL BCD—7段15V输出译码-驱动器74248 TTL BCD—7段译码-升压输出驱动器74273 TTL 带公共时钟复位八D触发器74299 TTL 三态输出八位通用移位寄存器74323 TTL 三态输出八位双向移位-存贮寄存器CD系列4008 CMOS 4位二进制并行进位全加器4013 CMOS 带置位-复位的双D触发器4014 CMOS 8级同步并入串入-串出移位寄存器4015 CMOS 双4位串入-并出移位寄存器4021 CMOS 异步8位并入同步串入-串出寄存器4027 CMOS 带置位复位双J-K主从触发器4028 CMOS BCD- 十进制译码器4030 CMOS 四异或门4042 CMOS 四时钟控制D 锁存器4043 CMOS 四三态或非R-S 锁存器4051 CMOS 8选1双向模拟开关、4052 CMOS 双4选1双向模拟开关4056 CMOS BCD—7段译码-驱动器4070 CMOS 四异或门4077 CMOS 四异或非门4094 CMOS 8级移位存储总线寄存器4099 CMOS 八位可寻址锁存器4502 CMOS 可选通六反相缓冲器4503 CMOS 六三态同相缓冲器4506 CMOS 双二组2输入可扩展与或非门4511 CMOS BCD-7段锁存-译码-LED驱动。
ADI方案
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 •
AD7746的EMC保护
作者：Holger Grothe和Mary McCarthy
差分模式 采样时钟 = 32 kHz 连续转换模式 增益 = 1 斩波禁用 激励电压 = VDD/2 转换时间 = 62.1 ms
使用一个固定4 pF电容来代替传感器。此电容产生接近满 量程的转换。为了确保在RF干扰期间AD7746转换不超出 范围，人为缩小输入电容。
Rev. 0 | Page 4 of 20
什么是EMC？
电磁兼容性(EMC)是指没有对环境造成电磁辐射并且能在 电磁辐射环境中工作的能力。当达到这个目标时，所有的 电子设备可以与其它设备一起正常工作。一个系统中包含 多个EMC耦合路径：空间耦合、传导耦合、电感耦合和电 容耦合(见表1)。
Rev. 0 | Page 1 of 20
08743-001
EMC SOURCE DEVICE 1
RADIATIVE COUPLING
EMC SINK DEVICE 2
CONDUCTIVE COUPLING
图1.EMC耦合路径
针对恶劣环境设计系统时，必须将EMC考虑在内且必须在 设计阶段进行EMC测试。EMC测试分为不同的级别：系统 级测试、子系统级测试和IC级测试。测试方法根据每个 EMC测试级别进行定义。 对一个子系统或者一颗IC器件在EMC性能上的要求取决于 器件的功能及其在系统中的位置。例如，在汽车应用中， 如果一个器件与汽车电池或底盘连接，那么它必须有较高 的EMC性能。如果器件局限于印制电路板(PCB)区域内， 那么它对EMC级别的要求较少。 AD7746是一款集成电路：因此，依据国际标准IEC62132第 4部分，用直接功率注入进行EMC测试。AD7746局限于 PCB区域内并与传感器有局部连接。因此，电磁干扰的级 别会较低。
基于FPGA和高速串行接口AD转换器AD7476的接口应用
线 性序列机，Ｆ Ｐ Ｇ Ａ， 数据采集 ， 接口
中图分类号 ： Ｔ Ｐ ２ １
４ ． 结语
基于 Ｆ Ｐ Ｇ Ａ与 高 速 串 行 口 Ａ Ｄ转 换 器
功能全面 ， 性价 比高。 Ａ Ｄ ７ ４ ７ ６支持高速 串行 Ａ Ｄ ７ ４ ７ ６， 本 文 论 述 了线 性 序 列机 的设 计 思
信， 信号处 理等领域。将 Ｆ Ｐ Ｇ Ａ编程的灵活性 成 Ａ Ｄ ７ ４ ７ ６的接 口设 计。软 件发 起 控制 命令
和高速 串行接 口的可靠性结合 ， 实现 Ａ Ｄ ７ ４ ７ ６ 后 ， 产生 Ａ Ｄ — Ｓ Ｔ Ａ Ｒ Ｔ脉 冲 信号 ， 标志 开 始采 【 参考文献】 的数 据采集功能。 集． 计数 器开始计 数．与计 数器相 配合 ， 根据 Ａ Ｄ ７ ４ ７ ６的时序要求发 出相应的控制信号 。在 时序控 制电路的作 用下 ， 将 １ ６ 位 串行总线的
沿由移位寄存器移动到 Ｓ Ｄ Ａ Ｔ Ａ信号线 ［ ２ １ ， 经过 在 Ｍｏ ｄ ｅ ｌ ｓ ｉ ｍ 进行 测试。时序仿 真结 果如图 ４ １ ６ 次的时钟信号 ， 完成 １ ６ 位数据的传输 。
所示 ， 基于线性序列机 思想 ， 实现了 Ａ Ｄ芯 片
２ ． 基于 Ｆ Ｐ Ｇ Ａ 的高 速串行 接口设计
接口标准。 Ｆ Ｐ Ｇ Ａ作为可编程逻辑器件 ， 以其
高性能和灵活性广泛应用在接 口逻辑 ， 数据通
Ｆ Ｐ Ｇ Ａ内部高速串行控 制电路采用 Ｖ ｅ ｒ ｉ ｌ ｏ ｇ 信 ， 为储罐底板漏磁检测 系统提 供了方便、快
Ｈ Ｄ Ｌ 语言 编程 ． 基于 线性 序列机 的思 想 ． 完 捷和可靠的接 口解决方案。
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・
—
０ ＋
ad7746例子程序
ad7746例子程序AD7746是一款高精度电容传感器，可用于测量压力、湿度、流量等物理量。
它具有多个特性和优势，下面将详细介绍其中的几个方面。
一、高精度测量AD7746采用了自校准技术，能够实现非常精确的电容测量。
它能够测量微小的电容变化，从而提供高精度的物理量测量结果。
这使得AD7746在许多应用中都得到了广泛的应用，比如医疗设备、工业自动化等领域。
二、灵活的接口AD7746提供了多种接口，包括I2C和SPI接口，使得它能够与各种微控制器和处理器进行通信。
这使得AD7746可以方便地集成到现有的系统中，与其他传感器和设备进行协同工作。
三、低功耗设计AD7746采用了低功耗设计，能够在工作时保持较低的功耗。
这使得它非常适合那些对电池寿命要求较高的应用，比如便携式设备和无线传感网络。
四、温度补偿AD7746具有温度补偿功能，能够自动校正由于温度变化引起的测量误差。
这使得它在温度变化较大的环境下仍能提供准确的测量结果。
五、可编程增益和滤波器AD7746具有可编程增益和滤波器功能，能够根据具体的应用需求进行调整。
这使得它可以适应不同范围和精度的测量要求，并提供更加稳定和可靠的测量结果。
六、多种应用领域由于AD7746具有高精度、灵活的接口和低功耗等特点，它在许多应用领域都得到了广泛的应用。
比如，它可以用于医疗设备中的体温测量、血压监测等；在工业自动化中可以用于流量测量、液位检测等；还可以用于环境监测中的湿度测量、气体检测等。
七、可靠性和稳定性AD7746采用了先进的工艺和设计，具有较高的可靠性和稳定性。
它能够在各种恶劣的环境条件下正常工作，并能够长时间稳定地提供准确的测量结果。
八、成本效益高尽管AD7746具有高精度和多种功能，但其价格相对较低，性价比较高。
这使得它成为许多应用中的首选传感器之一。
九、易于集成和使用AD7746具有简单的接口和易于使用的软件开发工具，使得它很容易进行集成和开发。
即使是对于没有深入了解传感器的开发人员来说，也可以很快地上手使用AD7746进行测量。
艾瓦特芯片规格书
艾瓦特芯片规格书如下：一、产品概述艾瓦特芯片是专为高性能计算和人工智能应用设计的高端芯片。
它采用最先进的7纳米工艺制造，具有高性能、低功耗和低热量排放的特点。
艾瓦特芯片支持并行计算，可以高效处理大规模数据和算法，是提高计算性能的关键组件。
二、技术规格1. 工艺技术：7纳米工艺制造2. 核心数量：双核心3. 内存带宽：高达51.2GB/s4. 计算能力：强大的计算能力，适用于高性能计算和人工智能应用5. 能耗：低功耗设计，适合节能环保6. 热量排放：先进的散热技术，确保芯片在高负荷运行时稳定可靠7. 工作温度：工作温度范围宽广，适应各种环境和使用场景三、性能特点1. 高性能：艾瓦特芯片采用并行计算架构，可高效处理大规模数据和算法，提高计算性能。
2. 高效能比：在相同的计算任务下，艾瓦特芯片的性能比传统处理器高得多。
3. 节能环保：低功耗设计和先进的散热技术，确保芯片在长时间运行和高温环境下稳定可靠。
4. 兼容性：艾瓦特芯片兼容现有的软件和硬件系统，方便用户使用。
四、应用领域艾瓦特芯片适用于各种高性能计算和人工智能应用，如大数据分析、云计算、机器学习和深度学习等。
它能够为各种应用提供强大的计算能力，提高工作效率和性能比。
五、生产与品质艾瓦特芯片采用最先进的生产工艺，确保产品的高品质和高稳定性。
我们的质量控制流程严格遵循行业标准，从原料到成品进行全面检测，确保产品的性能和质量达到最高水平。
六、服务与支持我们提供全面的售后服务和技术支持，包括产品咨询、故障排除、解决方案提供等。
我们承诺在第一时间解决客户的问题，确保客户的利益和满意度。
以上就是艾瓦特芯片的规格书，我们致力于为客户提供高性能、稳定可靠的产品，帮助客户实现更高的计算性能和效率。
半导体传感器AD7476ARTZ-REEL7中文规格书
AD7476/AD7477/AD7478Rev. F | Page 18 of 24SERIAL INTERFACESixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/ AD7477/AD7478. Figure 23, Figure 24, and Figure 25 show the detailed timing diagrams for serial interfacing to the AD7476, AD7477, and AD7478, respectively. The serial clock provides the conversion clock and controls the transfer of information from the part during conversion. CS going low provides the first leading zero to be read by the microcontroller or DSP . The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge, although the first leading zero has to be read on the first SCLK falling edge after the CS falling edge. Therefore, the first rising edge of SCLK after the CS falling edge provides the second leading zero. The 15th rising SCLK edge has DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input at this point. The conversion initiates and requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold goes back into track on the next SCLK rising edge as shown at Point B in , , and . On the sixteenth SCLK falling edge, the SDATA line will go back into three-state. If the rising edge of Figure 23Figure 24Figure 25CS occurs before 16 SCLKs have elapsed, the conversion terminates and the SDATA line goes back into three-state; otherwise, SDATAreturns to three-state on the 16th SCLK falling edge as shown in , , and .Figure 23Figure 24Figure 2501Figure 23. AD7476 Serial Interface Timing Diagram01Figure 24. AD7477 Serial Interface Timing Diagram010Figure 25. AD7478 Serial Interface Timing DiagramAD7476/AD7477/AD7478Rev. F | Page 19 of 24MICROPROCESSOR INTERFACINGThe serial interface on the AD7476/AD7477/AD7478 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7476/AD7477/AD7478 with some of the more common microcontroller and DSP serial interface protocols. AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7476/ AD7477/AD7478. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without any glue logic required. In addition, the serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format bit, FO, can be set to 1 to set the word length to eight bits, in order to implement the power-down mode on the AD7476/ AD7477/AD7478. The connection diagram is shown in Figure 26. Note that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provides equidistant sampling. 01024-0261ADDITIONAL PINS OMITTED FOR CLARITY Figure 26. Interfacing to the TMS320C5x/C54x AD7476/AD7477/AD7478 to ADSP-21xx Interface The ADSP-21xx family of DSPs are interfaced directly to theAD7476/AD7477/AD7478 without any glue logic required. The SPORT control register is set up as follows:TFSW = RFSW = 1, Alternate FramingINVRFS = INVTFS = 1, Active Low Frame SignalDTYPE = 00, Right Justify DataSLEN = 1111, 16-Bit Data-WordsISCLK = 1, Internal Serial ClockTFSR = RFSR = 1, Frame Every WordIRFS = 0ITFS = 1To implement the power-down mode, SLEN is set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 27. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt controls the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved. The timer registers, for example, are loaded with a value thatprovides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS controls the RFS and, therefore, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, such as, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data could be transmitted, or it could wait until the next clock edge.For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, a SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur betweeninterrupts and, subsequently, between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If thenumber of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP .01024-0271ADDITIONAL PINS OMITTED FOR CLARITY Figure 27. Interfacing to the ADSP-21xx AD7476/AD7477/AD7478 to DSP56xxx Interface The connection diagram in Figure 28 shows how the AD7476/ AD7477/AD7478 can be connected to the synchronous serial interface (SSI) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB =1) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode on the AD7476/AD7477/ AD7478, the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. Note that for signal process-ing applications, it is imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling.。
半导体传感器ADG711BRZ中文规格书
−65
−65
dB max
Intermodulation Distortion (IMD)3
Second-Order Terms
−68
−68
dB typ
Third-Order Terms
−68
−68
dB typ
Aperture Delay
10
10
ns typ
Aperture Jitter
30
30
ps typ
VDD – 0.2
VDD – 0.2
0.4
0.4
±10
±10
10
10
Straight Natural) Binary
V min V max μA max pF max
Conversion Time Track-and-Hold Acquisition Time Throughput Rate
800
A Version1,2 S Version1,2 Unit
Signal-to-(Noise + Distortion) (SINAD)
61
61
dB min
Total Harmonic Distortion (THD)3
−73
−73
dB max
Peak Harmonic or Spurious Noise (SFDR)3
VDD − 0.2
VDD − 0.2
0.4
0.4
±10
±10
10
10
Straight (Natural) Binary
V min V max μA max pF max
Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS
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20057718
2
ADCS7476/ADCS7477/ADCS7478
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Description 6-Lead SOT-23 Package, 1000 Units Tape & Reel 6-Lead SOT-23 Package, 1000 Units Tape & Reel 6-Lead SOT-23 Package, 1000 Units Tape & Reel 6-Lead SOT-23 Package, 3000 Units Tape & Reel
2 mW (typ) 10 mW (typ)
Applications
■ Automotive Navigation ■ FA/ATM Equipment ■ Portable Systems ■ Medical Instruments ■ Mobile Communications ■ Instrumentation and Control Systems
Package 6-Lead SOT-23
θJA 265°C / W
6-Lead LLP
78°C / W
ADCS7476/ADCS7477/ADCS7478 Specifications (Note 2)
Connection Diagram
20057701
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation 200577
Operating Temperature Range
TMIN = −40°C ≤ TA ≤
TMAX = +125°C
VDD Supply Voltage
+2.7V to +5.25V
Digital Input Pins Voltage Range (Note
4)
+2.7V to +5.25V
Package Thermal Resistance
Features
■ Variable power management ■ Packaged in 6-lead, SOT-23 and LLP ■ Power supply used as reference ■ Single +2.7V to +5.25V supply operation ■ SPI™/QSPI™/MICROWIRE™/DSP compatible
General Description
The ADCS7476, ADCS7477, and ADCS7478 are low power, monolithic CMOS 12-, 10- and 8-bit analog-to-digital converters that operate at 1 MSPS. The ADCS7476/77/78 are dropin replacements for Analog Devices' AD7476/77/78. Each device is based on a successive approximation register architecture with internal track-and-hold. The serial interface is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces.
6-Lead LLP, 3000 Units Tape & Reel 6-Lead SOT-23 Package, 3000 Units Tape & Reel
6-Lead LLP, 3000 Units Tape & Reel 6-Lead SOT-23 Package, 3000 Units Tape & Reel
1
ቤተ መጻሕፍቲ ባይዱ
VDD
2
GND
Block Diagram
Description
Analog input. This signal can range from 0V to VDD.
Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with guaranteed performance at 20 MHz. This clock directly controls the conversion and readout processes. Digital data output. The output words are clocked out of this pin by the SCLK pin. Chip select. A conversion process begins on the falling edge of CS.
10 seconds Junction Temperature Storage Temperature
−0.3V to +6.5V −0.3V to VDD +0.3V
-0.3V to 6.5V ±10 mA
3500V 200V
215°C +150°C −65°C to +150°C
Operating Ratings
6-Lead LLP, 3000 Units Tape & Reel 6-Lead SOT-23 Package, 250 Units Tape & Reel 6-Lead SOT-23 Package, 250 Units Tape & Reel 6-Lead SOT-23 Package, 250 Units Tape & Reel
ADCS7476/ADCS7477/ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP
ADCS7476 ADCS7477 ADCS7478
February 17, 2010
1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin. The ADCS7476/77/78 uses this power supply as a reference, so it should be thoroughly bypassed. The ground return for the supply.
Supply Voltage VDD Voltage on Any Analog Pin to GND
Voltage on Any Digital Pin to GND Input Current at Any Pin (Note 3) ESD Susceptibility
Human Body Model Machine Model Soldering Temperature, Infrared,
The ADCS7476/77/78 uses the supply voltage as a reference, enabling the devices to operate with a full-scale input range of 0 to VDD. The conversion rate is determined from the serial clock (SCLK) speed. These converters offer a shutdown mode, which can be used to trade throughput for power consumption. The ADCS7476/77/78 is operated with a single supply that can range from +2.7V to +5.25V. Normal power consumption during continuous conversion, using a +3V or +5V supply, is 2 mW or 10 mW respectively. The power down feature, which is enabled by a chip select (CS) pin, reduces the power consumption to under 5 µW using a +5V supply. All three converters are available in a 6-lead, SOT-23 package and in a 6-lead LLP, both of which provide an extremely small footprint for applications where space is a critical consideration. These products are designed for operation over the automotive/extended industrial temperature range of −40°C to +125°C.