BCD PROCESS

A Study on Process Integration of HighVoltage BCDMOS ICAbstractHV-BCDMOS-IC is a sort of complex circuit composed of Bipolar, CMOS andLDMOS devices. In this paper, a 600V RESURF LDMOS with a p-type buriedlayer and the metal field plate is proposed for improving the surface electricfield and reducing the on-resistance of LDMOS. A 600V BCD technology basedon standard Bi-CMOS process is realized by adding PN isolation, double welland other optimized processes. With the process simulator TSUPREM-4 and 2-Ddevice simulator MEDICI, the processes and structures of different devices havebeen simulated and optimized, especially for the HV-LDMOS. Using thistechnology we developed a power IC. The test results show a good consistencywith that we have expected. The 600V BCD technology thus can be used in thedesign of HVIC.Keywords: BCD technology; RESURF; LDMOS; Field Plate1IntroductionThe rapidly growing market of monolithic smart power IC’s (SPIC) greatly accelerates the evolution of BCD technology. Today’s smart power applications require IC control devices in the 50-1200V range. These technologies combine Bipolar, CMOS and power DMOS devices on a single chip. Compared with the traditional bipolar power technology, BCD technology has an obvious advantage. The designers of the BCD have more spaces to choose among high density and low power consumption of CMOS, high power drive capability and high speed of bipolar and large current and high breakdown voltage of DMOS [1]-[5]. A great many researches have been done by researchers both at home and abroad [6]-[11]. Now the research direction is along high voltage, high power and high density. As for high voltage, the key problem is the design of DMOS device and the process of integrating it with low voltage devices. The BCD technology abroad has already been very mature, but little research work has been done at home. In order to fill such vacancies, we conducted this investigation.In this paper, the RESURF-LDMOS with lateral double diffused structure, p-type buried layer and metal field plate was proposed to achieve the demand of integration on HVIC. Research was mainly on the choosing of materials, adjusting of impurity concentration, controlling of thedepth of the junctions, and the optimizing of the structure of HV devices. Based on the research of 600V LDMOS, a new process that can integrate the LDMOS with standard Bi-CMOS has been developed. PN isolation, double well and other optimized processed have also been used. The experimental results show that this technology can be used in the design of HVIC.2The optimization of structure on HV-LDMOS2.1The stru cture of LDMOSLDMOS is a lateral power device with double diffused structure. The channel length is decided by the length of the double lateral diffused region. Figure 1 displays the LDMOS device cross section introduced in this study. This device differs from a traditional NMOS device in that it has an extended drain region under field oxide (FOX) consisting of an n-drift region and an n-layer for on-resistance control. This extended drain region supports the high voltages applied to this device. The poly silicon gate extends over a thin gate oxide and the body (p-body) terminating on the FOX. Key LDMOS performance parameters are low onR and high drain breakdown voltage. Critical LDMOS I-D layout parameters are the distances from source to FOX edge and FOX width, since these distances must sustain the high LDMOS drain voltages.2.2D e s i gn o f H V-L DM OSBecause of the affection to the curvature in PN junction interface, the electric field in the surface tends to be larger than the maximum electric field in the body .and the breakdown voltage is decided by the surface breakdown. Meanwhile, when the impact ionization happens, the hot carriers generated in the ionization are apt to enter the silicon oxide layer and become fixed charges which will affect the distribution of the electric field, cause instability to the device and reduce the device reliability. Therefore, for this design, not only the material and structure parameters should be chosen properly to bear the breakdown voltage in a given voltage, but also some special structures should be introduced to reduce the maximum surface electric field. This design was based on the RESURF [12] theory including the buried layer and the field plate [13]-[14] techniques.2.2.1 Influence on brea kdown voltage by drift r eg io n do s e an d bu r ie d la y e r RESURF (Reduced-Surface-Field) has been extensively used in the design of High Voltage devices. The key function of it is to reduce the surface electric field by interactions of the electric fields between epitaxial layer depletion region and substrate depletion region. Thus the breakdown point will transfer from surface to the body. When these two breakdowns happen, the device will get its maximum breakdown voltage. As a result, the breakdown voltage of the device is improved. According to this rule, in order to get its maximum breakdown voltage, the drift layer must be fully depleted, and the breakdown point must be in the PN junction interface of the P-substrate and the N-drift layer [15] (A in Figure 1).The main factors that affect the breakdown voltage are the length of the drift region (d L ), the junction depth and the impurity concentration (d N ). Generally speaking, as the drift region length grows, the lateral breakdown voltage will increase. But when the length grows to a certain value, the lateral breakdown voltage remains constant. The deeper the drift region is, the higher the longitudinal breakdown voltage becomes. An analysis will be made between the drift region dose and the breakdown voltage in the following.The relation between the drift dose and breakdown characteristic has been obtained by 2D devices simulator MEDICI. And the result shows when the drift dose is too small, the breakdown voltage will be low, which is induced by the surface breakdown in the drain. When the drift dose is too large, the breakdown voltage will still stay low, which is ascribed to the avalanche breakdown in the PN junction between the channel and the drift region. As a result, too small or too large a drift dose will both do harm to the breakdown voltage. So a compromise dose should be included. According to the semiconductor device theory, we have the following equations [16],V N N q N N W a d a d s sub drift )()(2+=ε (1) )(2)(2a d s sub drifta d N N W N N q V +=ε (2)Where drift W is the width of the depletion region of the drift substrate PN junction,d N is the concentration of the n-drift region and a N the concentration of the p-type substrate. V is the backward voltage .For abrupt junction (such as drift /well junction), the breakdown voltage (BV) is,d cs drift wellc qN E W E BV 222ε== (3)Where c E is the critical electric field, drift well W is the width of the depletion region of drift/well junction.According to the RESURF theory, before the avalanche breakdown at the drift /well junction, the drift region must be fully depleted. So the following equation can be derived.222)(2)(c a d s sub dritf d a E N N W N N q ≤+ε (4) Defining D W N sub drift d =(drift dose), sub drift W is the vertical width of the depletion region when the drift region is fully depleted. The critical electric field of Si is about 4×105v/cm.If a d N N 10=，we can drive that 212108.0−×≤cm D .Because the c E we use is lower than the average. In order to get the expected device, comparing with the normal fabrication character and the simulation result, we defined 212100.1−×=cm D as a reference. The range of D was given from 212108.0−×cm to 212104.1−×cm , and the relationship between breakdown voltage and impurity concentration has been simulated by MEDICI. Finally we get the proper dose 212102.1−×=cm D and the drift region depth um W drift 6=. According to the RESURF theory, when breakdown happens in a LDMOS, the drift region is fully depleted, so we have sub drift dritf W W =. Together with the equation that has been defined before we get the concentration of the drift region 315102−×=cm N d (cm ⋅Ω=3.2ρ).In the RESURF LDMOS, p-type buried layer has also been introduced. It will decrease the curvature of equipotential lines. This electric field shaping method can ensure a thick epitaxy when given the epitaxy concentration and a high impurity concentration when given the epitaxy thickness. Both will result in a decrease in the on-resistance without any reduction of the breakdown voltage.2.2.2 Inf lue nc e o n t he b r eak d ow n v o l ta g e by t he le ng th of f ie ld pla teThe field plate technique has already been extensively applied in high voltage devices. By adding several peak electric filed to substitute the maximum peak electric field, the peak electric field in the surface will be obviously reduced. Compared with other mechanics that have the same function, this technique has the advantages that doesn’t need to an increase of the chip area and some extra process. In the following emphasis will be given to the fact that how the field plates on the right and left will affect the breakdown voltage.The metal field plate on the left is formed by the aluminum electrode extension from the source to the drain. The length of the field plate is X, and it is used to increase the breakdown voltage by reducing the peak electric field in the end of the poly-gate. As shown in Figure 2 (a), the potential lines are more intensive at the end of the poly-gate when no field gate is applied. But when metal field plate is introduced, the potential lines at the end of the poly-gate are moderated. And the peak electric field transfers from B to C, shown in Figure 2 (b). So the field plate here can play a great part in the reducing of the peak electric in the end of the poly-gate.(a) (b)Figure 2: (a) Potential distribution when X=0um(b) Potential distribution when X=6umSimilarly, the right side of the field plate can also make a decrease to the curvature of the equipotential lines and thus improve the breakdown voltage. More simulations have down by changing the length of the field plate on both side and finally a typical value that fit the design was obtained, the values are um X 6=,um K 10=.2.2.3 Influence on the breakdown voltage and on-resistance by the leng th ofd r i f t r eg i onIn order to get a high breakdown voltage, the drift region length should also be extended. But meanwhile, the width of the drift region also has to be extended for the sake of reducing the on- resistance. This is why most of the power devices always have large areas. In order to find the proper drift length, more simulations about the breakdown voltage and on-resistance have been done by MEDICI at different drift region lengths. Figure 3 shows the simulation result.Figure 3: Profiles of BV and sp on R . atDifferent d L As shown in Figure3, when d L increases, BV and sp on R . (Defined A R R on sp on ⋅=., A is the area of the device) increase at the same time. To get the expected device, we choose d L as 75um or 80um, and the simulation results are as follows,Table 1: Simulation Result when Dose is 1.2×1012cm -2Ld(um)sp on R . (Ω·um 2) Ron （W ＝2630um) (Ω) 75 23.44 118．83 8026．09124.00Table 1 shows us that onR at the given impurity concentration and the device width are more or less the same. Considering the minimum device area, finally we choose 75um as the drift length.2.3The optimu m stru cture and process parameter of LDMOSBased on the simulation of the parameters of LDMOS, such as the dose of the drift region, the length of the metal field plate, the length of the drift, finally the optimum structure and process parameters of HV-LDMOS are obtained. The impurity concentration of the p-type substrate is 1.5×1014 cm-3, the dose of the drift region is 1.2×1012 cm-2,the length of the drift region is 75um and the thickness is 6um. The length of the field plate is 6um in the source end and 10um in the drain end. Figure 4 is the cross section of the optimized LDMOS structure.Figure 4: Cross section of the LDMOS structure3Optimization design for BCDMOS processThe BCDMOS process is based on the Bi-CMOS process which has been dramatically improved. In order to get the expected device characteristic, some special structures and process have been proposed in this paper. Figure 5 is the cross section of the BCDMOS device.Figure 5: Cross section of the BCDMOSIn order to have the different devices well isolated, PN isolation was used here. As shown in Figure5, bottom isolation (BP in Figure 5) with a doping of Boron (60kev, 1.1×1012 cm-2) has been done before the epitxy procedure. This will reduce the anneal time and the impurity dose of the top isolation (GA in Figure 5) which also has a doping of Boron with the doping energy and dose 60kev, 8.0×1012 cm-2 respectively. And the epitaxy procedure will help the bottom isolation to anneal. This method can obviously increase the density of the device integration and achieve a better isolation result. To compatible with CMOS process, LOCOS isolation has also been introduced. This technique will help to the surface isolation of the device and reduce the surface current as well. T-SUPREM4 simulation results show that the LOCOS process should have a FOX thickness of 0.8um and be done at ℃1000 for 600 minutes.The double well (PW and NW in Figure 5) is used mainly to insure the performance of CMOS devices. The process parameters thus can be set independently. It will improve the CMOS parameters such as the threshold voltage, the breakdown voltage and the saturation current. It will also avoid the latch-up effect. So the concentration and the depth of the double well should be well designed. Meanwhile, the N+ buried layer can also reduce the latch-up effect and the series resistance of NPN collector [17].As shown in Figure 6, the relationship between threshold voltage and well dose has been simulated and the implantation status of p-well is 100kev, 9.0×1012cm-2. The implantation status of n-well is 80kev, 1.0×1012cm-2, and the anneal condition is 1200℃, 300 minutes.Gate oxide is most crucial for the stability of the threshold of CMOS and LDMOS, and in order to get the expected threshold, an implantation should be done to adjust the threshold voltage. Simulation results show that the threshold is proportional to the thickness of gate oxide and the dose of adjusting implantation. In this design, the thickness of the gate oxide is 450Å, and the implantation dose is 3.0×1012cm-2. The design of source and drain in CMOS and LDMOS is also very important for the device current, breakdown voltage and transconductance. Both of them have a high impurity concentration and a small junction depth. The bipolar transistor in this design also needs a high concentration in the emitter and the Ohmic contacts. So an optimized structure should be made to fulfill all the requirements and reduce the complexity and the steps of the process. After simulation, we get the implantation dose for n-type region 60kev, 3.0×1015cm-2 and p-type 40kev, 1.8×1015cm-2.(a) (b)Figure6: (a) NMOS transistor th V versus P-well dose(b) PMOS transistor th V versus N-well doseThe parasites in BCDMOS can not be omitted and measures should be taken to avoid this phenomenon. In this design, parasitic MOS transistors are formed below the thick field oxide. To prevent the conduction of the parasitic MOS channel, an adjusting implantation should be done below the field oxide. Considering the whole process, the implantation should be done after the etching of 43N Si , using the mask of n-well and p-well to save the cost of extra masks. For NMOS, the implantation status is phosphorus, 40kev, and 3.1×1012cm -2. For PMOS, the implantation status is Boron, 25kev and 1.6×1014cm -2. The dose and energy of the implantation must be low enough to reduce the influence on the former concentration and improve the device performances. If the energy is too high, the peak of the implantation ion will be far below the surface and can not act to increase the threshold voltage of the parasitic MOS channel.4 Simulations of BCDMOSFor NMOS transistor (W=1um, L=3um), the main structure characters are as follows. The thickness of n-epi is 6um, the implantation status of p-well is 100kev, 9.0×1012cm -2, the anneal condition of p-well is dry O 2 for 2 hours and N 2 for 3 hours at 1200℃, the thickness of gate oxide is 0.045um,the implantation status of n + drain is 60kev, 3.0×1015cm -2, and the anneal condition of n + drain is N 2 for 20 minutes at 1000℃. The simulation results are shown below.Figure7: Breakdown V oltage Simulation of NMOS Figure8: Output Characteristic Simulation of NMOSTable 2: Simulation Result of NMOS Characters (W=1.0um, L=3.0um)Vth(Ids=100nA) Ids(Vd=Vg=5V)for 50um width BVds(Ids=10uA)0.94V 3.41mA 20.10VFigure 9: Breakdown V oltage of PMOS Figure 10: Output Characteristic of PMOSFor PMOS transistor (W=1um,L=3um),the main structure characters are as follows, the thickness of n-epi is 6um,the implantation status of n-well is 80kev, 1.0×1012cm-2,the anneal condition of n-well is dry O2 for 2 hours and N2 for 3 hours at 1200,the thickness of gate oxide is 0.045um,the adjust℃implantation of the channel is 5×1011cm-2,the implantation status of p+ drain is 40kev, 1.8×1015cm-2, and the anneal condition of p+ drain is N2 for 20 minutes at 1000.℃ The simulation results are shown in Figure 9, 10 and Table 3.Table 3: Simulation Result of PMOS Characters (W=1.0um, L=3.0um)Vth(Ids=100nA) Ids(Vd=Vg=5V)for 50um widthBVds(Ids=10uA)1.12V 1.55mA -17.67VFigure11: Simulation of Emitter-Base Junction Figure12: Simulation of Emitter-Collector JunctionFor NPN triode, the main structure characters are as follows, the thickness of n-epi is 6um, the resistivity is 2.3Ω·cm, the implantation dose of base is 3.6×1013cm-2, the anneal condition of base is N2 for 90 minutes at 1150℃, the implantation dose of n+ region is 3.0×1015cm-2, the anneal condition of n+ region is N2 for 20 minutes at 1000℃.The simulation results are shown in Figure 11, 12 and Table 4.Table 4: Simulation Result of NPN Triode CharactersBvce(Ic=10uA) Bveb(Ic=10uA) R B85.79V 12.51V 804.10Ω/□For lateral PNP triode (base=epi), the main structure characters are as follows, the thickness of n-epi is 6um, the resistivity is 2.3Ω·cm,the implantation status of p+ region is 40kev, 1.88×1015cm-2,the anneal condition of p+ region is N2 for 20 minutes at 1000℃, and the width of the base region is 6um. The simulation results are shown below.Figure 13: Breakdown Simulation of LPNPTable 5: Simulation Result of LPNP Triode CharactersLPNP Bvce(Ic=10uA) -39.0VFor HV-LDMOS transistor, the main structure characters are as follows, the thickness of n-epi is 6um, and the resistivity is 2.3Ω·cm,the implantation status of buried layer is 40kev, 6.25×1012cm-2, the implantation dose of Dbase is 3.6×1013cm-2, the anneal condition of n+ drain is N2 for 90 minutes at 1150℃. The implantation status of n+ drain is60kev, 3.0×1015cm-2, and the anneal condition of n+ drain is N2 for 20 minutes at 1000℃. The simulation results are shown below.Table 6: Simulation Result of LDMOS (W=1.0um, L=3.0um)Vth(Ids=10uA) BVds(Ids=100uA)Rdson(Vd=1V,Vg=12V)for 2630um widthBVbs(Ids=10uA)1.83V 769.6V 110.00Ω 11.14VFigure 14: Output characteristic of LDMOS Figure 15: Breakdown voltage of LDMOS5 Result and discussionIn our design, p-type silicon (100) was used as the substrate. The concentration of the substrate is 1.5×1014cm -3 and the n-type epitaxy concentration is 2.0×1015cm -3. This design is mainly on 3um Bi-CMOS process. In order to reduce the influence of the small curvature radius on the breakdown voltage of LDMOS, the LDMOS is designed in a circular structure. Figure 16 shows the structure of the LDMOS and Figure 17 is the chip we have fabricated.Figure 16: The structure of the LDMOSFigure 17: The overall view of the BCDMOSTable 7 shows the test results of different devices in this chip and the results can well fulfill our requirements. It can be used in the design of HVIC. More specific test results are attached in the appendix.Table 7: The result of testingDevice Parameter Result β80 CEO BV 35V NPNCBO BV90VEBO BV 11V BEF V 0.95V CEF V0.52V β25 CEO BV 32V CBO BV 36V PNPEBO BV 36V DS BV12-28V TH V 0.8-1.2V PMOSDS I 0.5mA DS BV 28V TH V 1.1V NMOSm G 100us DS BV >650V TH V 1.4-2.0V LDMOSm G250us6 ConclusionIn this paper, a method of HV-BCD-IC process integration was proposed. This process included not only an optimized LDMOS structure with the breakdown voltage above 600V but also a process to integrate LDMOS with Bi-CMOS devices. After series of simulations by the process simulator T-SUPREM4 and device simulator MEDICI, a chip with these devices was fabricated and tested and the feasibility and reliability of our method was approved. The process we proposed has the following advantages. Both the high voltage device and the low voltage devices had a good performance and a small influence from the process. The process we use was compatible very well with the conventional integrated circuit process and can be well used in the manufactory of high voltage integrated circuit. References[1] Murari B. Smart power technologies evolution [A] .Industry Applications Conf [C]. Rome, Italy. 2000.10215.[2] Contiero C. Characteristics and applications of a 0.6m–Bipolar-CMOS-DMOS technology combining VLSI non-volatile memories [A]. IEEE Int Elec Dev Meeting [C] . San Francisco, CA, USA. 1996. 4652468.[3] Jacob A. A-BCD: an economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications [A]. ISPSO. Toulouse, France. 2000. 3272330.[4] Kim J. High-voltage power integrated circuit technology using SOI for driving plasma display panels [J ] .IEEE Trans Elec Dev , 2001 , 48 (6) : 125621258.[5] YANG Yintang, ZHU Haigang. State-of-the-Art of BCD Technology and Its Developing Trends. Microelectronics. V ol.36.No.3, Jun, 2006[6] Moscatelli A, Merlini A,Croce G , et al. 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Optimization of RESURF LDMOS transistors: An Analytical Approach.IEEE Trans.Elect.Dev.1990, 12(3):789-795[13] A.Nezar, C.A.T.Salanma. Breakdown voltage in LDMOS transistors using internal field rings.IEEE Trans.Elect. Dev.1991, 38(7):1676-1680[14] M.A.Shibib, Forward of special issue on high-voltage and power integrated circuits and devices.IEEE Trans Electron Device Letters, 1991, 38(7):1565-1567[15] LU Shengli, SUN Weifeng, YI Yangbo, WU Yuping. Research on the 500 V Bulk-SiliconN-LDMOS. Research & Progress of SSE. VO l. 25, No. 4Nov. 2005[16] Gray S.May, Simon M.Sze. Fundamentals of semiconductor fabrication. 2004[17] De.Souza.M.M, Narayanan E.M.S. Double RESURF technology for HV IC’s. Electronics Letters,1996, 32(12):1092-1093Appendix1. NPN transistor test resultsProject SOG1 SOG2PSGβ 80 76 94 BVceo（V ） 31 35 37 BVcbo （V ） 90 87 85BVebo （V ）11 11 11Vbef(V) 1 1 0.95NPN with Sinker Ae ＝10*10Vces(V) 0.50 0.50 0.50β 83 75 97 BVceo （V ） 35 35 38BVcbo （V ） 88 90 92BVebo （V ） 11 11 11Vbef （V ） 1 1 1 NPN with n＋drain in collector region and without sinker Vces （V ）0.4 0.5 0.4β 70 74 90BVceo （V ） 38 35 39 BVcbo （V ） 90 90 90 BVebo （V ） 10.5 10.7 10.7Vbef （V ） 1 1 1 NPN n ＋drain collector region and with sinker base is dmos baseVces （V ）0.5 0.5 0.52. LPNP transistor test resultsProject SOG1 SOG2PSG β 20 18 13BVceo(V) / / 28 BVcbo(V) 36 34 34LPNP with n-well with sinker Ae=6*6 BVebo(V) 55 53 56β 25 23 31 LPNP withoutBVceo(V) // 27BVcbo(V)45 45 42 n-well with sinker BVebo(V)70 72 79β 15 13 11 BVceo(V)/ / 30 BVcbo(V)36 35 33 LPNP withn-wellwithout sinkerBVebo(V)54 52 55β 180 185 190BVceo(V)12 13 13 BVcbo(V)15 16 44 VPNPBVebo(V)/ / 723. PMOS FET test resultsTest condition ： BVds （I ＝1μA ）Ids （Vg ＝Vd ＝5V ） Gm （Vg ＝5V ，Vds ＝5V ） Vth （I ＝1μA ）（1）Project SOG1 SOG2 PSG BVds(V)30 30 35 Ids(Ma) 0.2 0.16 0.25 Gm(μS)16.8 15.2 21.1W=50L=50Vth(V) 1.1 1.2 0.9 BVds / / 34 Ids / / 0.004Gm / / 0.48 W=6 L=50Vth / / 1.1 BVds 25 25 32 Ids 0.034 0.028 0.006Gm 3.3 2.8 1.1 W=12L=50Vth 1.6 1.6 1.1 BVds 28 28 34Ids 1.3 1.3 2.5 Gm 341 320 720 W=50L=3.5Vth 0.9 1.0 0.9 BVds 25 25 42 Ids 0.6 0.6 1.0 Gm 152 148 54 W=50L=7Vth 1.4 1.4 1.1 BVds 25 25 32Ids 0.115 0.101 0.20 Gm 27 22 52 W=6L=3.5Vth 1.6 1.7 1.1BVds 25 25 35Ids 0.120 0.1200.20Gm 17.6 15 22 W=12 L=7Vth 1.6 1.7 1.1 (2) double drainProject SOG1 SOG2PSGBVds(V) 40 40 42 Ids(Ma) 0.07 0.06 0.1 Gm(μS) 10.2 8.2 32 W=50 L=50Vth(V) 1.1 1.6 1.0 BVds / / 35 Ids / / 4.2u Gm / / 0.6u W=6 L=50Vth / / 1.2 BVds 43 42 36 Ids 0.013 0.0120.021Gm 2.3 2.2 3.2 W=12 L=50Vth 1.2 1.3 1.1 BVds 40 42 36 Ids 1.2 1.3 2.5 Gm 241 220 460 W=50 L=3.5Vth 1.1 1.2 0.9BVds 40 38 38 Ids 0.6 0.6 1.0 Gm 98.5 92 190 W=50 L=7Vth 1.0 1.1 1.0 BVds 38 38 40 Ids 0.11 0.10 0.16 Gm 16.4 15.2 31 W=6 L=3.5Vth 1.6 1.7 1.0BVds 38 40 37 Ids 0.16 0.12 0.25 Gm 194 165 310 W=12 L=7Vth 1.2 1.3 1.0(3) NormalProject SOG1 SOG2PSG BVds(V) 33 33 34 Ids(Ma) 0.07 0.07 0.12 Gm(μS) 10.2 10 19.5 W=50 L=50 Vth(V) 1.1 1.2 1.0 BVds / / 28 Ids / / 4u W=6 L=50Gm / / 0.55 Vth / / 1.2 BVds 33 33 32 Ids 0.013 0.012 0.028Gm 2.3 2.2 4.0 W=12L=50Vth 1.2 1.2 1.0 BVds 28 28 34 Ids 1.2 1.0 2.0 Gm 192 156 392 W=50L=3.5Vth 1.1 1.3 1.0 BVds 28 27 34 Ids 0.55 0.48 1.05 Gm 80 72 172 W=50L=7 Vth 1.1 1.3 0.9 BVds 28 28 27 Ids 0.12 0.10 0.19 Gm 30 18 95 W=6L=3.5Vth 1.3 1.5 1.0 BVds 28 28 32 Ids 0.10 0.09 0.205Gm 15 12 34.5 W=12L=7 Vth 1.2 1.3 1.04. NMOS FET test results(1) Project SOG1 SOG2 PSG BVds(V)12 12 22Ids(Ma) 0.12 0.12 0.23 Gm(μS) 16 18 42.4 W=50L=50Vth(V) 1.3 1.2 0.9 BVds 16 15 15 Ids 0.012 0.012 0.022Gm 1.8 2.0 3.7 W=6L=50Vth 1.4 1.4 0.9 BVds 16 16 24 Ids 0.03 0.03 0.07 Gm 4.8 4.8 9.2 W=12L=50Vth 1.3 1.4 0.9 BVds 11 11 12 Ids 2.3 2.3 3.0 Gm 360 405 820 W=50L=3 Vth 0.9 1.0 0.9 BVds 11 11 12 W=50L=6Ids 1.1 1.2 2.15Gm 170 190 368 Vth 0.9 0.9 0.9 BVds 12 12 14 Ids 0.18 0.15 0.27 Gm 30 24 42 W=6 L=3Vth 1.2 1 1.0 BVds 12 11 13.5Ids 0.22 0.25 0.325Gm 33 53 85 W=12 L=6Vth 1.2 1 1.0(2) Double drainProject SOG1 SOG2 PSGBVds(V) 23 22 32Ids(Ma) 0.18 0.18 0.25 Gm(μS) 23 22 41.5 W=50 L=50Vth(V) 1.1 1.1 1.0 BVds 22 22 34.5Ids 0.01 0.01 0.026 Gm 1.7 3.8 5.7 W=6 L=50Vth 1.1 1.1 1.0 BVds 22 22 33Ids 0.03 0.03 0.06 Gm 7 6 12 W=12 L=50Vth 1.1 1.1 1.0 BVds 20 22 31Ids 2.5 2.5 3.2 Gm 460 500 860 W=50 L=3Vth 0.9 0.8 0.9 BVds 20 20 33 Ids 1.2 1.25 1.9 Gm 180 192 352 W=50 L=6Vth 1.2 1.2 0.9 BVds / / 35 Ids / / 0.18 Gm / / 29 W=6 L=3Vth / / 1.0 BVds 25 25 35Ids 0.25 0.25 0.46Gm 36 37 76 W=12 L=6Vth 1.0 1.0 0.9(3) NormalProject SOG1 SOG2 PSG BVds(V)13 10 23Ids(Ma) 0.15 0.14 0.275Gm(μS) 22 21.4 45.6 W=50L=50Vth(V) 1.1 1.0 1.0 BVds 12 12 23 Ids 0.012 0.012 0.024Gm 1.75 3 4.13 W=6L=50Vth 1.6 1.2 1.0 BVds 12 12 25 Ids 0.03 0.04 0.06 Gm 4.7 9 22 W=12L=50Vth 1.1 1.2 1.0 BVds 12 11 21 Ids 2.5 2.5 3.4 Gm 430 503 702 W=50L=3 Vth 1.0 1.0 0.9 BVds 12 11 22 Ids 1.3 1.4 1.9 Gm 197 210 352 W=50L=6 Vth 1.0 1.0 0.9 BVds 12 11 23 Ids 0.18 0.09 0.31 Gm 30 30 64.5 W=6L=3 Vth 1.0 1.0 0.9 BVds 12 12 23 Ids 0.22 0.25 0.39 Gm 40 70 124 W=12L=6 Vth 1.1 1.1 0.95. LDMOS FET （self-aligh ）test results I DS 为 Vg=5V , Vd=20V 8#Vth=1.8-2V Ron=430-450Ohm Ids=28mA gm=4000uS6# Vth=1.8-2.2VRon=400-420OhmIds=25mA gm=3800uS。