ADN2849中文资料
ADN2860资料
a3-Channel DigitalPotentiometer with Nonvolatile MemoryPreliminary Technical DataADN2860REV. Pr D Page 1 of 15Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. FEATURES3 Channels: Dual 512-Position Single 128-Position 25K Ω or 150K Ω Full-Scale Resistance Low Temperature Coefficient: 35ppm/°C Nonvolatile Memory Retains Wiper Settings Permanent Memory Write-Protection Linear Increment/Decrement Log taper Increment/Decrement I 2C Compatible Serial Interface 3V to 5V Single Supply Operation ±2.5V Dual Supply Operation256 Bytes General Purpose User EEPROM 11 Bytes RDAC user EEPROMGBIC and SFP Compliant EEPROM100-year Typical Data Retention at TA=55°CAPPLICATIONS Laser Diode Drivers Optical Amplifiers TIA Gain SettingTEC Controller Temperature Set PointsW0W1W2GENERAL DESCRIPTIONThe ADN2860 provides dual 512-position and a single 128-position digitally controlled variable resistor 1 (VR) in a single 4x4mm LFCSP package. This device performs the sameelectronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the Wiper or the B terminal and the Wiper. The fixed A-to-B terminal resistance of 25k Ω or 250k Ω has a 1% channel-to-channel matching tolerance and a nominal temperature coefficient of 35ppm/°C.Wiper position programming, EEPROM reading, and EEPROM writing is conducted via the standard 2-wire I 2C interface. Previous/Default wiper position settings can be stored in memory, and refreshed upon system power-up.Additional features of the ADN2860 include preprogrammed linear and logarithmic increment/decrement wiper changing, and actual resistor tolerances are stored in EEPROM so that theactual end-to-end resistance is known, which is valuable for calibration in precision applications.The ADN2860 EEPROM, channel resolution, and package size conforms to GBIC and SFP specifications. The ADN2860 is available in a 4x4mm 24-lead LFCSP package. All parts are guaranteed to operate over the extended industrial temperature range of –40C to 85°C.1. The term nonvolatile memory, EEMEM, and EEPROM are usedinterchangeably2. The term programmable resistor, variable resistor, RDAC, and digitalpotentiometer are used interchangeably.元器件交易网11NOTES:1. Typical represent average readings at +25°C, V DD = +5V.2. Resistor position non-linearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures therelative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit.3. INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0V.DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.4. Resistor terminals A, B, W have no limitations on polarity with respect to each other.5. Guaranteed by design and not subject to production test.6. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R valueresults in the minimum overall power consumption.7. P DISS is calculated from (I DD x V DD). CMOS logic level inputs result in minimum power dissipation.8. All dynamic characteristics use V DD = +5V.9. See timing diagram for location of measured values.10. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700,000 cycles.11. Retention lifetime equivalent at junction temperature (T J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junctiontemperature.The ADN2860 contains 21,035 transistors. Die size: 88.2 mil x 87.0 mil, 7673 sq. mil.Specifications Subject to Change without NoticAbsolute Maximum Rating1(T A = +25°C, unless otherwise noted)V DD to GND..........................................................-0.3 V, +7 V V SS to GND..........................................................+0.3 V, -7 V V DD to V SS........................................................................+7 V V A, V B, V W to GND.............................V SS-0.3 V, V DD+0.3 V I A, I B, I WIntermittent2.................................................±20 mAContinuous.....................................................±2 mA Digital Inputs & Output Voltage to GND...-0.3 V, V DD+0.3 V Operating Temperature Range3.......................-40°C to +85°C Maximum Junction Temperature (T J MAX)...................+150°C Storage Temperature......................................-65°C to +150°C Lead Temperature, Soldering4Vapor Phase (60 sec).......................................+215 °C Infrared(15sec)...............................................+220 °C Thermal Resistance Junction-to-Ambient θJA,LFCSP-24...................................................TBD °C/W Thermal Resistance Junction-to-Case θJC,LFCSP-24...................................................TBD °C/W Package Power Dissipation = (T J MAX - T A) / θJANOTES1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the B, and W terminals at a given resistance.3. Includes programming of Nonvolatile memoryESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2860 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ADN2860ACP PIN CONFIGURATIONPIN DESCRIPTIONS# Name Description1 RESET Reset the scratch pad register with current contents of the EEMEM register. Factory defaults midscale before any programming2 WP Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and cmd 1 and 8 will refresh theRDAC register from EEMEM. Execute a NOP instruction before returning to WP high.3 SCL Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges.4 SDA Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.5 DGND Ground pin, logic ground reference6 V SS Negative Supply. Connect to zero volts for single supply applications.7 A2 A terminal of RDAC2.8 W2 Wiper terminal of RDAC29 B2 B terminal of RDAC2.10 A1 A terminal of RDAC1.11 W1 Wiper terminal of RDAC112 B1 B terminal of RDAC113 A0 A terminal of RDAC0.14 W0 Wiper terminal of RDAC0.15 B0 B terminal of RDAC016 V DD Positive Power Supply Pin.17 TEST3 Test pin 3 (Do Not Connect)18 TEST2 Test pin 2 (Do Not Connect)19 TEST1 Test pin 1 (Do Not Connect)20 TEST0 Test pin 0 (Do Not Connect)21 A1_EE I2C Device Address 1 for EEMEM22 A0_EE I2C Device Address 0 for EEMEM23 AD1 I2C Device Address 1 for RDAC24 AD0 I2C Device Address 0 for RDACI 2C Interface Timing DiagramSDASCLFigure 1. I2C Timing DiagramI 2C Interface General DescriptionS = Start Condition P = Stop ConditionA = Acknowledge (SDA Low) A = Not Acknowledge (SDA High)R/W = Read Enable at High and Write Enable at LowFigure 2. I 2C - Master Transmitting Data to SlaveFigure 3. I 2C - Master Reading Data From SlaveFigure 4. I 2C – Combined Transmit/Readthis pointFrom Slave to Master From Master to SlaveEEPROM I2C Interface DescriptionFigure 7. EEPROM Random Read EEPROM Interface OperationThe 256 bytes of EEPROM memory provided in the ADN2860 are organized into 16 pages of 16 bytes each. The word size of each memory location is one byte wide.The I2C slave address of the EEPROM is 10100(A1E)(A0E), where A1E and A0E are external pin programmable address bits. The two pin programmable address bits allow a total of four ADN2860 devices to be controlled by a single I2C master bus, each having its own EEPROM.An internal 8-bit address counter for the EEPROM is automatically incremented following each read or write operation. For read operations, the address counter is incremented after each byte is read, and the counter will rollover from address location 255 to 0.For write operations, the address counter will be incremented after each byte written. The counter rolls-over from the upper most address of the current page to the lower most address of the current page. For example, writing two bytes beginning at address location 31 will cause the counter to roll back to address location 16 after the first byte is written, and then the address will increment to 17 after the second byte is written. EEPROM WriteEach write operation issued to the EEPROM can program 1 byte to 16 bytes (1 page) of memory. Figure 5 shows the EEPROM write interface, the number of bytes of data, N, the user wishes to send to the EEPROM is unrestricted. If more than 16 bytes of data are sent in a single write operation, the address counter will rollback to the beginning address, and the previously sent data will be overwritten. EEPROM Write-Acknowledge PollingAfter each write operation, an internal EEPROM write cycle begins. During the EEPROM internal write cycle, the I2C interface of the device will be disabled. In order to determine if the internal write cycle is complete and whether the I2C interface is enabled, interface polling must be executed. I2C interface polling can be conducted by sending a start condition followed by the EEPROM slave address + desired R/W bit. If the ADN2860 I2C interface responds with an ACK, then the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, the I2C interface needs to be polled again to determine whether the write cycle has been completed.EEPROM ReadThe ADN2860 EEPROM provides two different read operations, shown in figures 6 and 7. The number of bytes, N, read from the EEPROM in a single operation is unrestricted. If more than 256 bytes are read, the address counter will rollback to the start address, and data previously read will be read again. Figure 6 shows the EEPROM Current Read operation. This operation does not allow an address location to be specified and reads data beginning at the current address location stored in the internal address counter.A random read operation is shown in figure 7. This operation changes the address counter to the specified memory address by performing a “dummy write” and then performing a read operation beginning at the new address counter location. EEPROM Write ProtectionSetting the WP pin to a logic LOW protects the EEPROM memory from future write operations. In this mode, EEPROM read operations and RDAC register loading can still operate normally.RDAC I2C Interface DescriptionS 0 1 0 1 1 A1R AR0 A CMD/W0 EE/REGA4A3A2A1AA Data A Data A/AP Figure 8. RDAC WriteFigure 9. RDAC Current ReadFigure 10. RDAC Random Read RDAC Register Addresses (CMD/W=0, EE/REG=0)A4 A3 A2 A1 A0 RDAC Byte Description0 0 0 0 00 0 0 0 10 0 0 1 00 0 0 1 10 0 1 0 00 0 1 0 1 to1 1 1 1 1RDAC0RDAC0RDAC1RDAC1RDAC2(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC0 8 LSBs(X)(X)(X)(X)(X)(X)(X)(D8) – RDAC0 MSB(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC1 8 LSBs(X)(X)(X)(X)(X)(X)(X)(D8) – RDAC1 MSB(X)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC2 7 bitsreservedTable 1. RDAC Register Address TableRDAC R/W EEPROM Address Table(CMD/W=0, EE/REG=1) RDAC Read-Only EEPROM Address Table(CMD/W=0, EE/REG=1) A4 A3 A2 A1 A0 Byte Description A4 A3 A2 A1 A0 Byte Description0 0 0 0 00 0 0 0 10 0 0 1 00 0 0 1 10 0 1 0 00 0 1 0 1 to0 1 1 1 1 RDAC0 8 LSBsRDAC0 MSBRDAC1 8 LSBsRDAC1 MSBRDAC2 7 bits11 bytes RDAC USER EEPROM1 0 0 0 01 0 0 0 11 0 0 1 01 0 0 1 11 0 1 0 01 0 1 0 1 to1 1 1 1 1% Tolerance% Tolerance% Tolerance% Tolerance% TolerancereservedTable 2. RDAC R/W EEPROM Address Table1 ReadRDAC I2C Interface Description (cont’d)Figure 11. RDAC Command Write (Dummy Write) RDAC Command Table (CMD/W=1)C3 C2 C1 C0 Command Description0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0 to1 1 1 1NOPLoad EEPROM to RDAC*Store RDAC to EEPROMDecrement RDAC 6dBDecrement All RDACs 6dB Decrement RDAC One Step Decrement All RDACs One Step Reset: Load EEPROM to all RDACs Increment RDAC 6dBIncrement All RDAC 6dB Increment RDAC One Step Increment All RDAC One Step reservedTable 3. RDAC Commands* This command leaves the device in the EEPROM Read power state. Issue the NOP command to return the device to the idle state.RDAC Interface OperationEach programmable resistor wiper setting is controlled by specific RDAC registers, as shown in the RDAC Register Address Table (table 1). Each RDAC register corresponds to an EEPROM memory location, which provides non-volatile wiper storage functionality.RDAC registers and their corresponding EEPROM memory locations can be programmed and read independently from each other. The RDAC register can be refreshed by the EEPROM locations either with a hardware reset via pin 1, or by issuing one of the various RDAC register load commands shown in the RDAC command table (table 3).RDAC WriteSetting the wiper position requires an RDAC write operation, shown in figure 8. RDAC write operations follow a format similar to the EEPROM write interface. The only difference between an RDAC write and an EEPROM write operation is the use of an RDAC address byte in place of the memory address used in the EEPROM write operation. The RDAC address byte is described in detail in the tables 1 and 2.As with the EEPROM write operation, the RDAC write operation disables the I2C interface during the internal write cycle. Acknowledge polling, as described in the EEPROM I2C interface section, is required to determine whether the write cycle has been completed.RDAC ReadThe ADN2860 provides two RDAC read operations. The first, shown in figure 9 reads the contents of the current RDAC address counter. Figure 10 illustrates the second read operation. This operation allows users to specify which RDAC register to read by first issuing a “dummy write” command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location.The read-only RDAC EEPROM memory locations can also be read by using the address and bits specified in the RDAC Read-Only EEPROM Address Table (table 2).RDAC Quick CommandsEleven shortcut “quick” commands are provided for easy manipulation of RDAC registers and their corresponding EEPROM memory locations. These commands are shown in table 3.The interface for issuing an RDAC quick command is shown in figure 11. All quick commands require Acknowledge polling to determine whether the command has finished executing.A more detailed discussion about the RDAC quick commands can be found in the Operational Overview section of this document.OPERATIONAL OVERVIEWThe ADN2860 digital potentiometer is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the ADN2860’s serial I2C interface. The format of the datawords and commands to program the RDAC registers are discussed in the RDAC I2C Interface section of this document.RDAC registers also have a corresponding EEPROM memory location, which provide non-volatile storage of resistor wiper position settings. The ADN2860 provides commands to store the RDAC register contents to their respective EEPROM memory locations. During subsequent power on sequences, the RDAC registers will automatically be loaded with the stored value.Saving data from an RDAC register to EEPROM memory takes approximately 25ms and consumes 20mA of current.In addition to the movement of data between RDAC registers and EEPROM memory, the ADN2860 provides other shortcut commands that facilitate the users’ programming needs.1. Restore EEPROM setting to RDAC2. Save RDAC register contents to EEPROM3. Decrement RDAC 6dB (Shift Data Bits Right)4. Decrement all RDACs 6dB (Shift All Data Bits Right)5. Decrement RDAC one step6. Decrement all RDACs one step7. Reset EEPROM setting to RDAC8. Increment RDAC 6dB (Shift Data Bits Left)9. Increment all RDACs 6dB (Shift All Data Bits Left)10. Increment RDAC one step11. Increment all RDACs one stepTable 4. ADN2860 Shortcut CommandsLinear Increment and Decrement CommandsThe increment and decrement commands (#10, #11, #5, #6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the ADN2860. The adjustment can be directed to an individual RDAC or all three RDACs.Logarithmic Taper Mode Adjustment (±6dB/step)The ADN2860 accommodates logarithmic taper adjustment of the RDAC wiper position(s) by shifting the register contents left/right for increment/decrement operations. Commands 8, 9, 3, and 4 can be used to logarithmically increment or decrement the wiper positions individually or change all three channel settings at the same time. Incrementing the wiper position by +6dB is essentially doubling the RDAC register value, while decrementing by –6dB is halving the register content. Internally, the ADN2860 uses a shift register to shift the bits left and right to achieve a logarithmic increment or decrement.Non-ideal ±6dB step adjustment occurs under certain conditions. Table 5 illustrates the shifting function on an individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift (#10 & #11) commands were modified such that if the data in the RDAC register is equal to zero, and the data is shifted the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to mid-scale, and the data is left shifted, the data in the RDAC register is automatically set to full-scale. This makes the left shift function as close to a logarithmic adjustment as possible.The right shift commands (#3 & #4) will be ideal only if the LSB is a 0 (ideal logarithmic = no error). If the LSB is a 1 then the right shift function generates a linear half LSB error, which translates to a number of error bits.Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right shift (#3 & #4) command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in figure 12 shows a plot of Log_Error[i.e. 20*Log10(error/code)] for the ADN2860.Figure 12. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits are ideal)Using Additional Internal Nonvolatile EEPROMThe ADN2860 contains additional internal user EEPROM for saving constants and other data. The user EEPROM I 2C dataword follows the same format as the general purpose EEPROM memory shown in figures 5 and 6. User EEPROM memory addresses are shown at the bottom of table 2.To support the use of multiple EEPROM modules on a single I 2C bus, the ADN2860 features two external addressing pins, pins 21 and 22 (A1_EE and A0_EE) to manually set the address of the EEPROM included with the ADN2860. This feature ensures that the correct EEPROM memory is accessed when using multiple memory modules on a single I 2C bus.Digital Input/Output ConfigurationAll digital inputs are ESD protected. Digital inputs are high impedence and can be driven directly from most digital sources. Active at logic low, RESET and WP should be biased to V DD if they are not used. There are no internal pull-up resistors present on any of the digital input pins of the ADN2860. As a result, pull-up resistors are needed if these functions are not used.ESD protection of the digital inputs is shown in figure 13.WPV DDGNDFigure 13. Equivalent WP Input ProtectionMultiple Devices On One BusFigure 14 shows four ADN2860 devices on the same serial bus. Each has a different slave address since the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently.S DAS CLFigure 14. Multiple ADN2860 Devices on a Single BusLevel Shift for Bi-Directional CommunicationWhile most old systems may be operating at one voltage, a new component may be optimized at another. When two systems transmit the same signal at two different voltages, proper level shifting is required.In some instances, for example, a 3.3V EEPROM memory module may be used along with a 5V digital potentiometer. A level shifting scheme is required in order to enable bi-directional communication between the two devices.SDA1SCL1SD A2SC L2V =5VFigure 15. Level Shifting for different voltage devices on an I2CbusFigure 15 shows one of many possible techniques to properly level shift signals between two devices. M1 and M2 can be N-channel FETs (2N7002). If V DD falls below 2.5V, M1 and M2 should be low threshold N-channel FETs (FDV301N).Terminal Voltage Operation RangeThe ADN2860 positive V DD and negative V SS power supply inputs define the boundary conditions for proper 2-terminal programmable resistance operation. Supply signals on terminals W and B that exceed V DD or V SS will be clamped by the internal forward biased diodes of the ADN2860.DDBSSFigure 16. Maximum Terminal Voltages Set by V DD & V SSThe ground pin of the ADN2860 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the ADN2860 must be referenced to the device ground pin, and satisfy the logic levels defined in the specification table of this datasheet.An internal level shift circuit insures that the common mode voltage range of the 2-terminals extends from V SS to V DDirrespective of the digital input level. In addition, there is nopolarity constraint on the voltage across terminals W and B. The magnitude of |V WB| is bounded by V DD -V SS.Power-Up SequenceSince there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (see figure 16), it is important to power V DD / V SS before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased such that V DD / V SS will be powered unintentionally and may affect the rest of the users’ circuit. The ideal power-up sequence is in the following order: GND, V DD, V SS, digital inputs, and V A/B/W. The order of powering V A, V B, V W, and digital inputs is not important as long as they are powered after V DD / V SS.Layout and Power Supply BiasingIt is always a good practice to employ compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low ESR (Equivalent Series Resistance) 1µF to 10µF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 17 illustrates the basic supply bypassing configuration for the ADN2860.Figure 17. Power Supply BypassingRDAC StructureThe patent pending RDAC contains a string of equal resistor segments, with an array of analog switches. The switches act as the wiper connection.The ADN2860 has two RDACs with 512 connection points allowing it to provide better than 0.2% set-ability resolution. The ADN2860 also contains a third RDAC with 128 step resolution.Figure 18 shows an equivalent structure of the connections between the two terminals that make up one channel of an RDAC. The SWB switch will always be ON, while on of the switches SW(0) to SW(2N-1) will be ON at any given time depending on the resistance position decoded from the databits in the RDAC register. Since the switches are non-ideal, there is a 50Ω wiper resistance, R W. Wiper resistance is a function of supply voltage and temperature, lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications where accurate prediction of output resistance is required.RRRR S=R WB_FS/2NDIGITALCIRCUITRYOMITTED FORCLARITYFigure 18.. Equivalent RDAC structure Calculating the Programmable ResistanceThe nominal resistance of the RDAC between terminals A and B is available in 25kΩ or 250kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g.25kΩ = 25 and 250kΩ = 250.The following discussion describes the calculation of resistance R WB(D) at different codes of a 25kΩ part for RDAC 0. The 9-bit data word in the RDAC latch is decoded to select one of the 512 possible settings.The wiper first connection starts at the B terminal for data000H. R WB(0) is 50Ω because of the wiper resistance and it is independent to the full-scale resistance. The second connection is the first tap point where R WB(1) becomes 48.8Ω + 50 = 98.8Ωf or data 001H. The third connection is the next tap point representing R WB(2)=97.6+50=147.6 for data 002H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at R WB(512)=25001Ω. See Figure 18 for a simplified diagram of the equivalent RDAC circuit.The general equations that determine the programmed output resistance between W and B are:Preliminary Technical DataADN2860W R AB R DD WB R +⋅=512)( (RDAC 0 and 1)(1) W R AB R DD WB R +⋅=128)( (RDAC 2 only)(2)Where D is the decimal equivalent of the data contained in the RDAC register and R W is the wiper resistance. The output resistance values in table 6 will be set for thefollowing RDAC latch codes with V DD = 5 V (applies to R AB = 25 k Ω Digital Potentiometers):Table 6. R WB at Selected Codes for R WB_FS = 25 k ΩNote that in the zero-scale condition a finite wiper resistance of 50Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20mA to avoid degradation or possible destruction of the internal switches.Channel-to-channel R WB matching is better than 1%. Thechange in R WB with temperature has a 35ppm/°C temperature coefficient.Like the mechanical potentiometer the RDAC replaces, theADN2860 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance R WA . When R WA is used, the B terminal can be let floating or tied to the wiper. Setting theresistance value for R WA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is:W R AB R DD WA R +⋅−=512512)( (RDAC 0 and 1) (3)W R AB R DD WA R +⋅−=128128)( (RDAC 2 only) (4)For example, the following output resistance values will be set for the following RDAC latch codes (applies to R AB =25 k Digital Potentiometers): Table 7. ADN2860. R WA (D) at selected codes for R AB = 25 k Ω.The typical distribution of R AB from channel-to-channel matches to ±0.2% within the same package. Device to device matching is process lot dependent, with a worst case of ±30% variation. Changes in R AB with temperature has a 35ppm/°C temperature coefficient.PROGRAMMING THE POTENTIOMETER DIVIDERVoltage Output OperationThe digital potentiometer can be configured to generate anoutput voltage at the wiper terminal, which is proportional to the input voltages applied to terminals A and B. Connectingterminal A to +5V and terminal B to ground produces an output voltage at the wiper which can be any value starting at zero volts up to +5V. Each LSB of voltage is equal to the voltage applied across terminals A and B divided by the 2N position resolution of the potentiometer divider.Since ADN2860 can also be supplied by dual supplies, thegeneral equations defining the output voltage at V W with respect to ground for any given input voltages applied to terminals A and B are:B V ABV DD W V +⋅=512)( (RDAC 0 and 1) (5)B V ABV DD W V +⋅=128)( (RDAC 2) (6)Equation 5 assumes V W is buffered so that the effect of wiper resistance is nulled. Operation of the digital potentiometer in the divider mode results in more accurate operation overtemperature. In this mode, the output voltage is dependent on the ratio of the internal resistors not the absolute value,therefore, the drift improves to 15ppm/°C. There is no voltage polarity restriction between terminals A, B, and W as long as the terminal voltage (V TERM ) stays within V SS < V TERM < V DD .APPLICATIONSLaser Diode Driver (LDD) calibrationThe ADN2860 can be used with any laser diode driver. Its high resolution, compact footprint, and superior temperature drift characteristics make it ideal for optical parameter setting.The ADN2841 is a 2.7 Gbps laser diode driver that utilizes a unique control algorithm to manage both the laser average power and extinction ratio after initial factory calibration. It stabilizes the laser data transmission by continuouslymonitoring its optical power, and correcting the variations caused by temperature and the laser degradation over time. In ADN2841, the I MPD monitors the laser diode current. Through its dual loop Power and Extinction Ratio control, calibrated by ADN2860, the internal driver controls the bias current I BIAS and consequently the average power. It also regulates themodulation current, I MODP by changing the modulation current linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are thereforecompensated. As a result, this optical supervisory system minimizes the laser characterization efforts and therefore。
5829中文资料
T E Logic Supply Voltage, VDD .................. 7.0 V N F Input Voltage Range, O E VIN ....................... -0.3 V to VDD + 0.3 V
12.5
= 6°C/W R θJT
10
7.5
5.0
2.5
0 25
R θJA = 30°C/W
50
75
100
TEMPERATURE IN °C
125
150
Dwg. GP-020B
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1991, 1995 Allegro MicroSystems, Inc.
Storage Temperature Range,
F TS ............................... -55°C to +150°C
* Fault conditions that produce excessive junction
— temperature will activate device thermal shut-
FEATURES
s 1.6 A Continuous Output Current s 50 V Minimum Sustaining Voltage s Internal Current Sensing s Constant-Frequency PWM Current Control s Control for External High-Side Driver s To 3.3 MHz Data Input Rate s Low-Power CMOS Logic & Latches s Internal Pull-Ups for TTL Compatibility s User-Defined Output Enable Timeout s Internal Thermal Shutdown Circuitry
L297 L298的中文资料
L297-L298中文资料L297的工作原理介绍L297是意大利SGS半导体公司生产的步进电机专用控制器，它能产生4相控制信号，可用于计算机控制的两相双极和四相单相步进电机，能够用单四拍、双四拍、四相八拍方式控制步进电机。
芯片内的PWM斩波器电路可开关模式下调节步进电机绕组中的电机绕组中的电流。
该集成电路采用了SGS公司的模拟/数字兼容的I2L技术，使用5V的电源电压，全部信号的连接都与TFL/CMOS或集电极开路的晶体管兼容。
L297的芯片引脚特别紧凑，采用双列直插20脚塑封封装，其引脚见图1，内部方框见图2。
在图2所示的L297的内部方框图中。
变换器是一个重要组成部分。
变换器由一个三倍计算器加某些组合逻辑电路组成，产生一个基本的八格雷码(顺序如图3所示)。
由变换器产生4个输出信号送给后面的输出逻辑部分，输出逻辑提供禁止和斩波器功能所需的相序。
为了获得电动机良好的速度和转矩特性，相序信号是通过2个PWM斩波器控制电动波器包含有一个比较器、一个触发器和一个外部检测电阻，如图4所示，晶片内部的通用振荡器提供斩波频率脉冲。
每个斩波器的触发器由振荡器的脉冲调节，当负载电流提高时检测电阻上的电压相对提高，当电压达到Uref时(Uref是根据峰值负载电流而定的)，将触发器重置，切断输出，直至第二个振荡脉冲到来、此线路的输出(即触发器Q输出)是一恒定速率的PWM信号，L297的CONTROL端的输入决定斩波器对相位线A，B，C，D或抑制线INH1和INH2起作用。
CONTROL 为高电平时，对A，B，C，D有抑制作用；为低电平时，则对抑制线INH1和INH2有抑制作用，从而可对电动机和转矩进行控制。
图1 L297引脚图图2 L297内部方框电路图图3 L297变换器换出的八步雷格码（顺时针旋转）图4 斩波器线路图5 多个L297同步工作连接图L297 ABSOLUTE MAXIMUM RATINGS绝对最大额定值：SymbolParameter 参数Value 数值Unit 单位符号Vs Supply voltage 电源电压10 VVi Input signals 输入信号7 VPtot Total power dissipation 总功率耗散(Tamb = 70℃) 1 WTstg, Tj Storage and junction temperature 储存和结温-40 to + 150 ℃L297 ELECTRICAL CHARACTERISTICS (Refer to the block diagram Tamb = 25℃, Vs = 5V unless otherwisespecified) L297 电气特性：Symbol符号Parameter 参数Test conditions测试条件最小典型最大单位Vs Supply voltage (pin 12) 电源电压 4.75 7 VIsQuiescent supply current静态电源电流（引脚12) Outputs floating580 mAViInput voltage输入电压（引脚11，17，18，19，20） Low0.6V High 2 Vs VIiInput current输入电流（引脚11，17，18，19，20） Vi = L1μA Vi = H 10μAVenEnable input voltage 使能输入电压（引脚10）Low1.3V High 2 Vs VIenEnable input current使能输入电流（引脚10） Ven = L10μA Ven = H 10μAVoPhase output voltage 相输出电压（引脚4，6，7，9）Io = 10mA VOL0.4V Io =5mA VOH 3.9 VVinhInhibit output voltage (pins 5, 8)抑制输出电压（引脚5，8）Io = 10mA Vinh L0.4VIo =5mA Vinh H 3.9 V VSYNC Sync Output Voltage 同步输出电压Io = 5mA VSYNC H 3.3 VIo = 5mA VSYNC V0.8IleakLeakage current(pin3)泄漏电流(引脚3) VCE = 7 V 1μAVsat Saturation voltage饱和电压(引脚3) I = 5 mA0.4V VoffComparators offset voltage比较器的偏移电压（引脚13，14，15）Vref = 1 V 5 mV IoComparator bias current 比较器偏置电流（引脚13，14，15）-100 10 mA VrefInput reference voltage输入参考电压（引脚15）0 3 V tCLK Clock time 时钟时间0.5μs tS Set up time 建立时间 1μs tH Hold time保持时间 4μs tR Reset time复位时间 1μs tRCLK Reset to clock delay 重置时钟延迟 1μsL297各引脚功能说明1脚(SYNG)——斩波器输出端。
R928中文资料
PHOTOMULTlPLlER TUBESR928, R955Subject to local technical requirements and regulations, availability of products included in this promotional material may vary. Please consult with our sales office. lnformation furnished by HAMAMATSU is believed to be reliabIe. However, no responsibility is assumed for possibIe inaccuracies or ommissions. Specifications are subject to change without notice. No patent right are granted to any of the circuits described herein. © 1997 Hamamatsu Photonics K.K.PHOTOMULTlPLlER TUBES R928, R955 MAXIMUM RATINGS (Absolute Maximum Values)CHARACTERISTlCS (at 25SuppIy Voltage : 1000VdcK : Cathode, Dy : Dynode, P : AnodeJ:K:L:The electron transit time is the interval between the arrival of delta function light pulse at the entrance window of the tube and the time when the anode output reaches the peak amplitude. In measurement, the whole photo-cathode is illuminated.Also called transit time jitter. This is the fluctuation in electron transit time between individual pulses in the signal photoelectron mode, and may be defined as the FWHM of the frequency distribution of electron transit times.Hysteresis is temporary instability in anode current after light and voltage are applied.(1)Current HysteresisThe tube is operated at 750 volts with an anode current of 1 micro-ampere for 5 minutes. The light is then removed from the tube for a minute. The tube is then re-illuminated by the previous light level for a minute to measure the variation.(2)Voltage HysteresisThe tube is operated at 300 volts with an anode current of 0.1 micro-ampere for 5 minutes. The light is then removed from the tube and the supply voltage is quickly increased to 800 volts. After a minute, the supply voltage is then reduced to the previous value and the tube is re-illuminated for a minute to measure the variation.Hysteresis =100(%)l max.l il min.Figure 2: Anode Luminous Sensitivity and Gain CharacteristicsFigure 3: Typical Time ResponseFigure 4: Typical Temperature Coefficient of Anode SensitivityFigure 5: Typical Temperature Characteristic of Dark Current (at 1000V, after 30minute storage)TPMSB0002EATPMSB0003EBTIMEA N O D E 200300500700100010–2A N O D E L U M I N O U S S E N S I T I V I T Y (A /l m )1500G A I N10–1100101102103104102103104105106107108SUPPLY VOLTAGE (V)SUPPLY VOLTAGE (V)T I M E (n s )124681020406080100TPMSB0005EA–40–200+20TEMPERATURE (°C)1608020A N O D E S E N S I T I V I T Y (%)140100+401206040TPMSB0006EA–40–200+20TEMPERATURE (°C)10010.01A N O D E D A R K C U R R E N T (n A )+40100.1PHOTOMULTlPLlER TUBES R928, R955TPMS1001E06MAY. 1997Figure 6: Dimensional Outline and Basing Diagram (Unit : mm)Figure 7: Optional Accessories (Unit : mm)TPMSA0008EADIRECTION OF LIGHTBOTTOM VIEW (BASING DIAGRAM)TACCA0064EASocketD Type Socket Assembly E717-21Warning–Personal Safety HazardsElectrical Shock–Operating voltages applied to thisdevice present a shock hazard.Hamamatsu also provides C4900 series compact high voltage power sup-plies and C6270 series DP type socket assemblies which incorporate a DC to DC converter type high voltage power supply.(E678 – 11A)TACCA0002ED: 330k: 0.01 F SOCKET HAMAMATSU PHOTONICS K.K., Electoron Tube Center314-5, Shimokanzo, Toyooka-village, Iwata-gun, Shizuoka-ken, 438-0193, Japan, Telephone: (81)539/62-5248, Fax: (81)539/62-2205U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater. N.J. 08807-0910, U.S.A., Telephone: (1)908-231-0960, Fax: (1)908-231-1218Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49)8152-375-0, Fax: (49)8152-2658France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: (33)1 69 53 71 00, Fax: (33)1 69 53 71 10United Kingdom: Hamamatsu Photonics UK Limted: Lough Point, 2 Gladbeck Way, Windmill Hill, Enfield, Middlesex EN2 7JA, United Kingdom, Telephone: (44)181-367-3560, Fax: (44)181-367-6384North Europe: Hamamatsu Photonics Norden AB: Färögatan 7, S-164-40 Kista Sweden, Telephone: (46)8-703-29-50, Fax: (46)8-750-58-95Italy: Hamamatsu Photonics Italia: S.R.L.: Via Della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39)2-935 81 733, Fax: (39)2-935 81 741Hybrid Assembly of R928H957-08The H957-08 integrates on R928, a voltage-divider circuit, and a high voltage power supply into a compact magnetic shield case. It can be readily operated by input of 15Vdc.。
MRF284中文资料
CASE 360C–03, STYLE 1 (MRF284S)
MAXIMUM RATINGS
Rating Drain–Source Voltage Gate–Source Voltage Total Device Dissipation @ TC = 25°C Derate above 25°C Storage Temperature Range Operating Junction Temperature Symbol VDSS VGS PD Tstg TJ Value 65 ± 20 87.5 0.5 – 65 to +150 200 Unit Vdc Vdc Watts W/°C °C °C
N–Channel Enhancement–Mode Lateral MOSFETs
MRF284 MRF284S
30 W, 2000 MHz, 26 V LATERAL N–CHANNEL BROADBAND RF POWER MOSFETs
CASE 360B–01, STYLE 1 (MRF284)
Ferrite Bead, Round 470 µF, 63 V, Mallory Electrolytic Capacitor 0.6 – 4.5 pF Johansen Gigatrim Variable Capacitors 0.8 – 8.0 pF Johansen Gigatrim Variable Capacitors 0.1 µF Chip Capacitor, KEMET 91 pF ATC RF Chip Capacitors, Case “B” 10 pF ATC RF Chip Capacitors, Case “B” 1000 pF ATC RF Chip Capacitors, Case “B” 5.1 pF ATC RF Chip Capacitors, Case “B” 2.7 pF ATC RF Chip Capacitors, Case “B” 0.4 – 2.5 pF Johansen Gigatrim Variable Capacitors 4 Turns, #27 AWG, 0.087″ OD, 0.050″ ID, 0.069″ Long, 10 nH 9 Turns, #26 AWG, 0.080″ OD, 0.046″ ID, 0.170″ Long, 30.8 nH 2 Turns, #24 AWG, 0.85″ OD, 0.042″ ID, 0.064″ Long, 5.2 nH 12 Ω Fixed Film Chip Resistor 0.08″ x 0.13″ 0.145″ x 0.080″ Microstrip 0.680″ x 0.080″ Microstrip
Instruction manual for Gaggenau RB 280 fridge free
Gaggenauen Information for Use zh-hk使用手冊RB 280Fridge-freezer組合式冷凍冷藏冰箱12en5Table of contents1Safety............................................ 71.1General information.................... 71.2Intended use............................... 71.3Restriction on user group........... 71.4Safe transport............................. 71.5Safe installation.......................... 81.6Safe use ..................................... 91.7Damaged appliance................. 112Preventing material damage ..... 123Environmental protection and saving energy............................. 123.1Disposing of packaging........... 123.2Saving energy........................... 124Installation and connection....... 124.1Scope of delivery...................... 124.2Criteria for the installationlocation..................................... 134.3Installing the appliance ............ 144.4Preparing the appliance forthe first time.............................. 144.5Connecting the appliance tothe electricity supply................. 145Familiarising yourself withyour appliance............................145.1Appliance ................................. 145.2Control panel............................ 146Features...................................... 156.1Shelf.......................................... 156.2Extendable shelf....................... 156.3Folding bottle shelf................... 156.4Fruit and vegetable con-tainer with humidity control...... 156.5Flat frozen food container........ 156.6Door rack.................................. 156.7Accessories.............................. 157Basic operation.......................... 167.1Switching on the appliance...... 167.2Operating tips (16)7.3Switching off the appliance...... 167.4Setting the temperature............ 178Additional functions .................. 178.1Fast cooling ............................. 178.2Automatic Fast freezing............ 178.3Manual Fast freezing................ 178.4Holiday mode........................... 189Alarm........................................... 189.1Door alarm ............................... 189.2Temperature alarm................... 1810Home Connect ......................... 1910.1Setting up Home Connect...... 2010.2Checking the signalstrength .................................. 2010.3Installing updates for theHome Connect software ........ 2010.4Resetting Home Connectsettings................................... 2110.5Data protection....................... 2111Refrigerator compartment....... 2111.1Tips for storing food in therefrigerator compartment ....... 2111.2Chill zones in the refriger-ator compartment................... 2211.3"OK" sticker............................ 2212Freezer compartment............... 2212.1Freezing capacity................... 2212.2Fully utilising the freezercompartment volume ............. 2312.3Tips for storing food in thefreezer compartment.............. 2312.4Tips for freezing fresh food.... 2312.5Shelf life of frozen food at−18 °C.................................... 2312.6Defrosting methods forfrozen food (23)en13Defrosting (24)13.1Defrosting in the refriger-ator compartment (24)13.2Defrosting in the freezercompartment (24)14Cleaning and servicing (25)14.1Preparing the appliance forcleaning (25)14.2Cleaning the appliance (25)14.3Cleaning the condensationchannel and drainage hole (26)14.4Removing the fittings (26)14.5Removing appliance com-ponents (26)15Troubleshooting (27)15.1Power failure (30)15.2Conducting an applianceself-test (30)16Storage and disposal (30)16.1Taking the appliance out ofoperation (30)16.2Disposing of old appliance (30)17Customer Service (31)17.1Product number (E-Nr.) andproduction number (FD) (31)18Technical data (31)19Declaration of Conformity (31)6Safety en71 SafetyObserve the following safety instructions.1.1 General information¡Read this instruction manual carefully.¡Keep the instruction manual and the product information safe for future reference or for the next owner.¡Do not connect the appliance if it has been damaged in transit.1.2 Intended useThis appliance is only intended to be fully fitted in a kitchen.Only use this appliance:¡for chilling and freezing food and for making ice cubes.¡In private households and in enclosed spaces in a domestic en-vironment.¡Up to an altitude of 2000 m above sea level.1.3 Restriction on user groupThis appliance may be used by children aged 8 or over and by people who have reduced physical, sensory or mental abilities or inadequate experience and/or knowledge, provided that they are supervised or have been instructed on how to use the appliance safely and have understood the resulting dangers.Do not let children play with the appliance.Cleaning and user maintenance must not be performed by chil-dren unless they are being supervised.1.4 Safe transportWARNING ‒ Risk of injury!The high weight of the appliance may result in injury when lifted.▶Do not lift the appliance on your own.en Safety81.5 Safe installationWARNING ‒ Risk of electric shock!Incorrect installation is dangerous.▶Connect and operate the appliance only in accordance with the specifications on the rating plate.▶Connect the appliance to a power supply with alternating cur-rent only via a properly installed socket with earthing.▶The protective conductor system of the domestic electrical in-stallation must be properly installed.▶Never equip the appliance with an external switching device,e.g. a timer or remote control.▶When the appliance is installed, the mains plug of the power cord must be freely accessible. If free access is not possible, an all-pole isolating switch must be installed in the permanent elec-trical installation according to the installation regulations.▶When installing the appliance, check that the power cable is not trapped or damaged.If the insulation of the power cord is damaged, this is dangerous.▶Never let the power cord come into contact with heat sources.WARNING ‒ Risk of explosion!If the appliance's ventilation openings are sealed, a leak in the re-frigeration circuit may result in a flammable mixture of gas and air.▶Keep ventilation openings, in the appliance enclosure or in thebuilt-in structure, clear of obstruction.WARNING ‒ Risk of fire!It is dangerous to use an extended power cord and non-approved adapters.▶Do not use extension cables or multiple socket strips.▶Only use adapters and power cords approved by the manufac-turer.▶If the power cord is too short and a longer one is not available,please contact an electrician to have the domestic installation adapted.Safety en9Portable multiple socket strips or portable power supply units may overheat and cause a fire.▶Do not place portable multiple socket strips or power supply units on the back of the appliance.1.6 Safe useWARNING ‒ Risk of electric shock!An ingress of moisture can cause an electric shock.▶Only use the appliance in enclosed spaces.▶Never expose the appliance to intense heat or humidity.▶Do not use steam- or high-pressure cleaners to clean the appli-ance.WARNING ‒ Risk of suffocation!Children may put packaging material over their heads or wrap themselves up in it and suffocate.▶Keep packaging material away from children.▶Do not let children play with packaging material.Children may breathe in or swallow small parts, causing them to suffocate.▶Keep small parts away from children.▶Do not let children play with small parts.WARNING ‒ Risk of explosion!If the cooling circuit is damaged, flammable refrigerant may es-cape and explode.▶To accelerate the defrosting process, do not use any other mechanical devices or means other than those recommended by the manufacturer.▶If food is stuck to the freezer compartment, loosen it with a blunt implement such as the handle of a wooden spoon.Products which contain flammable propellants and explosive sub-stances may explode, e.g. spray cans.▶Do not store products which contain flammable propellants (e.g.spray cans) or explosive substances in the appliance.en Safety10WARNING ‒ Risk of fire!Electrical devices within the appliance may cause a fire, e.g. heat-ers or electric ice makers.▶Do not operate electrical devices within the appliance.WARNING ‒ Risk of injury!Containers that contain carbonated drinks may burst.▶Do not store containers that contain carbonated drinks in the freezer compartment.Injury to the eyes caused by escaping flammable refrigerant and hazardous gases.▶Do not damage the tubes of the refrigerant circuit or the insula-tion.WARNING ‒ Risk of cold burns!Contact with frozen food and cold surfaces may cause burns by refrigeration.▶Never put frozen food straight from the freezer compartment into your mouth.▶Avoid prolonged contact of the skin with frozen food, ice andsurfaces in the freezer compartment.CAUTION ‒ Risk of harm to health!To prevent food from being contaminated, you must observe the following instructions.▶If the door is open for an extended period of time, this may lead to a considerable temperature increase in the compartments of the appliance.▶Regularly clean the surfaces that may come into contact with food and accessible drain systems.▶Store raw meat and fish in suitable containers in the refrigerator so that they do not touch or drip on other food.▶If the fridge/freezer is empty for an extended period of time,switch off the appliance, defrost it, clean it and leave the door open to prevent the formation of mould.Safety en11Metal or metal-style parts in the appliance may contain aluminium.If acidic food comes into contact with aluminium in the appliance,aluminium foil ions may pass into the food.▶Do not consume soiled food.1.7 Damaged applianceWARNING ‒ Risk of electric shock!If the appliance or the power cord is damaged, this is dangerous.▶Never operate a damaged appliance.▶Never pull on the power cord to unplug the appliance. Always unplug the appliance at the mains.▶If the appliance or the power cord is damaged, immediately un-plug the power cord or switch off the fuse in the fuse box.▶Call customer services. → Page 31Incorrect repairs are dangerous.▶Repairs to the appliance should only be carried out by trained specialist staff.▶Only use genuine spare parts when repairing the appliance.▶If the power cord of this appliance is damaged, it must be re-placed by the manufacturer, the manufacturer's Customer Ser-vice or a similarly qualified person in order to prevent any risk.WARNING ‒ Risk of fire!If the tubes are damaged, flammable refrigerant and harmful gases may escape and ignite.▶Keep naked flames and ignition sources away from the appli-ance.▶Ventilate the room.▶Switch off the appliance. → Page 16▶Unplug the appliance from the mains or switch off the circuit breaker in the fuse box.▶Call after-sales service. → Page 31en Preventing material damage122 Preventing material damageATTENTION!Using the base, runners or appliance doors as a seat surface or climbing surface may damage the appliance.▶Do not stand or support yourself on the base, runners or doors.Contamination with oil or fat maycause plastic parts and door seals to become porous.▶Keep plastic parts and door seals free of oil and grease.Metal or metal-style parts in the appli-ance may contain aluminium. Alu-minium reacts when it comes into contact with acidic foods.▶Do not store unpackaged food in the appliance.3 Environmental protec-tion and saving energy3.1 Disposing of packagingThe packaging materials are environ-mentally compatible and can be re-cycled.▶Sort the individual components by type and dispose of them separ-ately.3.2 Saving energyIf you follow these instructions, your appliance will use less power.Selecting the installation location ¡Keep the appliance out of direct sunlight.¡Install the appliance as far away as possible from heating elements,cookers and other heat sources:–Maintain a 30 mm clearance to electric or gas cookers.–Maintain a 300 mm clearance to oil or solid-fuel cookers.¡Use a niche depth of 560 mm.¡Never cover or block the external ventilation openings.Saving energy during useNote: The arrangement of the fittings does not affect the energy consump-tion of the appliance.¡Open the appliance only briefly and then close it carefully.¡Never cover or block the interior ventilation openings or the exterior ventilation openings.¡Transport purchased food in a cool bag and place in the appli-ance quickly.¡Allow warm food and drinks to cool down before storing them.¡Thaw frozen food in the refrigerator compartment to utilise the low tem-perature of the food.¡Always leave some space between the food and to the back panel.¡Defrost the freezer compartment regularly.4 Installation and con-nection4.1 Scope of deliveryAfter unpacking all parts, check for any transport damage and for com-pleteness of delivery.If you have any complaints, contact your dealer or our after-sales service → Page 31.Installation and connection en13The delivery consists of the following:¡Built-in appliance¡Equipment and accessories 1¡Installation material ¡Installation instructions ¡User manual¡Customer service directory ¡Warranty enclosure 2¡Energy label¡Information on energy consump-tion and noises¡Information about Home Connect4.2 Criteria for the installationlocationWARNING Risk of explosion!If the appliance is in a space that is too small, a leak in the refrigeration circuit may result in a flammable mix-ture of gas and air.▶Only install the appliance in a space with a volume of at least 1 m 3 per 8 g refrigerant. Theon the rating plate. → Fig. 1The weight of the appliance ex works may be up to 75 kg depending on the model.The subfloor must be sufficientlystable to bear the weight of the appli-ance.Permitted room temperatureThe permitted room temperature de-pends on the appliance's climate class.the rating plate. → Fig. 1Climate class Permitted room tem-peratureSN 10 °C to 32 °C N 16 °C to 32 °C ST 16 °C to 38 °C T 16 °C to 43 °CThe appliance is fully functional within the permitted room temperature.If an appliance with climate class SN is operated at colder room temperat-ures, the appliance will not be dam-aged up to a room temperature of 5 °C.Niche dimensionsObserve the niche dimensions if you install your appliance in the niche. If this is not the case, problems may occur when installing the appliance.Niche depthInstall the appliance in the recom-mended niche depth of 560 mm.If the niche depth is smaller, the en-ergy consumption increases slightly.The niche depth must be a minimum 550 mm.Niche widthAn inside niche width of at least 560 mm is required for the appli-ance.Over-and-under and side-by-side installationIf you want to install 2 refrigerating appliances one over the other or side by side, you must maintain a clear-ance of at least 150 mm between the appliances. Selected appliances can be installed without a minimum clear-ance. Ask your dealer or kitchen planner about this.1Depending on the appliance specifications 2Not in all countriesen Familiarising yourself with your appliance144.3 Installing the appliance▶Install the appliance in accordancewith the enclosed installation in-structions.4.4 Preparing the appliancefor the first time1.Remove the informative material.2.Remove the protective foil andtransit bolts, e.g. remove the ad-hesive strips and carton.3.Clean the appliance for the first time. → Page 254.5 Connecting the applianceto the electricity supply1.Insert the mains plug of the appli-ance's power cable in a socket nearby.The connection data of the appli-plate. → Fig. 12.Check the mains plug is inserted properly.a The appliance is now ready for use.5 Familiarising yourself with your appliance5.1 ApplianceYou can find an overview of the parts of your appliance here.→Fig. 1Note: Deviations between your appli-ance and the diagrams may differ with regard to their features and size.5.2 Control panelYou can use the control panel to con-figure all functions of your appliance and to obtain information about the operating status.→ Fig.2in °C.Features en156 FeaturesThe features of your appliance de-pend on the model.6.1 ShelfTo vary the shelf as required, you can remove the shelf and re-insert it elsewhere.→ "Removing the shelf", Page 266.2 Extendable shelfIn order to achieve an improved over-view and to remove food morequickly, pull out the extendable shelf.6.3 Folding bottle shelfStore bottles securely on the folding bottle shelf.To use the bottle shelf, fold the metal bracket down.→ Fig. 36.4 Fruit and vegetable con-tainer with humidity con-trolStore fresh fruit and vegetables loose in the fruit and vegetable container.Cover any chopped fruit and veget-ables, or store in air-tight packaging.You can adjust the humidity in the fruit and vegetable container using the humidity controller and a special seal. This allows fresh fruit and veget-ables to be stored for up to twice as long as with conventional storage.→ Fig. 4The air humidity in the fruit and vegetable container can be setaccording to the type and amount of food to be stored by moving the humidity controller:¡Low humidity required when primarily storing fruit or mixed items, or if the appliance is very full.¡High humidity required when primarily storing vegetables or when the appliance is not very full.Condensation may form in the fruit and vegetable container depending on the food and quantity stored.Remove the condensation with a dry cloth and adjust the air humidity to a lower setting using the humidity con-troller.To ensure that the quality and aroma are retained, store fruit and veget-ables that are sensitive to cold out-side of the appliance at temperatures of approx. 8 °C to 12 °C, e.g. pine-apple, bananas, citrus fruits, cucum-bers, courgettes, peppers, tomatoes and potatoes.6.5 Flat frozen food containerStore flat frozen items, the ice stor-age container and the ice scoop in the flat frozen food container.6.6 Door rackTo adjust the door rack as required,you can remove the door rack and re-insert elsewhere.→ "Removing door rack", Page 266.7 AccessoriesUse original accessories. These have been made especially for your appli-ance.The accessories for your appliance depend on the model.en operation16Egg trayStore eggs safely on the egg tray.Bottle holderThe bottle holder prevents bottles from falling over when the appliance door is opened and closed.Press the metal bracket together and slide the bottle tray as close to the bottle as possible .→ Fig. 5Freezer trayYou can freeze smaller quantities of food quickly in the freezer drawer,e.g. berries, pieces of fruit, herbs and vegetables.→ Fig. 6Distribute the frozen food evenly in the frozen food tray and allow to freeze for approx. 10 to 12 hours.Then place in a freezer bag or a freezer box.Ice packUse the ice pack for temporarilykeeping food cool, e.g. in a cool bag.Tip: If a power failure or malfunction occurs, the ice pack can be used to slow down the thawing process for the stored frozen food.Ice cube trayUse the ice cube tray to make ice cubes.Making ice cubesUse only drinking water to make ice cubes.1.Fill the ice cube tray with drinking water up to ¾ and place in the freezer compartment.If the ice cube tray is stuck to the freezer compartment, loosen it with a blunt implement only (e.g. spoon handle).2.To loosen the ice cubes, twist theice cube tray slightly or hold it briefly under flowing water.7 Basic operation7.1 Switching on the appli-ance1.Press.a The appliance begins to cool.a A warning signal sounds, the tem-perature display (freezer compart-ment) flashes and lights up be-cause the freezer compartment is still too warm.2.Switch off the warning tone using.a goes out as soon as the set temperature has been reached.3.Set the required temperature.→ Page 177.2 Operating tips¡Once you have switched on the appliance, the set temperature is only reached after several hours.Do not put any food in the appli-ance until the set temperature has been reached.¡The housing around the freezer compartment is temporarily heated slightly. This prevents condensa-tion in the area of the door seal.¡When you close the door, a va-cuum may be created. The door is then difficult to open again. Wait a moment until the vacuum is offset.7.3 Switching off the appli-ance▶Press.Additional functions en177.4 Setting the temperatureSetting the refrigerator compartment temperature▶Press / (Refrigerator compart-ment) repeatedly until the temper-ature display (refrigerator compart-ment) shows the required temper-ature.The recommended temperature in the refrigerator compartment is 4 °C.→ ""OK" sticker", Page 22Setting the freezer compartment temperature▶Press / (Freezer compartment)repeatedly until the temperature display (freezer compartment)shows the required temperature.The recommended temperature in the freezer compartment is −18 °C.8 Additional functions8.1 Fast coolingWith Fast cooling, the refrigerator compartment cools as cold as pos-sible.Switch on Fast cooling before placing large quantities of food.Note: When Fast cooling is switched on, increased noise may occur.Switching on Fast cooling▶Press (Refrigerator compart-ment).a (Refrigerator compartment)lights up.Note: After approx. 15 hours, the ap-pliance switches to normal operation.Switching off Fast cooling▶Press (Refrigerator compart-ment).a The previously set temperature is displayed.8.2 Automatic Fast freezingWith automatic Fast freezing, thefreezer compartment cools down to a much lower temperature than in nor-mal mode. This freezes food more quickly.The automatic Fast freezing switches on if you place fresh food in the frozen food tray that is attached to the rear of the large frozen food con-tainer or in the flat frozen food con-tainers, starting from the right-hand side.If the automatic Fast freezing is switched on, (Freezer compart-ment) lights up and increased noises may occur.After operation, the applianceswitches from automatic Fast freez-ing to normal operation.Cancelling automatic Fast freezing▶Press (Freezer compartment).a The previously set temperature is displayed.8.3 Manual Fast freezingWith Fast freezing, the freezer com-partment cools as cold as possible.Switch on Fast freezing four tosix hours before placing food weigh-ing 2 kg or more into the freezer compartment.In order to utilise the freezer capacity,use Fast freezing.→ "Prerequisites for freezing capa-city", Page 22en Alarm18Note: When Fast freezing is switched on, increased noise may occur.Switching on manual Fast freezing ▶Press (Freezer compartment).a (Freezer compartment) lights up.Note: After approx. 60 hours, the ap-pliance switches to normal operation.Switching off manual Fast freezing▶Press (Freezer compartment).a The previously set temperature is displayed.8.4 Holiday modeIf you are going to be away for a long time, you can switch on energy-sav-ing holiday mode on the appliance.CAUTIONRisk of harm to health!The refrigerator compartment heats up while the holiday mode isswitched on. The increased temperat-ure may cause bacteria to increase and spoil the food.▶When the holiday mode isswitched on, do not store any food in the refrigerator compartment.The appliance automatically sets the temperatures.Refrigerator com-partment14 °C Freezer compart-ment Temperature re-mains un-changedSwitching on holiday mode ▶Press (Refrigerator compart-ment) repeatedly until the temper-a No temperature is shown in the temperature display (refrigerator compartment).Switching off holiday mode ▶Press (Refrigerator compart-ment) repeatedly until the temper-ature display (refrigerator compart-ment) shows the required temper-ature.9 Alarm9.1 Door alarmIf the appliance door is open for awhile, the door alarm switches on.A warning tone sounds.Switching off the door alarm▶Close the appliance door or press.a The warning tone is switched off.9.2 Temperature alarmIf the freezer compartment becomes too warm, the temperature alarm is switched on.A warning tone sounds and lights up.CAUTIONRisk of harm to health!During the thawing process, bacteria may multiply and spoil the frozen food.▶Do not refreeze food after it has been defrosted or started to de-frost.▶Refreeze food only after cooking.Home Connect en19▶These items should no longer bestored for the maximum storage period.The temperature alarm can beswitched on in the following cases:¡The appliance is switched on.Do not store any food until the ap-pliance has reached the set tem-perature.¡Large quantities of fresh food are being placed inside.Switch on Fast freezing before pla-cing large quantities of food in the appliance.¡The freezer compartment door is open for too long.Check whether the frozen food has defrosted or thawed.Switching off the temperature alarm▶Press .a The warning tone is switched off.a The temperature display (freezer compartment) briefly indicates the warmest temperature reached in the freezer compartment. The tem-perature display (freezer compart-ment) then indicates the set tem-perature again.a From this time on, the warmest temperature is measured again and saved.a lights up until the set temperat-ure is reached again.10 Home ConnectThis appliance is network-capable.Connect your appliance to a mobile device to control its functions via the Home Connect app.The Home Connect services are not available in every country. The avail-ability of the Home Connect function depends on the availability ofHome Connect services in your coun-try. You can find information about this at: .To be able to use Home Connect,you must first set up the connection to the WLAN home network (Wi-Fi 1)and to the Home Connect app.After switching on the appliance, wait at least 2 minutes until internaldevice initialisation is complete. Only then should you set up Home Con-nect.The Home Connect app guides you through the entire login process. Fol-low the instructions in the Home Con-nect app to configure the settings.Tips¡Please consult the documents sup-plied by Home Connect.¡Please also follow the instructions in the Home Connect app.Notes¡Please note the safety precautions in this instruction manual and make sure that they are also ob-served when operating the appli-ance via the Home Connect app. → "Safety", Page 7¡Operating the appliance on the ap-pliance itself always takes priority.During this time it is not possible to operate the appliance using the Home Connect app.1Wi-Fi is a registered trademark of the Wi-Fi Alliance.。
世界各大测井集团仪器编码表
世界各大测井集团仪器编码表BAKER ATLAS WIRELINE (贝克休斯公司-电缆测井）3DEX 3D Induction Logging Service （三维感应）AC BHC Acoustilog （井眼补偿声波）CAL Caliper （井径）CBIL Circumferential Borehole Imaging Log （井周成像测井）CDL Compensated Density Log （补偿密度测井）CN Compensated Neutron Log （补偿中子测井）DAC Digital Array Acoustilog （数字阵列声波测井）DAL Digital Acoustilog （数字声波测井）DEL2 Dielectric Log - 200 Mhz （介电测井-200兆赫）DEL4 Dielectric Log - 47 Mhz （介电测井-47兆赫）DIFL Dual Induction Focused Log （双感应聚聚测井）DIP High Resolution 4-Arm Diplog （高分辨率4臂地层倾角）DLL Dual Laterolog （双侧向测井)DPIL Dual Phase Induction Log (双相位感应测井）EI Earth Imager （地层成像仪）FMT Formation Multi-Tester （地层多功能测试器）GR Gamma Ray （伽马仪）HDIL_BA High-Definition Induction Log （高分辨率感应测井）HDIP Hexagonol Diplog （六臂倾角测井）HDLL High-Definition Lateral Log （高分辨率侧向测井）ICAL Imaging Caliper （井径成像仪）IEL Induction Electrolog （感应-电测井）ISSB Isolation Sub - Spontaneous Potential （自然电位隔离短节）MAC Multipole Array Acoustilog （多极子阵列声波测井）MAC2 Multipole Array Acoustilog （多极子阵列声波测井2）MFC Multi-Finger Caliper （多臂井径仪）ML Minilog （微电极测井仪）MLL Micro Laterolog （微侧向）MREX Magnetic Resonance Explorer Imaging Log （核磁共振探测成像测井）MRIL Magnetic Resonance Imaging Log （核磁共振成像测井）MSL Micro Spherical Laterolog （微球侧向测井）ORIT Directional Survey （井斜方位测井仪）PDK PDK-100PROX Proximity Log （邻近侧向测井仪）RCI Reservoir Characterization Instrument （储层特征描述仪）RCOR Rotary Sidewall Coring Tool （钻进式井壁取心器）RPM Reservoir Performance Monitor （油藏动态监测仪）SBT Segmented Bond Tool （分区水泥胶结测井仪）SL Spectralog （能谱仪）SP Spontaneous Potential （自然电位）STAR Simultaneous Acoustic and Resistivity Imager （声波电阻联合成像仪） SWC Sidewall Coregun （井壁取心器）SYST Surface System （地面系统）TBRT Thin-Bed Resistivity （薄层电阻率）TTRM Temperature/Tension/Mud Resistivity Sub （温度张力泥浆电阻率短节）VS Velocity Survey （速度测量仪）VSP Vertical Seismic Profile （垂直地震剖面）WTS ECLIPS WTS Downhole Common Remote （ECLIPS 井下通用遥传）XMAC Cross-Multipole Array Acoustilog （交叉多极子阵列声波）XMAC-E XMAC Elite (Next generation XMAC) （特种交叉多极子声波）ZDL Compensated Z-Densilog （补偿Z-密度）BAKER INTEQ（贝克休斯INTEQ公司.-随钻测井）AP Annular Pressure （环空压力仪）APX Accoustic Porosity Explorer （声波孔隙度探测仪）CCN Caliper Corrected Neutron （井径校正中子）DIR Directional （定向仪）DPRT Deep Propagation Resistivity （深传播电阻率）FMT Formation Multi-Tester （地层多功能测试器）GR Gamma Ray （伽马仪）MPR Multiple Propogation Resistivity （多传播电阻率）MRT Magnetic Resonance （核磁共振）ORD Compensated Bulk Density（补偿体积密度）RIT Resistivity Imaging （电阻率成像仪）VSS Vibration and Stick Slip (振动蠕动仪）COMPUTALOG 公司AZD Azimuthal Density （方位密度）BCS Borehole Compensated Sonic （井眼补偿声波）CAL Caliper （井径）CDT Compensated Density （补偿密度）CNT Compensated Neutron （补偿中子）DAR Digital Acoustic Tool （数字声波）DLL Dual Laterolog （双侧向测井)DTD Tension Compression （张/压力计）FED Four Electrode Dipmeter （四电极倾角）GR Gamma Ray （伽马仪）GRN Gamma Ray Neutron (伽马中子）HADR High Temperature Azimuthal Gamma Ray （高温方位伽马）HBC High Resolution Borehole Sonic 高分辨率井眼声波）HMI High Resolution Micro Imager （高分辨率微成像）IEL Induction Electric Log （感应测井）MAN Multi Array Neutron （阵列中子）MDA Monopole Dipole Acoustic （单偶极子声波）MEL Micro Electric Log （微电极测井）MFR Multi Frequency Resistivity （多频电阻率测井）MRT400 Micro Resistivity Tool （微电阻率测井仪）MSC Multi Sensor Caliper （多探头井径）MSFL Micro Spherically Focused Log （微球型聚焦测井）NMRT Nuclear Magnetic Resonance Tool （核磁共振测井）NTT Single Detector Neutron （单探头中子）PND Pulsed Neutron Decay （脉冲中子衰变）（中子寿命）RSCT Rotary Sidewall Coring Tool （钻进式井壁取心器）SAGR Spectral Azimuthal Gamma Ray （方位能谱伽马）SED Six Electrode Dipmeter （六电极倾角）SFT Selective Formation Tester （选择性地层测试器）SGR Spectral Gamma Ray （能谱伽马）SP Spontaneous Potential （自然电位）SPeD Spectral Pe Density （能谱Pe密度）STI Simultaneous Triple Induction （联合三感应）TEN Tension （张力计）TNP Thermal Neutron Porosity （热中子孔隙度）HALLIBURTON（哈里伯顿公司.电缆测井）BCS Borehole Compensated Sonic （井眼补偿声波）BHPT Borehole Properties Tool （井眼特性仪器）CAST Circumferential Acoustic Scanning（环形声波扫描仪）CDL Compensated Density Log （补偿密度测井）CSNG Compensated Spectral Natural Gamma Ray （补偿能谱中子伽马） DIL Dual Induction Log （双感应测井）DLLT Dual Laterolog （双侧向测井)DSN Dual Spaced Neutron （双源距中子仪）EMI Electrical Micro Imaging （微电成像）FIAC Four Independent Arm Caliper （四独立臂井径）FWS Full Wave Sonic （全波列声波）GR Gamma Ray （伽马仪）HDIL_HAL Hostile Dual Induction （无敌双感应）HDTD Hostile Downhole Tension （无敌井下张力仪）HFDT High Frequency Dielectric （高频介电测井仪）HRI High Resolution Induction (includes HRAI) （高分辨率感应） HSN Hostile Short Normal （无敌短电位测井仪）LSS Laterolog 3 （三侧向） Long Spaced Sonic （长源距声波）MACT Multi-Arm Caliper Tool （多臂井径仪）MICLOG Microlog （微电极测井仪）MRIL Magnetic Resonance Imaging Log （核磁共振成像测井）MSFL Micro-Spherically Focused Log （微球型聚焦测井仪）NGRT Gamma Ray Tool （伽马仪）RDT Reservoir Description Tool （油藏描述测井仪）RSCT Rotary Sidewall Coring （钻进井臂取心器）SDL Spectral Density Log （能谱密度侧井）SED Six Arm Dipmeter （六臂倾角）SFT Sequential Formation Tester （连续地层测试器）SGR Spectral Gamma Ray （能谱伽马）SP Spontaneous Potential （自然电位）Thermal Multigate Decay-Lithology （热中子多选通衰变岩性测井仪） TMD-LWSD WaveSonic Dipole （偶极子声波）XYC XY Caliper Log （XY井径仪）HALLIBURTON SPERRY SUN（哈里伯顿-随钻测井）ACAL AcoustiCaliper （声波井径）AGR Azimuthal Gamma Ray （方位伽马）ALD Azimuthal Litho Density （方位岩性密度）ASLD Azimuthal Stabilized Litho Density （方位稳定岩性密度）BAT Bi-Modal Acoustic Tool （Bi模声波仪）CNP Compensated Neutron Porosity （补偿中子孔隙度）CTNCompensatedThermalNeu；DDSDrillingDynamicsSenso；DGRDualGammaRay（双伽马仪）；DIRDirectional（定向仪）；EWP4EWR-Phase4（电磁波电阻率-相4；EWR-M5EWR-M5Resistivity（；EWR-P4EWR-Phase4Resisiti；EWR-P4DEWR-PhCTN Compensated Thermal Neutron （补偿热中子）DDS Drilling Dynamics Sensor （钻进动态探测仪）DGR Dual Gamma Ray （双伽马仪）DIR Directional （定向仪）EWP4 EWR - Phase 4 （电磁波电阻率-相4）EWR-M5 EWR-M5 Resistivity （电磁波电阻率-M5）EWR-P4 EWR-Phase 4 Resisitivity （电磁波电阻率-P4）EWR-P4D EWR-Phase 4D Resistivity （电磁波电阻率-P4D）EWRS Electromagnetic Wave Resistivity (Shielded) （屏蔽电磁波电阻率测井仪） GeoTapGM GeoTap Formation Tester （GeoTa地层测试仪） Gamma Module （伽马探测单元）GPGR Geo-Pilot Azimuthal Gamma Ray （Geo-Pilot方位伽马）IVSS Insert Vibration Severity Sensor （嵌入式振动硬度探测仪）MRIL-WD Magnetic Resonance Image Logging （随钻核磁共振成像仪） NGP Natural Gamma Probe （自然伽马探测仪）NUCP Smoothed Neutron Porosity（平滑中子孔隙度）PCG Pressure Case GammaPPFG Pore Pressure/Fracture Gradient （孔隙压力与破裂梯度）PWD Pressure While Drilling （随钻压力探测仪）SFD Simultaneous Formation Density （同行地层密度）SLD Stabilized Litho Density （稳定岩性密度）SSEWR-P4 SuperSlim EWR-Phase 4 （超小井眼电磁波电阻率-P4）SVSS Sonde Vibration Severty Sensor （探头式振动强度探测仪）PATHFINDER LOGGING（导航测井公司）AWR Array Wave Resistivity/Gamma Ray（波列电阻率与伽马）CLSSM Compensated Long Spaced Sonic MultiLink （多连接补偿长源距声波） CWRGM Compensated Wave Resistivity Gamma MultiLink（多连接补偿波列电阻率伽马）DFT Dynamic Formation Tester （动态地层电阻率测试器）DIR Directional （定向仪）DNSCM Density Neutron Standoff Caliper MultiLink （多连接密度中子支撑井径）DPM Dynamic Pressure Module （动态压力单元）GAM Gamma Ray Sonde （伽马探头）GyroHDS1 Gyro High-Speed Directional Survey （旋转高速定向仪） HDS1LHDS1R High-Speed Directional Survey（高速定向仪1L） High-Speed Directional Survey Retrievable （高速定向仪1R） HDSM High-Speed Directional Survey MultiLink （多连接高速定向仪） PWD Pressure While Drilling （随钻压力探测仪）PZIG At-Bit Inclination and Gamma Ray （钻头倾斜于伽马）QPM Survivor Dynamic Pressure Module （动压探测单元）SAWR Slim Array Wave Resistivity/Gamma Ray （小井眼波列电阻率与伽马） SCLSS Slim Compensated Long Spaced Sonic （小井眼补偿长源距声波） SCWR Slim Compensated Wave Resistivity （小井眼补偿波列电阻率）SDNSC Slim Density Neutron Standoff Caliper （小井眼密度中子支撑井径） PRECISION ENERGY （精准能源）AZD Azimuthal Density （方位密度）BAP Bore/Annular Pressure （井眼环空压力）BCS Borehole Compensated Sonic （井眼补偿声波）CALI General Caliper （通用井径仪）CNS Compensated Neutron Service （补偿中子测井）CNT Compensated Neutron Tool （补偿中子仪）DLL Dual Laterolog （双侧向测井)ESM Environmental Severity Measurement （环境硬度测试仪）FCAL Single Axis Caliper （单轴井径仪）GR Flow Rate Tester （泵量测试仪） Gamma Ray （伽马仪）HAGR High Temperature Azimuthal Gamma Ray （高温方位伽马）HBC High Resolution Borehole Sonic （高分辨率井眼声波）HMI High Resolution Micro Imager (高分辨率微成像）IDS Integrated Directional Sonde （综合定向仪）MCG Compact Gamma （嵌入式伽马）MDA Monopole Dipole Array （单偶极子阵列声波）MDN Compact Dual Neutron Sonde （嵌入式双源距中子仪）MFR Multi-Frequency Resistivity （多频电阻率）MFT Compact Repeat Formation Pressure Tester （嵌入式反复式地层压力测试器）MGS Auxiliary Gamma Sub (辅助伽马短节）MPD Compact PhotoDensity Sonde （嵌入式光密度仪）MRT Micro Resistivity Tool （微电阻率测井仪）MSFL Micro Spherically Focused Log （微球型聚焦测井）NMRT Nuclear Magnetic Resonance Tool （核磁共振测井）RSCT Rotary Sidewall Coring Tool （钻进式井壁取心器）SED Six Electrode Dipmeter （六电极倾角）SFT Selective Formation Tester （选择性地层测试器）SGR Spectral Gamma Ray （能谱伽马）SGS-C Spectral Gamma Sonde （能谱伽马探头）SPeD Spectral Pe Density （能谱Pe密度）STI Simultaneous Triple Induction （联合三感应）SWC Sidewall Coring Gun （井壁取心器）TNP Thermal Neutron Porosity （热中子孔隙度）UGR Universal Gamma Ray （多功能伽马仪）VSP Vertical Seismic Profile （垂直地震剖面）PROTECHNICS公司SpectraS SpectraScan - spectral gamma ray （能谱伽马）REEVES WIRELINE 公司MAI Compact Array Induction （嵌入式阵列感应）MBN Compact Borehole Navigator （嵌入式井眼定向仪）MDL_R Compact Dual Laterolog Sonde （嵌入式双侧向）MDN Compact Dual Neutron （嵌入式双源距中子）MFE High Resolution Shallow Focused Electric （高分辨率浅聚焦电法仪） MFT Compact Repeat Formation Pressure Tester （嵌入式重复地层压力测试器） MGS Auxilary Gamma Sub （辅助伽马短节）MML Compact Microlog （嵌入式微电极）MMR Compact Microlaterolog （嵌入式微侧向）MPD Compact PhotoDensity （嵌入式光密度仪）MSS Compact Sonic Sonde （嵌入式声波）MTC Compact Two Arm Caliper （嵌入式两臂井径仪）MCG Compact Gamma （嵌入式伽马）SCHLUMBERGER(斯伦贝谢）AACT Aluminium Activation Clay Tool （铝活化粘土仪）ACT Geochemical Logging Tool （地球化学测井仪）ADN Azimuthal Density Neutron （方位密度中子）AGS Aluminium Gamma Ray Spectroscopy Sonde （铝伽马能谱仪） AIT Array Induction Imager （阵列感应）ALAT Azimuthal Laterolog （方位侧向）AMS Auxiliary Measurement Sonde （辅助测量仪）APS Accelerator Porosity Sonde （加速器型孔隙度探测仪）APWD Annular Pressure While Drilling （随钻环空压力）ARC Array Compensated Resistivity （阵列补偿电阻率）BHTV Borehole Televiewer （井下电视）BSP Bridle Spontaneous Potential （加长电缆自然电位）CALI Generalized Caliper （通用井径仪）CBTT Combinable Borehole Televiewer Tool (组合式井下电视）CDN Compensated Density Neutron （补偿密度中子）CDR Compensated Dual Resistivity （补偿双电阻率）CHFR Cased Hole Formation Resistivity （套管井地层电阻率） CHFT Cased Hole Dynamics Tester (套管井动态测试仪）CMR Combinable Magnetic Resonance （组合式核磁共振） CNL Compensated Neutron Log （补偿中子测井）CNT Compensated Neutron Tool （补偿中子仪）CNTS Slim Compensated Neutron Tool （小井眼补偿中子仪）CST Core Sample Taker; Chronological Sample Taker （井壁取心器） DGR Dual Gamma Ray （双伽马仪）DIT Directional （定向仪） Dual Induction （双感应）DLT Dual Laterolog （双侧向测井)DPT Deep Propagation Tool （深探测电磁波传播测井仪） DSI Dipole Shear Sonic Imager （双极子横波成像仪）DSLT Digitizing Sonic Logging （数字声波）DSST Dipole Shear Sonic Imager （双极子横波成像仪）DST Dual Laterolog with SRT （双侧向微球型聚焦仪）DWST Digital Waterform Sonic （数字波列）ECO Ecoscope （电子耦合仪）ECS Elemental Capture Spectroscopy Sonde （自然俘获能谱仪） EDTC Telemetry Cartridge （遥测短节）EMS Environmental Measurement Sonde （环测仪）EPT Electromagnetic Propagation (ADEPT) （电磁波传播仪） ES Electrical Survey Tool （电法测井仪）FBST Fullbore Formation Micro Imager （全井眼地层微成像仪） FGT Formation Gamma Gamma （地层伽马）FMI Fullbore Formation Micro Imager （全井眼地层微成像仪） FMS Formation Micro Scanner （地层微扫描仪）FPWD Formation Pressure While Drilling （随钻地层压力）GFAFormationTesterGammaR；GNTGammaNeutronTool（伽马中子；GPITGeneralPurposeInclin；GRGammaRay（伽马仪）；GRAGeochemicalReservoirA；GRSTGammaRaySpectrometry；GRTGammaRayTool（伽马仪）；GSTGeo-SteeringTooGFA Formation Tester Gamma Ray Detector （地层测试伽马探测器） GFT Formation Tester Gamma Ray （地层测试伽马探测器）GNT Gamma Neutron Tool （伽马中子）GPIT General Purpose Inclinometry Tool （通用测斜仪）GR Gamma Ray （伽马仪）GRA Geochemical Reservoir Analyzer （地球化学储层分析器）GRST Gamma Ray Spectrometry Tool （伽马能谱仪）GRT Gamma Ray Tool （伽马仪）GST Geo-Steering Tool （地质导向仪)HALS High Resolution Azimuthal Laterlog Sonde (高分辨率方位侧向）HAPS HPHT Accelator Porosity Sonde (aka XAPS) （HPHT加速度型孔隙度） HDT High Resolution Dipmeter （高分辨率倾角）HGNS HILT Gamma Ray Neutron Sonde （高集成伽马中子仪）HILT High Integrated Logging Tool 9(高集成测井仪）HIT Hostile Array Induction Tool (aka XAIT) （无敌阵列感应）HLDS Hostile Litho-Density Sonde （无敌岩性密度）HLDT Hostile Environment Litho-Density（无敌自然岩性密度）HNGS Hostile Gamma Ray Neutron Sonde （无敌伽马中子仪）HNGT Hostile Natural Gamma Ray Spectrometry （无敌中子伽马能谱） HRCC High Resolution Control Cartridge （高分辨率控制短节）HRDD HILT High Resolution Density Device （高集成高分辨率密度仪）HRGD HILT High Resolution Resitivity Gamma Ray Density Device （高集成高分辨率电阻率伽马密度仪）HRLT High-Resolution Laterolog Array Tool （高分辨率阵列侧向）HRMS High Resolution Measurement Sonde （高分辨率测试仪）HSGT Hostile Environment Gamma Ray （无敌自然伽马仪）HSLT HPHT Digial Sonic Logging Tool (aka XSLT) （高温高压数字声波） IMPA IMPulse Array Compensated Resistivity （脉冲阵列补偿电阻率） IPL Integrated Porosity Lithology （集成孔隙度岩性仪）IRT Induction Resistivity Tool （感应电阻率测井仪）LWD Sonic （随钻声波） ISONICLDS Litho Density Sonde （岩性密度测井仪）LDT Litho Density （岩性密度）LSS Long Spaced Sonic （长源距声波）MCFL Micro-Cylindrically Focused Log （微柱型聚焦测井）MDLT Medium Dual Laterolog （介质双侧向仪）MDT Modular Formation Dynamics Tester （模块式地层动态测试器） MLT Microlog （微电极测井仪）MRPS Modular Formation Dynamics Tester Single-Probe （模块式地层动态测试器单探头）MRSC Modular Formation Dynamics Tester Sample Chamber （模块式地层动态测试器取样筒）MRWD Magnetic Resonanace While Drilling （随钻核磁共振）MSCT Mechanical Sidewall Coring Tool （机械式井壁取心器）MSIP Modular Sonic Imaging Platform （模块式声波成像平台）MWD Measurement While Drilling （多功能随钻测量）NGS Natural Gamma Ray Sonde （自然伽马）NGT Natural Gamma Ray Spectrometry （自然伽马能谱）NMT Nuclear Magnetism （核磁共振仪）NPLC Nuclear Porosity Lithology （核孔隙度岩性仪）NPLT Nuclear Porosity Lithology （核孔隙度岩性仪）OBDT Oil Base Mud Dipmeter （油基泥浆地层倾角）OBMI Oil Base Micro Imager （油基泥浆微成像仪）OBMT Oil Base Mud Formation Imager （油基泥浆地层成像仪）PERI Periscope （潜望镜）PGT Compensated Density （补偿密度）PMIT PS Platform Multifinger Imaging Tool （PS平台多指成像仪） PNT Sidewall Neutron Tool （井壁中子仪）QAIT Slim Hostile Array Inducation Tool （小井眼阵列感应）QCNT Slim Hot Compensated Neutron Tool （小井眼高温补偿中子） QLDT Slim XtremeLitho-Density Tool （小井眼特种岩性密度）QSCS Slimhole Power Caliper Sonde （小井眼电动井径仪）QSLT Slim Xtreme Sonic Logging Tool （小井眼特种声波）QTGC SlimXtreme Telemetry and Gamma Ray （小井眼特种遥测伽马）RAB Resisitivity at Bit;Azimuthal Laterolog - Gamma Ray (aka GVR) （钻头位电阻率方位侧向伽马）RFT Repeat Formation Tester （重复式地层测试器）RST Reservoir Saturation Tool （储层饱和度测井）SAIT Slimhole Array Induction （小井眼阵列感应）SDT Sonic Digital （数字声波）SGT Scintillation Gamma Ray （闪烁伽马)SHARP Slim Hole Retrievable MWD Tool (SHDT Stratigraphic High Resolution Dipmeter Tool （地层高分辨率倾角） SLDT Slimhole Litho-Density （小井眼岩性密度）SLIM1 Slim Hole Retrievable MWD Tool （小井眼可起出随钻测井仪） SLT Borehole Compensated Sonic Logging Tool （井眼补偿声波）SMRT Slim Micro Resistivity Tool （小井眼微电阻率测井仪）SNPD Sidewall Neutron Tool （井壁中子仪）SONVIS SonicVISION （声波成像）SP Spontaneous Potential （自然电位）SPE SP Extender （自然电位增强仪）SPULSE Slim Pulse MWD Directional （小井眼脉冲随钻定向仪）SRT Microspherically Focused Resistivity （微球型聚焦电阻率测井仪） SSLT Slim Array Sonic Logging Tool （小井眼阵列声波）STETHO Stethoscope （金属探伤仪）SVWD Seismic Vision While Drilling （随钻地震成像）TDT Thermal Decay Time （热中子衰变时间）TELE Telescope （望远镜）TLD Three-Detector Lithology Density （三维岩性密度）UBI Ultrasonic Borehole Imager （超声井壁成像）USIT Ultrasonic Imager Tool （超声成像仪）VIPER VIPER Slimhole Coiled Tubing MWD Tool （VIPER小井眼随钻挠性管） VISP Vertical Incident Seismic Profile （垂直入射地震剖面）VSI Borehole Seismic Acquisition Tool （井眼地震剖面采集仪）VSP Vertical Seismic Profile （垂直地震剖面）WAVSP Walk Away Vertical Seismic Profile （偏离垂直地震剖面） XPT Pressure Express （快速压力探测仪）WEATHERFORD（威德福公司）AZD Azimuthal Density (方位密度）BAP Bore/Annular Pressure （井眼环空压力）BCS Borehole Compensated Sonic （井眼补偿声波）CAL Caliper （井径）CALI Generalized Caliper （通用井径仪）CDT Compensated Density （补偿密度）CNS Compensated Neutron Service （补偿中子测井）CNT Compensated Neutron Tool （补偿中子仪）DAR Digital Acoustic Tool （数字声波）DIR Directional Survey （井斜方位测井仪）DLL Dual Laterolog Log （双侧向测井仪）DTD Tension Compression （张/压力计）ESM Environmental Severity Measurement （环境硬度测试仪）FCAL Single Axis Caliper （单轴井径仪）FED Four Electrode Dipmeter （四电极倾角）GR Flow Rate Tool （泵量测试仪） Gamma Ray （伽马仪）GRN Gamma Ray Neutron （伽马中子）HAGR High Temperature Azimuthal Gamma Ray （高温方位伽马）HBC High Resolution Borehole Compensated Sonic Log （高分辨率井眼补偿声波）HMI High Resolution Micro Imager （高分辨率微成像）IEL Integrated Directional Sonde （综合定向仪） Induction Electrolog （感应-电测井）MAI Compact Array Induction （嵌入式阵列感应）MAN Multi Array Neutron （阵列中子）MBN Compact Borehole Navigation （嵌入式井眼定位仪）MCG Compact Gamma （嵌入式伽马）MDA Monopole Dipole Acoustic （单偶极子声波）MDL_R Compact Dual Laterolog Sonde （嵌入式双侧向）MDN Compact Dual Neutron （嵌入式双源距中子）MEL Micro Electric Log （微电极测井）MFE High Resolution Shallow Focused Electric （高分辨率浅聚焦电法仪） MFR Multi Frequency Resistivity （多频电阻率测井）MFT Compact Repeat Formation Pressure Tester （嵌入式反复式地层压力测试器）MGS Auxilary Gamma Sub （辅助伽马短节）MMR Compact Microlaterolog （嵌入式微侧向）MPD Compact PhotoDensity （嵌入式光密度仪）MRT400 Micro Resistivity Tool （微电阻率测井仪）MRT-P Micro Resistivity Tool （微电阻率测井仪）MSFL Micro-Spherically Focused Log （微球型聚焦测井仪）MSS Compact Sonic Sonde （嵌入式声波）MTC Compact Two Arm Caliper （嵌入式两臂井径仪）NMRT Nuclear Magnetic Resonance Tool （核磁共振测井）NTT Single Detector Neutron （单探头中子）RSCT Rotary Sidewall Coring (HRSCT) （钻进式井壁取心器）SAGRSpectralAzimuthalGam；SFTSequentialFormationTe；SGS-CSpectralGammaSonde（；SPEDSpectralPeDensity（能谱；SST；STIShockWaveSonicTool（冲击；TENTension（张力计）；TNPThermalNeutronPorosit；SAGR Spectral Azimuthal Gamma Ray （方位能谱伽马） SEDSix Arm Dipmeter Survey （六臂倾角）SFT Sequential Formation Tester （连续地层测试器） SGR Spectral Gamma Ray （能谱伽马）SGS-C Spectral Gamma Sonde （能谱伽马探头） SP Spontaneous Potential （自然电位）SPED Spectral Pe Density （能谱Pe密度）STI Shock Wave Sonic Tool （冲击波声波仪） Simultaneous Triple Induction （联合三感应） SWC Sidewall Coregun （井壁取心器）TEN Tension （张力计）TNP Thermal Neutron Porosity （热中子孔隙度） UGR Universal Gamma Ray （多功能伽马仪） VSP Vertical Seismic Profile （垂直地震剖面）。
液偶说明书-中文
4 运输和储存 .................................................................................................错误！未定义书签。
ANSI_B92.1-1970(R1993)_SAE花键
外径配合部分，（与旧版相比）公差和配合情况没有改变。
The Standard recognizes the fact that proper assembly between mating splines is dependent only on the spline being within effective specifications from the tip of the tooth to the form diameter. Therefore, on side fit splines, the internal spline major diameter now is shown as a maximum dimension and the external spline minor diameter is shown as a minimum dimension. The minimum internal major diameter and the maximum external minor diameter must clear the specified form diameter and thus do not need any additional control.
译注A4：内花键尺寸不变，外花键变，原理等同于基孔制。
In American National Standard ANSI B92.1-1970 (R 1993), many features of the 1960 Copyright 2008, Industrial Press Inc., New York, NY -
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Communication Products and Converters, Data Acquisition and Analysis Software, Data Loggers Plug-in Cards, Signal Conditioners, USB, RS232, RS485, Ehernet and Parallel Port Data Acquisition Systems, Wireless Transmitters and Receivers
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Band Heaters, Cartridge Heaters, Circulation Heaters, Comfort Heaters, Controllers, Meters and Switching Devices, Flexible Heaters, General Test and Measurement Instruments, Heater Hook-up Wire, Heating Cable Systems, Immersion Heaters, Process Air and Duct, Heaters, Radiant Heaters, Strip Heaters, Tubular Heaters
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Displacement Transducers, Dynamic Measurement Force Sensors, Instrumentation for Pressure and Strain Measurements, Load Cells, Pressure Gauges, Pressure Reference Section, Pressure Switches, Pressure Transducers, Proximity Transducers, Regulators, Pressure Transmitters, Strain Gauges, Torque Transducers, Valves
UC2879中文资料
3
元器件交易网
UC1879 UC2879 UC3879 ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL =12V, CT = 470pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01µF, TA = TJ.
DIL-20, SOIC-20 (Top View) J or N Package, DW Package
CLCC-28 (Top View) L Package
PLCC-20 (Top View) Q Package
2
元器件交易网
UC1879 UC2879 UC3879 ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL =12V, CT = 470pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01µF, TA = TJ.
PARAMETER Undervoltage Lockout Start Threshold UVLO Hysteresis Input Bias, UVSEL Pin Supply Current IVIN Startup IVC Startup IVIN Operating IVC Operating Voltage Reference Output Voltage Line Regulation Load Regulation Total Variation Short Circuit Current Error Amplifier Error Amplifier Input Voltage Input Bias Current AVOL PSRR Output Sink Current Output Source Current Output Voltage High Output Voltage Low Slew Rate PWM Comparator RAMP Offset Voltage PWM Phase Shift, TDELSETA-B, TDELSETC-D = 0, Note 1 Output Skew, TDELSETA-B, TDELSETC-D = 0, Note 1 Ramp to Output Delay, TDELSETA-B = 0, TDELSETC-D = 0 Oscillator Initial Accuracy Voltage Stability Total Variation CLKSYNC Threshold Clock Out High Clock Out Low Clock Out Pulse Width Ramp Valley Voltage TA = 25°C 11V < VIN < 18V Line, Temperature 160 2.3 2.8 0.5 180 200 1 200 2.5 4 1 400 0.2 1.5 600 0.4 220 2 240 2.7 kHz % kHz V V V ns V TJ = 25°C, Note 3 VCOMP > VRAMPpeak + VRAMPoffset VCOMP < Zero Phase Shift Voltage VCOMP > VRAMPpeak + VRAMPoffset VCOMP < Zero Phase Shift Voltage UC3879, UC2879 UC1879 1.1 98 0 1.25 99.7 0.3 10 10 115 115 250 300 1.4 102 2 V % % ns ns ns ns 1V < VCOMP < 4V 11V < VIN < 18V VCOMP = 1V VCOMP = 4V ICOMP = –0.5mA ICOMP = 1mA TA = +25°C 4 0 6 60 85 1 2.4 2.5 0.6 90 100 2.5 −1.3 4.7 0.5 11 −0.5 5 1 2.6 3 V µA dB dB mA mA V V V/µs TJ = +25°C 11V < VIN < 18V IVREF = –10mA Line, Load, Temperature VREF = 0V, TJ = 25°C 4.875 –60 4.92 5 1 5 5.08 10 20 5.125 –15 V mV mV V mA VIN = VUVSEL = 8V, VC = 18V, IDELSETA-B = IDELSETC-D = 0 VIN = VUVSEL = 8V, VC = 18V, IDELSETA-B = IDELSETC-D = 0 UC3879, UC2879 UC1879 150 10 23 23 4 600 100 33 36 8 µA µA mA mA mA VUVSEL = VIN VUVSEL = Open VUVSEL = VIN VUVSEL = Open VUVSEL = VIN = 8V 9 12.5 1.15 5.2 10.75 15.25 1.75 6 30 12.5 16.5 2.15 7.4 V V V V µA TEST CONDITIONS MIN TYP MAX UNITS
DS90CR284MTD中文资料
DS90CR283/DS90CR28428-Bit Channel Link-66MHzGeneral DescriptionThe DS90CR283transmitter converts 28bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling)data streams.A phase-locked transmit clock is transmitted in par-allel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28bits of input data are sampled and transmitted.The DS90CR284receiver converts the LVDS data streams back into 28bits of CMOS/TTL data.At a trans-mit clock frequency of 66MHz,28bits of TTL data are trans-mitted at a rate of 462Mbps per LVDS data ing a 66MHz clock,the data throughput is 1.848Gbit/s (231Mbytes/s).The multiplexing of the data lines provides a substantial cable reduction.Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability).Thus,for a 28-bit wide data bus and one clock,up to 58conductors are required.With the Channel Link chipset as few as 11conductors (4data pairs,1clock pair and a minimum of one ground)are needed.This provides a 80%reduction in required cablewidth,which provides a system cost savings,reduces con-nector physical size and cost,and reduces shielding require-ments due to the cables’smaller form factor.The 28CMOS/TTL inputs can support a variety of signal combinations.For example,74-bit nibbles or 39-bit (byte +parity)and 1control.Featuresn 66MHz clock supportn Up to 231Mbytes/s bandwidthn Low power CMOS design (<610mW)n Power Down mode (<0.5mW total)n Up to 1.848Gbit/s data throughputn Narrow bus reduces cable size and cost n 290mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package n Rising edge data strobenCompatible with TIA/EIA-644LVDS StandardBlock DiagramsTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS90CR283DS012889-27Order Number DS90CR283MTD See NS Package Number MTD56DS90CR284DS012889-1Order Number DS90CR284MTD See NS Package Number MTD56July 1997DS90CR283/DS90CR28428-Bit Channel Link-66MHz©1998National Semiconductor Corporation Pin DiagramsTypical ApplicationDS90CR283DS012889-21DS90CR284DS012889-22DS012889-23 2Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)−0.3V to+6V CMOS/TTL Input Voltage−0.3V to(V CC+0.3V) CMOS/TTL Ouput Voltage−0.3V to(V CC+0.3V) LVDS Receiver Input Voltage−0.3V to(V CC+0.3V) LVDS Driver Output Voltage−0.3V to(V CC+0.3V) LVDS Output Short CircuitDuration Continuous Junction Temperature+150˚C Storage Temperature Range−65˚C to+150˚C Lead Temperature(Soldering,4sec.)+260˚C Maximum Package Power Dissipation@+25˚CMTD56(TSSOP)Package:DS90CR283 1.63W DS90CR284 1.61W Package Derating:DS90CR28312.5mW/˚C above+25˚C DS90CR28412.4mW/˚C above+25˚C This device does not meet2000V ESD rating(Note4)Recommended Operating ConditionsMin Nom Max Units Supply Voltage(V CC) 4.75 5.0 5.25V Operating Free AirTemperature(T A)−10+25+70˚C Receiver Input Range0 2.4V Supply Noise Voltage(V CC)100mV P-PElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONSV IH High Level Input Voltage 2.0V CC VV IL Low Level Input Voltage GND0.8VV OH High Level Output Voltage I OH=−0.4mA 3.8 4.9VV OL Low Level Output Voltage I OL=2mA0.10.3VV CL Input Clamp Voltage I CL=−18mA−0.79−1.5VI IN Input Current V IN=V CC,GND,2.5V or0.4V±5.1±10µAI OS Output Short Circuit Current V OUT=0V−120mA LVDS DRIVER DC SPEClFlCATIONSV OD Differential Output Voltage R L=100Ω250290450mV∆V OD Change in V OD between35mV Complementary Output StatesV OS Offset Voltage 1.1 1.25 1.375V∆V OS Change in Magnitude of V OSbetween Complementary OutputStates35mVI OS Output Short Circuit Current V OUT=OV,R L=100Ω−2.9−5mAI OZ Output TRI-STATE®Current Power Down=0V,V OUT=0V or V CC±1±10µA LVDS RECEIVER DC SPECIFlCATIONSV TH Differential Input High Threshold V CM=+1.2V+100mVV TL Differential Input Low Threshold−100mVI IN Input Current V IN=+2.4V,V CC=5.0V±10µAV IN=0V,V CC=5.0V±10µA TRANSMITTER SUPPLY CURRENTI CCTW Transmitter Supply Current,R L=100Ω,C L=5pF,f=32.5MHz4963mAWorst Case Worst Case Pattern f=37.5MHz5164mA(Figures1,2)f=66MHz7084mAI CCTZ Transmitter Supply Current,Power Down=LowPower Down Driver Outputs in TRI-STATEunder Power Down Mode125µA3Electrical Characteristics(Continued)Over recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENTI CCRW Receiver Supply Current,Worst Case C L=8pF,f=32.5MHz6477mA Worst Case Pattern f=37.5MHz7085mA (Figures1,3)f=66MHz110140mAI CCRZ Receiver Supply Current,Power Down=LowPower Down Receiver Outputs in Previous Stateduring Power Down Mode110µA Note1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the device should be operated at these limits.The tables of“Electrical Characteristics”specify conditions for device operation.Note2:Typical values are given for V CC=5.0V and T A=+25˚C.Note3:Current into device pins is defined as positive.Current out of device pins is defined as negative.Voltages are referenced to ground unless otherwise speci-fied(except V OD and∆V OD).Note4:ESD Rating:HBM(1.5kΩ,100pF)PLL V CC≥1000VAll other pins≥2000VEIAJ(0Ω,200pF)≥150VNote5:V OS previously referred as V CM.Transmitter Switching CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time(Figure2)0.75 1.5ns LHLT LVDS High-to-Low Transition Time(Figure2)0.75 1.5ns TCIT TxCLK IN Transition Time(Figure4)8ns TCCS TxOUT Channel-to-Channel Skew(Note6)(Figure5)350psTPPos0Transmitter Output Pulse Position for Bit0f=66MHz−0.3000.30ns(Figure16)TPPos1Transmitter Output Pulse Position for Bit1 1.70(1/7)T clk 2.50ns TPPos2Transmitter Output Pulse Position for Bit2 3.60(2/7)T clk 4.50ns TPPos3Transmitter Output Pulse Position for Bit3 5.90(3/7)T clk 6.75ns TPPos4Transmitter Output Pulse Position for Bit48.30(4/7)T clk9.00ns TPPos5Transmitter Output Pulse Position for Bit510.40(5/7)T clk11.10ns TPPos6Transmitter Output Pulse Position for Bit612.70(6/7)T clk13.40TCIP TxCLK IN Period(Figure6)15T50ns TCIH TxCLK IN High Time(Figure6)0.35T0.5T0.65T ns TCIL TxCLK IN Low Time(Figure6)0.35T0.5T0.65T ns TSTC TxIN Setup to TxCLK IN(Figure6)5 3.5ns THTC TxIN Hold to TxCLK IN(Figure6) 2.5 1.5ns TCCD TxCLK IN to TxCLK OUT Delay@25˚C, 3.58.5ns V CC=5.0V(Figure8)TPLLS Transmitter Phase Lock Loop Set(Figure10)10ms TPDD Transmitter Power Down Delay(Figure14)100ns Note6:This limit based on bench characterization.4Receiver Switching CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time(Figure3) 2.5 4.0ns CHLT CMOS/TTL High-to-Low Transition Time(Figure3) 2.0 4.0ns RSKM RxIN Skew Margin(Note7),f=40MHz700ps V CC=5V,T A=25˚C(Figure17)f=66MHz600ps RCOP RxCLK OUT Period(Figure7)15T50ns RCOH RxCLK OUT High Time(Figure7)f=40MHz6nsf=66MHz 4.35ns RCOL RxCLK OUT Low Time(Figure7)f=40MHz10.5nsf=66MHz7.09ns RSRC RxOUT Setup to RxCLK OUT(Figure7)f=40MHz 4.5nsf=66MHz 2.5 4.2ns RHRC RxOUT Hold to RxCLK OUT(Figure7)f=40MHz 6.5nsf=66MHz4 5.2ns RCCD RxCLK IN to RxCLK OUT Delay@25˚C, 6.410.7ns V CC=5.0V(Figure9)RPLLS Receiver Phase Lock Loop Set(Figure11)10ms RPDD Receiver Power Down Delay(Figure11)1µsNote7:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.This margin takes into account transmitter output skew(TCCS) and the setup and hold time(internal data sampling window),allowing for LVDS cable skew dependent on type/length and source clock(TxCLK IN)jitter.RSKM≥cable skew(type,length)+source clock jitter(cycle to cycle)AC Timing DiagramsDS012889-2FIGURE1.“WORST CASE”Test PatternDS012889-3DS012889-4 FIGURE2.DS90CR283(Transmitter)LVDS Output Load and Transition TimingDS012889-5DS012889-6 FIGURE3.DS90CR284(Receiver)CMOS/TTL Output Load and Transition Timing5AC Timing Diagrams(Continued)DS012889-7FIGURE4.DS90CR283(Transmitter)Input Clock Transition TimeDS012889-8 Note8:Measurements at V diff=0VNote9:TCCS measured between earliest and latest initial LVDS edges.Note10:TxCLK OUT Differential Low→High EdgeFIGURE5.DS90CR283(Transmitter)Channel-to-Channel SkewDS012889-9FIGURE6.DS90CR283(Transmitter)Setup/Hold and High/Low TimesDS012889-10FIGURE7.DS90CR284(Receiver)Setup/Hold and High/Low Times 6AC Timing Diagrams(Continued)DS012889-11FIGURE8.DS90CR283(Transmitter)Clock In to Clock Out DelayDS012889-12FIGURE9.DS90CR284(Receiver)Clock In to Clock Out DelayDS012889-13FIGURE10.DS90CR283(Transmitter)Phase Lock Loop Set TimeDS012889-14FIGURE11.DS90CR284(Receiver)Phase Lock Loop Set Time7AC Timing Diagrams(Continued)DS012889-15FIGURE12.Seven Bits of LVDS in One Clock CycleDS012889-16 FIGURE13.28Parallel TTL Data Inputs Mapped to LVDS Outputs(DS90CR283)DS012889-17FIGURE14.Transmitter Powerdown Delay8AC Timing Diagrams(Continued)DS012889-19FIGURE16.Transmitter LVDS Output Pulse Position MeasurementDS012889-20SW—Setup and Hold Time(Internal data sampling window)TCCS—Transmitter Output SkewRSKM≥Cable Skew(type,length)+Source Clock Jitter(cycle to cycle)Cable Skew—typically10ps–40ps per foot.FIGURE17.Receiver LVDS Input Skew Margin9DS90CR283Pin Description—Channel Link TransmitterPin Name I/O No.DescriptionTxIN I28TTL Level inputsTxOUT+O4Positive LVDS differential data outputTxOUT−O4Negative LVDS differential data outputTxCLK IN I1TTL level clock input.The rising edge acts as data strobeTxCLK OUT+O1Positive LVDS differential clock outputTxCLK OUT−O1Negative LVDS differential clock outputPWR DOWN I1TTL level input.Assertion(low input)TRI-STATES the outputs,ensuring low current at powerdownV CC I4Power supply pins for TTL inputsGND I5Ground pins for TTL inputsPLL V CC I1Power supply pin for PLLPLL GND I2Ground pins for PLLLVDS V CC I1Power supply pin for LVDS outputsLVDS GND I3Ground pins for LVDS outputsDS90CR284Pin Description—Channel Link ReceiverPin Name I/O No.DescriptionRxIN+I4Positive LVDS differential data inputsRxIN−I4Negative LVDS differential data inputsRxOUT O28TTL level outputsRxCLK IN+I1Positive LVDS differential clock inputRxCLK IN−I1Negative LVDS differential clock inputRxCLK OUT O1TTL level clock output.The rising edge acts as data strobePWR DOWN I1TTL level input.Assertion(low input)maintains the receiver outputs in the previous stateV CC I4Power supply pins for TTL outputsGND I5Ground pins for TTL outputsPLL V CC I1Power supply for PLLPLL GND I2Ground pin for PLLLVDS V CC I1Power supply pin for LVDS inputsLVDS GND I3Ground pins for LVDS inputsApplications InformationThe Channel Link devices are intended to be used in a widevariety of data transmission applications.Depending uponthe application the interconnecting media may vary.For ex-ample,for lower data rate(clock rate)and shorter cablelengths(<2m),the media electrical performance is less criti-cal.For higher speed/long distance applications the media’sperformance becomes more critical.Certain cable construc-tions provide tighter skew(matched electrical length be-tween the conductors and pairs).Twin-coax for example,hasbeen demonstrated at distances as great as5meters andwith the maximum data transfer of1.848Gbit/s.Additionalapplications information can be found in the following Na-tional Interface Application Notes:AN=####TopicAN-1041Introduction to Channel LinkAN-1035PCB Design Guidelines for LVDS andLink DevicesAN-806Transmission Line TheoryAN=####TopicAN-905Transmission Line Calculations andDifferential ImpedanceAN-916Cable InformationCABLES:A cable interface between the transmitter and re-ceiver needs to support the differential LVDS pairs.The 21-bit CHANNEL LINK chipset(DS90CR213/214)requires four pairs of signal wires and the28-bit CHANNEL LINK chipset(DS90CR283/284)requires five pairs of signal wires. The ideal cable/connector interface would have a constant 100Ωdifferential impedance throughout the path.It is also recommended that cable skew remain below350ps(@66 MHz clock rate)to maintain a sufficient data sampling win-dow at the receiver.In addition to the four or five cable pairs that carry data and clock,it is recommended to provide at least one additional conductor(or pair)which connects ground between the transmitter and receiver.This low impedance ground pro-vides a common mode return path for the two devices.Some of the more commonly used cable types for point-to-point ap-10Applications Information(Continued) plications include flat ribbon,flex,twisted pair and Twin-Coax.All are available in a variety of configurations and options.Flat ribbon cable,flex and twisted pair generally per-form well in short point-to-point applications while Twin-Coax is good for short and long applications.When using ribbon cable,it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling be-tween adjacent pairs.For Twin-Coax cable applications,it is recommended to utilize a shield on each cable pair.All ex-tended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type.This overall shield results in improved transmis-sion parameters such as faster attainable speeds,longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.The high-speed transport of LVDS signals has been demon-strated on several types of cables with excellent results. However,the best overall performance has been seen when using Twin-Coax cable.Twin-Coax has very low cable skew and EMI due to its construction and double shielding.All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem com-munications designer with many useful guidelines.It is rec-ommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution.BOARD LAYOUT:To obtain the maximum benefit from the noise and EMI reductions of LVDS,attention should be paid to the layout of differential lines.Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise can-celing of the differential signals.The board designer should also try to maintain equal length on signal traces for a given differential pair.As with any high speed design,the imped-ance discontinuities should be limited(reduce the numbers of vias and no90degree angles on traces).Any discontinui-ties which do occur on one signal line should be mirrored in the other line of the differential pair.Care should be taken to ensure that the differential trace impedance match the differ-ential impedance of the selected physical media(this imped-ance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input).Finally,the location of the CHANNEL LINK TxOUT/ RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.All of these consider-ations will limit reflections and crosstalk which adversely ef-fect high frequency performance and EMI.UNUSED INPUTS:All unused inputs at the TxIN inputs of the transmitter must be tied to ground.All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION:Use of current mode drivers requires a ter-minating resistor across the receiver inputs.The CHANNEL LINK chipset will normally require a single100Ωresistor be-tween the true and complement lines on each differential pair of the receiver input.The actual value of the termination resistor should be selected to match the differential mode characteristic impedance(90Ωto120Ωtypical)of the cable. Figure18shows an example.No additional pull-up or pull-down resistors are necessary as with some other differ-ential technologies such as PECL.Surface mount resistors are recommended to avoid the additional inductance that ac-companies leaded resistors.These resistors should be placed as close as possible to the receiver input pins to re-duce stubs and effectively terminate the differential lines. DECOUPLING CAPACITORS:Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance.For a conservative approach three parallel-connected decoupling capacitors(Multi-Layered Ce-ramic type in surface mount form factor)between each V CC and the ground plane(s)are recommended.The three ca-pacitor values are0.1µF,0.01µF and0.001µF.An example is shown in Figure19.The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane.If board space is limiting the number of bypass capacitors,the PLL V CC should receive the most filtering/bypassing.Next would be the LVDS V CC pins and finally the logic V CC pins.DS012889-24FIGURE18.LVDS Serialized Link Termination11Applications Information(Continued)CLOCK JITTER:The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface.The width of each bit in the serialized LVDS data stream is one-seventh the clock period.For example,a 66MHz clock has a period of 15ns which results in a data bit width of 2.16ns.Differential skew (∆t within one differential pair),interconnect skew (∆t of one differential pair to an-other)and clock jitter will all reduce the available window for sampling the LVDS serial data streams.Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal.Individual bypassing of each V CC to ground will minimize the noise passed on to the PLL,thus creating alow jitter LVDS clock.These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget.COMMON MODE vs.DIFFERENTIAL MODE NOISE MAR-GIN:The typical signal swing for LVDS is 300mV centered at +1.2V.The CHANNEL LINK receiver supports a 100mV threshold therefore providing approximately 200mV of differ-ential noise mon mode protection is of more im-portance to the system’s operation due to the differential data transmission.LVDS supports an input voltage range of Ground to +2.4V.This allows for a ±1.0V shifting of the cen-ter point due to ground potential differences and common mode noise.POWER SEQUENCING AND POWERDOWN MODE:Out-puts of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 3V.Clock and data outputs will begin to toggle 10ms after V CC has reached 4.5V and the Powerdown pin is above 2V.Either device may be placed into a powerdown mode at any time by asserting the Power-down pin (active low).Total power dissipation for each de-vice will decrease to 5µW (typical).The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or re-ceiver.If power to the transmit board is lost,the receiver clocks (input and output)stop.The data outputs (RxOUT)re-tain the states they were in when the clocks stopped.When the receiver board loses power,the receiver inputs are shorted to V CC through an internal diode.Current is limited (5mA per input)by the fixed current mode drivers,thus avoiding the potential for latchup when powering the device.DS012889-25FIGURE 19.CHANNEL LINK Decoupling Configuration DS012889-26FIGURE 20.Single-Ended and Differential Waveforms 1213Physical Dimensions inches(millimeters)unless otherwise notedLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or(b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,canbe reasonably expected to result in a significant injuryto the user.2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system,or to affect its safety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5620-6175Fax:81-3-5620-617956-Lead Molded Thin Shrink Small Outline Package,JEDECOrder Number DS90CR283MTD or DS90CR284MTDNS Package Number MTD56DS9CR283/DS9CR28428-BitChannelLink-66MHzNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。
L297,L298中文资料介绍
L297-L298中文资料介绍默认分类 2009-09-10 17:03 阅读985 评论0字号：大大中中小小L297的工作原理介绍L297是意大利SGS半导体公司生产的步进电机专用控制器，它能产生4相控制信号，可用于计算机控制的两相双极和四相单相步进电机，能够用单四拍、双四拍、四相八拍方式控制步进电机。
芯片内的PWM斩波器电路可开关模式下调节步进电机绕组中的电机绕组中的电流。
该集成电路采用了SGS公司的模拟/数字兼容的I2L技术，使用5V的电源电压，全部信号的连接都与TFL/CMOS或集电极开路的晶体管兼容。
L297的芯片引脚特别紧凑，采用双列直插20脚塑封封装，其引脚见图1，内部方框见图2。
在图2所示的L297的内部方框图中。
变换器是一个重要组成部分。
变换器由一个三倍计算器加某些组合逻辑电路组成，产生一个基本的八格雷码(顺序如图3所示)。
由变换器产生4个输出信号送给后面的输出逻辑部分，输出逻辑提供禁止和斩波器功能所需的相序。
为了获得电动机良好的速度和转矩特性，相序信号是通过2个PWM斩波器控制电动波器包含有一个比较器、一个触发器和一个外部检测电阻，如图4所示，晶片内部的通用振荡器提供斩波频率脉冲。
每个斩波器的触发器由振荡器的脉冲调节，当负载电流提高时检测电阻上的电压相对提高，当电压达到Uref时(Uref是根据峰值负载电流而定的)，将触发器重置，切断输出，直至第二个振荡脉冲到来、此线路的输出(即触发器Q输出)是一恒定速率的PWM信号，L297的CONTROL端的输入决定斩波器对相位线A，B，C，D或抑制线INH1和INH2起作用。
CONTROL为高电平时，对A，B，C，D有抑制作用；为低电平时，则对抑制线INH1和INH2有抑制作用，从而可对电动机和转矩进行控制。
图1 L297引脚图图2 L297内部方框电路图图3 L297变换器换出的八步雷格码（顺时针旋转）图4 斩波器线路图5 多个L297同步工作连接图L297各引脚功能说明1脚(SYNG)——斩波器输出端。
PDA TR29(1998)中英文对照版[1]
![PDA TR29(1998)中英文对照版[1]](https://img.taocdn.com/s3/m/a7cef87f02768e9951e738ca.png)
Russell E. Madsen Chairman, Pharmaceutical Cleaning Validation Task Force
制药清洁验证工作小组主席
蒲公英论坛首发。Eleven 制作，未经许可请勿在其他网站和论坛发布。
Table of Contents
目录
1. Introduction 简介 1.1 Background 背景 1.2 Purpose 目的 1.3 Scope 范围 1.4 Report Organization 本报告的组织架构 Finished Pharmaceuticals 制剂 Biopharmaceuticals 生物制品 Bulk Pharmaceutical Chemicals 原料药 Clinical Products 临床试验用品
蒲公英论坛首发。Eleven 制作，未经许可请勿在其他网站和论坛发布。
believe this approach accomplished the widest possible review of the document and ensures its suitability as a valuable guide to industry in the area of cleaning validation. This document should be considered as a guide; it is not intended to establish any mandatory or implied standard. 在出版之前，本技术报告的草案曾经过公众的讨论与建议；许多建议都已并入本最终文 件中。我们相信这广征意见的处理方式能使本文件成为制药工业在清洁确认方面游泳的 指导。本文件应被视为是一种指南，其内容并非强制性，不在于强制或暗示的标准。
福禄克287_289
使用手冊
終生有限保證
Fluke 保證，每 一台 Fluke 20、70、80、170、180 和 280 系列的 DMM，其用料和做工終生皆毫無瑕疵。此處所謂的 “終生”意指 Fluke 停止製造該產 品之後七年，但保證有效期限應為購買日算起至少十年。本項保證不包括保險 絲、拋 棄式電池以及因疏忽、誤用、污 染、改變、意外或非正常狀 況下的使用或處理所造成的損壞（包括超出產 品規格的使用所引起的故障或機械部件的正常損耗）。本項保證僅適用於原購買者並且不得轉讓。
June 2007 (Traditional Chinese)
© 2007 Fluke Corporation. All rights reserved. All product names are trademarks of their respective companies.
®
287/289
True-rms Digital Multimeters
阴极射线管[发明专利]
![阴极射线管[发明专利]](https://img.taocdn.com/s3/m/cea2ad3b5022aaea998f0ffc.png)
专利名称：阴极射线管
专利类型：发明专利
发明人：泷泽智纪,藤井儱,前田美佳子申请号：CN95118523.3
申请日：19951027
公开号：CN1134033A
公开日：
19961023
专利内容由知识产权出版社提供
摘要：本发明的目的是获得能抑制阴极射线管的荧光屏表面上的外界反射光带色的3层或两层低反射涂层。
在3层或两层低反射涂层中，将黄色染料或颜料添加在每一层或若干层中。
通过添加黄色染料或颜料，可见光区域的反射光谱被平坦化，因此能抑制短波长及长波长区域的反射，能获得备有具有带色少的自然的外界反射光的3层或两层低反射涂层的阴极射线管。
申请人：三菱电机株式会社
地址：日本东京都
国籍：JP
代理机构：中国专利代理(香港)有限公司
更多信息请下载全文后查看。
ul2849 中文标准
ul2849 中文标准
UL2849的中文标准是电动自行车充电器安全认证。
UL2849是由美国UnderwritersLaboratories（UL）制定的电动自行车安全标准，该认证涵盖了电动自行车的电气系统、电池系统、机械结构以及其他相关安全要求，主要关注的是充电器的安全性和可靠性，涉及电气安全、EMC、机械等多个方面的要求。
具体而言，UL2849标准主要解决的产品寿命期间充电过程中的电击危险和潜在的触电危险，要求电动自行车充电器符合安全标准，以确保在使用过程中不会对使用者或设备造成任何伤害或损坏。
ADN2809资料
REV . P rB Sept 2001Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U .S .A .aMulti-Rate to 2.7Gbps Clock and DataFEATURESMeets SONET Requirements for Jitter Transfer / Generation / ToleranceQuantizer Sensitivity: 6 mV typical•Adjustable Slice Level: +/- 100 mV • 1.9GHz minimum BandwidthLoss of Signal Detect Range: 4mV to 17mV Single Reference Clock Frequency for all rates Including 15/14 (7%) Wrapper Rate•Choice of 19.44, 38.88, 77.76 or155.52MHzLVPECL / LVDS / LVCMOS / LVTTL compatible inputs (LVPECL / LVDS only at 155.52 MHz)19.44MHz Crystal Oscillator for Module apps Loss of Lock indicatorLoopback mode for High Speed Test Data Output Squelch & Clock Recovery Functions Single Supply Operation: 3.3 Volts (+10%) Low Power: 780 mW TypicalPatented Clock Recovery Architecture 7 x 7 mm 48 pin LFCSPAPPLICATIONSSONET OC-3/12/48, SDH STM-1/4/16, and all associated FEC rates WDM transpondersSONET/SDH regenerators and test equipmentBackplane applicationsPRODUCT DESCRIPTIONThe ADN2809 provides the receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for -40 to 85C ambient temperature unless otherwisenoted.The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator crystal. Both native rates and 15/14 rate digital ‘wrappers’ rates are supported by the ADN2809, without any change of reference clock required.This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver.The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The ADN2809 is available in a compact 48 pin chip scale package.Functional Block Diagram元器件交易网Note: (1) Recommended for Optimum Sensitivity.Note: (2) Equipment Limitation.ABSOLUTE MAXIMUM RATINGSSupply Voltage.................................................................+8 V Input Voltage (pin x or pin xto Vcc)................................TBD Maximum Junction Temperature..............................165 deg C Storage Temperature Range..............-65 deg C to +150 deg C Lead Temperature (Soldering 10 sec)......................300 deg C ESD Rating (human body model)....................................TBDStress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Figure 1. Output Timing definitionsFigure 2. Signal Level DefinitionFigure 6. Recommended AC Output TerminationFigure 7. ADN2809 S11 vs. FrequencyADN2809THEORY OF OPERATIONThe ADN2809 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops which share a common control voltage.A high speed delay- locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. A separate phase control loop, comprised of the vco, tracks the low frequency components of input jitter. The initial frequency of the vco is set by yet a third loop which compares the vco frequency with the reference frequency and sets the coarse tuning voltage. The jitter tracking phase-locked loop controls the vco by the fine tuning control.The delay- and phase- loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the vco to higher frequency, and also, increases the delay through the phase shifter: these actions both serve to reduce the phase error between the clock and data. The faster clock picks up phase while the delayed data loses phase. Since the loop filter is an integrator, the static phase error will be driven to zero.Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second order phase-locked loop, and this zero is placed in the feedback path and thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Since this circuit has no zero in the closed-loop transfer, jitter peaking is minimized.The delay- and phase- loops together simultaneously provide wide-band jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 8 shows the jitter transfer function , Z(s)/X(s), is a second order low pass providing excellent filtering. Note the jitter transfer has no zero, unlike an ordinary second order phase-locked loop. This means that the main PLL loop has low jitter peaking, see Figure 9. This makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation.The error transfer, e(s)/X(s), has the same high pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wide-band jitter accommodation since the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. See Figure 5 for a table of error transfer bandwidths and jitter transfer bandwidths at the various data rates.The delay- and phase- loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case the vco is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the vco tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation.At medium jitter frequencies, the gain and tuning range of the vco are not large enough to track input jitter. In this case the vco control voltage becomes large and saturates and the vco frequency dwells at one or the other extreme of its tuning range. The size of the vco tuning range, therefore has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve . The phase shifter has a minimum range of 2UI at all data rates. The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region the gain of the integrator determines the jitter accommodation. Since the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 3MHz for all data rates.ADN2809Figure 8. ADN2809 ArchitectureADN2809Figure 9. ADN2809 Jitter Response vs. Conventional PLLADN2809FUNCTIONAL DESCRIPTIONLimiting Amplifier / Bypass & LoopbackThe limiting amplifier has differential inputs (PIN/NIN), which are normally AC coupled to the internal 50 ohm termination (although DC coupling is possible). Input offset is factory trimmed to achieve better than 6mV typical sensitivity with minimal drift. The Quantizer Slicing level can be offset by +/-100mV to mitigate the effect of ASE (amplified spontaneous emission) noise by a differential voltage input of +/-0.8V applied to ‘SLICEP/N’ inputs. If no adjustmentof the slice level is needed, SLICEP/N should be tied to VCC. When the ‘Bypass’ input is driven to a TTL high state, the Quantizer output is connected directly to the buffers driving the Data Out pins, thus bypassing the clock recovery circuit (Figure 10). This feature can help the system to deal with non standard bit rates. The loopback mode can be invoked by driving the‘LOOPEN’ pin to a TTL high state, which facilitates system diagnostic testing. This will connect the Test inputs (TDINP/N) to the clock and data recovery circuit (per Figure 10). The Test inputs can be left floating, when not in use. They accept AC or DC coupled signal levels, or AC coupled LVDS.Loss of Signal (LOS) DetectorThe receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor, as illustrated in figure 4, which assumes that the slice inputs are inactive.If the LOS detector is used the Quantizer Slice Adjust pins must both be tied to VCC, to avoid interaction with the LOS threshold level. Note that it is not expected to use both LOS and Slice Adjust at the same time: systems with optical amplifiers need the slice adjust to evade ASE, but a loss of signal causes the optical amplifier output to be full scale noise, thus the LOS would not detect the failure. In this case the Loss of Lock signal will indicate the failure.Reference ClockThe ADN2809 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88MHz, 77.76MHz atLVTTL/LVCMOS/LVPECL/LVDS levels or 155.52MHz at LVPECL/LVDS levels via the REFCLKN/P inputs, independent of data rate (including gigabit ethernet). The input buffer accepts any differential signal with a peak to peak differential amplitude of greater than 64mV (e.g. LVPECL or LVDS) or a standard single ended low voltage TTL input, providing maximum system flexibility. The appropriate division ratio can be selected using the REFSEL0/1 pins, according to Table 3. Phase noise and duty cycle of the Reference Clock are not critical and 100ppm accuracy is sufficient.A crystal oscillator is also provided, as an alternative to using the REFCLKN/P input. Details of the recommended crystal are given in Table 3.REFSEL must be tied to VCC when the REFCLKN/P inputs are active, or tied to VEE when the oscillator is used. No connection between the XO pin and REFCLK input is necessary (see figure 11). Please note that the crystal should operate in series resonant mode, which renders it insensitive to external parasitics. No trimming capacitors are required.Lock Detector Oper ationThe lock detector monitors the frequency difference between the VCO and the reference clock, and de-asserts the ‘Loss of Lock’ signal when the VCO is within 500ppm of center frequency. This enables the phase loop which then maintains phase lock, unless the frequency error exceeds 0.1%. Should this occur, the ‘Loss of Lock’ signal is re-asserted and control returns to the frequency loop which will re-acquire, and maintain a stable clock signal at the output. The frequency loop requires a single external capacitor between CF1 and CF2. The capacitor specification is given in Table 5.Squelch ModeWhen the ‘Squelch’ input is driven to a TTL high state, both the clock and data outputs are set to the zero state, to suppress downstream processing. If desired, this pin can be directly driven by the LOS (Loss-Of-Signal) or LOL (Loss-Of-Lock) detector outputs. If the Squelch function is not required, the pin should be tied to VEE.ADN2809Figure 11. Reference SourcesFigure 12. Data Input TerminationsNote:The value of Cin required depends on the data rate, # ConsecutiveIdentical Digits (CID) and amount of Patter Dependent Jitter (PDJ) which can be tolerated. e.g. for 1000 CID and <0.01UI pk-pk PDJ, 100nF is needed at OC48 and 1.6uF at OC3.ADN 2809ADN 2809Figure 10. Test Modes(3) No additional external components are requiredADN2809 PIN CONFIGURATIONMechanical Outline Dimensions Dimensions shown in millimeters and (inches).。
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10.7 Gbps Electro-Absorption Modulator Driver Preliminary Technical Data ADN2849Rev.Pr. G August 2004Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESData Rates up to 10.709Gb/sTypical Rise/Fall Time 27psPower Dissipation 900mW (at 2V swing, 1V offset) Programmable Modulation Voltage up to 3V Programmable Bias Offset Voltage up to 2VVoltage-input control for offset, modulationCross Point Adjust Range 30%- 85%Selectable Data RetimingPECL/CML Data & Clock Inputs50Ω on Chip Data & Clock TerminationsModulation Ebnable/Disable|S11|<-10dB , |S22|<-8dB at 10GHzPositive or negative 5.2 or 5.0V single supply operation Available in dice and 4x4mm 24 Lead LFCSP packageAPPLICATIONSSONET OC-192 Optical TransmittersSDH STM-64 Optical Transmitters10Gb Ethernet IEEE802.3XFP/X2/XENPACK/MSA-300 Optical Modules PRODUCT DESCRIPTIONThe ADN2849 is a low power 10.7Gbps driver for electro-absorption modulator (EAM) applications. The modulation voltage is programmable via an external voltage up to a maximum swing of 3V when driving 50Ω. The bias offset voltage and output eye cross point are also programmable. On-chip 50Ω resistor is provided for back termination of the output. The ADN2849 is driven by AC coupled differential CML level data and has selectable data retiming to remove jitter from data input signal. The modulation voltage can be enabled or disabled by driving the MOD_ENB pin with the proper logic levels. It can operate with positive or negative (5.2V or 5.0V) supply voltage.The ADN284949 is available in a compact 4x4mm plastic package or dice format.DATDAMODPFigure 1. Functional Block DiagramADN2849Rev. Pr. G | Page 2 of 17Specifications(Electrical Specifications (VEE=VEE MIN to VEE MAX . All specifications T min to T max , Z L =50Ω unless otherwise noted. Typical values specified at 250C)Table 1.Parameter Min Typ Max Unit ConditionsBias Offset Voltage(MODP)Bias offset voltage -0.25 -2.0 V Note 1 BIAS_SET voltage to bias offset voltage gain 0.9 1.1 V/V T a =250C, VEE=-5.2V Bias offset voltage drift over temperature and VEE -5 5 %Modulation Voltage(MODP)Modulation voltage swing 0.6 3.0 V Note1 MOD_SET voltage to modulation voltage swing gain 1.5 1.9 V/v T a =250C, VEE=-5.2V Modulation voltage drift over temperature and VEE -5 5 % Back termination resistance 40 60 Ω Rise time (20% - 80%) 27 36 ps Fall time (20% - 80%) 27 36 ps Random jitter 0.75 ps RMS Total jitter 10 ps p-p Cross point adjust range 30 85 % Cross point drift over temperature and VEE -5 5 % Minimum output voltage(single ended) VEE+1.7 V Note1 |S 22| -8 dB At 10GHz Modulation enable time 100 ns Modulation disable time 100 nsData Inputs (DATAP, DATAN)Differential Input voltage 600 1600 mV p-p Termination resistance 40 60 Ω Setup time (see figure 2) 25 ps CLK_SELB=’0’ Hold time (see figure 2) 25 ps CLK_SELB=’0’ |S 11| -10 DB At 10GHzClock Inputs (CLKP, CLKN)Differential Input voltage 600 1600 mV p-p Termination resistance 40 60 Ω|S 11| -10 dB At 10GHzCross point adjust (CPAN, CPAP)Input voltage range -0.85 -1.85 V CPAP, CPAN differential voltage 0.6 V p-p Input current 85 115 µALogic Inputs (MOD_ENB, CLK_SELB)V IH VEE+2 V V IL VEE+0.8 V I IL -400 µA V I =VEE+0.4V I IH 20 µAV I =VEE+2.4V 200 µA V I =0V SupplyVEE -4.75 -5.2 -5.5 V IMOD=0 I EE 52 mA V MODP/MODN =0Notes:Minimum supply voltage and minimum output voltage determine maximum output swing and maximum bias offset that can be achieved concurrently. Measured using the characterization circuit shown in figure 3.Preliminary Technical DataPreliminary Technical DataADN2849Rev. Pr. G | Page 3 of 17CLKP/NFigure 2. Setup and hold timeFigure 3. High-speed characterization circuitADN2849Rev. Pr. G | Page 4 of 17ABSOLUTE MAXIMUM RATINGSTable 2.Parameter Min Max Units ConditionsVEE to GND TBD TBD V VBB to GNDTBD TBD V DATAP, DATAN to GND TBD TBD V CLKP, CLKN to GND TBD TBD V CPAP, CPAN to GND TBD TBD V MOD_SET to GND TBD TBD V BIAS_SET to GND TBD TBD V MOD_ENB to GND TBD TBD V CLK_SELB to GNDTBD TBD V Staorage temperature range-60+150CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability PACKAGE THERMAL SPECIFICATIONSTable 3.PARAME TER MIN TYP MAX UNI TS CONDI TIONS/COMMEN TSθJ-TOPTBD TBD TBD 0C/W Thermal resistance from junction to top of package θJ-PADTBD TBD TBD 0C/WThermal resistance from junction to bottom of exposed padORDERING GUIDETable 4. Model Temperature range Package descriptionADN2849ACP -400C to +850C 24 Lead LFCSPADN2849ACP-RL -400C to +850C 24 Lead LFCSPADN2849ACP-RL7 -400C to +850C 24 Lead LFCSPADN2849SURF -400C to +850C Bare dieESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.Preliminary Technical DataPreliminary Technical DataADN2849Rev. Pr. G | Page 5 of 17TYPICAL PERFORMANCE CHARACTERISTICS (T A =250C, VEE=-5.2V)ALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 4. Rise time vs. SwingALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 5. Fall time vs. SwingALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 6. Random jitter vs. SwingALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 7. Total jitter vs. SwingALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 8. Cross point vs. differential voltage at CPAP/CPAN pinsALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 9. Differential S11 vs. frequencyADN2849Rev. Pr. G | Page 6 of 17ALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 10. Single-ended S22 vs. frequencyALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 21. Total supply current vs. Swing with retiming disabledALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 12. Total supply current vs. Swing with retiming enabledALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 13. Electrical eye diagram (2.5V swing, 0.5V offset, PRBS31 at 10.7Gbps)ALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 14. Optical eye diagram using the FLD5F20NP EML (Pav=0dBm, ER=10dB, PRBS31 pattern at 9.95328Gbps, SONETOC192 mask test)Preliminary Technical DataPreliminary Technical DataADN2849Rev. Pr. G | Page 7 of 17PIN CONFIGURATION AND FUNCTION DESCRIPTIONGND DATAP DATAN VBB CLKP CLKNVEEGND MODN_TERM MODP GNDVTERM G N DM O D _S E TM O D _E N BC L K _S E L BV E EC P A NC P A PB I A S _S E T V E EV T E R MG N DG N DFigure 15. Pin configurationNote: There is a n exposed pad on the bottom of the package that must be connected to the most negative supply rail of the ADN2849Table 5. Pin numberMnemonic Description1, 10, 11, 14,17, 20 GND Positive power supply2 DATAP AC coupled CML data, positive differential terminal3 DATAN AC coupled CML data, negative differential terminal4 VBB CML termination resistor5 CLKP AC coupled CML clock, positive differential terminal6 CLKNAC coupled CML clock, negative differential terminal 7 MOD_ENB Modulation enable logic input 8 CLK_SELB Retiming select logic input 9MOD_SET Modulation voltage set input 12, 13, 21 VEENegative power supply15 MODN_TERM Termination resistor for MODN 16 MODP Positive modulation voltage output 18, 19 VTERM Back termination voltage output 22 BIAS_SET Bias offset voltage set input23 CPAP Cross point adjust positive control input 24CPAN Cross point adjust negative control inputExposed PadPadConnect to the most negative supply rail of the ADN2849ADN2849Rev. Pr. G | Page 8 of 17PAD CONFIGURATION AND FUNCTION DESCRIPTION1234456Figure 16. Pad configuration(Die size 2.05×2.05mm, single bond pad size 84×84µm with 76×76µm glass opening, double bond pad size 184×84µmwith 176×76µm)Notes:1. The metallization photograph and the die pad coordinates appear at the end of this document.2.The pads that have the same number must be bonded together.3. The back side of the die must be connected to the most negative supply rail of the ADN2849Table 6. Pad numberMnemonic Description1, 10, 11, 14,17, 20, 25, 26, 27 GND Positive power supply2 DATAP AC coupled CML data, positive differential terminal3 DATAN AC coupled CML data, negative differential terminal4 VBB CML termination resistor5 CLKP AC coupled CML clock, positive differential terminal6 CLKNAC coupled CML clock, negative differential terminal 7 MOD_ENB Modulation enable logic input 8 CLK_SELB Retiming select logic input 9MOD_SET Modulation voltage set input 12, 13, 21 VEENegative power supply15 MODN_TERM Termination resistor for MODN 16 MODP Positive modulation voltage output 18, 19 VTERM Back termination voltage output 22 BIAS_SET Bias offset voltage set input23 CPAP Cross point adjust positive control input 24CPANCross point adjust negative control inputPreliminary Technical DataPreliminary Technical DataADN2849Rev. Pr. G | Page 9 of 17THEORY OF OPERATIONGENERALFigure 17 shows a typical EA modulator characteristic. Vm represents the voltage across the modulator and Pout represents the optical output power. For small voltages across the modulator it is in its high transmission state. As the voltage becomes more negative, the modulator becomes less transparent to the laser light. Fig. 17 also shows a typical drive signal for an EA modulator. It consists of a modulation signalwith a swing Vs, and a bias offset voltage VbPoutFigure 17. Typical transfer function of an EA modulatorAs shown in the functional block diagram (figure 1), the ADN2849 consists of an input stage for data signals, a cross point adjust block and the output stage that generates the bias offset and modulation voltages. The retiming option allows the user to reduce the jitter by applying a reference clock to the clock inputs of the ADN2849. The cross point adjust block pre-distorts the data signal applied to the output stage in order to compensate for the non-linear transfer function of the EA modulator as shown in figure 17. The modulation and the bias offset voltage can be programmed via external DC voltages applied to the ADN2849. These voltages are converted to currents internally and applied to the output stage. The single-ended output stage provides both the bias offset and modulation voltages at the same pin (MODP) without the need of any external components. The ADN2849 can operate with positive or negative (5.0V or 5.2V) supply voltage.INPUT STAGEThe input stage of the ADN2849 gains the data and clock signals applied to the DATAP , DATAN and CLKP , CLKN pins respectively to a level that ensures proper operation of the ADN2849’s output stage. The data and clock inputs are PECL/CML compatible and can accept input signal swings in the range of 600mV to 1600mV peak-to peak differential. The equivalent circuit for the data and clock input pins is shown in figure 18.Figure 18. Equivalent circuit for the data and clock input pinsThe data and clock input pins are internally terminated with a 100Ω differential termination resistor to minimize signal reflections at the input pins that could otherwise lead to degradation in the output eye diagram. The ADN2849 input pins must be AC-coupled with the signal source to eliminate the need of matching between the common mode voltages of the data signal source and the inputs stage of the driver. Also, the common mode terminal of the internal termination resistors (VBB) must be externally decoupled. Figure 19 shows the recommended connection between the data/signal source and the ADN2849 input pins.Figure 19. AC-coupling the data/clock signal source to the ADN2849input pinsADN2849Rev. Pr. G | Page 10 of 17The capacitors used AC-coupling and the decoupling of the VBB pin must have an impedance less than 50Ω over therequired operating frequency range. Generally this is achieved using values from 10nF to 100nF.The retiming feature of the ADN2849 allows the user to remove the data dependent jitter present on the DATAP and DATAN pins by applying the data and clock signals to the ADN2849’s internal latch. The retiming feature can be enabled or disabled depending on the logic level applied to the CLK_SELB pin as described in table 7. Note that any jitter present on the CLKP and CLKN pins is added to the output.Table 7.CLK_SELB logic level Retiming functionHigh Disabled Low EnabledIf the retiming feature is disabled the CLKP and CLKN inputs can be left floating.The CLK_SELB is a 5V TTL and CMOS compatible digital input. Its equivalent circuit is shown in figure 20.Figure 20. Equivalent circuit of the CLK_SELB pinCROSS POINT ADJUSTThe cross point adjust function allows the user to move the eye crossing level in the modulation voltage to compensate for asymmetry in the EA modulator electrical-to- optical transfer function. Figure 21 shows an example on how the cross point adjust can compensate the asymmetry of the EA modulator transfer function. The 50% cross point in the optical eye can be obtained in this case by moving the cross point of the signal applied to the EA modulator away from the 50% point.Figure 21. Cross point adjust compensationThe cross point is controlled by the differential voltage applied to the CPAP and CPAN pins. The equivalent circuit of theCPAP and CPAN pins is shown in figure 22.Figure 22. Equivalent circuit of the CPAP and CPAN pinsPreliminary Technical DataThe single-ended voltage at CPAP and CPAN pins must be within the –0.8V to-1.85V range for proper operation of the cross point adjust block. The cross point will be controlled by the differential voltage obtained from the single-ended voltages applied to CPAP and CPAN pins. A simple implementation of a cross point adjust circuit is shown in figure 23 where a 20K Ω potentiometer generates the required differential voltage within the specified input voltage range.Figure 23. Cross point adjust control circuitAn alternative implementation is to use a voltage DAC and a single-ended to differential conversion amplifier such as the AD138 that will allow digital control of the cross point. When designing the circuitry that will drive the voltages at the CPAP and CPAN pins the user should take in account that each pin is sinking 100µΑ. If the cross point adjust feature is not required both the CPAP and CPAN pins should be connected to GND. This will automatically set the cross point to 50%. Once the cross point adjust has been calibrated under nominal conditions it has very low drift over temperature and supply voltage variations.MODULATION ENABLEThe modulation voltage generated by the ADN2849 can be enabled or disabled under the control of the MOD_ENB pin. When the modulation is disabled, the input data is ignored and the voltage at the output of the ADN2849 will place the EA modulator in a high absorption (low transparency) state. The relationship between the logic state of the MOD_ENB input and the modulation voltage is described in table 8.Table 8.MOD_ENB logic level Modulation voltageLow Enabled High DisabledThe MOD_ENB pin is a 5V TTL and CMOS compatible logic input. Its equivalent circuit of the MOD_ENB pin is shown in figure 24.Figure 24. Equivalent circuit of the MOD_ENB pinOUTPUT STAGEThe output stage of the ADN2849 can provide up to 2V bias offset and up to 3V modulation voltage across a single-ended 50Ω load. Both the bias offset and the modulation voltage are made available at a single pin (MODN) eliminating the need for external bias inductors as shown in figure 25.Figure 25. Output stage of the ADN2849Modulation voltageThe modulation voltage is established by switching the modulation current through the parallel combination of the modulator terminating impedance (50Ω) and the 50Ω back-termination resistor on the ADN2849. The modulation set voltage applied to the MOD_SET pin is converted into current (I MOD) using a voltage-to-current converter which forces a voltage equal to V MOD_SET across an internal fixed resistor. For IMOD range of 24mA to 120mA, the MOD_SET voltage ranges from 340mV to 1.7V . With its maximum modulation current of 120mA, the ADN2849 is capable of generating a 3V modulation voltage across the equivalent load resistance (25Ω). The equivalent circuit of the MOD_SET pin is shown in figure 26.Figure 26. Equivalent circuit of the MOD_SET pinBias offset voltageThe bias offset voltage is set by adjusting the voltage between the BIAS_SET pin and GND. An internal operational amplifier sets the termination voltage for the internal 50Ω output back-termination resistors (VTERM) by gaining up the BI AS_SET voltage by two. This gain of two cancels out the attenuation of the dividing network formed by the 50Ω back- termination resistor from the ADN2849 output and the 50Ω load termination, providing a nominal gain of one from the BIAS_SET input to the bias offset voltage available at the output of the ADN2849 (MODP pin). For proper operation, an external low ESR 100nF decoupling capacitor is required between the VTERM pin and GND to prevent transient disturbances on this node. The equivalent circuits of the B IAS_SET, MODP , MODN_TERM and VTERM pins are shown in figure27.Figure 27. Equivalent circuit of the BIAS_SET, MODP , MODN_TERMand VTERM pinsDuring factory calibration of the optical transmitter, the user adjusts the BI AS_SET and MOD_SET voltages to achieve the desired bias offset and modulation voltages. This adjustment calibrates out BIAS_SET to bias offset voltage and MOD_SET to modulation voltage gain variations in the ADN2849 due to resistor process variations and the offset of the internal amplifiers. The drift in the bias offset and modulation voltages over temperature and supply voltage variations is very low once it has been calibrated under nominal conditions.Headroom calculationsThe ADN2849 is capable of delivering up to 2V bias offset and up to 3V modulation voltage on a 50Ω single-ended load. However, these values for the bias offset and modulation voltages cannot be obtained at the same time due to headroom constraints. The minimum supply voltage and the MODP minimum output voltage specifications determine the maximum modulation and bias offset voltages that can be achieved concurrently. In order to guarantee proper operation of the ADN2849, the bias offset and modulation voltages must satisfy the following condition:min MODP ffset O Bias Modulation V VEE V V −≤+Where,V Modulation = the required modulation voltage V Bias Offset = the required bias offset voltage VEE = the supply voltageV MODPmin = the minimum voltage at the MODP pin (see table 1)POWER DISSIPATIONFor improved heat dissipation the module’s case can be used as heat sink as shown in figure 29. A compact optical module is a complex thermal environment, and calculations of device junction temperature using the package θJ-A (Junction-to-Ambient thermal resistance) do not yield accurate results .The power dissipated by the ADN2849 is a function of the supply voltage and the level of bias offset and modulation voltages required. Figure 28 shows the power dissipation of the ADN2849 vs. modulation voltage for different bias offset voltages. To ensure long-term reliable operation, the junction temperature of the ADN2849 must not exceed 1250C.ALL CAPS (Initial cap)000000000000000000000A L L C A P S (I n i t i a l c a p )000000000000000TBDFigure 28. Power dissipation of the ADN2849 vs. bias offset and modulation voltageP Thermo-coupleFigure 29. Typical optical module structureThe following procedure can be used to estimate the C junction temperature.T TOP = Temperature at top of package in 0C.T PAD = Temperature at package exposed paddle in 0C.T J = IC junction temperature in 0C.P = Power disipation in W.θJ-TOP = Thermal resistance from IC junction to package top.θJ-PAD= Thermal resistance from IC junction to package exposed pad.PTOPFig. 32. Electrical model for thermal calculations T TOP and T PAD can be determined by measuring the temperature at points inside the module, as shown in fig. 30. The thermo-couples should be positioned so as to obtain an accurate measurement of the package top and paddle temperatures. Using this model the junction temperature can be calculated using the formula:TOPJPADJTOPJPADPADJTOPTOPJPADJJTTPT−−−−−−+×+×+××=θθθθθθ)(Where θJ-TOP and θJ-PAD are given in table 3 and P is the power dissipated by the ADN2849 obtained from the graph shown in figure 28.APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITFigure 31 shows the typical application circuit for the ADN2849. Applying DC voltages to the BAS_SET and MOD_SET pins can control the Modulation and bias offset voltages. The data signal source must be connected to the DATAP and DATAN pins using 50Ω impedance transmission lines. If a reference clock signal is available, the retiming option can be enabled using the CLK_SELB input. Note that the connection between the clock signal source andthe CLKP and CLKN pins must be made using 50Ω transmission lines. The cross point can be adjusted using the potentiometer R3. The modulation voltage can be enabled or disabled using the MOD_ENB pin.The ADN2849 can operate with positive or negative (5.0V or 5.2V) supply voltage. Care should be taken to connect the GND pins to the positive rail of the supply voltage while the VEE and the exposed pad to the negative rail of the supply voltage.Figure 31. Typical ADN2849 application circuitPCB LAYOUT GUIDELINESDue to the high frequencies at which the ADN2849 operates, care should be taken when designing the PCB layout in order to obtain optimum performance. It is recommended to use controlled impedance transmission lines for the high-speed signal paths The length of the transmission lines must be kept to a minimum to reduce losses and pattern dependant jitter. All the VEE and GND pins must be connected to solid copper planes using low inductance connections. When the connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. TheVTERM, VBB, MODN_TERM and VEE pins must be locally decoupled with high quality capacitors. I f proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each GND pin. A 20µF tantalum capacitor must be used as general decoupling capacitor for the entire module The exposed pad should be connected to the most negative rail of the supply voltage using filled vias so that solder does not leak through the vias during reflow. Using filled vias under the package greatly enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow.DESIGN EXAMPLEThis section describes a design example that covers the followings:• Headroom calculation for the required bias offset and modulation voltages•Required voltage range at the B IAS_SET and MOD_SET pins to generate the required bias offset and modulation voltagesThis design example assumes a -5.2V supply voltage, 0.5V bias offset voltage and 2V modulation voltage.Headroom calculationsI n order to operate properly, the bias offset and modulation voltages must satisfy the following condition:min MODP ffset O Bias Modulation V VEE V V −≤+Assuming that V MODPmin =1.7V (see table1), the above condition became:V 5.37.12.5V 5.2=−≤BIAS_SET voltage rangeThe voltage range at the BIAS_SET pin to generate 0.5V bias offset voltage at the MODP pin can be calculated using the BIAS_SET voltage to bias offset voltage gain specification from table1 using the formulae:minOFFSETBIAS maxSET _BIAS maxOFFSETBIAS min SET _BIAS K VV K V V ==Where K min and K max are the minimum and maximum values of the BIAS_SET voltage to offset bias voltage gain from table1. Substituting the values the BIAS_SET voltage range is 0.45V to 0.55V .MOD_SET voltage rangeThe voltage range at the MOD_SET pin to generate 2V bias offset voltage at the MODP pin can be calculated using the MOD_SET voltage to bias offset voltage gain specification from table1 using the formulae:minMODULATIONmaxSET _MOD maxMODULATIONmin SET _MOD K VV K V V ==Where K min and K max are the minimum and maximum values of the MOD_SET voltage to offset bias voltage gain from table1. Substituting the values the MOD_SET voltage range is 1.05V to 1.33V .OUTLINE DIMENSIONSPLANESQ COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2Figure 32. 24-Lead Lead Frame Chip Scale Package (LFCSP) 4mm ×4mm Body (CP-24)Dimensions shown in millimetersFigure 33. ADN2849 metallization photographTable 9. Die pad coordinatesPad Number X(µm) Y(µm)1 -920.50 685.002 -920.50 331.553 -920.50 103.054 -920.50 -48.75 4 -920.50 -220.15 5 -920.50 -371.956 -920.50 -525.557 -609.10 -920.508 -457.30 -920.509 -305.50 -920.50 10 -103.70 -920.50 11 324.85 -920.50 12 584.00 -920.50 13 920.50 -688.20 14 920.50 -484.20 15 920.50 -271.10 16 920.50 274.50 17 920.50 490.00 18 920.50 694.00 19 628.00 920.50 19 501.10 920.50 20 349.30 920.50 21 182.40 920.50 22 3.50 920.50 23 -457.30 920.50 24 -609.10 920.50 25 -736.00 920.50 26 -736.00 -920.50 27 738.00 -920.50 Note: The coordinates are measured between the center of the die and the centerof the pad .P R 04323-0-9/04(P r G )。