MEMORY存储芯片MT29F16G08ABACAWP-IT B中文规格书

4.BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
READ Operation Followed by PRECHARGE Operation
The minimum external READ command to PRECHARGE command spacing to the same
bank is equal to AL + t RTP with t RTP being the internal READ command to PRECHARGE
command delay. Note that the minimum ACT to PRE timing, t RAS, must be satisfied as
well. The minimum value for the internal READ command to PRECHARGE command
delay is given by t RTP (MIN) = MAX (4 × n CK, 7.5ns). A new bank ACTIVATE command
may be issued to the same bank if the following two conditions are satisfied simultane-
ously:
•The minimum RAS precharge time (t RP [MIN]) has been satisfied from the clock at
which the precharge begins.
•The minimum RAS cycle time (t RC [MIN]) from the previous bank activation has been
satisfied.
Figure 150: READ to PRECHARGE with 1t CK Preamble
T0
T1T2T3T6Command DQ
CK_t CK_c
DQS_t,
DQS_c T20T21
T14T7T10T11T12T13T19T15T16T17T18Bank Group
Address Address DQ DQS_t,
DQS_c Notes: 1.RL = 11 (CL = 11, AL = 0 ), Preamble = 1t CK, t RTP = 6, t RP = 11.
2.DO n = data-out from column n .
3.DES commands are shown for ease of illustration; other commands may be valid at
these times.
4.The example assumes that t RAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that t RC (MIN) is satisfied at the next ACTIVATE command time (T18).
5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
4Gb: x8, x16 Automotive DDR4 SDRAM READ Operation
Table 112: Single-Ended Output Levels (Continued)
Note: 1.The swing of ±0.15 × V DDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of R ZQ /7 and an effective test load of 50Ω to V TT = V DDQ .
Using the same reference load used for timing measurements, output slew rate for fall-ing and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-ended signals.
Table 113: Single-Ended Output Slew Rate Definition
Figure 229: Single-ended Output Slew Rate Definition
TR se
V OH(AC)V OL(AC)
S i n g l e -E n d e d O u t p u t V o l t a g e (D Q )4Gb: x8, x16 Automotive DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels
Figure 10: 96-Ball FBGA – ×16, "LY"
Ball A1 ID (covered by SR)1.8 CTR
Nonconductive
overmold
Notes: 1.All dimensions are in millimeters.
2.Solder ball material: SAC302 (Pb-free 96.8% Sn, 3% Ag, 0.2% Cu).
3.Reference CSN33 for recommended PCB pad dimension for this package.4Gb: x8, x16 Automotive DDR4 SDRAM Package Dimensions。