FPGA可编程逻辑器件芯片5SGSED6K3F40I4N中文规格书

General Operation
ADSP-BF54x Blackfin Processor Hardware Reference
Network Initialization
Once the network is locked, the Master node typically changes the value of the MSB in the MXVR_CONFIG register. Once the MSB field is changed, the Master will distribute the new synchronous boundary over the network. The update of the RSB value in each of the slave nodes and in the master node is used to indicate that the network lock is stable and the ring is closed. In the slave nodes, the update of the RSB value will cause the SBU interrupt event to be asserted. Note that once the network is in operation, a special procedure must be followed to dynamically change the synchro-nous boundary without disrupting the asynchronous packet channel.The MXVR will automatically determine the node position, node delay, maximum node position, and maximum node delay from the network. Once the lock level of the MXVR is such that these values can be deter-mined, the fields and valid bits in the MXVR_POSITION , MXVR_DELAY , MXVR_MAX_POSITION , and MXVR_MAX_DELAY registers will be updated. In addition, the PRU , DRU , MPRU , and MDRU interrupt events in the
MXVR_INT_STAT_0 register will assert when these values become valid or change.
The MXVR will also automatically receive the Allocation Table distrib-uted by the Master node in the MXVR_ALLOC_x registers. The Master node in the network distributes its Allocation Table once every 1024 frames. Once the distribution of the Allocation Table has completed, the ATU interrupt event will assert. The assertion of the ATU interrupt event only indicates that the Allocation Table distribution is received and does not indicate whether the Allocation Table has changed since the last distribu-tion. In the Master node, the ATU interrupt event also asserts when a
Resource Allocate or Resource De-Allocate control message has caused the Allocation Table to be updated.
For the logical address to be used in the address comparison for received control messages and receive asynchronous packets, the LADDR field should be written and the LVALID bit should be set to 1 in the MXVR_LADDR register. Note that software must determine the uniqueness of the logical address.
General Operation
ADSP-BF54x Blackfin Processor Hardware Reference
the associated Logical Channel and will start writing the data to L1 mem-ory starting at the address specified by MXVR_DMAx_START_ADDR + MXVR_DMAx_COUNT . The DMA channel then finds the transfer count in the received data itself in the position determined by the COUNTPOSx field. Once the DMA channel has written the total number of bytes specified by the transfer count found in the packet, the DONEx status bit is set to 1. The DMA channel then stops and will again start monitoring the incoming data in the Logical Channel looking for the occurrence of the Start Pat-tern. The third packet received is written to the address specified by MXVR_DMAx_START_ADDR and the fourth packet is written to the address specified by MXVR_DMAx_START_ADDR + MXVR_DMAx_COUNT , and so on. The DMA channel continues to operate in this fashion indefinitely until it is manually disabled. See DMA channel 2 in Listing 29-1 on page 29-130 for an example of a DMA channel being programmed for Synchronous Packet-Variable Count Mode.
When the DMA channel is enabled to receive in Synchronous
Packet-Start/Stop Mode, the DMA channel waits until the start of the next frame so that the data is always frame aligned. The DMA channel then monitors incoming data in the Logical Channel looking for the occurrence of the Start Pattern as defined by the STARTPATx field and the FIXEDPMx bit. Once the Start Pattern is found, the DMA channel then starts receiving the data on the physical channels defined in the associated Logical Channel and will start writing data to L1 memory starting at the address specified by MXVR_DMAx_START_ADDR . The DMA channel then monitors incoming data in the Logical Channel looking for the occurrence of the Stop Pattern as defined by the STOPPATx field and the FIXEDPMx bit. Once the DMA channel finds the Stop Pattern, the HDONEx status bit is set to 1. The DMA channel then stops and will again start monitoring the incoming data in the Logical Channel looking for the occurrence of the Start Pattern. Once the Start Pattern is found, the DMA channel then starts receiving the data on the physical channels defined in the associated Logical Channel and will start writing the data to L1 memory starting at the address specified by MXVR_DMAx_START_ADDR + MXVR_DMAx_COUNT . The DMA channel then monitors incoming data in the Logical Channel。