IRF5810TRPBF;中文规格书,Datasheet资料

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IRFTS9342TRPBF;中文规格书,Datasheet资料

IRFTS9342PbFHEXFET ® Power MOSFETNotes through are on page 2Applicationsl Battery operated DC motor inverter MOSFET lSystem/Load SwitchFeatures and Benefitsresults in ⇒PD - 96411AIRFTS9342PbFNotes:Repetitive rating; pulse width limited by max. junction temperature. Pulse width ≤ 400μs; duty cycle ≤ 2%.When mounted on 1 inch square copper board.Static @ T = 25°C (unless otherwise specified)IRFTS9342PbFFig 4. Normalized On-Resistance vs. TemperatureFig 2. Typical Output CharacteristicsFig 1. Typical Output CharacteristicsFig 6. Typical Gate Charge vs.Gate-to-Source VoltageFig 5. Typical Capacitance vs.Drain-to-Source Voltage T J , Junction Temperature (°C)R D S (o n ) , D r a i n -t o -S o u r c e O n R e s i s t a n c e 110100-V DS , Drain-to-Source Voltage (V)10100100010000C , C a p a c i t a n c e (p F )0246810121416Q G Total Gate Charge (nC)0.02.04.06.08.010.012.014.0-V G S , G a t e -t o -S o u r c e V o l t a g e (V )DS -V DS , Drain-to-Source Voltage (V)0.1110100-I D , D r a i n -t o -S o u r c e C u r r e n t (A )IRFTS9342PbFFig 11. Maximum Effective Transient Thermal Impedance, Junction-to-CaseFig 8. Maximum Safe Operating AreaFig 9. Maximum Drain Current vs.Case TemperatureFig 7. Typical Source-Drain Diode Forward VoltageFig 10. Threshold Voltage vs. Temperature255075100125150T A , Ambient Temperature (°C)0123456-I D , D r a i n C u r r e n t (A)0.010.1110100V DS , Drain-to-Source Voltage (V)0.010.11101001000I D , D r a i n -t o -S o u r c e C u r r e n t (A)0.1110100-I S D , R e v e r s e D r a i n C u r r e n t (A )T J , Temperature ( °C )-V G S (t h ), G a t e t h r e s h o l d V o l t a g e (V )IRFTS9342PbFFig 12. On-Resistance vs. Gate VoltageFig 14. Maximum Avalanche Energy vs. Drain Current Fig 15. Typical Power vs. Time* Reverse Polarity of D.U.T for P-Channel* V GS = 5V for Logic Level Devices®2468101214161820-V GS, Gate -to -Source Voltage (V)255075100125150Starting T J , Junction Temperature (°C)020406080100120E A S , S i n g l e P u l s e A v a l a n c h e E n e r g y (m J )Time (sec)P o w e r (W )IRFTS9342PbFFig 17a. Gate Charge Test CircuitFig 17b. Gate Charge WaveformFig 18b. Unclamped Inductive WaveformsFig 18a. Unclamped Inductive Test CircuitFig 19b. Switching Time WaveformsFig 19a. Switching Time Test CircuitIdQgs1Qgs2Qgd QgodrV DDR DV DDI ASV DSV GSt t t tNote: For the most current drawing please refer to IR website at: /package/WW = (27-52) IF PRECEDED BY A LETTERYEA R Y Z52W WORK WEEK 26ZF = IRF5801(a s show n here) indica tes Lead-F ree.Note: A line above the w ork w eek G = IRF5803D = IRF5851E = IRF5852I = IRF 5805C = IRF5850N = IRF 5802K = IRF5810J = IRF5806H = IRF 5804S = Not a pplicable R = IRFTS 9342TRPBF T = IRLT S2242TRPBFIRFTS9342PbFTSOP-6 Tape and Reel Information† Qualification standards can be found at International Rectifier’s web site /product-info/reliability†† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: /whoto-call/salesrep/†††Applicable version of JEDEC standard at the time of product release.IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact information . 02/2012Data and specifications subject to change without notice.8mmFEED DIRECTION4mmNOTES :1. OUTLINE CONFORMS TO EIA-481 & EIA-541.9.90 ( .390 )8.40 ( .331 )178.00( 7.008 ) MAX.NOTES:1. CONTROLLING DIMENSION : MILLIMETER.2. OUTLINE CONFORMS TO EIA-481 & EIA-541.Qualification information †分销商库存信息: IRIRFTS9342TRPBF。

IRFR220NTRPBF中文资料

Units
mJ A mJ
Thermal Resistance
Parameter
RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
RDS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
TJ = 25 ° C
10
3.0 2.5
TJ = 175 ° C
2.0 1.5
1
1.0
0.5 0.0 -60 -40 -20
0.1 4.0
Notes through are on page 10

1
11/29/00
元器件交易网
IRFR/U220N
Static @ TJ = 25°C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units Conditions 200 ––– ––– V VGS = 0V, I D = 250µA ––– 0.23 ––– V/°C Reference to 25°C, ID = 1mA ––– ––– 600 mΩ VGS = 10V, I D = 2.9A 2.0 ––– 4.0 V VDS = VGS , ID = 250µA ––– ––– 25 VDS = 200V, VGS = 0V µA ––– ––– 250 VDS = 160V, VGS = 0V, T J = 150°C ––– ––– 100 VGS = 20V nA ––– ––– -100 VGS = -20V

AON5820;中文规格书,Datasheet资料

Crss
Reverse Transfer Capacitance
Rg
Gate resistance
VGS=0V, VDS=10V, f=1MHz VGS=0V, VDS=0V, f=1MHz
1000 1255 1510 pF
150 220 290 pF
100 168 235 pF
2.5
KΩ
SWITCHING PARAMETERS
Qrr
Body Diode Reverse Recovery Charge IF=10A, dI/dt=500A/µs
12
15
18
nC
A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's specific board design.
VDS=VGS, ID=250µA
0.3 0.65 1.0
V
ID(ON)
On state drain current
VGS=4.5V, VDS=5V
85
A
VGS=4.5V, ID=10A
5.5 7.4 9.5 mΩ
TJ=125°C 8

5810R使用手册

离心机 5804/5804 R/5810/5810 R使用手册图1 ：5804 / 5810 （非冷冻离心机）显示界面和控制面板图2：5804 R/ 5810 R （冷冻离心机)显示界面和控制面板目录1.简介1.1.包装1.2.开箱1.3.仪器安装2.安全警告与应用限制3.操作3.1.控制键3.2.装载/装卸转子3.3.转子盖F-45—30—113.4.装上转子3.5.屏幕上显示预设时间/转速的常规离心3.6.持续运行3.7.瞬时离心3.8运行中时间变更3.9冷冻(仅对5804R/5810R）3.10预设半径3.11软启动/软停止离心3.12定速记时功能3.13预调程序3.14编辑状态3.15写保护3.16设定定值显示3.17自动转子识别3.18显示已运行时间3.19开关报警信号3.20退出服务程序3.21通过系列界面控制（可选）3.22断电情况下打开机器3.23断流器开关/保险4.保养与清洗4.1.主机4.2.转子4.3.气密型转子4.4.转子消毒4.5.玻璃破损4.6.冷冻离心机5.问题及解决方法6.技术参数1.简介5804/5810 是不带冷冻功能的台式离心机，5804R/5810R是带冷冻功能的台式离心机。

5804/5804R最大样品容量400ml，5810/5810R最大样品容量1600ml。

所有离心机适于医药以及科学研究等领域的实验室科学研究。

在离心机上和此操作手册里多处见到此标记。

注此标记的文字说明包含了安全注意。

第一次使用离心机前仔细阅读安全警告.在第一次启动5804/5810和5804R/5810R时，请仔细阅读使用手册。

1.1.运输包装1 带冷却风扇的5804/5810R离心机或者是冷冻型5804R/5810R（不包括转子）1 主电源线(欧式插座）1 使用手册1 转子起子1。

2 开箱从包装箱取离心机时，首先将仪器整个包装搬至承重桌面最近的位置，尔后需要两个人分别从仪器左右两侧底部接近橡皮脚附近的位置着手,将仪器放置水平桌面。

IRF8721TRPBF;IRF8721PBF;中文规格书,Datasheet资料

107/30/07IRF8721PbFHEXFET ®Power MOSFETBenefitsl Very Low Gate Charge l Low R DS(on) at 4.5V V GS l Low Gate Impedancel Fully Characterized Avalanche Voltage and Currentl 20V V GS Max. Gate Rating l Lead-Free Applicationsl Control MOSFET of Sync-BuckConverters used for Notebook Processor Powerl Control MOSFET for Isolated DC-DC Converters in Networking Systems SO-8PD - 97119DescriptionThe IRF8721PbF incorporates the latest HEXFET Power MOSFET Silicon Technology into the industry standard SO-8 package The IRF8721PbF has been optimized for parameters that are critical in synchronous buck operation including Rds(on) and gate charge to reduce both conduc-tion and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors for Notebook and Netcom applications.IRF8721PbFStatic @ T = 25°C (unless otherwise specified)IRF8721PbF 3Fig 4. Normalized On-ResistanceVs. TemperatureFig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics Fig 3. Typical Transfer CharacteristicsV DS , Drain-to-Source Voltage (V)T J , Junction Temperature (°C)R D S (o n ) , D r a i n -t o -S o u r c e O n R e s i s t a n c e(N o r m a l i z e d )V GS , Gate-to-Source Voltage (V)V DS , Drain-to-Source Voltage (V)IRF8721PbFFig 8. Maximum Safe Operating AreaFig 6. Typical Gate Charge Vs.Gate-to-Source VoltageFig 5. Typical Capacitance Vs.Drain-to-Source VoltageFig 7. Typical Source-Drain DiodeForward Voltage110100V DS , Drain-to-Source Voltage (V)100100010000C , C a p a c i t a n c e (p F )0.11101001000I S D , R e v e r s e D r a i n C u r r e n t (A )0.1110100V DS , Drain-to-Source Voltage (V)0.11101001000I D , D r a i n -t o -S o u r c e C u r r e n t (A)510152025Q g , Total Gate Charge (nC)0481216V G S , G a t e -t o -S o u r c e V o l t a g e (V )IRF8721PbF 5Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-AmbientFig 9. Maximum Drain Current Vs.Case TemperatureFig 10. Threshold Voltage Vs. Temperature255075100125150T A , Ambient Temperature (°C)0481216I D , D r a i n C u r r e n t (A)T J , Temperature ( °C )V G S (t h ) G a t e t h r e s h o l d V o l t a g e (V )t 1, Rectangular Pulse Duration (sec)T h e r m a l R e s p o n s e ( Z t h J A )Fig 13. Maximum Avalanche Energyvs. Drain CurrentFig 12. On-Resistance vs. Gate VoltageFig 15b. Switching Time WaveformsFig 14b. Unclamped Inductive WaveformsFig 14a. Unclamped Inductive Test CircuitI ASFig 15a. Switching Time Test Circuit6810121416R D S (o n ), D r a i n -t o-S o u r c e O n R e s i s t a n c e (m Ω)V DDStarting T J , Junction Temperature (°C)V V d(on)rd(off)fV DDIRF8721PbF7DSCurrent Sampling ResistorsFig 16a. Gate Charge Test CircuitFig 16b. Gate Charge WaveformFig 17. Peak Diode Recovery dv/dt Test Circuit for N-ChannelHEXFET ® Power MOSFETs* V GS = 5V for Logic Level DevicesIdQgs1Qgs2Qgd QgodrIRF8721PbFSO-8 Package OutlineDimensions are shown in milimeters (inches)IRF8721PbF 9Notes:Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25°C, L = 1.09mH, R G = 25Ω, I AS = 11A. Pulse width ≤ 400μs; duty cycle ≤ 2%.When mounted on 1 inch square copper board. R θ is measured at T J of approximately 90°C.Data and specifications subject to change without notice.This product has been designed and qualified for the Consumer market.Qualification Standards can be found on IR’s Web site.IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact information .07/2007Note: For the most current drawing please refer to IR website at /package/330.00(12.992) MAX.14.40 ( .566 )12.40 ( .488 )NOTES :1. CONTROLLING DIMENSION : MILLIMETER.2. OUTLINE CONFORMS TO EIA-481 & EIA-541.FEED DIRECTIONTERMINAL NUMBER 112.3 ( .484 )11.7 ( .461 )8.1 ( .318 )7.9 ( .312 )NOTES:1. CONTROLLING DIMENSION : MILLIMETER.2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).3. OUTLINE CONFORMS TO EIA-481 & EIA-541.SO-8 Tape and ReelDimensions are shown in milimeters (inches)分销商库存信息:IRIRF8721TRPBF IRF8721PBF。

IRF5851TRPBF中文资料

IRF5851TRPBF中文资料Max.N-ChannelP-Channel V DSDrain-to-Source Voltage20-20I D @ T A = 25°CContinuousDrainCurrent,************.2ID@TA= 70°C Continuous Drain Current, V***********.7IDM Pulsed Drain Current 11-9.0P D @T A = 25°C Power Dissipation 0.96W P D @T A = 70°C Power Dissipation 0.62Linear Derating Factor 7.7mW/°C V GS Gate-to-Source Voltage± 12V T J, T STGJunction and Storage Temperature Range°C09/02/02IRF5851DescriptionParameterTyp.Max.UnitsR θJAMaximum Junction-to-Ambient–––130°C/WThermal Resistance 1These N and P channel MOSF ETs from International Rectifier utilize advanced processing techniques to achieve the extremely low on-resistance per silicon area. This benefit provides the designer with an extremely efficient device for use in battery and load management applications.This Dual TSOP-6 package is ideal for applications where printed circuit board space is at a premium and where maximum functionality is required.With two die per package, the IRF5851can provide the functionality of two SOT-23 packages in a smaller footprint. Its unique thermal design and R DS(on) reduction enables an increase in current-handling capability.ParameterUnitsAAbsolute Maximum Ratings-55 to + 150l Ultra Low On-Resistancel l Surface Mountl Available in Tape & Reel lLow Gate ChargePD-93998BIRF5851ParameterMin.Typ.Max. Units ConditionsN-Ch 20——V GS = 0V, I D = 250μA P-Ch -20——V GS = 0V, I D = -250μA N-Ch —0.016—Reference to 25°C, I D = 1mA P-Ch —-0.011—Reference to 25°C, I D = -1mA ——0.090V GS = 4.5V, I D = 2.7A ——0.120 V GS = 2.5V, I D = 2.2A ——0.135V GS = -4.5V, I D = -2.2A ——0.220V GS = -2.5V, I D = -1.7A N-Ch 0.60— 1.25V DS = V GS , I D = 250μA P-Ch -0.45—-1.2V DS = V GS , I D = -250μA N-Ch 5.2——V DS = 10V, I D = 2.7A P-Ch 3.5——V DS = -10V, I D = -2.2A N-Ch —— 1.0V DS = 16V, V GS = 0V P-Ch ——-1.0V DS = -16V, V GS = 0VN-Ch ——25V DS = 16V, V GS = 0V, T J = 70°C P-Ch ——-25V DS = -16V, V GS = 0V, T J = 70°C I GSS Gate-to-Source Forward Leakage N-P ––—±100V GS = ± 12VN-Ch — 4.0 6.0P-Ch — 3.6 5.4N-Ch —0.95—P-Ch —0.66—N-Ch —0.83—P-Ch — 5.7—N-Ch — 6.6—P-Ch —8.3—N-Ch — 1.2—P-Ch —14—N-Ch —15—P-Ch —31—N-Ch — 2.4—P-Ch —28—N-Ch —400—P-Ch —320—N-Ch —48—P-Ch —56—N-Ch —32—P-Ch—40—V (BR)DSSDrain-to-Source Breakdown VoltageV (BR)DSS /?T J Breakdown Voltage Temp. CoefficientR DS(ON)Static Drain-to-Source On-ResistanceV GS(th)Gate Threshold Voltage g fs F orward TransconductanceI DSS Drain-to-Source Leakage Current Q g T otal Gate Charge Q gs Gate-to-Source Charge Q gd Gate-to-Drain ("Miller") Charge t d(on)Turn-On Delay Time t r Rise Timet d(off)Turn-Off Delay Time t f Fall Time C iss Input Capacitance C oss Output CapacitanceC rssReverse Transfer CapacitanceElectrical Characteristics @ T J = 25°C (unless otherwise specified)VV/°CVSμAnCnspFN-ChannelI D = 2.7A, V DS = 10V, V GS = 4.5VP-ChannelI D = -2.2A, V DS = -10V, V GS = -4.5V N-ChannelV DD = 10V, I D = 1.0A, R G = 6.2?, V GS = 4.5VP-ChannelV DD = -10V, I D = -1.0A, R G = 6.0?, V GS = -4.5VN-ChannelV GS = 0V, V DS = 15V, ? = 1.0MHz P-ChannelV GS = 0V, V DS = -15V, ? = 1.0MHzN-ChP-ChRepetitive rating; pulse width limited bymax. junction temperature. ( See fig. 10 & 26 ) Surface mounted on FR-4 board, t ≤ 10sec.Pulse width ≤ 400μs; duty cycle ≤ 2%.Notes:ParameterMin.Typ.Max. Units Conditions N-Ch ——0.96P-Ch ——-0.96N-Ch ——11P-Ch ——-9.0N-Ch ——1.2T J = 25°C, I S = 0.96A, V GS = 0V P-Ch ——-1.2T J = 25°C, I S = -0.96A, V GS = 0V N-Ch —2538P-Ch —2335N-Ch — 6.59.8P-Ch—7.712Source-Drain Ratings and CharacteristicsI S Continuous Source Current (Body Diode)I SM Pulsed Source Current (Body Diode) V SD Diode Forward Voltage t rr Reverse Recovery Time Q rrReverse Recovery ChargeA V ns nC N-Channel T J = 25°C, I F = 0.96A, di/dt = 100A/μs P-ChannelT J = 25°C, I F = -0.96A, di/dt = -100A/μsIRF5851 3 N-Channel Vs. Temperature IRF5851Gate-to-Source Voltage Drain-to-Source Voltage Forward VoltageN-ChannelIRF5851 5N-ChannelCase TemperatureFig 10a. Switching Time Test Circuit V DSV d(on)rd(off)fFig 10b. Switching Time Waveforms V DDIRF5851N-ChannelFig 12. Typical On-Resistance Vs. Drain CurrentFig 11. Typical On-Resistance Vs. GateVoltageV GS, Gate -to -Source Voltage (V)R DS (o n ), D r a i n -t o -S o u r c e O n R e s i s t a n c e (?) Fig 13b. Gate Charge Test CircuitFig 13a.Basic Gate Charge Waveform V 4.5 VDSCurrent SamplingResistors24681012I D , Drain Current (A)0.000.100.200.30R D S (o n ) , D r a i n -t o -S o r c e O n R e s i s t a n c e (?) IRF5851 7Fig 14. Threshold Voltage Vs. Tempera-ture Fig 15. Typical Power Vs. TimeN-ChannelT J , Temperature ( °C )V G S (t h ) , V a r ia c e ( V )Time (sec)P o w e r (W )IRF5851 P-Channel Vs. Temperature IRF5851 9Gate-to-Source Voltage Drain-to-Source Voltage Forward VoltageP-ChannelIRF5851Junction TemperatureV DDV V t t t t Fig 25a. Switching Time Test Circuit Fig 25b. Switching Time WaveformsP-Channel11Fig 28. Typical On-Resistance Vs. DrainCurrentFig 27. Typical On-Resistance Vs. GateVoltageFig 29b. Gate Charge Test Circuit Fig 29a. Basic Gate Charge WaveformVDSCurrent Sampling ResistorsP-Channel-V GS, Gate -to -Source Voltage (V) RDS(on),Drain-to-SourceOnResitance()0246810-I D , Drain Current (A) 0.100.200.300.40RDS(on),Drain-t-SourceOnResistance()IRF5851P-ChannelT J , Temperature ( °C )-V G S (t h ) , V a r i a c e ( V ) Time (sec)P o w e r (W )IRF5851233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact information. 09/02 。

IRS2101STRPBF中文资料

2
元器件交易网
IRS2101(S)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 °C unless otherwise specified.
50 1.0 0.625 125 200 150 150 300
Units
V
V/ns W
°C/W °C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
Package power dissipation @ TA ≤ +25 °C
Thermal resistance, junction to ambient
Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
V
— 0.05 0.2
IO = 2 mA
— 0.02 0.1
—
—
50
VB = VS = 600 V
—
30 55
— 150 270 µA
VIN = 0 V or 5 V

ir2117strpbf规格书

ir2117strpbf规格书【实用版】目录1.产品概述2.主要特性3.规格参数4.应用领域5.环境要求6.安全信息7.结构说明8.工作原理9.测试方法10.维护与保养正文1.产品概述ir2117strpbf 是一种高性能、低成本的电子元器件，具有出色的稳定性和可靠性。

它广泛应用于各种电子设备和系统中，为设备提供稳定的电源和信号传输功能。

2.主要特性ir2117strpbf 具有以下主要特性：- 高稳定性：在恶劣的工作环境下，仍能保持稳定的工作性能。

- 低失真：信号传输过程中失真度低，保证了信号的完整性和准确性。

- 宽工作温度范围：能在 -40℃至 +125℃的温度范围内正常工作。

- 抗干扰能力强：能有效抵抗各种电磁干扰，保证设备的正常运行。

3.规格参数ir2117strpbf 的规格参数如下：- 电压范围：3.3V-5V- 电流范围：50mA-100mA- 工作温度范围：-40℃至 +125℃- 存储温度范围：-40℃至 +125℃- 抗静电能力：±15KV- 封装形式：SOP-84.应用领域ir2117strpbf 广泛应用于以下领域：- 电子消费品：如电视机、收音机、音响设备等。

- 通讯设备：如手机、电话机、传真机等。

- 计算机及周边设备：如电脑、路由器、打印机等。

- 工业控制设备：如工控机、可编程控制器等。

5.环境要求为了保证 ir2117strpbf 的正常工作和延长使用寿命，应满足以下环境要求：- 避免阳光直射和潮湿环境。

- 避免暴露在高温、低温、高湿度的环境中。

- 避免与腐蚀性物质接触。

- 避免强烈的机械振动和冲击。

6.安全信息在操作和使用 ir2117strpbf 时，请注意以下安全信息：- 请勿用湿手触摸或操作设备。

- 请勿在未断电的情况下拆卸设备。

- 请确保设备接地良好，以防止静电损伤。

- 如有异常现象，请立即停止使用并联系专业人员处理。

7.结构说明ir2117strpbf 的结构说明如下：- 引脚 1：电源正极（VCC）- 引脚 2：电源负极（GND）- 引脚 3：输出信号（OUT）- 引脚 4：控制信号（CTRL）- 引脚 5：公共地（GND）- 引脚 6：公共地（GND）- 引脚 7：公共地（GND）- 引脚 8：输出信号（OUT）8.工作原理ir2117strpbf 的工作原理如下：当控制信号（CTRL）为高电平时，输出信号（OUT）跟随输入信号；当控制信号为低电平时，输出信号呈高阻态。

5815中文资料

Designed primarily for use with high-voltage vacuum-fluorescent displays, the UCN5815A and UCN5815EP BiMOS II integratedcircuits consist of eight npn Darlington source drivers with output pull-down resistors, a CMOS latch for each driver, and common STROBE,BLANKING, and ENABLE functions.BiMOS II devices have considerably better data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will operate to at least 4.4 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs cause minimum loading and arecompatible with standard CMOS and NMOS logic commonly found in microprocessor designs. TTL circuits may require the use of appropri-ate pull-up resistors.The bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. All eight outputs can be activated simultaneously at ambient temperatures in excess of 75°C.To simplify printed wiring board layout, output connections are opposite the inputs. A minimum component display subsystem,requiring few or no discrete components, can be assembled using the UCN5815A/EP with the UCN5810AF/EPF/LWF, UCN5812AF/EPF,or UCN5818AF/EPF serial-to-parallel latched drivers.Suffix ‘A’ devices are furnished in a standard 22-pin plastic DIP;suffix ‘EP’ indicates a 28-lead PLCC.BiMOS II 8-BITLATCHED SOURCE DRIVERSFEATURESI To 4.4 MHz Date-lnput Rate I High-Voltage Source OutputsI CMOS, NMOS, TTL Compatible Inputs I Low-Power CMOS Latches I Internal Pull-Down Resistors IWide Supply-Voltage RangeAlways order by complete part number:Part Number Package UCN5815A 22-Pin DIP UCN5815EP28-Lead PLCCData Sheet 26183.10A*58155815BiMOS II8-BIT LATCHEDSOURCE DRIVERS115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000ELECTRICAL CHARACTERISTICS at T A = +25°C, V BB = 60 V, V DD = 5 V and 12 V (unless otherwise noted).Limits Characteristic Symbol Test ConditionsMin.Max.Units Output Off Voltage V OUT — 1.0V Output On Voltage V OUT I OUT = -25 mA, V BB = 60 V 57.5—V Output Pull-Down Current I OUT V OUT = V BB 400850µA Output Leakage Current I OUT T A = 70°C —-15µA Input VoltageV IN(1)V DD = 5.0 V 3.5 5.3V V DD = 12 V10.512.3V V IN(0)-0.3+0.8V Input CurrentI IN(1)V DD = V IN = 5.0 V —100µA V DD = V IN = 12 V—240µA Input lmpedance Z IN V DD = 5.0 V50—k ΩSupply Currentl BBAll outputs on, All outputs open —10.5mA All outputs off, All outputs open—100µA l DDV DD = 5.0 V, All outputs off, All inputs = 0 V —100µA V DD = 12 V, All outputs off, All inputs = 0 V —200µA V DD = 5.0 V, One output on, All inputs = 0 V — 1.0mA V DD = 12 V, One output on, All inputs = 0 V—3.0mANOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.TYPICAL INPUTCIRCUITTYPICAL OUTPUTDRIVERINDwg. No. EP-010-4A Dwg. No. EP-021-3Copyright © 1984, 2000 Allegro MicroSystems, Inc.5815BiMOS II 8-BIT LATCHEDSOURCE DRIVERSUCN5815EPX = irrelevantT-1 = previous output stateT = present output stateTRUTH TABLETiming is representative of a 4.4 MHz data input rate. Higher speeds may beattainable with increased supply voltage; operation at high temperatures willreduce the specified maximum clock frequency.5815BiMOS II8-BIT LATCHEDSOURCE DRIVERS115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000UCN5815ADimensions in Inches (cvontrolling dimensions)Dimensions in Millimeters (for reference only)NOTES:1.Exact body and lead configuration at vendor ’s option within limits shown.2.Lead spacing tolerance is non-cumulative.3.Lead thickness is measured at seating plane or below.4.Supplied in standard sticks/tubes of 17 devices.12311Dwg. MA-002-22 in12311Dwg. MA-002-22 mm5815BiMOS II8-BIT LATCHED SOURCE DRIVERSUCN5815EPDimensions in Inches (controlling dimensionsNOTES:1.Exact body and lead configuration at vendor ’s option within limits shown.2.Lead spacing tolerance is non-cumulative.3.Supplied in standard sticks/tubes of 38 devices or add “TR ” to part number for tape and reel.Dimensions in Millimeters (for reference only)Dwg. MA-005-28A inDwg. MA-005-28A mm5815BiMOS II8-BIT LATCHEDSOURCE DRIVERS115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000POWERINTERFACE DRIVERSFunctionOutput Ratings*Part Number †SERIAL-INPUT LATCHED DRIVERS8-Bit (saturated drivers)-120 mA 50 V‡58958-Bit 350 mA 50 V 58218-Bit 350 mA 80 V 58228-Bit 350 mA 50 V‡58418-Bit350 mA 80 V‡58428-Bit (constant-current LED driver)75 mA 17 V 62758-Bit (DMOS drivers)250 mA 50 V 65958-Bit (DMOS drivers)350 mA 50 V‡6A5958-Bit (DMOS drivers)100 mA 50 V 6B59510-Bit (active pull-downs)-25 mA 60 V 5810-F and 6809/1012-Bit (active pull-downs)-25 mA 60 V 5811 and 681116-Bit (constant-current LED driver)75 mA 17 V 627620-Bit (active pull-downs)-25 mA 60 V 5812-F and 681232-Bit (active pull-downs)-25 mA 60 V 5818-F and 681832-Bit100 mA 30 V 583332-Bit (saturated drivers)100 mA 40 V 5832PARALLEL-INPUT LATCHED DRIVERS4-Bit350 mA 50 V‡58008-Bit -25 mA 60 V 58158-Bit350 mA 50 V‡58018-Bit (DMOS drivers)100 mA 50 V 6B2738-Bit (DMOS drivers)250 mA 50 V 6273SPECIAL-PURPOSE DEVICESUnipolar Stepper Motor Translator/Driver 1.25 A 50 V‡5804Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡6A259Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259Addressable 28-Line Decoder/Driver 450 mA30 V6817*Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.Negative current is defined as coming out of (sourcing) the output.†Complete part number includes additional characters to indicate operating temperature range and package style.‡Internal transient-suppression diodes included for inductive-load protection.。

NCP5810MUTXG;中文规格书,Datasheet资料

NCP5810Dual 1 W Output AMOLED Driver SupplyThe NCP5810 is a dual-output DC/DC converter which can generate both a positive and a negative voltage. Both PWM converters achieve high efficiency for portable application. Thanks to the high output voltage accuracy and signal integrity the NCP5810 is particularly suitable for powering applications such as AMOLED display drivers. The output voltage of the inverter is fully configurable using external feedback resistors, where the output voltage of the boost is internally fixed. The switching regulator operates at 1.75ĂMHz which allows the use of small inductors and ceramic capacitors. In addition both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle-by-cycle peak current limit and thermal shut down provide value added features to protect the device. The NCP5810 is housed in low profile space-efficient 3x3 mm LLGA packages.Features•ăHigh Overall Efficiency: 83% (Refer to Figure 4)•ăLow Noise 1.75 MHz PWM DC/DC Converter•ăPositive Output Fixed + 4.6 V•ăNegative Output from - 2.0 to - 15.0 V•ăHigh Output V oltage Accuracy•ăExcellent Line Transient Rejection•ăSoft Start to Limit Inrush Current•ăEnable Control Facility with True-Cutoff•ăSmall LLGA 3x3 mm Packages•ăThese are Pb-Free DevicesTypical Applications•ăAMOLED Driver Supply♦ăCellular Phones♦ăMP3 Player♦ăDigital Cameras♦ăPersonal Digital Assistant and Portable Media Player♦ăGPS12 PIN LLGAMU SUFFIXCASE 513ADMARKING DIAGRAM5810= Device CodeA= Assembly LocationY= YearW= Work WeekG= Pb-Free Package(Note: Microdot may be in either location)5810AYW GGLXPPVINSWNENAVINFBN VOUTPSWPPGNDAGNDVREFVS(T op View)12-pin 3 x 3 x 0.55 mm LLGAExposed pad must be soldered to PCB Ground planeSee detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.ORDERING INFORMATIONC1: 4.7 m C1,C3,C4: 4.7 m Figure 1. Typical Application CircuitL1 4.7 m HC2: 1 mFigure 2. Simplified Block DiagramPIN FUNCTION DESCRIPTIONPin Pin Name Type Description1VOUTP OUTPUT Positive Power Output: A filter capacitor is necessary on this pin for the stability of the loop, tosmooth the current flowing into the load, and limit the noise created by the fast transients present inthis circuitry. A 4.7 m F ceramic bypass capacitor to GND is recommended. Care must be observed toavoid EMI through the PCB copper tracks connected to this pin.2SWP POWER Switch LXP: Positive power switch pin where one end of the L1 inductor is connected. Typical ap‐plication uses a 4.7 m H inductor.3PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high qualityground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed toavoid high-density current flow in a limited PCB copper track.4AGND POWER Analog Ground: This pin is the analog ground of the device notably used by VREF.5VREF OUTPUT Voltage Reference: This output provides a 1.265 V voltage reference used notably for the negativefeedback resistive network.6VS INPUT Positive Output Voltage Sense: This pin is the output voltage sense input for the positive boostconverter and must be connected to COUTP bypass capacitor.7FBN INPUT Feedback Negative: This pin is the feedback voltage input for the negative Buck-Boost inverter. Themiddle point of a resistive bridge divider must be connected here. The resistive network must be con‐nected between VREF and the anode of external Schottky.8AVIN POWER Analog Power Supply: The external voltage supply is connected to this pin. A 4.7 m F ceramic ca‐pacitor must be connected across this pin and the power ground to achieve the specified output pow‐er parameters.9EN INPUT Enable: An active high logic level on this pin enables the circuit. A built-in pull-down resistor disablesthe device if the pin is left open. Also in disable condition the device provides a true cut-off from PVINto VOUTP and SWN.10SWN INPUT Switch Negative: Negative power switch pin where one end of the L2 inductor is connected. Typicalapplication uses a 4.7 m H inductor.11PVIN POWER Power Supply: This pin is the power supply of the device. A 4.7 m F ceramic capacitor or larger mustbypass this input to the ground. This capacitor should be placed as close as possible to this input.12LXP POWER Switch LXP: The inductor should be connected between this node and SWP. This output suppliespower from PVIN and gives a true-cut off function in disable condition.MAXIMUM RATINGS (Note 1)Rating Symbol Value Unit AVIN and PVIN Pin: Power Supply Voltage (Note 2)V BAT7.0V EN Pin: Digital Logic Input (Note 2)V EN-0.3 ≤ V IN≤ V BAT+0.3V LXP Pin: Output (Note 2)V LXP-0.3 ≤ V IN≤ V BAT+0.3V VREF Pin: Output Reference Voltage (Note 2)V VREF-0.3 ≤ V IN≤ V BAT+0.3V VS Pin: Input (Note 2)V VS+17V SWN Pin: Output (Note 2)V SWN-17V SWP Pin: Input (Note 2)V SWP9.8V VOUTP Pin: Output (Note 2)V VOUTP+17V FBN Pin: Input (Note 2)V FBN-0.3 ≤ V IN≤ V BAT+0.3V Human Body Model (HBM) ESD Rating are (Note 3)ESD HBM2000V Machine Model (MM) ESD Rating are (Note 3)ESD MM200VDigital Input Voltage Digital Input Current EN-0.3 ≤ V IN≤ V BAT+0.31VmALLGA 3x3 mm package (Notes 6 and 7)Thermal Resistance Junction-to-CaseR q JC12°C/W Operating Ambient T emperature Range T A-40 to +85°C Operating Junction T emperature Range T J-40 to +125°C Maximum Junction T emperature T JMAX+150°C Storage T emperature Range T STG-65 to +150°C Moisture Sensitivity (Note 5)MSL Level 1Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.NOTES:1.Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T A = 25°C2.According to JEDEC standard JESD22-A108B.3.This device series contains ESD protection and passes the following tests:Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22-A114 for all pins.Machine Model (MM) ±200 V per JEDEC standard: JESD22-A115 for all pins.tchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78., class II5.Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A.6.The thermal shutdown set to 165°C (typical) avoids irreversible damage on the device due to power dissipation.7.The R q CA is dependent on the PCB heat dissipation. The maximum power dissipation (P D) is dependent on the min input voltage, the max outputcurrent and external components selected.R q CA+125Ă*ĂT APD*R q JCELECTRICAL CHARACTERISTICS Min & Max Limits apply for T A between -40°C to +85°C and V IN between 2.7 V to 4.6 V (Unless otherwise noted). Typical values are referenced to T A = +25°C and V IN = 3.7 V (Unless otherwise noted)Characteristic Symbol Min Typ Max Unit POSITIVE BOOST DC/DC CONVERTERPositive Operational Output Voltage Range V OUTP 4.55 4.6 4.65V Maximum Inductor Peak Current I PEAKP_MAX530700800mA Switches P0 ON Resistance P0MOSR DSON-320640m WSwitches N1 ON Resistance N1MOSR DSON-300600m WSwitches N1 Leakage CurrentAt V IN = 4.2 VN1MOS L-0.050.5m A Efficiency (Notes 8, 9)E FF-85-%Positive Output Current Available (Notes 9, 10) VIN ≥ 3.1 VVIN ≥ 2.9 V, T A between 0 to +85°C I OUTP270--145mAOutput Voltage Line Regulation I OUTP = 0 mA2.7 < V IN < 4.6L INE_RP--10mV Output Voltage Line Transient Overshoot (Note 12)L INE_TP-4-mVPower Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz1.0 kHz to 10 kHz P SRRP--6040--dBOutput Voltage Load Regulation (Note 14)L OAD_RP--0.5%/100mA Output Voltage Load Transient Response: Overshoot andUndershoot Vs. Steady State Voltage (Notes 9, 15)L TRP--100mVNEGATIVE BUCK DC/DC CONVERTERTypical Negative Operational Output Voltage Range V OUTN-15--2.0V Peak Inductor Current (Note 9)I PEAKN_MAX620800920mA Switches P2 ON Resistance P2MOSR DSON-7001400m WSwitches P2 Leakage CurrentAt V IN = 4.2 VP2MOS L-0.050.5m A Efficiency (Notes 8, 9)E FF-80-%Negative Output Power Available (Notes 9, 10) @ V OUTN = -5.4ĂV VIN ≥ 3.1 VVIN ≥ 2.9, T A between 0 to +85°C P OUTN-175--100mAOutput Voltage Reference 0 m A < I REF< 100 m A O VR-1 % 1.265+1 %VFeedback Voltage Threshold in Steady State:2.7 < V IN < 4.6F BVN-2 %0.632+2 %mV Feedback Input Current F BICN-50-50nAOutput Voltage Line Regulation at I OUTN = 0 mA (Note 11)2.7 < V IN < 4.6L INE_RN--20mV Output Voltage Line Transient Overshoot (Note 12)L INE_TN-4-mVPower Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz1.0 kHz to 10 kHz P SRRN--6040--dBLoad Regulation (Notes 11, 14)L OAD RN--0.5%/100mA Load Transient Response: Overshoot and Undershoot Vs.Steady State Voltage (Notes 9, 15)L TRN--100mVELECTRICAL CHARACTERISTICS (Min & Max Limits apply for T A between -40°C to +85°C and V IN between 2.7 V to 4.6 V. Typical values are referenced to T A = +25°C and V IN = 3.7 V, unless otherwise noted)Rating Symbol Min Typ Max Unit Operational Power Supply V IN 2.7- 4.6V Internal Oscillator Frequency, T A = 25°C, V IN = 3.7ĂV F OSC 1.6 1.75 1.9MHz Maximum Duty Cycle M DCY8790-% Stand by Current at I OUTP = I OUTN = 0 mA, EN = LowV IN = 4.2 V, T A between 0 to +85°CI STB-- 2.0m AQuiescent Current @ V OUTN = -5.4 V @ T A = +25°C Switching (Note 9)No Switching I Q--1.51.03.0-mASoft Start Time to limit the Inrush Current S ST- 1.0-ms Thermal Shut Down Protection T SD-165-°C Thermal Shut Down Protection Hysteresis T SDH-15-°C Voltage Input Logic Low V IL--0.4V Voltage Input Logics High V IH 1.2--V EN pin Pull Down Resistance R ENP280400670k W NOTES:8.Efficiency is defined by 100 * (Pout / Pin), Vin = 3.1 to 4.2 V, L = VLF3010AT-4R7MR70 (DCR = 280 m W max, Isat = 700 mA), Load = 15to 30ĂmA, Voutn = -5.4 V.9.Guaranteed by design and characterized.10.Typical application circuit and components depicted Figure 1.11.T ested at 25°C and guaranteed from -40°C to +85°C by characterization.12.Line drop and rise between 3.4 to 2.9 V in 50 m s at I OUT = 25 mA, V OUTN = -5.4 V.13.Ripple = 0.2 V p-p at 25°C, Cout = 4.7 m F, I OUT = 0 to 100 mA, V IN = 3.7 V.14.I OUT from 0 to 100 mA.15.Load step 10 to 90 mA and 90 to 10 mA, rising and falling edge in 10 m s, Cout = 4.7 m F, V IN = 3.7 V.Figure 3. Efficiency vs. I OUTL = MARUWA CXFU0208-4R7Figure 4. Efficiency vs. I OUT , L = MARUWACXFU0208-4R7 plus Optional D2 NSR0320MW2I OUT (mA)I OUT (mA)Figure 5. Line Transient Response V OUTP at 100ĂmA1 VBAT , 500 mV/div DC, from 3.5 to 3.0 V in 50 m s2 VOUTP , 10 mV/div AC, T = 400 m s/divFigure 6. Line Transient Response V OUTN = -5.4 V,100 mA 1 VBAT , 500 mV/div DC, from 3.5 to 3.0 V in 50 m s2 VOUTN, 10 mV/div AC, T = 400 m s/divFigure 7. Continuous Conduction Mode (CCM)1 SWP , 5 V/div DC, 4 I LP , 100 mA/div, DC, I OUTP = 100 mAFigure 8. Discontinuous Current Mode (DCM)1 SWP , 5 V/div, DC 4 I LP , 50 mA/div, DC, I OUTP = 20 mAE F F I C I E N C Y (%)E F F I C I E N C Y (%)Figures 7 and 8 have been done at VBAT = 3.7 V, V OUTN = -5.4 VFigure 9. Continuous Conduction Mode (CCM)1 SWN, 5 V/div DC, 4 I LN , 100 mA/div, DC, I OUTN = 100 mAFigure 10. Discontinuous Current Mode (DCM)1 SWN, 5 V/div, DC 4 I LN , 50 mA/div, DC, I OUTN = 20 mAFigure 11. Positive Output Voltage Ripple in CCM1 V OUTP , 10 mV/div AC, 4 I LP , 100 mA/div DC, I OUTP = 100 mAFigure 12. Negative Output Voltage Ripple in CCM1 V OUTN , 10 mV/div AC, 4 I LN , 100 mA/div DC, I OUTN = 100 mAFigure 13. Start-Up After Enable1 VOUTP ,2 V/div, 2 VOUTN, 2 V/div,3 EN pin, 2 V/divV OUTPV OUTNFigures 9 through 12 have been done at VBA T = 3.7 V and schematic depict Figure 1DETAILED OPERATING DESCRIPTIONFigure 14. Functional Block DiagramDetailed DescriptionsThe NCP5810 is a dual-output DC/DC converter which can generate both a positive and a negative voltage. The output voltage of the inverter is fully configurable using external feedback resistors. The switching regulator operates at 1.75 MH z which allows the use of small inductors and ceramic capacitors. The both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle-by-cycle peak current limit and thermal provide value added features to protect the device.Boost OperationThe internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the low side MN1 switch is turned on thus increasing the current through the inductor L1. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPP compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the MN1 power switch is turned off until the rising edge of the next clock cycle. Inaddition, there are five functions which can reset the flip-flop logic to switch off the MN1. The MAX DP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 700 mA (nom). If the current exceeds this value, the controller turns off the NMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. The boost regulator is internally compensated and provides a minimum of 45° phase margin.Buck-Boost Inverter OperationFigure 9 depicts the two intervals of the buck-boost operation in Continuous Conduction Mode (CCM) in a simplified way. During the first interval, the internal PMOS power switch is turned on and the external Schottky diode is reverse biased. The inductor stores energy through the battery while the load is supplied by the output capacitor to maintain regulation. During the second interval, the switch is turned off and the diode is forward biased, this allows the energy stored in the inductor to be supplied to both the load and the capacitor.In CCM, the voltage ratio of a buck-boost inverter converter can be expressed as:VOUT_N VIN +D1*DĂwhereĂD+TONTSWThe internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the high side PMOS switch is turned on thus increasing the current through the inductor. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPN compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the PMOS power switch is turned off until the rising edge of the next clock cycle. In addition, there are five functions which can reset the flip-flop logic to switch off the NMOS. The MAX DUTY CYCLE COMP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 800 mA (nom). If the current exceeds this value, the controller turns off the PMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage.Buck-Boost CompensationBasically the buck-boost inverter is internally compensated and provides a minimum of 45° phase margin. But a 10 pF (C6) feed-forward capacitor is needed to improved stability with C OUTN = 4.7 m F (C4) used to bypass VOUTN. Moreover in order to achieve excellent the line transient rejection in critical conduction mode two 10Ăm F X5R in parallel for C OUTN can be used. In this case the feed-forward capacitor (C6) must be change from 10ĂpF to 68 pF as depicted Figure 15.Figure 15. Inverter CompensationFeed-forwardHigh Output Voltage AccuracyNCP5810 integrates a very accurate internal voltage reference (1% nom). Combined with the use of precision feedback resistors, the NCP5810 will achieve highly precise output voltages.Excellent Line Transient Rejection and High Power Supply Rejection RatioHigh output voltage accuracy and signal integrity makes the NCP5810 the perfect solution for biasing Active Matrix OLED displays. In order to have a steady, clean display, OLEDs have to be biased by a very accurate voltage with high immunity to line and load transients. Both regulators have been specifically designed with high loop gain and high phase margin to satisfy the great constraints of AMOLED driving.The boost converter features a high power supply rejection ratio of 60 dB (nom).PSRR is defined by*20LOGǒOutputRippleVinRippleǓEnableThis input logic allows enabling and disabling the converter. An active high logic level on this pin enables the device. A built-in pull-down resistor disables the device if the pin is left open.True Shut DownWhen in disable condition, the switch MP0 is turned off and truly isolates the battery from the output. The True shut down eliminates the leakage current from the battery to the load and significantly reduces battery consumption during disable condition, thus increasing battery life.Inrush Current Limiting CircuitryBefore the NCP5810 boost converter is turned on, it is unknown whether the output capacitor COUTP is charged分销商库存信息: ONSEMINCP5810MUTXG。

NCP5810中文资料

er parameters.
9
EN
INPUT Enable: An active high logic level on this pin enables the circuit. A built−in pull−down resistor disables
the device if the pin is left open. Also in disable condition the device provide a true cut−off from PVIN
smooth the current flowing into the load, and limit the noise created by the fast transients present in
this circuitry. A 4.7 mF ceramic bypass capacitor to GND is recommended. Cares must be observed
8
AVIN
POWER Analog Power Supply: The external voltage supply is connected to this pin. A 4.7 mF ceramic ca-
pacitor must be connected across this pin and the power ground to achieve the specified output pow-
Typical Applications
• AMOLED Driver Supply
♦ Cellular Phones ♦ MP3 Player ♦ Digital Cameras ♦ Personal Digital Assistant and Portable Media Player ♦ GPS

IRF640NPBF中文资料—易通商城

TO-220RoHS Compliance DocumentContents:1. Composition2,Tin Whisker Report易通商城：/ehsTO-220 BOM 1ComponentChipEncapsulant Lead Frame Die Attach Wire bond Lead Finish Material Name Silic onEpoxyResin Copper J-AlloyAluminum Matte Tin over Nickel*Material Mass (g)0.01960 0.52430 1.37530 0.011500.00580 0.01520Element Name Composition Si SiO2 Epox y Other Cu Sn Sn Ag Sb Al Ni Sn CAS #7440-21-3 7631-86-9 90598-46-2 - 7440-50-8 7440-31-5 7440-31-5 7440-22-4 7440-36-0 7429-90-5 7440-02-0 7440-31-5 Substance Mass (g) 0.01960 0.44041 0.03670 0.04718 1.37324 0.00206 0.00748 0.00288 0.00115 0.00580 0.00213 0.01307 MaterialAnalysisWeight(%)100% 84% 7%9% 100% 0% 65% 25% 10% 100% 14% 86%% ofTotal Weight 1.0% 22.6% 1.9% 2.4% 70.3% 0.1% 0.4% 0.1% 0.1% 0.3% 0.1% 0.7%Total Weight(g)* Tin whisker mitigation strategy is nickel under-plate.TO-220 BOM 21.95170Component Chip EncapsulantLead Frame Die Attach Wire bond Lead Finish Material Name Silic onEpoxy ResinCopper J-Alloy Aluminum Matte Tin* MaterialMass (g)0.01960 0.52430 1.37530 0.01150 0.00580 0.01520ElementName Composition Si SiO2 Epox y Other Cu Sn Sn Ag Sb Al Sn CAS # 7440-21-3 7631-86-9 90598-46-2 - 7440-50-8 7440-31-5 7440-31-5 7440-22-4 7440-36-0 7429-90-5 7440-31-5 Substance Mass (g) 0.019600.44041 0.03670 0.04718 1.37324 0.00206 0.00748 0.00288 0.00115 0.00580 0.01520 MaterialAnalysisWeight(%) 100% 84% 7%9% 100% 0% 65% 25% 10% 100% 100%% ofTotal Weight 1.0% 22.6% 1.9% 2.4% 70.4% 0.1% 0.4% 0.1% 0.1% 0.3% 0.7%Total Weight(g)1.95170* Tin whisker mitigation strategy is 150 C, 1 hour anneal within 24 hours of tin plating.TO-220 BOM 3ComponentChipEncapsulant Lead Frame Die Attach Wire bond Lead Finish Material Name Silic onEpoxyResin CopperSoft Solder Aluminum Matte Tin* Material Mass (g)0.01960 0.52430 1.375300.01150 0.00580 0.01520Element Name Composition Si SiO2Epox yOther Cu Sn Pb Sn Ag Al Sn CAS #7440-21-3 7631-86-9 90598-46-2 - 7440-50-8 7440-31-5 7439-92-1 7440-31-5 7440-22-4 7429-90-5 7440-31-5 Substance Mass (g) 0.01960 0.44041 0.03670 0.04718 1.37324 0.00206 0.01098 0.00023 0.00029 0.00580 0.01520 MaterialAnalysisWeight(%)100%84% 7% 9% 100%0% 95.5% 2% 2.5% 100% 100% % ofTotal Weight 1.0% 22.6% 1.9% 2.4% 70.4% 0.1% 0.4% 0.1% 0.1% 0.3% 0.7%Total Wt (g) 1.95170* Tin whisker mitigation strategy is 150 C, 1 hour anneal within 24 hours of tin plating.TO-220 BOM 4Component Chip EncapsulantLead Frame Die Attach Wire bond Lead Finish Material Name Silic onEpoxy ResinCopperSoft Solder Aluminum Matte Tinover Nickel* MaterialMass (g)0.01960 0.52430 1.375300.01150 0.005800.01520ElementName Composition Si SiO2Epox y Other Cu Sn Pb Sn Ag Al NiSnCAS # 7440-21-3 7631-86-9 90598-46-2 - 7440-50-8 7440-31-5 7439-92-1 7440-31-5 7440-22-4 7429-90-5 7440-02-0 7440-31-5 Substance Mass (g) 0.01960 0.44041 0.03670 0.04718 1.37324 0.00206 0.01098 0.00023 0.00029 0.00580 0.00213 0.01307 MaterialAnalysisWeight(%)100%84% 7%9% 100%0% 95.5% 2% 2.5% 100%14% 86% % ofTotal Weight 1.0% 22.6% 1.9% 2.4% 70.3% 0.1% 0.4% 0.1% 0.1% 0.3% 0.1% 0.7%Total Wt (g) * Tin whisker mitigation strategy is nickel under-plate.1.95170This part is compliant with EU Directive 2002/95/EC (RoHS) and does not contain lead, mercury,cadmium (0.01%), hexavalent chromium, PBB or PBDE in concentrations greater than 0.1%, except as permitted by Annex (7).TO-220 IRTin Whisker testing per JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface FinishTin Whisker Results (number of failing whiskers)。

IRFR1205TRPBF中文资料

IRFR/U1205HEXFET ®Power MOSFETDescription5/11/98ParameterMax.UnitsI D @ T C = 25°C Continuous Drain Current, V GS @ 10V 44 I D @ T C = 100°C Continuous Drain Current, V GS @ 10V 31 A I DMPulsed Drain Current 160P D @T C = 25°C Power Dissipation 107W Linear Derating Factor 0.71W/°C V GS Gate-to-Source Voltage± 20V E AS Single Pulse Avalanche Energy 210mJ I AR Avalanche Current25A E AR Repetitive Avalanche Energy 11mJ dv/dt Peak Diode Recovery dv/dt 5.0V/ns T J Operating Junction and-55 to + 175T STGStorage Temperature RangeSoldering Temperature, for 10 seconds300 (1.6mm from case )°CAbsolute Maximum RatingsParameterTyp.Max.UnitsR θJC Junction-to-Case––– 1.4R θJA Junction-to-Ambient (PCB mount) **–––50°C/WR θJAJunction-to-Ambient–––110Thermal ResistanceD -P AK T O -252AA I-PA K TO -251AAl Ultra Low On-Resistance l Surface Mount (IRFR1205)l Straight Lead (IRFU1205)l Fast SwitchinglFully Avalanche RatedFifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications.The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques.The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.PD - 91318BIRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205IRFR/U1205元器件交易网Note: For the most current drawings please refer to the IR website at:/package/。

IRF5806TRPBF;中文规格书,Datasheet资料

-VDS , Drain-to-Source Voltage (V)
4
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
10
ID = -4.0A
VDS =-16V
8
C,
Ciss
6
400
4
200
Coss Crss
1 10 100
2
0
0
-VDS , Drain-to-Source Voltage (V)
0
4
8
12
16
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Max.
-20 -4.0 -3.3 -16.5 2.0 1.3 0.02 ± 20 -55 to + 150
Units
V A W W W/°C V °C
Thermal Resistance
Parameter
RθJA Maximum Junction-to-Ambient
Max.
62.5
Units
°C/W
D D
1 6 2
A D
5
D
G
3
4
S
Top View
TSOP-6
Absolute Maximum Ratings
Parameter
VDS ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C PD @TA = 70°C VGS TJ , TSTG Drain-Source Voltage Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Junction and Storage Temperature Range

IR2101STRPBF中文资料

Data Sheet No. PD60043 Rev.OTypical ConnectionFeatures•Fully operational to +600VdV/dt immune••Undervoltage lockout•••phase with inputs (IR2102)•Also available LEAD-FREEHIGH AND LOW SIDE DRIVERProduct SummaryIR2101(S )/IR2102(S ) & (PbF)Description 1IR2101(S )/IR2102(S) & (PbF)Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.Note 1: Logic operational for V S of -5 to +600V. Logic state held for V S of -5V to -V BS . (Please refer to the Design Tip DT97-3 for more details).Recommended Operating ConditionsThe input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 15V differential.IR2101(S )/IR2102(S) & (PbF) 3Static Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V and T A = 25°C unless otherwise specified. The V IN , V TH and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO.Dynamic Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V, C L = 1000 pF and T A = 25°C unless otherwise specified.IR2101(S )/IR2102(S) & (PbF)Functional Block DiagramIR2101(S )/IR2102(S) & (PbF)5Lead DefinitionsSymbolDescriptionHIN Logic input for high side gate driver output (HO), in phase (IR2101)HIN Logic input for high side gate driver output (HO), out of phase (IR2102)LINLogic input for low side gate driver output (LO), in phase (IR2101)LIN Logic input for low side gate driver output (LO), out of phase (IR2102)V B High side floating supply HOHigh side gate drive output V S High side floating supply return V CC Low side and logic fixed supply LO Low side gate drive output COMLow side returnLead Assignments8 Lead PDIP 8 Lead SOICIR2101IR2101S8 Lead PDIP 8 Lead SOICIR2102IR2102SIR2101(S )/IR2102(S) & (PbF)Figure 2. Switching Time Waveform DefinitionsFigure 1. Input/Output Timing DiagramHIN LINHO LOHIN LIN Figure 3. Delay Matching Waveform DefinitionsHIN LIN50%50%IR2101(S )/IR2102(S) & (PbF) 7IR2101(S )/IR2102(S) & (PbF)IR2101(S )/IR2102(S) & (PbF)9IR2101(S )/IR2102(S) & (PbF)10IR2101(S )/IR2102(S) & (PbF)IR2101(S )/IR2102(S) & (PbF)Case outlinesIR2101(S )/IR2102(S) & (PbF)IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105This product has been qualified per industrial levelData and specifications subject to change without notice. 4/2/2004LEADFREE PART MARKING INFORMATIONORDER INFORMATIONBasic Part (Non-Lead Free)8-Lead PDIP IR2101 order IR21018-Lead SOIC IR2101S order IR2101S 8-Lead PDIP IR2102 order IR21028-Lead SOIC IR2102S order IR2102SLeadfree Part8-Lead PDIP IR2101 order IR2101PbF 8-Lead SOIC IR2101S order IR2101SPbF 8-Lead PDIP IR2102 order IR2102PbF 8-Lead SOIC IR2102S order IR2102SPbFPer SCOP 200-002。

IR3721MTRPBF;中文规格书,Datasheet资料

Power Monitor IC withAnalog OutputFEATURESAccurate TruePower TMmonitor • 2.5% static accuracy• Minimizes dynamic errors Minimizes power dissipation• 5mV - 150mV full scale current range Versatile• Monitors power or current• Single buck or multiphase converters • Inductor DCR or resistive shunt sensing Simple add-on to existing converters 10 pin 3x3 DFN lead free package RoHS compliantDESCRIPTIONThe IR3721 is a versatile power or current monitor ICfor low-voltage DC-DC converters. The IR3721 monitors the inductor current in buck or multiphase converters using either a current sensing resistor or the inductor’s winding resistance (DCR). The output (DI) is a pulse code modulated signal whose duty ratio is proportional to the inductor current. An analog voltage that is proportional to power is realized by connecting V K to V O and connecting an RC filter to DI.The IR3721 uses Patent Pending TruePower TMtechnology to accurately capture highly dynamic power waveforms typical of microprocessor loads.TYPICAL APPLICATION CIRCUITORDERING INFORMATIONDevice Package Order Quantity IR3721MTRPBF 10 lead DFN (3x3 mm body) 3000 piece reel * IR3721MPBF 10 lead DFN (3x3 mm body) 121 piece tube* Samples onlyABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings (Referenced to GND) VDD:.................................................................3.9V All other Analog and Digital pins......................3.9VOperating Junction Temperature....-10°C to 150°C Storage Temperature Range..........-65°C to 150°C ESD Rating............HBM Class 2 JEDEC Standard MSL Rating..................................................Level 2 Reflow Temperature.....................................260°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ELECTRICAL SPECIFICATIONSUnless otherwise specified, these specifications apply: VDD = 3.3V ± 5%, 0o C ≤ T J ≤ 125o C, 0.5 ≤ Vo ≤ 1.8 V, and operation in the typical application circuit. See notes following table.NOTES: 1. Guaranteed by designPARAMETER TEST CONDITION MIN TYP MAX UNITBIAS SUPPLYVDD Turn-on Threshold, VDD UP 3.10 V VDD Turn-off Threshold, VDD DN 2.4 V VDD UVLO Hysteresis DI output low when off 75 mV VDD Operating Current, ICC 350 450 μA VOLTAGE REFERENCE V RT Voltage R T = 25.5k Ω 1.452 1.493 1.535 V R T resistance range Note 1 25.5 k Ω ΔΣ CONVERTERVo common mode range 0.5 1.8 V Duty Ratio Accuracy V DCR =20 mV, V O =1V, R T =25.5k Ω, R CS1+R CS2=600 Ω T j =65°C, Note 12.5 %Duty Ratio Accuracy V DCR =20 mV, V O =1V,R T =25.5k Ω, R CS1+R CS2=600 Ω, Note 14 % Sampling frequency, f CLK 435 512 589 kHz Comparator Offset -0.5 +0.5 mV CS pin input current, I CS DI output low -250 +250 nA DIGITAL OUTPUT VK pin voltage range 0.5 1.8 V DI source resistance 1250 2000 3000 ΩBLOCK DIAGRAMVOVGNDIC PIN DESCRIPTIONDESCRIPTIONLEVELI/ONAME NUMBERAnalog Current sensing input, connect through resistor to sensing nodeVCS 1Analog Current sensing reference connect to output voltageVO 2Analog R T thermistor network from this pin to GND programs thermal monitor VRT 3GND 4 Bias return and signal referencesupplybias3.3VVDD 5ICGND 6 Connect to pin 4GND7 Connect to pin 4Analog Power Monitor output; connect to output filterDI 8VK 9 1.8V Connect to fixed voltage or VO, multiplied by DI to become analog output VDD10 3.3V Connect to pin 5BASE PAD Connect to pin 4IC PIN FUNCTIONSVDD PINSThese pins provide operational bias current to circuits internal to the IR3721. Bypass them with a high quality ceramic capacitor to the GND pins.GND PINSThese pins return operational bias current to system ground. VO is measured with respect to GND. The GND pin sinks reference current established by the external resistor R T.VO PINSince this pin measures DCR voltage drop it is critical that it be Kelvin connected to the buck inductor output. Power accuracy may be degraded if the voltage at this pin is below VO min.VCS PINA switched current source internal to the IR3721 maintains the average voltage of this pin equal to the voltage of the VO pin. The average current into this pin is therefore proportional to buck inductor current. VRT PINA voltage reference internal to the IR3721 drives the V RT pin while the pin current is monitored and used to set the amplitude of the current monitor switched current source I REF. Connect this pin to GND through a precision resistor network R T. This network may include provision for canceling the positive temperature coefficient of the buck inductor’s DC resistance (DCR).VK PINThe voltage of the VK pin is used to modulate the amplitude of the DI pin. This is one of the terms used to determine the product of the multiplier output. If VK is connected to a fixed voltage then the output of the multiplier is proportional to current. If VK is connected to the buck converter output voltage then the output of the DI driven RC filter is proportional to power.DI PINThe Dl pin output has a duty ratio proportional to the current into VCS, and an amplitude equal to the voltage at the VK pin. The DI pin is intended to drive an external low pass filter. The output of this filter is the product of the current and voltage terms.FUNCTIONAL DESCRIPTIONPlease refer to the Functional Description Diagram below. Power flow from the buck converter inductor is the product of output voltage times the current I L flowing through the inductor.Power is measured with the aid of InternationalRectifier’s proprietary TruePower™ circuit. Current is converted to a duty ratio that appears at the DI pin. The duty ratio of the DI pin isΤ⋅)+(⋅=R T 2CS 1CS L RATIO DUTY V RR R DCR I DI Equation 1The full-scale current that can be measured corresponds to a duty ratio of one.The amplitude of the DI pin is the voltage appearing at pin VK. If a fixed voltage is applied to VK then the output of the RC filter driven by DI will be proportional to inductor current I L .If VO is applied to V K as shown in the figure then the output of the DI driven RC network will beproportional to power. The full-scale voltage that can be measured is established on the chip to be 1.8V.The full scale power P FS that can be measured is the product of full-scale voltage and full scale current.Figure 1 Functional Description DiagramTHERMAL COMPENSATION FOR INDUCTOR DCR CURRENT SENSINGThe positive temperature coefficient of the inductor DCR can be compensated if R T varies inversely proportional to the DCR. DCR of a copper coil, as a function of temperature, is approximated by)⋅)(+(⋅)(=)(Cu R R TCR T T T DCR T DCR -1Equation 2T R is some reference temperature, usually 25 °C, and TCR Cu is the resistive temperature coefficient ofcopper, usually assumed to be 0.39 %/°C near room temperature. Note that equation 2 is linearly increasing with temperature and has an offset of DCR(T R ) at the reference temperature.If R T incorporates a negative temperature coefficient thermistor then temperature effects of DCR can be minimized. Consider a circuit of two resistors and a thermistor as shown below.RpFigure 2 R T NetworkIf Rth is an NTC thermistor then the value of the network will decrease as temperature increases. Unfortunately, most thermistors exhibit far more variation with temperature than copper wire. One equation used to model thermistors is⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛⋅)(=)(0110TT th th e T R T R - βEquation 3where R th (T) is the thermistor resistance at some temperature T, R th (T 0) is the thermistor resistance at the reference temperature T 0, and β is the material constant provided by the thermistor manufacturer. Kelvin degrees are used in the exponential term of equation 3. If R S is large and R P is small, thecurvature of the equivalent network resistance can be reduced from the curvature of the thermistor alone. Although the exponential equation 3 can nevercompensate linear equation 2 at all temperatures, a spreadsheet can be constructed to minimize error over the temperature interval of interest. Theequivalent resistance R T of the network shown as a function of temperature is)(++=)(T R R R T R th p s T 111Equation 4using R th (T) from equation 3.Equation 2 may be rewritten as a new function of temperature using equations 2 and 4 as follows:())(+⋅)(=)(ΤT DCR R R T R V T I 2CS 1CS T R FS Equation 5With Rs and Rp as additional free variables, use a spreadsheet to solve equation 5 for the desired full scale current while minimizing the I FS (T) variation over temperature.TYPICAL 2-PHASE DCR SENSING APPLICATIONThe IR3721 is capable of monitoring power in a multiphase converter. A Two Phase DCR Sensing Circuit is shown below. The voltage output of any phase is equal to that of any and every other phase because they are electrically connected and monitored at VO as before.Output current is the sum of the two inductor currents (I L1 + I L2). Superposition is used to derive the transfer function for multiphase sensing. The voltage on R CS2 due to I L1 is)||(+)||(⋅⋅3213211CS CS CS CS CS L R R R R R DCR ILikewise, the voltage on RCS2 due to IL2 is)||(+)||(⋅⋅1231222CS CS CS CS CS L R R R R R DCR IThe current through R CS2 due to both inductor currents is I CS . From the two equations above323121122311CS CS CS CS CS CS CS L CS L CS R R R R R R R DCR I R DCR I I +++=The duty ratio of DI isREFTCS DUTYRATIO V R I DI ⋅=If DCR1=DCR2, and RCS1=RCS3, then I CS can be simplified to211212CS CS L L CS R R DCR I I I +⋅)+(=and the DI duty ratio simplifies toΤ⋅)+(⋅⋅)+(=R 2CS 1CS T2L 1L DUTYRATIO V R 2R R DCR I I DIFull scale current occurs when DI duty ratio becomes one.Figure 3 Two Phase DCR Sensing CircuitRESISTOR SENSING APPLICATIONThe Resistor Sensing Circuit shown below is an example of resistive current sensing. Because the voltage on the shunt resistor is directly proportional to the current I L through the inductor, R CS2 and C CS2 do not need to match the L / DCR time constant. Because the value of the shunt resistance does not change with temperature as the inductor DCR does, R T can be a fixed resistor.IFigure 4 Resistor Sensing CircuitCOMPONENT SELECTION GUIDELINES Use a 0.1 μF, 6.3V, X7R ceramic bypass capacitorfrom VDD to GND and from VK to GND.Filter the DI output with an RC filter to give a stable analog representation of the current or power. Some of the DI source resistance of this filter is internal to the IR3721 and specified in the electrical specifications table. Add twenty thousand to fifty thousand additional ohms externally to minimize resistance variation. As the DI source resistance increases beyond these guidelines, the voltage measurement error caused by non-ideal voltmeter conductance will increase.Select a filter capacitor that limits 512 kHz sampling frequency ripple to an acceptable value. Sampling frequency ripple will appear as an error, but can be reduced 20 dB for each decade that the filter corner frequency is below 512 kHz. Select a capacitor value that achieves the desired balance between low sampling frequency ripple and adequate bandwidth. Resistor current sensingFor resistor current sensing select a precision resistor for R T inside the R T resistance range limits specified in the Electrical Specifications table, such as 25.5kΩand 1% tolerance.Next, select a shunt resistor that will provide the most current sensing voltage while also considering the allowable power dissipation limitations. The DI output will saturate to the VK voltage when full scale current I FS flows through this shunt. Recommended maximum current sensing voltage range is 5 to 150 mV. Maximum sensing voltages less than 5 mV will cause comparator input offset voltage errors to dominate, and voltages larger than 150 mV will cause comparator leakage current, I CS, errors to dominate. Select R CS2 to be the next higher standard value resistor from (R SHUNT·I FS·R T) / V RT in order to accommodate full scale current I FS.Bypass VCS to VO with capacitor C CS2. The value of this capacitor limits the bandwidth, but is required because it is the integrator of the delta sigma modulator. Consider selecting the value of C CS2 to place a filter corner frequency at 5 kHz, which will reduce sampling ripple by 40 dB.DCR current sensingSelect an R T network resistance between 20kΩ and 45.3kΩ. Consider the R T network of Figure 5 for DCR current sensing.26.1 kΩ, 1%15.0 kΩ, 1%2.00 kΩ, 1%Murata ThermistorNCP15WB473F03RC47 kΩ, 1%Figure 5 R T networkThe resistance of the network above at 25°C, R T(25), is 37.58kΩ. Over temperature R T(T) is multiplied by copper resistance, DCR(25)·(1+(T-25)·0.0039), divided by (DCR(25)·( R T(25)) to normalize the results, and plotted as nominal error in Figure 6.Figure 6 Nominal error vs. TemperatureNote that the error due to temperature compensation at 25°C is zero, assuming ideal R T components. At other temperatures the results are over or under reported by the factor in percent indicated.Proceed to calculate R SUM, defined as the sum ofR CS1 plus R CS2, as follows.R SUM=I FS·DCR(25) ·R T(25) / V RTAgain, I FS is full scale current and V RT is the reference voltage establishing the current in R T.Estimate the capacitance C CS1 with the following equation.SUMCS R DCR LC ⋅)(⋅>2541Choose a standard capacitor value larger than indicated by the right hand side of the inequality above.Calculate the equivalent resistance R eq .R eq = L / (DCR(25) ·C CS1)We now have two equations, R SUM = R CS1 + R CS2 and Req = (R CS1 · R CS2) / (R CS1 + R CS2). Calculate R CS1 and R CS2 using the following two equations.⎟⎟⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎜⎜⎝⎛⋅+⋅=2R R 411R R SUM eq SUM CS1- and⎟⎟⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎜⎜⎝⎛⋅⋅=2R R 411R R SUM eq SUM 2CS --Use the next higher standard 1% value than indicated in the equations above. This will insure that full scale current can be measured.Bypass VCS to VO with capacitor C CS2. The value of this capacitor limits the bandwidth, but is required because it is the integrator of the delta sigmamodulator. Consider selecting the value of C CS2 to place a filter corner frequency at 5 kHz, which will reduce sampling ripple by 40 dB.分销商库存信息: IRIR3721MTRPBF。