P89LPC914

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飞利浦单片机选型指南

ＸＴＡＬ１／Ｐ３．１ 2
１６字节可擦除页规格。
ＣＬＫＯＵＴ／ＸＴＡＬ２／Ｐ３．０ 3
● ２个１６位定时／计数器（ＬＰＣ９０１的定时器０可作为ＰＷＭ输出）。 ● 模拟比较器：２个（ＬＰＣ９０２／９０３／９０４），１个（ＬＰＣ９０１）。
ＲＳＴ／Ｐ１．５ 4
● ２路输入的Ａ／Ｄ转换器／１个ＤＡＣ输出，可选择参考源（ＬＰＣ９０４）。
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
１２８Ｂ
８脚
１Ｋ
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
ＳＰＩ、Ｉ２Ｃ
１６脚１４脚
２５６Ｂ２Ｋ１Ｋ１２８Ｂ
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
ＳＰＩ、Ｉ２ＣＩＳＰ
８Ｋ４Ｋ２５６Ｂ２０脚２Ｋ
在程序运行时改变代码。 ● ６４脚ＬＱＦＰ封装。 ● ＤＰ－９４０１开发套件。
智能卡水表／气表“单片”解决方案
Ｐ８９ＬＰＣ９１０２／９１０３／９１０７Ｆｌａｓｈ单片机
０４ ● １２８字节ＲＡＭ数据存储器。１ｋＢ可字节擦除的Ｆｌａｓｈ程序存储器，组成２５６字节扇区和１６字节擦除页规格。
13 Ｐ０．２／ＣＩＮ２Ａ／ＫＢＩ２ 12 Ｐ０．４／ＣＩＮ１Ａ／ＫＢＩ４ 11 Ｐ０．５／ＣＭＰＲＥＦ／ＫＢＩ５ 10 ＶＤＤ
9 Ｐ１．０／ＴＸＤ
8 ＣＬＫＯＵＴ／ＸＴＡＬ２／Ｐ３．０
Ｐ２．２／ＭＯＳＩ 1 ＳＰＩＣＬＫ／Ｐ２．５ 2
● Ｆｌａｓｈ保密位可防止程序被读出。 ● 在应用中编程（ＩＡＰ－Ｌｉｔｅ）和字节擦写功能使得程序存储器可用于非易
失性数据的存储。 ● 实时时钟可作为系统定时器。 ● ２个模拟比较器。可选择输入和参考源。 ● ＳＰＩ通信端口、４个键盘中断输入。 ● 选择片内振荡和片内复位时可多达１２个Ｉ／Ｏ口。 ● １４脚ＴＳＳＯＰ和ＤＩＰ封装。

P89LPC922FDH中文资料

0
plastic dual in-line package; 20 leads (300 mil) SOT146-1
3.1 Ordering options
Table 2: Part options
Type number
Flash memory
P89LPC920FDH
2 kB
P89LPC921FDH
8-bit microcontrollers with two-clock 80C51 core
3. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
Version
P89LPC920FDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm
s Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt.
s Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 µA (total Power-down with voltage comparators disabled).

Philips89LPC900系列单片机的低功耗分析与设计

0引言
单片机技术已在工程实践与研究中得到广泛应
用。由于用户与市场的需要 , 设计者在关心单片机系
统的高效性与可靠性同时, 越来越关心系统的低功耗
特性。一些系统由于工作条件特殊 , 需要长期在野外或
地下工作, 必须使用电池供电 (像矿井下的数据采集系
( 解放军炮兵学院五系四十四队安徽合肥 230031 )
【摘要】以基本的CMOS电路为基础, 分析了单片机的功耗组成, 总结了低功耗系统设计的一般规律。分析了 Philips89LPC900系列单片机的功耗特性。以Philips89LPC935为例, 设计了一个低功耗数据采集系统。【关键词】单片机; 低功耗设计; 数据采集【中图分类号】 TP311 【文献标识码】 A 【文章编号】 1003- 773X( 2007) 04- 0130- 02
MOS 管组成, T1是 NMOS 型驱动管 , T2 是 FMOS 型负载管 ,
两个栅极连在一起的输出端是非的逻辑关系。在稳定状态图 1 CMOS 反相器图
时, 两管总处在一个导通 , 另一个必为截止的状态 , 这
时在门电路中没有从 Vdd 到 Vss 的通路 , 电源向反相器提供的电流为截止电流, 因此功耗很小, 而在切换状
态时 , 反相器向负载电容充电 , 或负载电容向反相器充
电, 这时的功耗大大增加。因此, CMOS 电路的功耗可
分为静态功耗和动态功耗[1][2]。电路在稳定状态时功耗
为静态功耗 P 静=Vdd I, 电路在转换状态时产生动态功

P89LPC914FDH,129,P89LPC912FDH,129,P89LPC913FDH,129, 规格书,Datasheet 资料

P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 core, 1 kB 3 Vﬂash with 128-byte RAMRev. 05 — 28 September 2007Product data sheet1.General descriptionThe P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices. Many system-level functionshave been incorporated into the P89LPC912/913/914 in order to reduce componentcount, board space, and system cost.2.Features2.1Principal featuresI 1 kB byte-erasable ﬂash code memory organized into 256B sectors and 16B pages.Single-byte erasing allows any byte(s) to be used as non-volatile data storage.I128B RAM data memory.I Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output upontimer overﬂow or to become a PWM output.I23-bit system timer that can also be used as a RTC.I Two analog comparators with selectable inputs and reference source.I Enhanced UART with fractional baud rate generator, break detect, framing errordetection, automatic address detection and versatile interrupt capabilities(P89LPC913, P89LPC914).I SPI communication port.I Internal RC oscillator (factory calibrated to±1%) option allows operation withoutexternal oscillator components.The RC oscillator option is selectable andﬁne tunable.I 2.4V to 3.6V V DD operating range. I/O pins are 5V tolerant (may be pulled up ordriven to 5.5V).I Up to 12 I/O pins when using internal oscillator and reset options.2.2Additional featuresI14-pin TSSOP packages.I A high performance 80C51 CPU provides instruction cycle times of 111ns to 222nsfor all instructions except multiply and divide when executing at 18MHz (167ns to333ns at12MHz).This is six times the performance of the standard80C51running atthe same clock frequency.A lower clock frequency for the same performance results inpower savings and reduced EMI.I In-Application Programming(IAP-Lite)and byte erase allows code memory to be usedfor non-volatile data storage.I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding withcommercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.I Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight values.I Low voltage reset (brownout detect) allows a graceful system shutdown when powerfails. May optionally be conﬁgured as an interrupt.I Idle and two different power-down reduced power modes. Improved wake-up fromPower-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1µA (total power-down with voltage comparators disabled).I Active-LOW reset. On-chip power-on reset allows operation without external resetcomponents. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.I Conﬁgurable on-chip oscillator with frequency range options selected by userprogrammed ﬂash conﬁguration bits. Oscillator options support frequencies from 20kHz to the maximum operating frequency of 18MHz (P89LPC912, P89LPC913).I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillatorallowing it to perform an oscillator fail detect function.I Programmable port output conﬁguration options: quasi-bidirectional, open-drain,push-pull, input-only.I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value ofthe pins match or do not match a programmable pattern.I LED drive capability (20mA) on all port pins. A maximum limit is speciﬁed for theentire chip.I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10nsminimum ramp times.I Only power and ground connections are required to operate the P89LPC912/913/914when internal reset option is selected.I Four interrupt priority levels.I Four keypad interrupt inputs.I Second data pointer.I Schmitt trigger port inputs.I Emulation support.3.Product comparisonTable 1 highlights the differences between these three devices. For a complete list of device features, please see Section 2 “Features” on page 1.4.Ordering information4.1Ordering optionsTable 1.Product comparisonType numberExternal crystal pinsX2 CLKOUT T0 PWM outputSPI with SS pinSPI without SS pinUART Max f osc (MHz)TXD RXDP89LPC912X X X X ---18P89LPC913X X --X X X 18P89LPC914--XX-XX12Table 2.Ordering informationType numberPackage NameDescriptionVersion P89LPC912FDH TSSOP14plastic thin shrink small outline package; 14leads; body width 4.4mmSOT402-1P89LPC912HDH P89LPC913FDH P89LPC914FDHTable 3.Ordering optionsType number Temperature range Frequency P89LPC912FDH −40°C to +85°C 0 MHz to 18MHz P89LPC912HDH −40°C to +125°C 0 MHz to 18MHz P89LPC913FDH −40°C to +85°C 0 MHz to 18MHz P89LPC914FDH−40°C to +85°C0 MHz to 12 MHz5.Block diagramFig 1.P89LPC912 block diagram1 kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2[5:2]P3[1:0]P1.2, P1.5P0.2, P0[6:4]MOSI SPICLK MISO T0P89LPC912002aaa472SS128 BYTE DATA RAMPORT 3CONFIGURABLE I/O PORT 2CONFIGURABLE I/OPORT 1CONFIGURABLE I/OPORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockCRYST ALORRESONATORXT AL1XT AL2CONFIGURABLE OSCILLATORON-CHIP OSCILLATORPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)ANALOG COMPARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERinternal busHIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPUFig 2.P89LPC913 block diagram1kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2.2, P2.3, P2.5P3[1:0]P1.0, P1.1, P1.5P0.2, P0[6:4]TXDRXDMOSI SPICLK MISOP89LPC913002aaa473128 BYTE DATA RAM PORT 3CONFIGURABLE I/OPORT 2CONFIGURABLE I/OPORT 1CONFIGURABLE I/OPORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockCRYSTAL ORRESONA TORXT AL1XT AL2CONFIGURABLE OSCILLATORON-CHIP OSCILLATORANALOG COMP ARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERUARTHIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPUinternal busPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)Fig 3.P89LPC914 block diagram1 kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2[5:2]P1.5, P1[2:0]P0.2, P0[6:4]MOSI SPICLK MISO T0P89LPC914002aaa474SSTXDRXD HIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPU128 BYTE DAT A RAM PORT 2CONFIGURABLE I/O PORT 1CONFIGURABLE I/O PORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockON-CHIP OSCILLATORPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)ANALOG COMP ARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERUARTinternal bus6.Functional diagramFig 4.P89LPC912 functional diagramFig 5.P89LPC913 functional diagramKBI2KBI4KBI5KBI6CIN2ACIN1A CMPREF CMP1T0RSTP89LPC912MOSIMISO SS SPICLK002aaa475V DDV SSCLKOUTXTAL2XTAL1PORT 0PORT 3PORT 1PORT 2KBI2KBI4KBI5KBI6CIN2ACIN1A CMPREF CMP1TXD RXDRSTP89LPC913MOSIMISOSPICLK002aaa476V DD V SSCLKOUTXTAL2XTAL1PORT 0PORT 3PORT 1PORT 2KBI2KBI4 KBI5 KBI6CIN2ACIN1ACMPREFCMP1TXDRXDT0RSTP89LPC914MOSIMISOSSSPICLK002aaa477V DD V SSPORT 0PORT 1PORT 2Fig 6.P89LPC914 functional diagram7.Pinning information7.1PinningFig 7.P89LPC912 TSSOP14 pin conﬁgurationFig 8.P89LPC913 TSSOP14 pin conﬁgurationFig 9.P89LPC914 TSSOP14 pin conﬁgurationP89LPC912P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.2/T0P2.4/SSP3.1/XTAL1P3.0/XTAL2/CLKOUT002aaa4781234567810912111413P89LPC913P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.1/RXD P1.0/TXDP3.1/XTAL1P3.0/XTAL2/CLKOUT002aaa4791234567810912111413P89LPC914P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.1/RXD P1.0/TXD P1.2/T0P2.4/SS002aaa48012345678109121114137.2Pin description Table 4.P89LPC912 pin descriptionSymbol Pin Type DescriptionP0.2, P0.4 to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input4.P0.5/CMPREF/ KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input6.P1.2, P1.5I/O(P1.2);I(P1.5)Port1:Port1is a2-bit I/O port with P1.2having a user-conﬁgurable output type as noted below.During reset Port1latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the P1.2 input and outputs depends upon the port conﬁguration selected. Refer to Section 8.12.1 “Port conﬁgurations”and T able13“Static characteristics”for details.P1.2is an open drain when used as an output. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.2/T06I/O P1.2 —Port1 bit2. (Open drain when used as an output.)I/O T0 —Timer/counter0 external count input or overﬂow output. (Open drain whenused as outputs.).P1.5/RST3I P1.5 —Port1 bit5. (Input only.)I RST —External Reset input during power-on or if selected via UCFG1. Whenfunctioning as a reset input a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.When using an oscillator frequency above12MHz,the reset input function ofP1.5 must be enabled. An external circuit is required to hold the device inreset at power-up until V DD has reached its speciﬁed level. When systempower is removed V DD will fall below the minimum speciﬁed operatingvoltage. When using an oscillator frequency above 12MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum speciﬁed operatingvoltage.P2.2 to P2.5I/O Port 2:Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.The operation of Port 2pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 2 also provides various special functions as described below:P2.2/MOSI 1I/OP2.2 —Port 2 bit 2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO 14I/O P2.3 —Port 2 bit 3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.4/SS 9I/O P2.4 —Port 2 bit 4.I SS —SPI Slave select.P2.5/SPICLK 2I/O P2.5 —Port 2 bit 5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.P3.0 to P3.1I/OPort 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During resetPort 3 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 3pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 3 also provides various special functions as described below:P3.0/XT AL2/CLKOUT 8I/O P3.0 —Port 3 bit 0.OXTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the ﬂash conﬁguration).O CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator orexternal clock input, except when XTAL1/XT AL2 are used to generate clock sourcefor the Real-Time clock/system timer.P3.1/XT AL17I/O P3.1 —Port 3 bit 1.I XTAL1 —Input to the oscillator circuit and internal clock generator circuits (whenselected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator orwatchdog oscillator is used as the CPU clock source,and if XTAL1/XT AL2 are notused to generate the clock for the Real-Time clock/system timer.V SS 4I Ground: 0V reference.V DD 10IPower Supply:This is the power supply voltage for normal operation as well as Idleand Power-down modes.Table 4.P89LPC912 pin description …continued Symbol Pin TypeDescriptionTable 5.P89LPC913 pin descriptionSymbol Pin Type DescriptionP0.2,P0.4to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input 2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input 4.P0.5/CMPREF/ KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input 5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input 6.P1.0, P1.1, P1.5I/O(P1.0,P1.1);I(P1.5)Port1:Port1is a3-bit I/O port with a user-conﬁgurable output type,except for P1.5noted below.During reset Port1latches are conﬁgured in the input only mode withthe internal pull-up disabled.The operation of the conﬁgurable Port1pins as inputsand outputs depends upon the port conﬁguration selected.Each of the conﬁgurableport pins are programmed independently. Refer to Section 8.12.1 “Portconﬁgurations” and Table 13 “Static characteristics” for details. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.0/TXD9I/O P1.0 —Port1 bit0.O TXD —T ransmitter output for the serial port.P1.1/RXD6I/O P1.1 —Port1 bit1.I RXD —Receiver input for the serial port.P1.5/RST3I P1.5 —Port1 bit5 (input only).I RST —External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input, a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.When using an oscillator frequency above12MHz,the reset input function ofP1.5 must be enabled. An external circuit is required to hold the device inreset at power-up until V DD has reached its speciﬁed level. When systempower is removed V DD will fall below the minimum speciﬁed operatingvoltage. When using an oscillator frequency above 12MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum speciﬁed operatingvoltage.P2.2, P2.3,P2.5I/O Port 2: Port 2 is a 3-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 2pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 2 also provides various special functions as described below:P2.2/MOSI 1I/OP2.2 —Port 2 bit 2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO 14I/O P2.3 —Port 2 bit 3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.5/SPICLK 2I/O P2.5 —Port 2 bit 5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.P3.0 to P3.1I/OPort 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During resetPort 3 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 3pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 3 also provides various special functions as described below:P3.0/XT AL2/CLKOUT 8I/O P3.0 —Port 3 bit 0.OXTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the ﬂash conﬁguration).O CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator orexternal clock input, except when XTAL1/XT AL2 are used to generate clock sourcefor the Real-Time clock/system timer.P3.1/XT AL17I/O P3.1 —Port 3 bit 1.I XTAL1 —Input to the oscillator circuit and internal clock generator circuits (whenselected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator orwatchdog oscillator is used as the CPU clock source,and if XTAL1/XT AL2 are notused to generate the clock for the Real-Time clock/system timer.V SS 4I Ground: 0V reference.V DD 10IPower Supply:This is the power supply voltage for normal operation as well as Idleand Power-down modes.Table 5.P89LPC913 pin description …continued SymbolPin Type DescriptionTable 6.P89LPC914 pin descriptionSymbol Pin Type DescriptionP0.2,P0.4to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input 2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input 4.P0.5/CMPREF / KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input 5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input 6.P1.0to P1.2, P1.5I/O(P1.0toP1.2);I(P1.5)Port1: Port1 is a 4-bit I/O port with a user-conﬁgurable output type, except forthree pins noted below. During reset Port1 latches are conﬁgured in the input onlymode with the internal pull-up disabled. The operation of the conﬁgurable Port1pins as inputs and outputs depends upon the port conﬁguration selected. Each ofthe conﬁgurable port pins are programmed independently. Refer to Section 8.12.1“Port conﬁgurations” and Table 13 “Static characteristics” for details. P1.2 is anopen drain when used as an output. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.0/TXD9I/O P1.0 —Port1 bit0.O TXD —T ransmitter output for the serial port.P1.1/RXD6I/O P1.1 —Port1 bit1.I RXD —Receiver input for the serial port.P1.2/T07I/O P1.2 —Port1 bit2. (Open drain when used as an output.)I/O T0 —Timer/counter0 external count input or overﬂow output. (Open drain whenused as outputs.)P1.5/RST3I P1.5 —Port1 bit5 (input only).I RST —External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input, a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.Table 6.P89LPC914 pin description …continuedSymbol Pin Type DescriptionP2.2 to P2.5I/O Port2: Port2 is a 4-bit I/O port with a user-conﬁgurable output type. During resetPort2 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port2pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port2 also provides various special functions as described below:P2.2/MOSI1I/O P2.2 —Port2 bit2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO14I/O P2.3 —Port2 bit3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.4/SS8I/O P2.4 —Port 2 bit 4.I SS —SPI Slave select.P2.5/SPICLK2I/O P2.5 —Port2 bit5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.V SS4I Ground: 0V reference.V DD10I Power Supply: This is the power supply voltage for normal operation as well asIdle and Power-down modes.8.Functional descriptionRemark:Please refer to the P89LPC912/913/914 User manual for a more detailedfunctional description.8.1Special function registersRemark:SFR accesses are restricted in the following ways:•User must not attempt to access any SFR locations not deﬁned.•Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.•SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:–‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any valuewhen read (even if it was written with ‘0’). It is a reserved bit and may be used infuture derivatives.–‘0’must be written with ‘0’, and will return a ‘0’ when read.–‘1’must be written with ‘1’, and will return a ‘1’ when read.P89LPC912_913_914_5© NXP B.V . 2007. All rights reserved.Product data sheet Rev. 05 — 28 September 200717 of 66NXP Semiconductors P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 coreTable 7.P89LPC912 Special function registers* indicates SFRs that are bit Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex BinaryBit address E7E6E5E4E3E2E1E0ACC*Accumulator E0H 000000 0000AUXR1Auxiliary function register A2H CLKLP --ENT0SRST 0-DPS 00[1]0000 00x0Bit address F7F6F5F4F3F2F1F0B* B register F0H 000000 0000CMP1Comparator 1 control register ACH --CE1-CN1OE1CO1CMF100[1]xx00 0000CMP2Comparator 2 control register ADH --CE2-CN2-CO2CMF200[1]xx00 0000DIVM CPU clock divide-by-M control95H 000000 0000DPTR Data pointer (2 bytes)DPH Data pointer high 83H 000000 0000DPL Data pointer low 82H 000000 0000FMADRH Program ﬂash address high E7H ------000000 0000FMADRL Program ﬂash address low E6H 000000 0000FMCON Program ﬂash control (Read)E4H BUSY ---HVA HVE SV OI 700111 0000Program ﬂash control (Write)FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.FMDA T A Program ﬂash data E5H 000000 0000Bit address AF AE AD AC AB AA A9A8IEN0*Interrupt enable 0A8H EA EWDRT EBO -ET1-ET0-000000 0000Bit address EF EE ED EC EB EA E9E8IEN1*Interrupt enable 1E8H ----ESPI EC EKBI -00[1]00x0 0000Bit address BF BE BD BC BB BA B9B8IP0*Interrupt priority 0B8H -PWDRT PBO -PT1-PT0-00[1]x000 0000IP0H Interrupt priority 0 high B7H -PWDRT HPBOH -PT1H -PT0H -00[1]x000 0000Bit address FF FE FD FC FB FA F9F8IP1*Interrupt priority 1F8H ----PSPI PC PKBI -00[1]00x0 0000IP1H Interrupt priority 1 high F7H ----PSPIH PCH PKBIH -00[1]00x0 0000芯天下--/P89LPC912_913_914_5© NXP B.V . 2007. All rights reserved.Product data sheet Rev. 05 — 28 September 200718 of 66NXP Semiconductors P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 core KBCON Keypad control register 94H ------P ATN _SELKBIF 00[1]xxxx xx00KBMASK Keypad interrupt mask register86H 000000 0000KBP ATN Keypad pattern register 93H FF 1111 1111Bit address 8786858483828180P0*Port 080H CMP1/KB6CMPREF / KB5CIN1A/KB4CIN2A/KB2[1]Bit address 9796959493929190P1*Port 190H RST T0[1]Bit address A7A6A5A4A3A2A1A0P2*Port 2A0H SPICLK SS MISO MOSI [1]Bit address B7B6B5B4B3B2B1B0P3*Port 3B0H XTAL1XT AL2[1]P0M1Port 0 output mode 184H (P0M1.6)(P0M1.5)(P0M1.4)(P0M1.2)FF 1111 1111P0M2Port 0 output mode 285H (P0M2.6)(P0M2.5)(P0M2.4)(P0M2.2)000000 0000P1M1Port 1 output mode 191H (P1M1.2)D3[1]11x1 xx11P1M2Port 1 output mode 292H (P1M2.2)-00[1]00x0 xx00P2M1Port 2 output mode 1A4H (P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)FF 1111 1111P2M2Port 2 output mode 2A5H (P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)000000 0000P3M1Port 3 output mode 1B1H (P3M1.1)(P3M1.0)03[1]xxxx xx11P3M2Port 3 output mode 2B2H (P3M2.1)(P3M2.0)00[1]xxxx xx00PCON Power control register 87H --BOPD BOI GF1GF0PMOD1PMOD0000000 0000PCONA Power control register A B5H RTCPD -VCPD --SPPD --00[1]0000 0000Bit address D7D6D5D4D3D2D1D0PSW*Program status word D0H CY AC F0RS1RS0OV F1P 000000 0000PT0AD Port 0 digital input disable F6H --PT0AD.5PT0AD.4-PT0AD.2--00xx00 000x RSTSRC Reset source register DFH --BOF POF -R_WD R_SF R_EX [2]RTCCON Real-time clock control D1H RTCF RTCS1RTCS0---ERTC RTCEN 60[1][5]011x xx00RTCH Real-time clock register high D2H 00[5]0000 0000Table 7.P89LPC912 Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/。

基于P89LPC915微处理器控制的数字化高压电源模块

控制方式。例如，了能够补偿由于温度变化为引起的光电倍增管参数变化而引起的仪器误差，器需要根据温度的变化调整提供给光电仪倍增管的高压＿，高仪器的温度稳定性。－提１］随着使用方式的改变和对电源性能要求的提高，高压电源的设计也提出了新的要求。对
收稿日期：０９Ｏ－３２０７Ｏ－
作者简介：米昶（９２，，１５一）男山东青岛，副教授，教师，硕士学位，主要研究方向：入式系统，能仪嵌智
器。
１６４６
关。在传统的电路设计中，该部分电路的实现
方式一般有两种：分立元件构成的振荡电路，例
由于在传统的高压电源模块设计中电源参数的控制一般都是通过人工调节模拟电路用电位器，若要实现智能化的自动控制须通过附加电
路的形式实现。例如使用ＤＡ控制芯片将电源电压的控制由模拟控制方式转变为数字控制方式。如果在高压电源模块中能自动实现上述功能，该类仪器的设计必将带来非常有意义的对１２系统模块功能的常规实现技术．
电路特性的限制，这类电路的频率稳定性受到定的局限而且实现ＰＷＭ控制较为困难。
另外，为一个完整的电源系统的控制部作
分，了高频信号发生电路外，除还需稳定电压输
出的电路。在由分立元件构成的电路中，由于
电路实现方法的限制，般采用高压稳压管的一方式。这种方式不但体积较大，而且电源的效率也较低。因此，现代电源的电路结构普遍在信号发生电路的基础上附加输出电压的取样电路，通过控制频率发生电路输出的方法实现稳定的直流高压输出。为了满足电源的性能和简化设计，许多在高压电源模块的设计中采用了开关集成控制器，例如Ｓ５４Ｔ４４等［。这类控制器属Ｇ３２、Ｌ９１］

P89LPC9401 中文手册

I/O P2.1
I/O P2.2
I/O MOSI SPI 主机输出/从机输入。当配置为主机时，该管脚为输出；当配置
20 63 64 BP0~BP3 S0~S31 Vss VDD VLCD 27-30 31-62 12 25 26
SPICLK SPI 时钟。当配置为主机时，该管脚为输出；当配置为从机时，
I/O SDALCD I/O SCLLCD O O I I I
BP0-3：LCD 背电极输出。 S0-S31: LCD 段输出。地: 0V 参考点。
电源: 正常操作模式、空闲模式和掉电模式时的电源。 LCD 电源：LCD 电源电压。
[1] P1.0～P1.4、P1.6、P1.7 为输入/输出口，P1.5 仅为输入口。
6. 逻辑符号
图 3 P89LPC9401 逻辑符号
5
广州周立功单片机发展有限公司 Tel：（020）38730976 38730977 Fax：38730925 http：//
7. 功能描述
备注：更详细的功能描述请参考 P89LPC9401 使用指南。 7.1 特殊功能寄存器备注：对特殊功能寄存器（SFR）的访问必须遵循以下方式：用户不要试图访问任何未经定义的 SFR 地址。对任何已定义的 SFR 的访问必须符合 SFR 的功能。标注为‘-’,‘0’或‘1’的 SFR 位只能以如下方式读或写：－除非特别说明， ‘-’必须写入 0，但当读出时不返回任何确定的值（即使向其写入 0）。这是一个保留位，作为将来功能扩展之用。－‘0’必须写入 0，并且当读出时返回 0。－‘1’必须写入 1，并且当读出时返回 1。表 4 特殊功能寄存器带*的 SFR 表明可位寻址
名称定义地址位地址 ACC* AUXR1 累加器辅助功能寄存器 E0H A2H 位地址 B* BRGR0 BRGR1

基于LPC系列单片机的串口扩展器设计

基于LPC系列单片机的串口扩展器设计唐洪富【摘要】介绍了一种基于单片机 P89LPC931的 SPI 总线扩展异步串行接口UART 的装置，讲述了P89LPC931单片机的开发使用，重点详细阐明了扩展芯片GM8142的开发使用。

用户可以根据不同的应用环境灵活配置参数。

本装置成本低，可靠性高，稳定性强。

%An UART extended by SPI bus based on single chip microcomputer P89LPC931 was introduced. The development ofP89LPC931 was described, and the development of the chip GM8142 was emphatically elaborated. The configuration parameters are flexible depended on the application environment. The extender has the characters of low cost , reliability and stability.【期刊名称】《微型机与应用》【年(卷),期】2015(000)013【总页数】3页(P97-99)【关键词】LPC 单片机;GM8142;SPI 总线【作者】唐洪富【作者单位】中国电子信息产业集团有限公司第六研究所，北京 100083【正文语种】中文【中图分类】TP23随着单片机技术的不断发展，特别是网络技术在测控领域的广泛应用，由单片机构成的多机网络测控系统已成为单片机技术发展的一个方向。

单片机的应用已不仅仅局限于传统意义上的自动监测或控制，而是形成了向以网络为核心的分布式多点系统发展的趋势。

但是，大多数单片机都只有一个串行接口，在多数情况下限制了这些单片机的进一步应用。

要实现单片机在应用系统中的有效通信，就必须对单片机进行串口扩展。

TKS-932、935、936仿真器快速入门

TKS-932/935/936仿真器快速入门（2005/03/16 V2.2）注：本用户使用手册适用于TKS-932、TKS-935和TKS-936，以下统称为TKS-900。

目录一、 TKS-900技术特点和背景资料二、 TKS-900型号的分类三、 TKS-900仿真器使用前应该了解的知识四、 TKS-900在Keil中的快速操作五、使用TKS-900进行仿真六、 TKS-900的物理结构七、 TKS-900仿真头组件的使用八、 TKS-900仿真器的限制九、 TKS-900使用中的常见问题十、 TKS-900的升级十一、结束语警告：该文档的内容可能会在以后发生改变，用户需要以随机提供的电子文档为标准。

一、TKS-900技术特点和背景资料TKS-900仿真器是广州致远电子有限公司推出的系列实时在线仿真器，TKS-900完全支持PHILIPS公司P89LPC900系列芯片的仿真（TKS-932、TKS-935分别支持P89LPC932、P89LPC935以下芯片的仿真，均可有偿升级到TKS-936，支持P89LPC938以下芯片的仿真）。

在仿真性能上进行了全面的优化设计，能保证用户更加方便的操作和真实的仿真效果。

兼容Keil公司的硬件仿真环境，使用户能够在先进的编译环境下编译，同时也能在先进的仿真环境下进行硬件仿真；使用PHILIPS公司授权的专用BondOut芯片，仿真更加真实；采用更加合理的BondOut通讯方式，BondOut工作更加稳定；真实仿真LPC900的掉电模式和空闲模式；真实仿真LPC900的各种方式的复位（软件复位、看门狗复位、外部复位）；支持用户程序嵌入配置字节，使用户仿真/烧写更加方便可靠，同时在仿真中可随意观察和修改用户配置字节（等待标准制定）；内部更加可靠的保护，避免使用中误操作引起仿真器的损坏；连续单步运行速度更快；支持使用外部用户电源电压，用户提供的电源电压最低可达3.3伏；支持使用外部复位信号；仿真时多而详细的状态信息提示，帮助用户迅速查找目标系统的故障；系统内部多种检查，当系统配置错误时避免进入错误的运行状态。

EP3.0双串口通用编程器

EP3.0双串口通用编程器EP3.0编程器是EP51编程器的升级版本，可以支持ATMEL华邦，飞利浦，STC,SST等单片机以及EPROM等型号超过500种，而价格仅100多元，具有性能稳定,烧录速度快,性价比高等优点。

双串口设计，可以运行第三方软件，特别支持目前具有高度加密特性和性能价格比的STC系列单片机。

也是目前唯一一款可以支持第三方软件的编程器！直接USB供电，无需电源，串口通信，速度11520BPS,烧写8K的S52 只需要不到6秒！全黑色高档双面pcb设计，是目前最为经济，美观和方便实用的编程器单价：130元，不含税，不含运费;硬件说明1、c51/2051选择。

这里有两个跳线，如果要烧写2051/1051/4051 等20pin 的芯片，把两个跳线都跳到2051这一端，另外把下面的ISP接口的rxd1和gnd短路，则可获得更加快的速度和稳定性！（看本叶面最后的图片）其他时候都跳到c51这一端。

2、89s系列ISP下载头。

当你的目标板上有ISP接口的时候，可以用引线把相应的管脚连接到目标板。

用于89s51等片子的外部ISP下载。

3、STC/SST/PHILPS下载头。

可以用于连接COM信号到目标板上进行ISP下载4、电源指示，通电后亮。

5、烧写指示，通信时亮。

同时在上电后1秒会闪一下，表示系统自检ok.6、USB电源，插入USB线，为系统提供5v电源，注意这里不提供通信作用。

仅仅用来供电。

7、COM2 运行第三方软件（SST,PHLIPS,STC软件）的时候配合使用8、COM1 运行EASY 51PRO.EXE的时候配合使用。

（注意，以上两个COM口不能同时运行）硬件连接1. 将串口COM1 (注意：COM1是EP51PRO的串口! COM2是STC/SST/PHILPS的串口，切勿搞错！)插入电脑串口。

(注意COM端口号，默认是COM1,如果是其他口，则应当以后在编程器软件设置中更改为相应的COM号。

LPCPRO编程器功能介绍-LPCPRO编程器

LPC PRO编程器LPC PRO编程器是一款全面支持PHILIPS LPC系列单片机烧写的专用型编程器产品。

LPC PRO编程器不仅支持LPC700和LPC900系列单片机，也支持大部分24、25、93系列串行EEPROM的编程。

LPC PRO编程器经过全面技术创新，可同时支持串行下载(ICP)方式和并行方式编程，充分体现面向用户的设计理念。

LPC PRO编程器体现人性化设计，为用户带来操作的享受！方便灵活的编程方式，为用户消除烧写芯片的烦恼！LPC PRO编程器的超强功能 = CP900编程器+CP76X编程器+MiniICP下载线！参考图片功能特点U SB接口，支持多机操作，编程速度快；USB供电，无需电源适配器；体积小，重量轻，携带、使用方便；内置可靠电源电路，保证系统工作稳定；完善过流保护功能，编程芯片更安全；多种编程接口设计，使用更灵活；附加MiniICP功能，各种封装芯片任我选！支持ISP代码恢复，支持芯片内部EEPROM编程；软件可免费无限升级，维护用户利益！采用美国进口锁紧座，品质保障，质量更稳定！软件界面友好美观，功能强，操作方便；LPCPRO适用与产品的研发、量产和维护阶段。

支持器件：LPC900系列P89LPC90x：P89LPC901/902/903/904/906/907/908P89LPC910x：P89LPC9102/9103/9107P89LPC91x：P89LPC912/913/914/915/916/917P89LPC92x：P89LPC920/921/922/924/925P89LPC93x：P89LPC930/931/932/933/934/935/936/938P89LPC9401LPC700系列P87LPC759 P87LPC760 P87LPC761P87LPC762 P87LPC764 P87LPC767P87LPC768 P87LPC769 P87LPC776P87LPC777 P87LPC778 P87LPC779I2C接口的24系列芯片，SPI接口的25，93系列芯片支持ATC，ATMEL，CATALYAT，FAIRCHILD，HOLTEK，ISSI，LINKSMART，MICROCHIP，RAMTRON，ROHM，ST，XICOR等厂商的绝大多数串口EEPROM。

基于P89LPC935的四相步进电机细分驱动器设计

细分数为２６当细分数为１８，５，２时采用８ＩＣ３９９５内部ＲＰＣ振荡器，步进电机的最高转速可达１０ｒｉ，２ｍｎ运行／
．
收稿日期：０８０．Ｏ２０．１６
７８
＿２００８年
控制町根据应用需要，选择端口电平、串口通信、ｃ接口通信等多种方式，Ｉ２具有较高的实用价值。
出，的Ｉ它／１０３可配置为准双向、推挽、为输入和开漏４仅
种模式，具有最大２Ａ电流驱动能力，０ｍ虽然工作电压为
２７．但Ｉ口在开漏模式下可承受５ｖ电压，． —３６Ｖ，／Ｏ与其它电路接口方便，使用十分灵活ｎ］卫。
的控制方式均采用ＰＷＭ恒流控制。这种控制方式电源效率高、系统温升低、适用电压范围宽，优点十分显
著；但其驱动电路复杂，生产成本高，用于驱动小功率步进电机，驱动器的价格往往数倍于电机的价格，这在
很大程度上限制了它的应用。８ＩＣ３９．９５是ＰＩＩＳ推出的新型８Ｃ１ＰＨＬＰ０５指令兼容单
１细分驱动原理
步进电机的驱动，实质是通过开关步进电机各相的电流，其定子中产生一个旋转的磁场，动中间其在带
的转子实现同步转动。在步进电机的常规驱动中，电流为恒压或恒流供电，相在开关供电状态下，相电流的变化是电阻和电感串联的瞬变过程，由此产生的旋转磁场是一个脉动变化的磁场，导致电机运行时的震动和
运行噪音。
关键词：８ＬＣ３；Ｐ９Ｐ９５步进电机；细分驱动器

内置LCD驱动器的P89LPC9401 Flash单片机

内置LCD驱动器的P89LPC9401 Flash单片机
佚名
【期刊名称】《单片机与嵌入式系统应用》
【年(卷),期】2005(0)4
【总页数】1页(Pi006-i006)
【正文语种】中文
【中图分类】TP
【相关文献】
1.可编程单片机内置LCD模块和纳瓦技术 [J],
2.Microchip发布全球首款28引脚LCD单片机及首款可驱动192段LCD的80引脚可编程单片机——PIC单片机系列提供可再编程闪存、内置LCD模块和纳瓦技术电源管理功能 [J],
3.可驱动168段LCD的64引脚单片机：提供14Kb闪存，采用纳瓦技术并内置LCD模块 [J],
4.电源内置LCD控制驱动器AMI3801设计研究 [J], 曾永红;邹雪城;付智辉;范文
5.Maxim发布最新LED背光驱动器，内置LCD偏置 [J],
因版权原因，仅展示原文概要，查看原文内容请购买。

um_EP900 _cn_v2.0

EP900仿真/编程器操作指南概览EP900仿真/编程器支持在电路调试以及对飞利浦P89LPC900系列单片机闪存并行编程。

EP900直接与KEIL的仿真调试软件KEIL µVision3连接，并且提供全面控制用户程序的执行。

特点通过USB接口给仿真器供电，并且与PC快速通信。

实时在线仿真，支持器件全速及可编程时钟运行。

支持Keil公司的硬件仿真环境，使用户在先进的编译环境下编译，而且也能在先进的仿真环境下进行硬件仿真。

使用PHILIPS公司授权的专用BondOut芯片，仿真更加真实。

真实仿真LPC900系列单片机的掉电模式和空闲模式。

真实仿真LPC900系列单片机的各种方式的复位(软件复位，看门狗复位，外部复位)。

支持START900.A51文件中UCFG1及用户程序嵌入配置字节，使用户仿真，烧写更加方便可靠，同时在仿真中可随意观察和修改用户配置字节。

内部更加可靠的保护，避免使用中误操作引起仿真器的损坏。

支持使用外部用户电源电压，用户提供的电源电压最低可达2.7V。

仿真时多而详细的状态信息提示，帮助用户迅速查找目标系统的故障。

支持并行模式及ICP模式对LPC900片内闪存进行编程。

八只带缓冲的LED指示P2口的状态。

LED指示器EP900提供一些LED指示各种不同的状态。

POWER点亮时表示EP900已经上电。

STAT 表示EP900 在以下情况下的状态USB 设备被检测到时: 点亮0.3秒.启动µVision3调试: 一直点亮.用户应用程序在调试状态下运行:熄灭LED.闪存正在编程: 一直点亮.P2口的LED通过缓冲器驱动后来指示P2的状态信息。

默认情况下LED驱动器是禁能的，以避免影响开放设备输入信号产生摆动。

P2口的LED可以在µVision2/3中以下设置使能：Project — Options for Target — Debug — EP900 Settings — Enable P2 LED driver.支持的芯片有P89LPC90x：P89LPC901/902/903/904/906/907/908P89LPC910x：P89LPC9102/9103/9107P89LPC91x：P89LPC912/913/914/915/916/917/918P89LPC92x：P89LPC920/921/922/924/925P89LPC93x：P89LPC930/931/932/933/934/935/936/938（需要LPC936或者LPC938 BONDOUT芯片）P89LPC9401 P89LPC9408Emulation Mode仿真模式为了能在目标板上使用EP900仿真器，您必须:•连接EP900到您的目标系统。

pricelist

“周立功单片机”产品零售价一览表更新：2004年3月19日以下产品的邮购均须根据具体情况收取邮费PHILIPS LPC700单片机型号零售封装型号零售封装P87LPC760BN 7.0 PDIPP87LPC759BN 6.2 PDIPP87LPC761BN 7.3 PDIPP87LPC760BDH 7.0 TSSOPP87LPC761BDH 7.3 TSSOP P87LPC762BN 9.2 PDIPP87LPC762BD 9.0 PSOP P87LPC762BDH 9.0 TSSOPP87LPC762FN 10.0 PDIP P87LPC762FD 10.0 PSOPP87LPC764BN 10.8 PDIP P87LPC764BD 10.8 SOICP87LPC764BDH 10.8 TSSOP P87LPC764FN 11.5 PDIPP87LPC764FD 11.5 SOIC P87LPC767BN 13.8 PDIPP87LPC767BD 13.8 PSOP P87LPC767FN 15.8 PDIPP87LPC767FD 15.8 PSOP P87LPC768BN 18.0 PDIPP87LPC768FN 20.0 PDIP P87LPC769HD 27.0 PSOPPHILIPS LPC900单片机型号零售封装型号零售封装P89LPC901FN 6.8 PDIP P89LPC901FD 6.5 PSOPP89LPC902FD 7.5 PSOPP89LPC902FN 8.0 PDIPP89LPC906FD 7.0 PSOP P89LPC903FD 8.0 PSOPP89LPC908FD 8.2 PSOP P89LPC907FD 7.5 PSOPP89LPC913FDH 8.8 TSSOP P89LPC912FDH 8.5 TSSOPP89LPC921FDH 11.0 TSSOP P89LPC914FDH 8.8 TSSOPP89LPC922FN12.0 PDIP P89LPC922FDH11.5 TSSOPP89LPC930BA 12.5 PLCCP89LPC930BDH12.5 TSSOPP89LPC931BA 13.0 PLCCP89LPC930FDH 12.0 TSSOPP89LPC931FDH 13.5 TSSOPP89LPC932BA 18.0 PLCCP89LPC932FDH 17.0 TSSOPP89LPC932BDH 16.5 TSSOPP89LPC935FDH 20.0 TSSOPP89LPC935FA 23.0 PLCCPHILIPS ARM系列型号零售封装型号零售封装LPC2105BBD 70.0 LQFP LPC2104BBD 62.0 LQFPLPC2114FBD 62.0 LQFP LPC2106BBD 75.0 LQFPLPC2119FBD 72.0 LQFPLPC2124FBD 77.0 LQFPLPC2214FBD 85.0 LQFP LPC2129FBD 85.0 LQFPPHILIPS 8xC5x/5xX2单片机型号零售封装型号零售封装P87C51X2BA 9.3 PLCC P87C51X2BN 8.7 DIPP87C51SFPN 10.3 DIPP87C51X2BBD 9.3 LQFPP89C51X2BN 7.5 DIPP89C51X2BA 8.1 PLCCP87C52X2BA 10.8 PLCCP87C52X2BN10.0 DIPP87C52X2FN 12.1 DIPP87C52SFBB 11.8 QFPP89C52X2BN 8.6 DIPP87CL52X2BBD14.8 LQFPP89C52X2BBD 9.7 LQFPP89C52X2BA 9.2 PLCCP87C54UBAA 17.2 PLCCP87C54X2BN 16.2 DIPP87CL54X2BBD 18.0 LQFPP87C54X2BDH 14.2 TSSOPP87C58X2BN 18.7 DIPP87C54X2FBD 18.0 LQFPP89C58BP 21.0 PDIPP87C58X2BA 19.5 PLCCP89C58BA 22.0 PLCCP89C58X2FN 19.0 DIPOM4358BA 18.0 PLCCOM4368BN 17.0 DIPPHILIPS 80C51单片机型号零售封装型号零售封装38.0 PDIPP87C51RC+JA/N 35.0 LQFPP89C51RD+JA/NPDIPP89C60X2BP 23.0P87C51RD2BA 33.0PLCCPLCC24.0PLCCP89C61X2BAP89C60X2BA 23.0P89C51RD2HBP 40.0 PDIPP89C61X2BN 24.0 PDIPP89C51RD2HBA 40.0 PLCC40.0 LQFPP89C51RD2HBBDP89C51RD2BA39.0 PLCCP89C51RD2BN39.0 PDIPP89C51RD2FN42.0 PDIPP89C51RD2BBD39.0 LQFPP89LV51RD2BBD45.0 LQFPP89C51RD2FA 42.0 PLCC51.0P89C662HBBDLQFPPLCCP89C662HBA 51.055.0PLCCP89C668HBAPLCCP89C664HBA 55.0PLCCP89C669FA 52.0P89C668HFA 64.0PLCCPLCC50.0P80C552EFAP89C669BA 50.0PLCCPLCC50.0P87C591VFA 54.0P51XAG30KFAPLCCPLCCPXAG30KFA 50.0PHILIPS 外围器件I2C-bus器件型号零售封装型号零售封装5.7PCF8563TSODIPPCF8563P 7.512.5SOPCF8583TDIPPCF8583P 12.510.3VSOVSOPCF8576CTPCF8566T 9.48.3PCF8576DTSSOPSOPCF8574T 11.0PCA9554 10.4SOSAA1064T 17.5CAN-bus器件6.8SOPCA82C250TDIPPCA82C250 6.87.6PCA82C251TSO PCA82C251 7.6DIPTJA1040T 7.6 SOTJA1050T 6.3 SOTJA1054T 9.8 SOTJA1041T 9.5 SODIP AU5790D14 10.0 SJA1000 23.5TJA1020T 7.8 SO SJA1000T 23.5 SOUSB-bus 器件PDIUSBD12PW 15.5 TSSOP ISP1161A1BM 45.0 LQFP ISP1581BD 42.0 LQFPUSB-bus1.1分析仪 1800.0Mifare IC 卡及读卡模块Mifare IC 卡 10.0 RC500 65.0 ZLG500模块135.0电源器件MAX809L2.2 SOT MAX8102.2 SOTSA56600 5.5 SO MAX708 5.5 TSSOP/SO NE56604 7.5 SO NE56605 7.5 SO TEA1520P （2W ） 4.0 DIPTEA1520T （2W ） 4.0 SO TEA1521T （3W ） 4.5 SOTEA1522T （7W ） 5.0 SOCATALYST 半导体型号零售封装型号零售封装CSI24WC02J 1.8 SOIC CSI24WC02P 1.8 DIP CSI24WC02PI 2.3 SOIC CSI24WC04P 2.5 DIP CSI24WC08J 2.2 SOIC CSI24WC16P 3.2 DIP CSI24WC16J 2.8 SOIC CSI24WC64P 4.8 DIP CSI24WC256P21.0 DIP CSI24WC256PI 24.0 SOICCSI93C46P 1.7 DIP CSI93C46J 1.7 SOIC CSI1161-42 5.5 DIP CSI1161(工规) 6.3 SOHOLTEK 半导体型号零售封装型号零售封装HT46R22 6.5 SKDIP HT46R23 8.0 SKDIP HT46R47 4.8 DIP1 HT46R63 15.0 SKDIP/SOP HT47R20 9.6 QFPHT48R05A-1 3.5 DIP HT48RA0A 4.8 SOP HT48RA0A 5.0 SOP HT48R06A-1 3.6 DIP HT48R30A-1 5.8 SKDIP HT48R10A-1 5.3 DIP HT48R30A-1 6.4 SKDIP HT48R50A-1 7.3 SKDIP HT48R50A-1 8.0 SSOP HT48R70A-1 11.5 SSOP HT48R70A-1 12.3 QFPHT49R30A-1 8.0 SSOP HT49R50A-1 8.8 SSOP HT49R50A-1 11.0 SSOPHT70XXA 1.4 TO-92 HT70XXA 2.0 TO-89 HT71XX 1.4 TO-92 HT71XX 1.9 TO-89 HT13803.8DIPHT1620 (DIE)3.2QFPHT1621(Dice) 1.7 SSOP HT1621B 5.3 SSOP/PDIPHT1621D 5.3 Skinny HT82V731 2.0HT24LC02 1.7 HT9200A 2.0 DIP/SOP HT9170D 3.8 SOPZLG-MCU型号零售封装型号零售封装ZLG7289BP 7.7 DIP ZLG7289BS 7.7 SOIC ZLG7290AP 9.5 PDIP ZLG7290AS 9.5 SOMDT 单片机型号零售封装型号零售封装MDT2005EP 4.0 MDT2005ES 4.0 MDT2010EP 4.8 MDT2020BP 6.0 MDT2020BS 6.5MDT2051AP7.6DC-DC 电源模块型号零售型号零售型号零售B0505S-1W 25.0 D240505S-2W 45.0 B2405S-1W 30.0 IB0505LS-W75 36.0 D050505S-1W 40.0 IB2405LS-W75 40.0 D240505S-1W 40.0 PH2405S-01 70.0 D050505S-2W 45.0 PH2405D-03 120.0 B2415S-1W 30.0 D241515S-1W 43.0LCD 模块(成品)型号零售型号零售型号零售ZY886A(水表) 17.0 ZY886B （水表） 17.0ZY886C(气表)13.5 ZY886D(气表) 17.0ZY886E(水、气表)17.0 ZY1420A 21.0 ZY1420B20.0金卡产品型号零售型号零售RC500 读卡芯片 65 MUR-100 读卡器 (USB 通信) 390 mifare 1C 卡9.5 MSR-100 读卡器 (RS232通信) 390 ZLG500A/B 读卡模块(含V1.0天线) 135 MSR-260 读卡器 (兼容MFRD260) 450 ZLG500A 模块四层板天线(配套价) 25 ICCUR-100B 通用读卡器 280 ZLG500开发板 650 PAR-100韦根读卡器 280 Mifare 韦根读卡器230电子模块型号价格型号价格SM200-02无时钟IC 卡水表模块批发价50 SM200-02A 带时钟IC 卡水表模块批发价60电子指南针模块160CAN-bus系列产品型号零售型号零售CANalyst-II 双路CAN分析仪6900 CANalyst-I 单路CAN分析仪5500 CAN485智能CAN转换器980 CAN232智能CAN接口卡1200 USBCAN-II双路智能CAN接口卡2800 USBCAN-I单路智能CAN接口卡2500 PCI-5110单路智能CAN接口卡2500 PCI-5121双路智能CAN接口卡2800 PCI-9820双路非智能CAN接口卡1880 PCI-9810单路非智能CAN接口卡1500 CANrep-A智能全隔离CAN中继器1200 CANrep-B隔离CAN中继器600 CANstarter-I开发套件1460 CAN232B 智能CAN转换卡980 CANmini 微型CAN接口卡680 CANlite 便携式CAN接口卡780 ISA-5420 双路智能CAN接口卡2200 DB9-OPEN5转换座20 ISA-9620 双路非智能CAN接口卡1200开发工具—编程器与适配器型号零售型号零售EasyPRO 80 通用编程器980 LQFP48 适配器450 EasyPRO 100通用编程器1680 TSSOP20 适配器350 ExpertPRO I通用编程器2180 SOP20 适配器350 ExpertPRO II通用编程器2680 PLCC28 适配器100 CP76X 编程器350 TSSOP28 适配器200 CP76X 编程拷贝机800SOIC28 适配器350 CP9XX编程器350 TSSOP38 适配器450 ZLG-ISP 下载编程器240 SO16Z适配器75 ZY1420 语音编程器550Holtek OTP编程器550开发工具—仿真器型号零售型号零售TKS-52S 仿真器 (HOOKS技术) 1300 TKS-58B 仿真器 (HOOKS技术) 1600 TKS-61S 仿真器 (HOOKS技术) 1800 TKS-58 仿真器 (HOOKS技术) 1600 TKS-61 仿真器 (HOOKS技术) 2100 TKS-RD2S 仿真器 (HOOKS技术) 2100 TKS-591B 仿真器 (HOOKS技术) 3200 TKS-RD2 仿真器 (HOOKS技术) 2400 TKS-591S 仿真器 (HOOKS技术) 2800 TKS-668B 仿真器 (HOOKS技术) 2600 TKS-591 仿真器 (HOOKS技术) 3200 TKS-668S 仿真器 (HOOKS技术) 2400 TKS-764 仿真器1300 TKS-668 仿真器 (HOOKS技术) 2600 TKS-932 仿真器1300 KEIL C51软件(送TKS-52S) 14800 HT各系列仿真器1300 TB90X仿真头50 P87LPC759/60/61仿真适配器50 TKS-PLCCPOD 仿真适配器200积压库存产品(可以谈价)SE-52仿真器850 SE-52S仿真器900 SE-52P仿真器950 ME-52仿真器1000 SE-764仿真器1300 ME-52P仿真器1200 AE-52仿真器1600 MP-764编程器290AE-52E仿真器1500开发工具—开发板与实验仪型号零售型号零售DP-51H单片机数据通信综合仿真实验仪1380 DP-1581单片机与USB2.0仿真实验仪780DP-51+单片机仿真实验仪(配出版图书) 780 DP-MCU/Xilinx综合仿真实验仪(配出版图书)650DP-51S单片机仿真实验仪680 DP-MCU/Altera综合仿真实验仪(配出版图书)650 DP-51单片机仿真实验仪680DP-Xilinx下载开发实验仪480 DP-TEST单片机开发实验仪580 DP-Altera下载开发实验仪500 DP-932单片机仿真实验仪580 DP-668单片机与TCP/IP仿真实验仪780 DP-XC2S100 FPGA开发实验仪780 EasyARM2104开发套件(配出版图书) 400 PDIUSBD12 SMART USB开发板450 1602A液晶显示屏50.0 PDIUSBD12 大容量存贮器开发板680 A/D、D/A转换板130 ZY1420 DEMO板240 步进电机/伺服电机控制板180 I2C总线DEMO板240ZLG7289 DEMO板240。

P89LPC932中文资料

1.General descriptionThe P89LPC932A1is a single-chip microcontroller,available in low cost packages,based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC932A1 in order to reduce component count, board space, and system cost.2.Features2.1Principal featuress 8kB byte-erasable ﬂash code memory organized into 1kB sectors and 64-byte pages.Single-byte erasing allows any byte(s) to be used as non-volatile data storage.s 256-byte RAM data memory, 512-byte auxiliary on-chip RAM.s 512-byte customer data EEPROM on chip allows serialization of devices, storage of set-up parameters, etc.s Two analog comparators with selectable inputs and reference source.s Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer overﬂow or to become a PWM output)and a 23-bit system timer that can also be used as a RTC.s Enhanced UART with fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400kHz byte-wide I 2C-bus communication port and SPI communication port.s CCU provides PWM, input capture, and output compare functions.s High-accuracy internal RC oscillator option allows operation without external oscillator components. The RC oscillator option is selectable and ﬁne tunable.s 2.4V to 3.6V V DD operating range. I/O pins are 5V tolerant (may be pulled up or driven to 5.5V).s 28-pin TSSOP , PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26I/O pins while using on-chip oscillator and reset options.2.2Additional featuress A high performance 80C51 CPU provides instruction cycle times of 111ns to 222ns for all instructions except multiply and divide when executing at 18MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable ﬂash with 512-byte data EEPROMRev. 02 — 10 May 2005Product data sheets In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive applicationprograms.s Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted in the end application.s In-Application Programming(IAP)of theﬂash code memory.This allows changing the code in a running application.s Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight values.s Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt.s Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1µA (total power-down with voltage comparators disabled).s Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spuriousand incomplete resets. A software reset function is also available.s Conﬁgurable on-chip oscillator with frequency range options selected by user programmed ﬂash conﬁguration bits. Oscillator options support frequencies from20kHz to the maximum operating frequency of 18MHz.s Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.s Programmable port output conﬁguration options: quasi-bidirectional, open drain, push-pull, input-only.s Port ‘input pattern match’ detect. Port0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.s LED drive capability (20mA) on all port pins. A maximum limit is speciﬁed for the entire chip.s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns minimum ramp times.s Only power and ground connections are required to operate the P89LPC932A1 when internal reset option is selected.s Four interrupt priority levels.s Eight keypad interrupt inputs, plus two additional external interrupt inputs.s Schmitt trigger port inputs.s Second data pointer.s Emulation support.2.3Comparison to the P89LPC932The P89LPC932A1includes several improvements compared to the P89LPC932.Please see P89LPC932A1 User manual for additional detailed information.s Byte-erasability has been added to the user code memory space.s All of the errata described in the P89LPC932 Errata sheet have been ﬁxed.s Serial ICP has been added.s The RCCLK bit has been added to the TRIM register allowing the RCCLK to beselected as the CPU clock (CCLK) regardless of the settings in UCFG1, allowing the internal RC oscillator to be selected as the CPU clock without the need to reset the device.s Enhancements added to the ISP/IAP code to improve code safety and increase ISP/IAP functionality. This may require slight changes to original P89LPC932 code using IAP function calls. Some ISP/IAP settings are different than the originalP89LPC932.T ools designed to support the P89LPC932A1should be used to program this device, such as Flash Magic version 1.98, or later.3.Ordering information3.1Ordering optionsTable 1:Ordering informationType numberPackage NameDescriptionVersion P89LPC932A1FAPLCC28plastic leaded chip carrier; 28 leads SOT261-2P89LPC932A1FDH TSSOP28plastic thin shrink small outline package;28leads; body width 4.4mmSOT361-1P89LPC932A1FHN HVQFN28plastic thermal enhanced very thin quad ﬂat package; no leads; 28 terminals;body 6×6×0.85mmSOT788-1Table 2:Ordering optionsType number Flash memory Temperature range Frequency P89LPC932A1FA 8kB −40°C to +85°C 0 MHz to 18MHz P89LPC932A1FDH 8kB −40°C to +85°C 0 MHz to 18MHz P89LPC932A1FHN8kB−40°C to +85°C0 MHz to 18 MHz4.Block diagramFig 1.Block diagram.ACCELERATED 2-CLOCK 80C51 CPU8 kBCODE FLASH256-BYTEDAT A RAMPORT 2CONFIGURABLE I/OsPORT 1CONFIGURABLE I/OsPORT 0CONFIGURABLE I/OsKEYPADINTERRUPTPROGRAMMABLEOSCILLATOR DIVIDERCPUclockCONFIGURABLEOSCILLATORON-CHIPRCOSCILLATORinternalbusCRYST ALOR RESONATORPOWER MONITOR(POWER-ON RESET,BROWNOUT RESET)002aaa885UARTANALOGCOMPARATORS 512-BYTEAUXILIARY RAMI2C-BUS512-BYTEDAT A EEPROMPORT 3CONFIGURABLE I/OsCCU (CAPTURE/COMPARE UNIT)P89LPC932A1WATCHDOG TIMERAND OSCILLATORTIMER 0TIMER 1REAL-TIME CLOCK/SYSTEM TIMERSPIP3[1:0]P2[7:0]P1[7:0]P0[7:0]X1X2TXD RXDSCL SDASPICLK MISO MOSI SST0T1 CMP2 CIN2A CIN2B CMP1 CIN1A CIN1B OCA OCB OCC OCD ICA ICB5.Functional diagramFig 2.Functional diagram of P89LPC932A1.V DDV SSPORT 0PORT 3TXD RXD T0INT0INT1RST SCL SDA002aaa890CMP2CIN2B CIN2A CIN1B CIN1A CMPREF CMP1T1XT AL2XT AL1KBI0KBI1KBI2KBI3KBI4KBI5KBI6KBI7CLKOUTOCB OCC ICB OCD MOSI MISO SSSPICLK OCA ICAPORT 1PORT 2P89LPC932A16.Pinning information6.1PinningFig 3.P89LPC932A1 TSSOP28 pin conﬁguration.P89LPC932A1FDH002aaa88612345678910111213141615181720192221242326252827P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1P0.2/CIN2A/KBI2P0.3/CIN1B/KBI3P0.4/CIN1A/KBI4P0.5/CMPREF/KBI5V DDP0.6/CMP1/KBI6P0.7/T1/KBI7P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SSP2.0/ICB P2.1/OCDP0.0/CMP2/KBI0P1.7/OCC P1.6/OCB P1.5/RSTV SSP3.1/XTAL1P3.0/XTAL2/CLKOUTP1.4/INT1P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISOFig 4.P89LPC932A1 PLCC28 pin conﬁguration.Fig 5.P89LPC932A1 HVQFN28 pin conﬁguration.P89LPC932A1FA002aaa88756789101125242322212019121314151617184321282726P1.6/OCB P1.5/RSTV SSP3.1/XTAL1P3.0/XTAL2/CLKOUTP1.4/INT1P1.3/INT0/SDA P 1.7/O C CP 0.0/C M P 2/K B I 0P 2.1/O C D P 2.0/I C BP 2.7/I C AP 2.6/O C AP 0.1/C I N 2B /K B I 1P0.2/CIN2A/KBI2P0.3/CIN1B/KBI3P0.4/CIN1A/KBI4P0.5/CMPREF/KBI5V DDP0.6/CMP1/KBI6P0.7/T1/KBI7P 1.2/T 0/S C L P 2.2/M O S I P 2.3/M I S O P 2.4/S S P 2.5/S P I C L K P 1.1/R X D P 1.0/T X D 002aaa889P89LPC932A1FHNTransparent top view71561651741831922012189101112131428272625242322terminal 1index area P 1.7/O C CP 2.7/I C AP 2.1/O C DP 2.0/I C BP 0.0/C M P 2/K B I 0P 2.6/O C AP 0.1/C I N 2B /K B I 1P 2.4/S S P 2.2/M O S IP 2.3/M I S O P 1.2/T 0/S C LP 2.5/S P I C L K P 1.0/T X D P 1.1/R X D P1.4/INT1P1.3/INT0/SDAP3.0/XTAL2/CLKOUTP3.1/XTAL1V SS P1.5/RSTP1.6/OCB P0.6/CMP1/KBI6P0.7/T1/KBI7P0.5/CMPREF/KBI5V DDP0.4/CIN1A/KBI4P0.3/CIN1B/KBI3P0.2/CIN2A/KBI26.2Pin descriptionTable 3:Pin descriptionSymbol Pin Type DescriptionTSSOP28,PLCC28HVQFN28P0.0 to P0.7I/O Port0:Port0 is an 8-bit I/O port with a user-conﬁgurable output type.During reset Port0 latches are conﬁgured in the input only mode with theinternal pull-up disabled. The operation of Port0 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer to Section 7.13.1 “Port conﬁgurations”and Table 9 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt trigger inputs.Port0 also provides various special functions as described below:P0.0/CMP2/ KBI0327I/O P0.0 —Port0 bit0.O CMP2 —Comparator2 output.I KBI0 —Keyboard input0.P0.1/CIN2B/ KBI12622I/O P0.1 —Port0 bit1.I CIN2B —Comparator2 positive input B.I KBI1 —Keyboard input1.P0.2/CIN2A/ KBI22521I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input2.P0.3/CIN1B/ KBI32420I/O P0.3 —Port0 bit3.I CIN1B —Comparator1 positive input B.I KBI3 —Keyboard input3.P0.4/ CIN1A/ KBI42319I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input4.P0.5/ CMPREF/ KBI52218I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input5.P0.6/CMP1/ KBI62016I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input6.P0.7/T1/KBI71915I/O P0.7 —Port0 bit7.I/O T1 —Timer/counter1 external count input or overﬂow output.I KBI7 —Keyboard input7.P1.0 to P1.7I/O,I [1]Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type,except for three pins as noted below. During reset Port 1 latches areconﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 7.13.1 “Portconﬁgurations” and T able 9 “Static characteristics” for details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is input only.All pins have Schmitt trigger inputs.Port 1 also provides various special functions as described below:P1.0/TXD 1814I/O P1.0 —Port 1 bit 0.O TXD —Transmitter output for the serial port.P1.1/RXD 1713I/O P1.1 —Port 1 bit 1.I RXD —Receiver input for the serial port.P1.2/T0/SCL128I/O P1.2 —Port 1 bit 2 (open-drain when used as output).I/O T0 —Timer/counter 0 external count input or overﬂow output (open-drain when used as output).I/OSCL —I 2C serial clock input/output.P1.3/INT0/SDA117I/O P1.3 —Port 1 bit 3 (open-drain when used as output).I INT0 —External interrupt 0 input.I/OSDA —I 2C serial data input/output.P1.4/INT1106I P1.4 —Port 1 bit 4.I INT1 —External interrupt 1 input.P1.5/RST62I P1.5 —Port 1 bit 5 (input only).IRST —External Reset input during power-on or if selected via UCFG1.When functioning as a reset input, a LOW on this pin resets themicrocontroller, causing I/O ports and peripherals to take on their default states,and the processor begins execution at address 0.Also used during a power-on sequence to force ISP mode.When using an oscillator frequency above 12MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V DD has reached its speciﬁed level. When system power is removed V DD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above12MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V DD falls below the minimum speciﬁed operating voltage.P1.6/OCB 51I/O P1.6 —Port 1 bit 6.O OCB —Output Compare B.P1.7/OCC428I/O P1.7 —Port 1 bit 7.OOCC —Output Compare C.Table 3:Pin description …continuedSymbolPinType DescriptionTSSOP28,PLCC28HVQFN28P2.0 to P2.7I/O Port2: Port2 is an 8-bit I/O port with a user-conﬁgurable output type.During reset Port2 latches are conﬁgured in the input only mode with theinternal pull-up disabled. The operation of Port2 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer to Section 7.13.1 “Port conﬁgurations”and Table 9 “Static characteristics” for details.All pins have Schmitt trigger inputs.Port2 also provides various special functions as described below:P2.0/ICB125I/O P2.0 —Port2 bit0.I ICB —Input Capture B.P2.1/OCD226I/O P2.1 —Port2 bit1.O OCD —Output Compare D.P2.2/MOSI139I/O P2.2 —Port2 bit2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin isoutput; when conﬁgured as slave, this pin is input.P2.3/MISO1410I/O P2.3 —Port2 bit3.I/O MISO —When conﬁgured as master,this pin is input,when conﬁgured asslave, this pin is output.P2.4/SS1511I/O P2.4 —Port2 bit4.I SS —SPI Slave select.P2.5/SPICLK1612I/O P2.5 —Port2 bit5.I/O SPICLK —SPI clock.When conﬁgured as master,this pin is output;whenconﬁgured as slave, this pin is input.P2.6/OCA2723I/O P2.6 —Port2 bit6.O OCA —Output Compare A.P2.7/ICA2824I/O P2.7 —Port2 bit7.I ICA —Input Capture A.P3.0 to P3.1I/O Port3: Port3 is a 2-bit I/O port with a user-conﬁgurable output type.During reset Port3 latches are conﬁgured in the input only mode with theinternal pull-up disabled. The operation of Port3 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer to Section 7.13.1 “Port conﬁgurations”and Table 9 “Static characteristics” for details.All pins have Schmitt trigger inputs.Port3 also provides various special functions as described below:P3.0/XT AL2/ CLKOUT 95I/O P3.0 —Port3 bit0.O XTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillatoroption is selected via the ﬂash conﬁguration.O CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator,watchdog oscillator or external clock input,except when XTAL1/XT AL2areused to generate clock source for the RTC/system timer.Table 3:Pin description …continuedSymbol Pin Type DescriptionTSSOP28,PLCC28HVQFN28[1]Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.P3.1/XT AL184I/OP3.1 —Port 3 bit 1.I XTAL1 —Input to the oscillator circuit and internal clock generator circuits(when selected via the ﬂash conﬁguration). It can be a port pin if internalRC oscillator or watchdog oscillator is used as the CPU clock source,andif XTAL1/XTAL2 are not used to generate the clock for the RTC/systemtimer.V SS 73I Ground: 0V reference.V DD2117I Power supply: This is the power supply voltage for normal operation aswell as Idle and Power-down modes.Table 3:Pin description …continued Symbol PinType DescriptionTSSOP28,PLCC28HVQFN287.Functional descriptionRemark:Please refer to the P89LPC932A1 User manual for a more detailed functionaldescription.7.1Special function registersRemark:Special Function Registers (SFRs) accesses are restricted in the followingways:•User must not attempt to access any SFR locations not deﬁned.•Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.•SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:–‘-’ Unless otherwise speciﬁed,must be written with logic 0, but can return anyvalue when read(even if it was written with logic0).It is a reserved bit and may beused in future derivatives.–Logic 0must be written with logic 0, and will return a logic 0 when read.–Logic 1must be written with logic 1, and will return a logic 1 when read.9397 750 14871© Koninklijke Philips Electronics N.V . 2005. All rights reserved.Product data sheet Rev. 02 — 10 May 200513 of 64Philips Semiconductors P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 coreTable 4:Special function registers* indicates SFRs that are bit Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex BinaryBit address E7E6E5E4E3E2E1E0ACC*Accumulator E0H 0000000000AUXR1Auxiliary function register A2H CLKLP EBRR ENT1ENT0SRST 0-DPS 00000000x0Bit address F7F6F5F4F3F2F1F0B* B register F0H 0000000000BRGR0Baud rate generator rate low BEH 00[1]00000000BRGR1Baud rate generator rate high BFH 00[1]00000000BRGCON Baud rate generator control BDH ------SBRGS BRGEN 00[1]xxxx xx00CCCRA Capture compare A control registerEAH ICECA2ICECA1ICECA0ICESA ICNFA FCOA OCMA1OCMA00000000000CCCRB Capture compare B control registerEBH ICECB2ICECB1ICECB0ICESB ICNFB FCOB OCMB1OCMB00000000000CCCRC Capture compare C control registerECH -----FCOC OCMC1OCMC000xxxx x000CCCRD Capture compare D control registerEDH -----FCOD OCMD1OCMD000xxxx x000CMP1Comparator 1 control register ACH --CE1CP1CN1OE1CO1CMF100[2]xx000000CMP2Comparator 2 control register ADH --CE2CP2CN2OE2CO2CMF200[2]xx000000DEECON Data EEPROM control registerF1H EEIF HVERR ECTL1ECTL0---EADR80E 00001110DEEDA T Data EEPROM data register F2H 0000000000DEEADR Data EEPROM address registerF3H 0000000000DIVM CPU clock divide-by-M control95H 0000000000DPTR Data pointer (2bytes)DPH Data pointer high 83H 0000000000DPL Data pointer low 82H 0000000000I2ADR I 2C slave address register DBH I2ADR.6I2ADR.5I2ADR.4I2ADR.3I2ADR.2I2ADR.1I2ADR.0GC 0000000000Bit address DF DE DD DC DB DA D9D8I2CON*I 2C control register D8H -I2EN STA STO SI AA -CRSEL 00x00000x09397 750 14871© Koninklijke Philips Electronics N.V . 2005. All rights reserved.Product data sheet Rev. 02 — 10 May 200514 of 64Philips Semiconductors P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 core I2DA T I 2C data register DAHI2SCLH Serial clock generator/SCL duty cycle register highDDH 0000000000I2SCLL Serial clock generator/SCL duty cycle register lowDCH 0000000000I2ST AT I 2C status register D9H STA.4STA.3ST A.2STA.1STA.0000F811111000ICRAH Input capture A register high ABH 0000000000ICRAL Input capture A register low AAH 0000000000ICRBH Input capture B register high AFH 0000000000ICRBL Input capture B register low AEH 0000000000Bit address AF AE AD AC AB AA A9A8IEN0*Interrupt enable 0A8H EA EWDRT EBO ES/ESR ET1EX1ET0EX00000000000Bit address EF EE ED EC EB EA E9E8IEN1*Interrupt enable 1E8H EIEE EST -ECCU ESPI EC EKBI EI2C 00[2]00x00000Bit address BF BE BD BC BB BA B9B8IP0*Interrupt priority 0B8H -PWDRT PBO PS/PSR PT1PX1PT0PX000[2]x0000000IP0H Interrupt priority 0 high B7H -PWDRT H PBOH PSH/PSRHPT1H PX1H PT0H PX0H 00[2]x0000000Bit address FF FE FD FC FB FA F9F8IP1*Interrupt priority 1F8H PIEE PST -PCCU PSPI PC PKBI PI2C 00[2]00x00000IP1H Interrupt priority 1 high F7H PIEEH PSTH -PCCUH PSPIH PCH PKBIH PI2CH 00[2]00x00000KBCON Keypad control register 94H ------P A TN _SELKBIF 00[2]xxxx xx00KBMASK Keypad interrupt mask register86H 0000000000KBP ATN Keypad pattern register 93H FF 11111111OCRAH Output compare A register highEFH 0000000000OCRAL Output compare A register low EEH 0000000000Table 4:Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary9397 750 14871© Koninklijke Philips Electronics N.V . 2005. All rights reserved.Product data sheet Rev. 02 — 10 May 200515 of 64Philips Semiconductors P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 core OCRBH Output compare B register highFBH 0000000000OCRBL Output compare B register lowFAH 0000000000OCRCH Output compare C register highFDH 0000000000OCRCL Output compare C register lowFCH 0000000000OCRDH Output compare D register highFFH 0000000000OCRDL Output compare D register lowFEH 0000000000Bit address 8786858483828180P0*Port 080H T1/KB7CMP1/KB6CMPREF /KB5CIN1A /KB4CIN1B /KB3CIN2A /KB2CIN2B /KB1CMP2/KB0[2]Bit address 9796959493929190P1*Port 190H OCC OCB RST INT1INT0/SDAT0/SCL RXD TXD [2]Bit address 9796959493929190P2*Port 2A0H ICA OCA SPICLK SS MISO MOSI OCD ICB [2]Bit address B7B6B5B4B3B2B1B0P3*Port 3B0H ------XTAL1XT AL2[2]P0M1Port 0 output mode 184H (P0M1.7)(P0M1.6)(P0M1.5)(P0M1.4)(P0M1.3)(P0M1.2)(P0M1.1)(P0M1.0)FF [2]11111111P0M2Port 0 output mode 285H (P0M2.7)(P0M2.6)(P0M2.5)(P0M2.4)(P0M2.3)(P0M2.2)(P0M2.1)(P0M2.0)00[2]00000000P1M1Port 1 output mode 191H (P1M1.7)(P1M1.6)-(P1M1.4)(P1M1.3)(P1M1.2)(P1M1.1)(P1M1.0)D3[2]11x1xx11P1M2Port 1 output mode 292H (P1M2.7)(P1M2.6)-(P1M2.4)(P1M2.3)(P1M2.2)(P1M2.1)(P1M2.0)00[2]00x0xx00P2M1Port 2 output mode 1A4H (P2M1.7)(P2M1.6)(P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)(P2M1.1)(P2M1.0)FF [2]11111111P2M2Port 2 output mode 2A5H (P2M2.7)(P2M2.6)(P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)(P2M2.1)(P2M2.0)00[2]00000000P3M1Port 3 output mode 1B1H ------(P3M1.1)(P3M1.0)03[2]xxxx xx11P3M2Port 3 output mode 2B2H ------(P3M2.1)(P3M2.0)00[2]xxxx xx00PCON Power control register 87H SMOD1SMOD0BOPD BOI GF1GF0PMOD1PMOD00000000000Table 4:Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary9397 750 14871© Koninklijke Philips Electronics N.V . 2005. All rights reserved.Product data sheet Rev. 02 — 10 May 200516 of 64Philips Semiconductors P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 core PCONA Power control register A B5H RTCPD DEEPD VCPD -I2PD SPPD SPD CCUPD 00[2]00000000Bit address D7D6D5D4D3D2D1D0PSW*Program status word D0H CY AC F0RS1RS0OV F1P 0000000000PT0AD Port 0 digital input disable F6H --PT0AD.5PT0AD.4PT0AD.3PT0AD.2PT0AD.1-00xx00000x RSTSRC Reset source register DFH --BOF POF R_BK R_WD R_SF R_EX [3]RTCCON Real-time clock control D1H RTCF RTCS1RTCS0---ERTC RTCEN 60[2][4]011x xx00RTCH Real-time clock register high D2H 00[4]00000000RTCL Real-time clock register low D3H 00[4]00000000SADDR Serial port address register A9H 0000000000SADEN Serial port address enable B9H 0000000000SBUF Serial Port data buffer register99H xx xxxx xxxxBit address 9F 9E 9D 9C 9B 9A 9998SCON*Serial port control 98H SM0/FE SM1SM2REN TB8RB8TI RI 0000000000SSTA T Serial port extended status registerBAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 0000000000SP Stack pointer 81H 0700000111SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1SPR00400000100SPST AT SPI status register E1H SPIF WCOL ------0000xx xxxx SPDA T SPI data register E3H 0000000000T AMOD Timer 0 and 1 auxiliary mode 8FH ---T1M2---T0M200xxx0xxx0Bit address 8F 8E 8D 8C 8B 8A 8988TCON*Timer 0 and 1 control 88H TF1TR1TF0TR0IE1IT1IE0IT00000000000TCR20*CCU control register 0C8H PLEEN HLTRN HLTEN ALTCD ALT AB TDIR2TMOD21TMOD200000000000TCR21CCU control register 1F9H TCOU2---PLLDV .3PLLDV .2PLLDV .1PLLDV .0000xxx 0000TH0Timer 0 high 8CH 0000000000TH1Timer 1 high 8DH 0000000000TH2CCU timer high CDH 0000000000TICR2CCU interrupt control register C9H TOIE2TOCIE2D TOCIE2C TOCIE2B TOCIE2A -TICIE2B TICIE2A 0000000x00TIFR2CCU interrupt ﬂag register E9H TOIF2TOCF2D TOCF2C TOCF2B TOCF2A -TICF2B TICF2A 0000000x00Table 4:Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary9397 750 14871© Koninklijke Philips Electronics N.V . 2005. All rights reserved.Product data sheet Rev. 02 — 10 May 200517 of 64Philips Semiconductors P89LPC932A18-bit microcontroller with accelerated two-clock 80C51 core[1]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN =1, the result is unpredictable.[2]All ports are in input only (high-impedance) state after power-up.[3]The RSTSRC register reﬂects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value isxx110000.[4]The only reset source that affects these SFRs is power-on reset.[5]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.[6]After reset,the value is 111001x1,i.e.,PRE2to PRE0are all logic 1,WDRUN =1and WDCLK =1.WDTOF bit is logic 1after watchdog reset and is logic 0after power-on reset.Other resets will not affect WDTOF .TISE2CCU interrupt status encode register DEH -----ENCINT .2ENCINT .1ENCINT .000xxxx x000TL0Timer 0 low 8AH 0000000000TL1Timer 1 low 8BH 0000000000TL2CCU timer low CCH 0000000000TMOD Timer 0 and 1 mode 89H T1GA TE T1C/T T1M1T1M0T0GA TE T0C/T T0M1T0M00000000000TOR2H CCU reload register high CFH 0000000000TOR2L CCU reload register low CEH 0000000000TPCR2H Prescaler control register high CBH ------TPCR2H.1TPCR2H.000xxxx xx00TPCR2L Prescaler control register low CAH TPCR2L.7TPCR2L.6TPCR2L.5TPCR2L.4TPCR2L.3TPCR2L.2TPCR2L.1TPCR2L.00000000000TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5TRIM.4TRIM.3TRIM.2TRIM.1TRIM.0[5][4]WDCON Watchdog control register A7H PRE2PRE1PRE0--WDRUN WDTOF WDCLK [6][4]WDL Watchdog load C1H FF 11111111WFEED1Watchdog feed 1C2HWFEED2Watchdog feed 2C3HTable 4:Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary7.2Enhanced CPUThe P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and mostinstructions execute in one or two machine cycles.7.3Clocks7.3.1Clock deﬁnitionsThe P89LPC932A1 device has several internal clocks as deﬁned below:OSCCLK —Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure6) and can also be optionally divided to a slower frequency (seeSection 7.8 “CCLK modiﬁcation: DIVM register”).Note: f osc is deﬁned as the OSCCLK frequency.CCLK —CPU clock;output of the clock divider.There are two CCLK cycles per machine cycle,and most instructions are executed in one to two machine cycles(two or four CCLK cycles).RCCLK —The internal 7.373MHz RC oscillator output.PCLK —Clock for the various peripheral devices and is CCLK⁄2.7.3.2CPU clock (OSCCLK)The P89LPC932A1 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowestpossible cost.These options are conﬁgured when theﬂash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an externalcrystal, or an external clock source. The crystal oscillator can be optimized for low,medium, or high frequency crystals covering a range from 20kHz to 18MHz.7.3.3Low speed oscillator optionThis option supports an external crystal in the range of 20kHz to 100kHz. Ceramicresonators are also supported in this conﬁguration.7.3.4Medium speed oscillator optionThis option supports an external crystal in the range of 100kHz to 4MHz. Ceramicresonators are also supported in this conﬁguration.7.3.5High speed oscillator optionThis option supports an external crystal in the range of 4MHz to 18MHz. Ceramicresonators are also supported in this conﬁguration.7.3.6Clock outputThe P89LPC932A1 supports a user-selectable clock output function on theXT AL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs ifanother clock source has been selected (on-chip RC oscillator, watchdog oscillator,external clock input on X1) and if the RTC is not using the crystal oscillator as its clocksource. This allows external devices to synchronize to the P89LPC932A1. This output is enabled by the ENCLK bit in the TRIM register.。

LPC900_ICP_Spec_en

PhilipsTable of ContentsPin Configurations (3)Pin Descriptions (12)Device ID bytes (13)Programming mode (14)Getting into the serial programming mode (14)Programming commands (15)Checking status information (16)Flash operating sequences (17)Loading the full Page Register (17)Loading the Page Register partially (18)Programming User Code Memory (19)Erasing all sectors (global erase) (20)Erasing a single sector (21)Erasing a single page (22)Calculate Global CRC (23)Calculate Sector CRC (24)Reading Configuration, Boot Vector, Status Byte, Security Bits, Signature Bytes (25)Writing Configuration, Boot Vector, Status Byte, and Security Bits (27)Writing CCP Clear Configuration Protection (28)Calculating CRC (29)AC timings (30)Getting into the serial programming mode (30)Timing data shifting (31)Revision History (32)1.0 Pin Configurations8-Pin PackagesFigure 1: P89LPC901 pinoutFigure 2: P89LPC902 pinoutFigure 3: P89LPC903 pinoutFigure 4: P89LPC904 pinoutCLKOUT/XTAL2/P3.012348765RST /P1.5VSSVDDXTAL1/P3.1P1.2/T0P0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P89LPC90112348765RST /P1.5VSSVDDP0.2/CIN2A/KBI2P0.0/CMP2/KBI0P0.6/CMP1/KBI6P0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/P DA P89LPC902P1.1/RxD 12348765RST /P1.5VSSVDDP0.2/CIN2A/KBI2P1.0/TXDP0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P89LPC903P1.1/RxD 12348765RST /P1.5VSSVDDP0.2/CIN2A/KBI2P1.0/TXDP0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P89LPC904Figure 5: P89LPC906 pinoutFigure 6: P89LPC907 pinoutFigure 7: P89LPC908 pinoutCLKOUT/XTAL2/P3.012348765VSSVDDXTAL1/P3.1P0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P89LPC906P0.6/CMP1/KBI6RST /P1.512348765RST /P1.5VSSVDD P0.6/CMP1/KBI6P0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/P DA P89LPC907P1.2/T0P1.0/TxD12348765RST /P1.5VSSVDD P1.0/TXDP0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P89LPC908P0.6/CMP1/KBI6P1.1/RxD10-Pin PackagesFigure 8: P89LPC9102 pinoutFigure 9: P89LPC9103 pinoutFigure 10: P89LPC9107 pinout123410987VSSP0.3/CIN1B/AD12P0.2/KBI2/AD11RST /P1.5KBI1/AD10/P0.1VDDP0.4/CIN1A/DAC1/PDA P0.5/CMPREF/KBI5/PCL 56P1.2/T0P0.7/T1/CLKOUTP89LPC9102123410987VSSP0.3/CIN1B/AD12P0.2/KBI2/AD11RST /P1.5KBI1/AD10/P0.1VDDP0.4/CIN1A/DAC1/PDA P0.5/CMPREF/CLKIN/PCL 56P1.0/TXDP0.7/T1/CLKOUTP89LPC9103123414131211RST /P1.5P0.3/CIN1B/AD12P0.2/KBI2/AD11NC VSS P0.5/CMPREF/KBI5/PCL NCP0.4/CIN1A/KBI4/PDA 5610798P1.2/T0P1.2/T0P1.1/RXD P0.7/T1/CLKOUTVDD P89LPC9107P1.0/TXDFigure 11: P89LPC912 pinoutFigure 12: P89LPC913 pinoutFigure 13: P89LPC914 pinout123414131211RST /P1.5P2.3/MISO P2.2/MOSI SPICLK/P2.5VSSP0.5/CMPREF/KBI5/PCL P0.2/CIN2A/KBI2P0.4/CIN1A/KBI4/PDA 5610798P0.6/CMP1/KBI6XTAL1/P3.1P2.4/SSCLKOUT/XTAL2/P3.0VDD P89LPC912P1.2/T0123414131211RST /P1.5P2.3/MISO P2.2/MOSI SPICLK/P2.5VSSP0.5/CMPREF/KBI5/PCL P0.2/CIN2A/KBI2P0.4/CIN1A/KBI4/PDA 5610798P0.6/CMP1/KBI6XTAL1/P3.1P1.0/TXDCLKOUT/XTAL2/P3.0VDD P1.1/RXD P89LPC913123414131211RST /P1.5P2.3/MISO P2.2/MOSI SPICLK/P2.5VSSP0.5/CMPREF/KBI5/PCL P0.2/CIN2A/KBI2P0.4/CIN1A/KBI4/PDA 5610798P0.6/CMP1/KBI6P1.2/T0P1.0/TXD P2.4/SSVDD P1.1/RXD P89LPC914Figure 14: P89LPC915 pinout16-Pin PackagesFigure 15: P89LPC916 pinoutFigure 16: P89LPC917 pinout123414131211RST /P1.5CIN2B/KBI1/AD10/P0.1VSS P0.5/CMPREF/KBI5/CLKIN/PCL P0.2/CIN2A/KBI2/AD11P0.4/CIN1A/KBI4/AD13/DAC1/PDA 5610798INT1/P1.4SCL/TO/P1.2P1.0/TXD VDD P89LPC915KBI0/CMP2/P0.0P0.3/CIN2B/KBI3/AD12P1.1/RXDSDA/INT0/P1.2P89LPC916123416151413RST /P1.5CIN2B/KBI1/AD10/P0.1VSS P0.5/CMPREF/KBI5/CLKIN/PCL P0.2/CIN2A/KBI2/AD11P0.4/CIN1A/KBI4/AD13/DAC1/PDA 561271110MISO/P2.3SCL/TO/P1.2P1.0/TXD VDD KBI0/CMP2/P0.0P0.3/CIN2B/KBI3/AD12P1.1/RXDSDA/INT0/P1.289MOSI/P2.2P2.5/SPICLK P89LPC917123416151413RST /P1.5CIN2B/KBI1/AD10/P0.1VSS P0.5/CMPREF/KBI5/CLKIN/PCL P0.2/CIN2A/KBI2/AD11P0.4/CIN1A/KBI4/AD13/DAC1/PDA 561271110MISO/P2.3SCL/TO/P1.2P1.0/TXD VDDKBI0/CMP2/P0.0P0.3/CIN2B/KBI3/AD12P1.1/RXDSDA/INT0/P1.289MOSI/P2.2P0.7/T1/KBI7/CLKOUT20-Pin PackagesFigure 17: P89LPC922/921/920/924/925 pinout28-Pin PackagesFigure 18: P89LPC930/931/932A1*Only on the LPC932A11234567891020191817161514131211SCL/T0/P1.2SDA/INT0/P1.3INT1/P1.4RST/P1.5VDDVSSXTAL1/P3.1CLKOUT/XTAL2/P3.0P1.6P1.7P1.1/RXDP1.0/TXD P0.7/T1/KBI7P0.6/CMP1/KBI6P0.5/CMPREF/KBI5/PCL P0.4/CIN1A/KBI4/PDA P0.3/CIN1B/KBI3P0.2/CIN2A/KBI2P0.1/CIN2B/KBI1KBI0/CMP2/P0.0P89LPC922/921/920/924/925P89LPC930/931/932A112345678910111213142827262524232221201918171615SCL/T0/P1.2SDA/INT0/P1.3ICB*/P2.0OCD*/P2.1INT1/P1.4RST/P1.5VDDVSSXTAL1/P3.1CLKOUT/XTAL2/P3.0MOSI/P2.2MISO/P2.3OCB*/P1.6OCC*/P1.7P1.1/RXD P1.0/TXD P2.7/ICA*P2.6/OCA*P0.7/T1/KBI7P0.6/CMP1/KBI6P0.5/CMPREF/KBI5P0.4/CIN1A/KBI4P0.3/CIN1B/KBI3P0.2/CIN2A/KBI2P2.5/SPICLK P2.4/SSP0.1/CIN2B/KBI1KBI0/CMP2/P0.0Figure 19: P89LPC933/934/935/936/938 pinout*Only on the LPC93512345678910111213142827262524232221201918171615SCL/T0/P1.2SDA/INT0/P1.3AD03*/DAC0/ICB*/P2.0AD02*/OCD*/P2.1INT1/P1.4RST/P1.5VDDVSSXTAL1/P3.1CLKOUT/XTAL2/P3.0MOSI/P2.2MISO/P2.3OCB*/P1.6AD00*/OCC*/P1.7P1.1/RXD P1.0/TXD P2.7/ICA*P2.6/OCA*P0.7/T1/KBI7P0.6/CMP1/KBI6P0.5/CMPREF/KBI5P0.4/CIN1A/KBI4/DAC1/AD13P0.3/CIN1B/KBI3/AD12P0.2/CIN2A/KBI2/AD11P2.5/SPICLK P2.4/SSP0.1/CIN2B/KBI1/AD10AD01*/KBI0/CMP2/P0.0P89LPC933/934/935/936/938Figure 20: P89LPC952 LQFP48 pinout4546474812345671314154443423635343332313019181716SCL/T0/P1.2SDA/INT0/P1.3P 2.1/A D 06P 1.4/I N T 1P 1.5/R S TVDD VDD XTAL1/P3.1P3.0/XTAL2/CLKOUTP2.2/MOSI P2.3/MISO P 1.7/A D 04P1.1/RXD P1.0/TXD P0.7/T1/KBI7P0.6/CMP1/KBI6P0.5/CMPREF/KBI5P 0.3/C I N 1B /K B I 3/A D 02P 0.2/C I N 2A /K B I 2/A D 01 P2.5/SPICLK P2.4/SS P 0.1/C I N 2B /K B I 1/A D 00P 0.0/C M P 2/K B I 0/A D 0540413938372021222423891011122928272625P2.6P 4.1/T R I GP 4.3/R x D 1P 4.4/T D OP 4.5/T D IP 4.2/T x D 1P 4.7/T C KA V S SP 1.6V S SP5.7P5.6P5.4P 5.1P 5.0P 5.3P2.7/ICA P 2.0/A D 07AVDD P4.0V S SP 4.6/T M SP5.5P0.4/CIN1A/KBI4/AD03P 5.2P89LPC95xFigure 21: P89LPC952 PLCC44 pinout34567891011121318192021443938373635343324232221SCL/T0/P1.2SDA/INT0/P1.3P 2.1/A D 06P 1.4/I N T 1P 1.5/R S TAVDD VDD XTAL1/P3.1P3.0/XTAL2/CLKOUTP2.2/MOSI P2.3/MISO P 1.7/A D 04P1.1/RXD P1.0/TXD P0.7/T1/KBI7P0.6/CMP1/KBI6P0.5/CMPREF/KBI5P 0.3/C I N 1B /K B I 3/A D 02P 0.2/C I N 2A /K B I 2/A D 01 P2.5/SPICLK P2.4/SS P 0.1/C I N 2B /K B I 1/A D 00P 0.0/C M P 2/K B I 0/A D 0542434140252627281415161732313029P4.1/TRIGP 4.3/R x D 1P 4.4/T D OP 4.5/T D IP 4.2/T x D 1P 4.7/T C KP 1.6V S SP5.7/T3P5.6P5.4P 5.1P 5.0P 5.3P 2.0/A D 07P4.0/T3EX A V S SP 4.6/T M SP5.5P0.4/CIN1A/KBI4/AD03P 5.2P89LPC95x1.1 Pin DescriptionsMNEMONIC TYPE NAME AND FUNCTIONV SS P Ground: 0V reference.V DD P Power Supply: 3VPCL I Serial clock input for programming communication.PDA I/O Serial data I/O for programming communication.RESET I ICP programming entry pinTable 1: Programming pins used for ICP1.2 Device ID bytesDevice MFGID ID1ID2 P89LPC90115h DD0Dh P89LPC90215h DD0Fh P89LPC90315h DD10h P89LPC90415h DD21h P89LPC90615h DD11h P89LPC90715h DD12h P89LPC90815h DD13h P89LPC910215h DD22h P89LPC910315h DD23h P89LPC910715h DD27h P89LPC91215h DD14h P89LPC91315h DD15h P89LPC91415h DD16h P89LPC91515h DD17h P89LPC91615h DD18h P89LPC91715h DD20h P89LPC92015h DD1Ah P89LPC92115h DD0Bh P89LPC92215h DD0Ch P89LPC92415h DD1Bh P89LPC92515h DD1Ch P89LPC93015h DD19h P89LPC93115h DD09h P89LPC932A115h DD1Fh P89LPC93315h DD A0h P89LPC93415h DD1Dh P89LPC93515h DD1Eh P89LPC93615h DD24h P89LPC93815h DD25h P89LPC95215h DD28hTable 2: ID bytes for different devices2.0 Programming modeThe programming commands are sent by the programmer through the PCL and PDA lines.Each programming command is one byte shifted into the part by 8 clocks. The serial interface is identical to the 51’s 8-bit serial UART mode 0; LSB is the first bit in the serial byte. The PCL pin is the clock input from the programmer. The PDA pin is the data I/O. The Data is enabled on the falling edge of PCL, and is clocked on the rising edge of PCL. Data output from the part is disabled after the rising edge of PCL for the last bit in a data byte. Writing programming commands by the programmer Commands.When the P89LPC90x is in programming mode all pins that are not used for programming are tri-stated. During programming mode the reset pin has a weak pull-up resistor.2.1 Getting into the serial programming modeTo get in programming mode the RESET pin has to have a sequence of 7 pulses after the rising edge of VDD.The timing requirements have to be met to get into programming mode, otherwise the P89LPC9xx will run in nor-mal user mode. See AC specifications (section 5) for timings .Figure 22: Getting into the programming modePDA PCLV DDRESETXSerial communication2.2 Programming commandsProgramming operations can be done by shifting in commands and data in sequence. The following table shows the commands that can be used.Table 3: Programming commandsWhen the WR_FMCON command has been sent the FM_CON (Flash control register) can be loaded with the fol-lowing commands:Table 4: FMCON Write commandsCOMMANDS OPCODE FUNCTIONNOP00H NOPWR_FMADRL 08H Write address low command RD_FMADRL 09H Read address low command WR_FMADRH 0AH Write address high command RD_FMADRH 0BH Read address high command WR_FMCON 0EH Write a command to FMCON RD_FMCON0FH Read a command from FMCONWR_FMDATA_PG 14H Write a command to FMDATA and increment address RD_FMDATA_PG 15H Read a command from FMDATA and increment address WR_FMDATA 0CH Write a command to FMDATA RD_FMDATA 0DH Read a command from FMDATAWR_FMDATA_I 04H Write a command to FMDATA and increment address RD_FMDATA_I05HRead a command from FMDATA and increment addressFMCON Write COMMANDS Command CODE FUNCTIONLOAD 00H Clear and then load the page registerPROG 48H Program page with page register command ERS_G 72H Erase global command ERS_S 71H Erase sector command ERS_P 70H Erase page commandCONF 6CH Accesses user configuration information addressed by FMADRL CRC_G 1AH Calculate CRC on the entire user code command CRC_S 19H Calculate CRC on a sector command CCP67HClear configuration protection3.0 Checking status informationFMCON contains status information when the RD_FMCON command is used to read FMCON, and is updated by the last operation performed. FMCON contains the following bits:0OI Operation aborted by an interrupt.1SV Security Violation. Set if operation fails due to security violation.2HVE High Voltage Error. Set if error detected in high voltage generation cirrhosed.3HVA High Voltage Abort.Set if high volt. aborted due to bandgap/ brownout problems.4---unused5---unused6---unused7BUSY Set while a program, erase, or other programming operation is in progress.The Unused bits will read out as ‘1’s. When no errors occur FMCON will read out F0h when still busy preforming an operation and 70h when an operation has successfully completed.4.0 Flash operating sequences4.1 Loading the full Page RegisterThe page register is loaded by performing the following sequence:1.Activate the ICP Programming Mode, as previously described, if not already performed.2.Shift in the WR_FMCON opcode.3.Shift in 00h, the LOAD command to FMCON.4.Shift in 08h, WR_FMADRL opcode.5.Shift in X0 to FMADRL. This sets the destination of the first data byte to be loaded as the beginning of the page.6.Shift in the 14h, WRFMDATA_PG opcode.7.Shift in X bytes of data to be loaded into the page register. FMADRL is incremented after each byte. After the last byteFMADRL rolls over to point to the beginning of the page. *Note: LPC92x / LPC93x have 64 byte page registers, LPC91x / LPC90x have 16 byte page registers.Example of a sequence loading the Page register when in programming mode: Figure 23: loading page registerStartX DATA bytes shifted in?YesDoneLOADING PAGE REGISTERWR_FMCONLOADDATA (0x00)WR_FMADRLWR_FMDATA_PGNoDATA N4.2 Loading the Page Register partiallyThe page register is loaded by performing the following sequence:1.Activate the ICP Programming Mode, as previously described, if not already performed.2.Shift in the WR_FMCON opcode.3.Shift in 00h, the LOAD command to FMCON.4.Shift in 08h, WR_FMADRL opcode.5.Shift in X0 to FMADRL. This sets the destination of the first data byte to be loaded as the beginning of the page.6.Shift in the 14h, WRFMDATA_PG opcode.7.Shift in 16 bytes of data to be loaded into the page register. FMADRL is incremented after each byte. After the last byteFMADRL rolls over to point to the beginning of the page.Example of a sequence loading the Page register when in programming mode: Figure 24: loading page register partiallyStartall DATA bytes shifted in?YesDoneLOADING PAGE REGISTER PARTIALLYWR_FMCONLOADDATA start address in pageWR_FMADRLWR_FMDATA_INoDATA N4.3 Programming User Code MemoryCode memory may only be programmed by using the page register. This may be performed using the following sequence:1.Load the page register with the data to be programmed as previously described.ing the WR_FMADRL opcode, write the lower 8-bits of the page address.ing the WR_FMADRH opcode, write the upper 8-bits of the page address.ing the WR_FMCON opcode, shift in the PROG command.5.Read the FMCON register to obtain status. Continue reading until the interface is either not BUSY or until an error hasoccurred.Example of a sequence programming the Page register in Flash when in programming mode: Figure 25: Programming page registerPROGRAMMING PAGE REGISTERStartProgram done (Status[7] = 0)?YesDoneWR_FMADRLDATA addressWR_FMADRHWR_FMCONNoDATA status bytePROG commandRD_FMCONDATA addressAny Error bitsset?NoReport errorYes4.4 Erasing all sectors (global erase)Sectors and their sector security bits may be erased using the following sequence:1.Shift in the WR_FMCON command.2. Shift in the ERS_G command to the FMCON register3.Shift in the RD_FMCON command.4.Continue reading until the interface is either not BUSY or until an error has occurred.Example of a sequence erasing all sectors when in programming mode: Figure 26: Erasing all sectorsNOTE: The Global erase has an errata. After writing ERS_G read data using the FM_DATA_I command, after that RD_FMCON till the busy flag gets cleared.If this is not done the busy flag will never get cleared. Please check erratasheets for which revisions this bug applies.ERASING ALL SECTORSStartWR_FMCONERS_G Program done (Status[7] = 0)?YesDoneDATA status byteRD_FMCONNoAny Error bitsset?NoReport errorYes4.5 Erasing a single sectorA single sector and it’s sector security bits may be erased using the following sequence:1.Shift in the WR_FMADRH command2.Shift in the upper address of the page3.Shift in the WR_FMCON command.4.Shift in the ERS_S command to the FMCON register5.Shift in the RD_FMCON command.6.Continue reading until the interface is either not BUSY or until an error has occurred.Example of a sequence erasing a single sector when in programming mode:Figure 27: Erasing single sectorERASING SINGLE SECTORStartWR_FMCONERS_S Program done (Status[7] = 0)?YesDoneDATA status byteRD_FMCONWR_FMADRHDATA addressNoAny Error bitsset?NoReport errorYes4.6 Erasing a single pageA single page may be erased using the following sequence:1.Shift the WR_FMADRL command in.2.Write the lower 8-bits of the page register address to FMADRL. (only FMADRL[7:6] are used)3.Shift the WR_FMADRH command in.4.Write the upper 8-bits of the page register address to FMADRH.(only FMADRH[4:0] are used)5.Write the ERS_P command to the FMCON register.6.Read the FMCON register to obtain status. Continue reading until the interface is either not BUSY or until an error hasoccurred.Example of a sequence erasing a single page when in programming mode: Figure 28: Erasing single pageERASING SINGLE PAGEStartWR_FMCONERS_P Program done (Status[7] = 0)?YesDoneDATA status byteRD_FMCONWR_FMADRLDATA addressWR_FMADRHDATA addressNoAny Error bitsset?NoReport errorYes4.7 Calculate Global CRCA 32-bit global CRC of the entire user code memory may be calculated using the following sequence:1.Shift in the WR_FMCON command, followed by the CRC_G opcode.2.Shift in the RD_FMCON command, keep reading FMCON till the interface in not BUSY or until it reports an error.3.Shift int he RDFMCON command, and read out the 4 CRC bytes.Example of a sequence that will read the global CRC when in programming mode: Figure 29: Global CRCGLOBAL CRCStartProgram done (Status[7] = 0)?YesDoneNoDATA status byteRD_FMCONWR_FMCONCRC_GRead all 4 CRCbytes?YesNoDATA CRC byteRD_FMCON_IAny Error bitsset?NoReport errorYes4.8 Calculate Sector CRCA 32-bit sector CRC of a single sector of user code memory may be calculated using the following sequence:1.Shift in the WR_FMCON2.Shift in the WR_FMCON command, followed by the CRC_S opcode.3.Shift in the RD_FMCON command, keep reading FMCON till the interface in not BUSY or until it reports an error.4.Shift int he RDFMCON command, and read out the 4 CRC bytes.Example of a sequence that will read the CRC of a sector when in programming mode : Figure 30: Sector CRCSECTOR CRCStartProgram done (Status[7] = 0)?YesDoneDATA status byteRD_FMCONWR_FMCONCRC_SRead all 4 CRCbytes?YesNoDATA CRC byteRD_FMDATA_INoAny Error bitsset?NoReport errorYesWR_FMADRHDATA address4.9 Reading Configuration, Boot Vector, Status Byte, Security Bits, Signature BytesDevices parameters such as configuration bytes, status byte, boot vector, security bits, and signature bytes may be read by writing an address of FMADRL and a command to FMCON. These registers have the following addresses:Table 5: EEPROM bytesNotes:1. Applies only for the P89LPC922, P89LPC925, P89LPC931, P89LPC932A1, P89LPC934, LPC9352. Applies for all parts except P89LPC920Name Mapped Address Byte DescriptionUCFG100H User Configuration Reg. #1 (UCFG1) program/read by the programmer UCFG201H User Configuration Reg. #2 (UCFG2) program/read by the programmer Boot Vector 02H Bootvector Status Byte 03H Status Byte -04H --05H --06H --07H -SEC008H Security byte, sector 0SEC109H Security byte, sector 1SEC20AH Security byte, sector 22SEC30BH Security byte, sector 32SEC40CH Security byte, sector 41SEC50DH Security byte, sector 51SEC60EH Security byte, sector 61SEC70FH Security byte, sector 71MFGID 10H Manufacturer ID (READ ONLY)ID111H Device ID 1 (READ ONLY)ID212HDevice ID 2 (READ ONLY)These bytes may be read using the following sequence:1.Shift in the WR_FMCON2.Shift in the WR_FMCON command, followed by the CONF opcode.3.Shift in the WR_FMADRL command.4.Shift in the DATA address5.Shift in the RD_FMDATA command.6.Shift out the data of the config byte.READING CONFIG BYTES StartWR_FMCONCONFWR_FMADRLDATA addressRD_FMDATADATA config byteDoneFigure 31: Reading config bytes4.10 Writing Configuration, Boot Vector, Status Byte, and Security BitsDevice parameters such as configuration bytes, status byte, boot vector, and security bits, made be written by writing a CONF command to FMCON, an address to FMADRL, and then the data to FMDATA.Figure 32: Writing config bytesWRITING CONFIG BYTESStartWR_FMCONDATA addressWR_FMADRLWR_FMDATACONFDoneProgram done (Status[7] = 0)?YesNoDATA status byteRD_FMCONDATAAny Error bitsset?NoReport errorYes4.11 Writing CCP Clear Configuration ProtectionConfiguration protection can be set in the Boot Status byte, to clear this protection the Clear Configuration Protec-tion command has to be used.Figure 33: Clear Configuration ProtectionCLEAR CONFIGURATION PROTECTIONStartWR_FMCONWR_FMDATACCPDoneDATA (96h)5.0 Calculating CRCThe method used to calculate a 32-bit CRC check for the LPC9xx, is described below. The calculation may be per-formed on either a sector or the entire user code space.INITIALIZATIONDefine and initialize CRC polynomial, POLY0-POLY3 = 00400007HDefine and initialize a 32-bit CRC result, BCRC0-BCRC3 = 00000000HDefine and initialize a 32-bit temporary variable, TAP0-TAP3 = 00000000HDefine and initialize a 1-bit temporary variable to store the MSB of the CRC result, CRCF = 0.STARTING WITH THE FIRST BYTE AND, FOR EACH BYTE IN THE MEMORY (either sector or entire array), PERFORM THE FOLLOWING CRC CALCULATION:1.Shift the BCRC0-BCRC3 registers to the left by one and save the MSB in CRCF, this becomes the new CRC.CRCF BCRC3 BCRC2 BCRC1 BCRC0 313029282726252423222120191817161514131211109876543210‘0’2.Get the byte from memory and perform the following operations on it.a.Distribute the 8 bits of this new byte at the shown locations of the TAP registers and fill the rest of the TAP regis-ters with 0s (direction of LSB to MSB is right to left).TAP3 TAP2 TAP1 TAP0 0000000000000‘7’0‘6’00‘5’00‘4’0‘3’00‘2’0‘1’00‘0’76543210New Byte from Memoryb.XOR the corresponding TAP and BCRC registers and store the result back in the BCRC register.BCRC0 = TAP0 XOR BCRC0BCRC1 = TAP1 XOR BCRC1BCRC2 = TAP2 XOR BCRC2BCRC3 = TAP3 XOR BCRC3c.If the CRCF bit was zero, the CRC calculation is done and BCRC3:0 holds the current CRC result. If the CRCF was a one, XOR the CRC polynomial and BCRC registers and store the new result back in the BCRC registers. BCRC3:0 hold the new 32-bit CRC.BCRC0 = POLY0 XOR BCRC0BCRC1 = POLY1 XOR BCRC1BCRC2 = POLY2 XOR BCRC2BCRC3 = POLY3 XOR BCRC3Repeat this operation, starting at step 1, above, for each byte in the memory array.6.0 AC timings6.1 Getting into the serial programming modeFigure 34: Getting into the programming modeV DD = 2.4V to 3.6V; I PP = TBD mA during programming; T amb = 10°C to +40°C Table 6: Programming mode timingsSYMBOL FIGUREPARAMETERLIMITS UNIT MIN MAX t VR RST delay from V DD active 50-us t RH RST HIGH time 132us t RL RST LOW time 1-us t RPICP entry timeTBDTBDusPDA PCLV DDRESET6.2 Timing data shiftingFigure 35: Writing dataFigure 36: Reading dataTable 7: Programming commands timingSYMBOL PARAMETERLIMITS UNIT MIN MAX t SC Serial clock cycle time 200-ns t SCH Serial clock high 80-ns t SCL Serial clock low80-ns t WAIT Wait between two serial bytes200-ns t SDISU Serial data input setup time to the rising edge of the serial clock 20-ns t SDIH Serial data input hold time after the rising edge of the serial clock 40-ns t SDOH Serial data output hold time after the rising edge of the serial clock 10-ns t SCLDV Serial clock LOW to valid data of the first data bit in a byte -80ns t SCHZSerial clock HIGH to data Hi-Z at the last data bit in a byte-80nsPDALSB bitMSB bitPCLPDALSB MSB PCLLSB7.0 Revision History2005 May 20Section Added P89LPC95212005 January 19Section Added Clear Configuration Protection42004 September 8Section Added P89LPC9102/9103/9107/936/93812004 June 7Section Added P89LPC932A1/904/915/916/917/93312003 September 8Section Added CRC calculation5Added P89LPC920/930/93112003 July 31Section Added P89LPC912/913/914/921/922/934/93512003 May 29Section Added loading page register partially.4Added Global erase errata and workaround. 4Deleted SEC4 - SEC7.42003 May 7Section Fixed errors in reading CRC flowcharts and reading config flowchart4Corrected WR_FMDATA_PG and RD_FMDATA_PG commands2Added WR_FMDATA_I and RD_FMDATA_I commands for CRC reading22003 April 3Section Added error messages in flowcharts4Updated shift timings52003 March 27Section Added coversheet-Added table of contents-Added part types and packages1Added ID bytes12002 October 9Section Added flow charts-2002 September 10Section Initial version-Table 8: Revision History。

CP9XX 编程器使用指南

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芯片
选择芯片型号（S）
选择当前所操作芯片的型号读出（R） F4 将适配器中芯片的数据读出至缓冲区中编程（P） F5 将缓冲区中的数据编程至芯片中校验（C） F7 比较当前所操作芯片中的数据是否和缓冲区中的数据一致擦除（E）擦除当前芯片中的数据恢复ISP功能 (Z) 恢复0x1E00至0x1FFF程序空间的ISP代码设置芯片编号（I）设置当前所操作芯片的编号。此项功能只有在选择芯片后才有效设置芯片配置字（F）设置当前所操作芯片的配置字
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4. CP9XX菜单命令
文件
装载（L）
装载十六进制文件或二进制文件保存文件（S）将当前文件保存为十六进制文件或二进制文件关闭文件（C）关闭当前所打开的文件退出（E）退出系统
快捷功能按钮烧录芯片时的常用功能按钮，用户也可以在菜单中选择相应命令。程序代码缓冲区显示程序代码。信息栏显示当前用户所选择的芯片类型、缓冲区中数据的校验和、芯片具体配置。状态栏分别显示当前用户所进行操作、光标所在地址、Caps Lock键状态、Num Lock键状态及通信状态。通信状态指示灯当系统没有连接具体编程器时，状态栏最右边的指示灯显示为红色，否则显示为绿色。
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Tel: (020)38730916
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