Delay Testing Considering Power Supply Noise Effects

induced slowdown/speedup. The goal of delay testing is to detect all timing defects that can a ect the performance of the design. However, most of the existing techniques are based on simpli ed, logic-level delay fault models and cannot be directly used to model and test timing defects in high speed designs based on deep submicron technologies. Our research concentrates on developing new delay testing strategies needed to close the gap between the logic-level delay fault model and the physical defects. In this paper, we propose a delay test generation procedure that can take into account the power supply noise e ects on the delay of the circuit. In general, power supply noise includes two components: inductive I noise and power net IR voltage drop. The inductive I noise is caused by the change of the instantaneous current on either the package lead inductance or on wire/substrate inductance and di it is proportional to L dt . On the other hand, the IR voltage drop is caused by the instantaneous current through the resistive power and ground lines. The level of noise impact on the delays is highly dependent on the applied input patterns. Tests derived by our technique not only sensitize the given fault and propagate the fault e ect to the primary outputs but also produce the worst-case power supply noise e ects on the signal delays. Therefore, the tests cause the worst-case propagation delays for the nodes along the sensitized path. We focus on the path delay fault model, but a similar methodology (with a di erent cost function) can be derived for other fault models as well. We use a Genetic Algorithm-based (GA-based) approach 3] to generate patterns that maximize the power supply noise for the gates on the target path. Our experiments demonstrate the validity of the new method. We compare the propagation delays produced by test patterns derived for path delay faults under the assumption that there is no power supply noise versus the delays produced by patterns derived to activate and propagate worst-case power supply noise along the tested paths. The results show that, for designs based on a 0.25 , 2.5 V technology, our test
Delay Testing Considering Power Supply Noise E ects
Angela Krstic Yi-Min Jiang Kwang-Ting (Tim) Cheng
Department of Electrical and Computer Engineering University of California, Santa Barbara CA 93106 fangela, jym, timchengg@
The authors would like to thank MARCO/DARPA for supporting this work.
deep submicron process introduces new failure modes and a new set of design and test problems. Process variations are now more likely to cause marginal violations of the performance speci cations. Continuous shrinking of device feature size, increased number of interconnect layers and gate density, increased current density and higher voltage drop along the power nets give rise to the \noise faults" such as: distributed delay defects, power supply noise and crosstalk noise. Analysis shows that excessive noise most of the time leads to delay faults 1]. For example, with the increasing complexity of deep-submicron designs, more devices are switching simultaneously and this results in increased power supply noise. The power supply noise reduces the actual voltage level reaching a device, which, in turn, leads to increased cell and interconnect propagation delays. This results in increased signal arrival times at the primary outputs and the next state lines and causes performance degradation. SPICE simulations show that a 10-15% voltage drop during the cell transition period can cause a 20-30% increase in cell propagation delay 2]. If the cell is a clock bu er or is in the timing-critical path, this delay deviation could cause serious clock skew problems or a non-trivial increase in the critical path delay. Similarly, increase in design density leads to more signi cant crosstalk e ects between the interconnects that can again a ect the performance of the designs. Simulation examples by Breuer et al. 1] show a signi cant increase/decrease in the signal delay (compared to the signal nominal delay) as a result of crosstalk
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Abstract
We propose a new delay test generation technique that can take into account the impact of the power supply noise on the signal propagation delays. This is di erent from existing delay fault models and test generation techniques that ignore the dependence of path delays on the applied test patterns and cannot capture the worst-case timing scenarios in deep submicron designs. In addition to sensitizing the fault and propagating the fault e ects to the primary outputs, our new tests also produce the worst-case power supply noise on the nodes in the target path. Thus, the tests also cause the worst-case propagation delay for the nodes along the target path. Our experimental results on benchmark circuits show that the new delay tests produce signi cantly longer delays on the tested paths compared to the tests derived using existing delay testing methods.