Performance evaluation of rate-based congestion control algorithms in multimedia ATM networ

合集下载
  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。

PERFORMANCE EV ALUATION OF RATE-BASED CONGESTION

CONTROL ALGORITHMS IN MULTIMEDIA ATM NETWORKS

Hiroyuki Ohsaki,Masayuki Murata,Hiroshi Suzuki,Chinatsu Ikeda and Hideo Miyahara

Department of Information and Computer Sciences C&C System Research Laboratories

Faculty of Engineering Science,Osaka University NEC Corporation

Toyonaka,Osaka560,Japan Kawasaki,Kanagawa216,Japan Abstract

In this section,wefirst summarize basic operation of EPRCA++. EPRCA has been adopted as a standard mechanism for a traffic management scheme for ABR service class in the ATM Forum, and EPRCA++has been proposed in[4]as an improved version of EPRCA.Refer to[1,5]for details of EPRCA.

EPRCA++provides more effective(but expensive)explicit rate setting mechanism than EPRCA does[4];the value of backward RM cells are directly computed based on the number of active connections and the traffic load at the switch.The num-ber of active connections is kept to be known at the switch by using per-VC accounting,which can be implemented in several ways with additional hardware complexity.For instance,each switch can have a VC table to record the number of active con-nections.Each VC entry is marked or unmarked according to the status of its corresponding VC(active or inactive),and the number of marked entries represents the number of active con-nections.Furthermore,the switch is provided with an interval timer and it counts the number of cells received during every fixed time interval to monitor the traffic load.The value in the RM cell is computed as

Input rate

Overload

#of active VC’s

Overload

Simulation results for and (as LAN en-vironment)are first presented in Figs.2through 5.Each figure contains permitted cell rate at the source end system and queue length at the switch.The target utilization of EPRCA++

is set to 0.95as suggested in [4].

of selected connections and the aggregate rate for both of ABR and VBR connections are plotted in these figures.

50

100

150

200

250

050100

150200250300

C e l l R a t e (M b i t /s )

Time (ms)

ABR 1ABR 3ABR 5ABR 7ABR 9ABR VBR

50100150200250300

350

050100

150200250300

Q u e u e L e n g t h (c e l l )

Time (ms)

Fig.2:EPRCA with EFCI Switch (

,

).

We can observe that the frequency of the rate increase and decrease is directly influenced by the aggregate generation rate of VBR traffic as can be expected.When comparing EPRCA and EPRCA++,it may conclude that the overall performance of ABR connections are not very bad even in the existence of VBR connections,and that EPRCA++method outperforms EPRCA methods in LAN environment.

When the propagation delay becomes large,however,VBR traffic gives a different impact on each scheme.In Figs.6through 9,we show cell rates and the queue length for

ms as WAN environment.We also illustrate the aggregate throughput of ABR and VBR traffic in Fig.10to see that under-utilization occurs in these cases.In these figures,the BES switch gives better utilization since (1)the EFCI switch uses FECN-like slower congestion notification and (2)the EDS switch fre-quently does major reduction.It is true that the performance of the EDS switch may be improved by an appropriate use of con-trol parameters.However,it implies that too intelligent scheme causes unexpected results unless the careful parameter tuning is performed before applying such a scheme to real systems.

050

100

150

200

250

50

100

150200

250

300

C e l l R a t e (M b i t /s )

Time (ms)

ABR 1ABR 3ABR 5ABR 7ABR 9ABR VBR

50

100150200250

3000

50

100

150200

250

300

Q u e u e L e n g t h (c e l l )

Time (ms)

Fig.3:EPRCA with BES Switch (

).

50

100

150

200

250

050100

150200250300

C e l l R a t e (M b i t /s )

Time (ms)

ABR 1ABR 3ABR 5ABR 7ABR 9ABR VBR

20406080100

120050100

150200250300

Q u e u e L e n g t h (c e l l )

Time (ms)

Fig.4:EPRCA with EDS Switch (

).

相关文档
最新文档