MT29F2G08ABAEAH4-IT_E

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MEMORY存储芯片MT29F1G08ABBEAH4-ITE中文规格书

Erase OperationsErase operations are used to clear the contents of a block in the NAND Flash array toprepare its pages for program operations.Erase OperationsThe ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCKTWO-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When thedie (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify thatthis operation completed successfully.TWO-PLANE ERASE OperationsThe ERASE BLOCK TWO-PLANE (60h-D1h) command can be used to further systemperformance of erase operations by allowing more than one block to be erased in theNAND array. This is done by prepending one or more ERASE BLOCK TWO-PLANE (60h-D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Two-PlaneOperations for details.ERASE BLOCK (60h-D0h)The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flasharray. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).To erase a block, write 60h to the command register. Then write three address cyclescontaining the row address; the page address is ignored. Conclude by writing D0h to thecommand register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for t BERSwhile the block is erased.To determine the progress of an ERASE operation, the host can monitor the target'sR/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) for status output. Use of the READ STATUS(70h) command could cause more than one die (LUN) to respond, resulting in bus con-tention.The ERASE BLOCK (60h-D0h) command is used as the final command of an erase two-plane operation. It is preceded by one or more ERASE BLOCK TWO-PLANE (60h-D1h)commands. All blocks in the addressed planes are erased. The host should check thestatus of the operation by using the status operations (70h, 78h). See Two-Plane Opera-tions for two-plane addressing requirements.Figure 46: ERASE BLOCK (60h-D0h) OperationCycle typeI/O[7:0]RDYLOCK TIGHT (2Ch)The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and al-so prevents unlocked blocks from being locked. When this command is issued, the UN-LOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection against inadvertent PROGRAM and ERASE operations to locked blocks.To implement LOCK TIGHT in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK TIGHT (2Ch) command.When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for t LBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK TIGHT command was issued.After the LOCK TIGHT command is issued, the command cannot be disabled via a soft-ware command. Lock tight status can be disabled only by power cycling the device or toggling WP#. When the lock tight status is disabled, all of the blocks become locked,the same as if the LOCK (2Ah) command had been issued.The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.Figure 56: LOCK TIGHT OperationcommandLOCKWP#CLECE#WE#I/Ox R/B#Don’t CareFigure 57: PROGRAM/ERASE Issued to Locked BlockR/B#I/OxtLocked blockREAD STATUSBLOCK LOCK READ STATUS (7Ah)The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same format, as shown below,and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register, which contains the information on the protection status of the block.Table 17: Block Lock Status Register Bit DefinitionsFigure 58: BLOCK LOCK READ STATUSBLOCK LOCK READ STATUSBlock addressCLE CE#WE#ALE RE#I/OxOTP DATA READ (00h-30h)To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not.To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column ad-dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages.R/B# goes LOW (t R) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP op-eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-tions).Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command.The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)command.Only data on the current page can be read. Pulsing RE# outputs data sequentially.Figure 63: OTP DATA READWE#CE#ALECLERE#R/B#I/OxNote: 1.The OTP page must be within the 02h–1Fh range.。

MEMORY存储芯片MT29F4G08ABADAH4-ITX中文规格书

Data Valid Window per device, per pin:
tDVWp
0.66
–
0.66
–
0.69
–
0.72
–
UI
tQH - tDQSQ each device’s output per UI
8Gb: x4, x8, x16 DDR4 SDRAM AC Electrical Characteristics and AC Timing Parameters
Notes
DQ Input Timing
Data setup time to
Base (calibrated
tDS
Refer to DQ Input Receiver Specification section
–
DQS_t, DQS_c
VREF)
(approximately 0.15tCK to 0.28tCK )
Clock absolute low pulse width (includes duty cycle jitter)
Cycle-to-cycle jitter
Total
DLL locking
Symbol
tCK (AVG, DLL_OFF) tCK (AVG, DLL_ON) tCH (AVG)
tCL (AVG)
–63
63
–54
54
–47
47
–42
42
–31
31
–27
27
–23
23
–21
21
–50
50
–43
43
–38
38
-33
33
MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX + tJITper_tot MAX

MEMORY存储芯片MT29F4G08ABBEAH4-IT中文规格书

Address Hex Code
114:
- -03
115:
- -00
bit 0 = 1
bit 1 = 1
bit 4 = 0
bit 5 = 0
116:
- -18
ASCII Value (DQ[7:0]) – – Yes Yes No No 1.8V
117:
- -90
9.0V
Table 28: Optional Features Field
erase voltage.
bits 0 - 3 BCD 100 mV
bits 4 - 7 hex value in volts
1
VPP optimum program/erase voltage.
bits 0 - 3 BCD 100mV
bits 4 - 7 hex value in volts
Note: 1. See Optional Features Fields table.
Bit 1: Block lock-down bit status active.
Bit 4: EFA block lock-bit status register active.
Bit 5: EFA block lock-bit status active.
1
VCC logic supply highest performance program/
Address 27: 28: 29: 2A: 2B: 2C: 2D:
256Mb
Bottom
Top
--19
--19
--01
--01
--00
--00
--0A
--0A

MEMORY存储芯片MT29F1G08ABBDAH4-IT中文规格书

each mode and command type, the t RFC parameter has different values as defined inthe following table.For discussion purposes, the REFRESH command that should be issued at the normalrefresh rate and has the normal REFRESH cycle duration may be referred to as an REF1xcommand. The REFRESH command that should be issued at the double frequency(t REFI2 = t REFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESHcommand that should be issued at the quadruple rate (t REFI4 = t REFI(base)/4) may bereferred to as a REF4x command.In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2xrefresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh ratemode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh ratemode is enabled, both REF1x and REF2x commands are permitted. When the OTF1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted.Table 50: t REFI and t RFC Parameters4Gb: x8, x16 Automotive DDR4 SDRAM Fine Granularity Refresh ModeFigure 102: REFRESH Command to Power-Down Entry with CAL77 7D 7E 7E 7F 7F 7G 7G 7H 7H 7I'RQ¶W &DUH7LPH %UHDN 4Gb: x8, x16 Automotive DDR4 SDRAM Power-Down ModeData MaskThe DATA MASK (DM) function, also described as PARTIAL WRITE, is supported onlyfor x8 and x16 configurations (it is not supported on x4 devices). The DM functionshares a common pin with the DBI_n and TDQS functions. The DM function appliesonly to WRITE operations and cannot be enabled at the same time the WRITE DBIfunction is enabled. The valid configurations for the TDQS, DM, and DBI functions areshown here.Table 64: DM vs. TDQS vs. DBI Function MatrixWhen enabled, the DM function applies during a WRITE operation. If DM_n is sampledLOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. IfDM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data andwrites this data into the DRAM core. The DQ frame format for x8 and x16 configurationsis shown below. If both CRC write and DM are enabled (via MRS), the CRC will bechecked and valid prior to the DRAM writing data into the DRAM core. If a CRC erroroccurs while the DM feature is enabled, CRC write persistent mode will be enabled anddata will not be written into the DRAM core. In the case of CRC write enabled and DMdisabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAMcore even if a CRC error occurs.Table 65: Data Mask, DQ Frame Format (x8)Table 66: Data Mask, DQ Frame Format (x16)4Gb: x8, x16 Automotive DDR4 SDRAM Data Mask。

MEMORY存储芯片MT29F2G08ABBEAH4-IT中文规格书

4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – IDD Specifications and Conditions
Table 19: IDD7 Measurement Loop (Continued)
Command CS# RAS# CAS# WE# ODT
DQS, DQS# Differential Slew Rate
DQ Slew 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Rate V/ns ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH
2.0
80 45 80 40 61 38
1.0
0
0
0
0
0
0
8
8 16 16
0.9
–1 –3 –1 –3 7
5 15 13 23 21
0.8
–3 –8 5
1 13 9 21 17 29 27
0.7
–3 –5 11 3 19 11 27 21 35 37
3 × nFAW + 4 × nRRD D 19
3 × nFAW + 4 × nRRD + 1
Repeat sub-loop 11, use BA[2:0] = 5
Repeat sub-loop 10, use BA[2:0] = 6
Repeat sub-loop 11, use BA[2:0] = 7
2.0
68 45 68 45 68 45

MEMORY存储芯片MT29F4G08ABBDAH4-IT中文规格书

8.When DLL is disabled for I DD2N , current changes by approximately –5%.9.When CAL is enabled for I DD2N , current changes by approximately –25%.10.When gear-down is enabled for I DD2N , current changes by approximately 0%.11.When CA parity is enabled for I DD2N , current changes by approximately +7%.12.When additive latency is enabled for I DD3N , current changes by approximately +1%.13.When additive latency is enabled for I DD4R , current changes by approximately +5%.14.When read DBI is enabled for I DD4R , current changes by approximately 0%.15.When additive latency is enabled for I DD4W , current changes by approximately +3%(x4/x8), +4%(x16).16.When write DBI is enabled for I DD4W , current changes by approximately 0%.17.When write CRC is enabled for I DD4W , current changes by approximately +10%(x4/x8),+10%(x16).18.When CA parity is enabled for I DD4W , current changes by approximately +12% (x8),+12% (x16).19.When 2X REF is enabled for I DD5R , current changes by approximately –14%.20.When 4X REF is enabled for I DD5R , current changes by approximately –33%.21.I PP0 test and limit is applicable for I DD0 and I DD1 conditions.22.I PP3N test and limit is applicable for all I DD2x , I DD3x , I DD4x and I DD8 conditions; that is, test-ing I PP3N should satisfy the I PP s for the noted I DD tests.23.DDR4-1600 and DDR4-1866 use the same I DD limits as DDR4-2133.24.The I DD values must be derated (increased) when operated outside of the range 0°C ื T C ื 85°C:When T C < 0°C: I DD2P , and I DD3P must be derated by 6%; I DD4R and I DD4W must be derated by 4%; I DD6, I DD6ET , and I DD7 must be derated by 11%.When T C > 85°C: I DD0, I DD1, I DD2N , I DD2NT , I DD2Q , I DD3N , I DD3P , I DD4R , I DD4W , and I DD5R must be derated by 3%; I DD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test.25.I PP6x is applicable to I DD6N , I DD6E , I DD6R and I DD6A conditions.Table 155: I DD , I PP , and I DDQ Current Limits; Die Rev. J (-40° ื T C ื 85°C)8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – LimitsCCMTD-1725822587-98758gb_ddr4_dram.pdf - Rev. S 12/2020 ENTable 155: I DD , I PP , and I DDQ Current Limits; Die Rev. J (-40° ื T C ื 85°C) (Continued)8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – LimitsCCMTD-1725822587-98758gb_ddr4_dram.pdf - Rev. S 12/2020 ENTable 155: I DD , I PP , and I DDQ Current Limits; Die Rev. J (-40° ื T C ื 85°C) (Continued)Notes: 1.Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperaturerange of operation (-40–85°C).2.Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-ture range of operation (-40–95°C).3.Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (-40–45°C).4.I DD6E , I DD6R , I DD6A values are verified by design and characterization, and may not be subject to production test.5.When additive latency is enabled for I DD0, current changes by approximately +1%.6.When additive latency is enabled for I DD1, current changes by approximately +8%(x4/x8),+7%(x16).7.When additive latency is enabled for I DD2N , current changes by approximately +1%.8.When DLL is disabled for I DD2N , current changes by approximately –6%.9.When CAL is enabled for I DD2N , current changes by approximately –20%.10.When gear-down is enabled for I DD2N , current changes by approximately 0%.11.When CA parity is enabled for I DD2N , current changes by approximately +13%.12.When additive latency is enabled for I DD3N , current changes by approximately +2%.13.When additive latency is enabled for I DD4R , current changes by approximately +4(x4/x8),+3%(x16).14.When read DBI is enabled for I DD4R , current changes by approximately -14%(x4/x8),-20%(x16).15.When additive latency is enabled for I DD4W , current changes by approximately +4%(x4/x8), +3%(x16).16.When write DBI is enabled for I DD4W , current changes by approximately 0%.17.When write CRC is enabled for I DD4W , current changes by approximately -5%.18.When CA parity is enabled for I DD4W , current changes by approximately +12%.19.When 2X REF is enabled for I DD5R , current changes by approximately +0%.20.When 4X REF is enabled for I DD5R , current changes by approximately +0%.21.When 2X REF is enabled for I PP5R , current changes by approximately +0%.22.When 4X REF is enabled for I PP5R , current changes by approximately +0%.23.I PP0 test and limit is applicable for I DD0 and I DD1 conditions.24.I PP3N test and limit is applicable for all I DD2x , I DD3x , I DD4x and I DD8 conditions; that is, test-ing I PP3N should satisfy the I PP s for the noted I DD tests.25.DDR4-1600 and DDR4-1866 use the same I DD limits as DDR4-2133.26.The I DD values must be derated (increased) when operating between 85°C < T C ื 95°C:I DD0, I DD1, I DD2N , I DD2NT , I DD2Q , I DD3N , I DD3P , I DD4R , and I DD4W , must be derated by +3%;I DD2P must be derated by +13%; I DD5R and I PP5R must be derated by +43%; All I PP currents except I PP6x and I PP5R must be derated by +0%. These values are verified by design and characterization, and may not be subject to production test.27.I PP6x is applicable to I DD6N , I DD6E , I DD6R and I DD6A conditions.8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – LimitsCCMTD-1725822587-98758gb_ddr4_dram.pdf - Rev. S 12/2020 EN。

MEMORY存储芯片MT29F2G08ABBGAH4-IT-G中文规格书

General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-perform-ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfercommands, address, and data. There are five control signals used to implement theasynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals controlhardware write protection and monitor device status (R/B#).This hardware interface creates a low pin-count device with a standard pinout that re-mains the same from one density to another, enabling future upgrades to higher densi-ties with no board redesign.A target is the unit of memory accessed by a chip enable signal. A target contains one ormore NAND Flash die. A NAND Flash die is the minimum unit that can independentlyexecute commands and report status. A NAND Flash die, in the ONFI specification, isreferred to as a logical unit (LUN). There is at least one NAND Flash die per chip enablesignal. For further details, see Device and Array Organization.This device has an internal 4-bit ECC that can be enabled using the GET/SET features.See Internal ECC and Spare Area Mapping for ECC for more information.Signal DescriptionsTable 1: Signal DefinitionsNotes: 1.See Device and Array Organization for detailed signal connections.2.See Asynchronous Interface Bus Operation for detailed asynchronous interface signaldescriptions.Column Address OperationsThe column address operations affect how data is input to and output from the cacheregisters within the selected die (LUNs). These features provide host flexibility for man-aging data, especially when the host internal buffer is smaller than the number of databytes or words in the cache register.When the asynchronous interface is active, column address operations can address anybyte in the selected cache register.RANDOM DATA READ (05h-E0h)The RANDOM DATA READ (05h-E0h) command changes the column address of the se-lected cache register and enables data output from the last selected die (LUN). Thiscommand is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). Itis also accepted by the selected die (LUN) during CACHE READ operations(RDY = 1; ARDY = 0).Writing 05h to the command register, followed by two column address cycles containingthe column address, followed by the E0h command, puts the selected die (LUN) intodata output mode. After the E0h command cycle is issued, the host must wait at leastt WHR before requesting data output. The selected die (LUN) stays in data output modeuntil another valid command is issued.In devices with more than one die (LUN) per target, during and following interleaveddie (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must beissued prior to issuing the RANDOM DATA READ (05h-E0h). In this situation, using theRANDOM DATA READ (05h-E0h) command without the READ STATUS ENHANCED(78h) command will result in bus contention because two or more die (LUNs) couldoutput data.Figure 32: RANDOM DATA READ (05h-E0h) Operation Array Cycle typeI/O[7:0]SR[6]ble for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).To input a page to the cache register to move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write n address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-TERNAL DATA INPUT (85h) commands may be issued. When data input is complete, write 15h to the command register. The selected LUN will go busy(RDY = 0, ARDY = 0) for t CBSY to allow the data register to become available from a pre-vious program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block ad-dress.To determine the progress of t CBSY, the host can monitor the target's R/B# signal or, al-ternatively, the status operations (70h, 78h) can be used. When the LUN’s status shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check the status of the FAILC bit to see if a previous cache operation was successful.If, after t CBSY, the host wants to wait for the program cache operation to complete, without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor AR-DY until it is 1. The host should then check the status of the FAIL and FAILC bits.In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) com-mand could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a two-plane program cache operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the status opera-tions (70h, 78h).Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (Start)Cycle type I/O[7:0]RDYFigure 44: PROGRAM PAGE CACHE (80h–15h) Operation (End)As defined forPAGE CACHE PROGRAMPROGRAM PAGE TWO-PLANE (80h-11h)。

MEMORY存储芯片MT29F32G08CBACA中文规格书

Cell type Number of simultaneously programmed pages Interleaved operations between multiple due
Byte 3 Page size Spare area size (bytes) Block size (without spare) Organization
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READ ID Parameter Tables
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory READ ID Parameter Tables
READ ID Parameters for Address 00h b =
Command Address tWHR
90h
00h
DOUT
DOUT
DOUT
DOUT
DOUT
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Note: 1. See the READ ID Parameter tables for byte definitions. READ ID (90h) with 20h Address Operation
binary; h = hexadecimal
Byte 0 – Manufacturer ID Manufacturer Byte 1 – Device ID MT29F4G08ABADA MT29F4G16ABADA MT29F4G08ABBDA MT29F4G16ABBDA MT29F8G08ADBDA MT29F8G16ADBDA MT29F8G08ADADA MT29F8G16ADADA MT29F16G08AJADA Byte 2 Number of die per CE

MEMORY存储芯片MT29F2G08ABBGAH4-IT-G中文规格书

MEMORY存储芯片MT29F2G08ABAEA中文规格书

Table 140: I DD4R Measurement – Loop Pattern1Notes: 1.DQS_t, DQS_c are V DDQ when not toggling.2.BG1 is a "Don't Care" for x16 devices.3.Burst sequence driven on each DQ signal by a READ command. Outside burst operation,DQ signals are V DDQ.4.For x4 and x8 only.Table 144: I DD7 Measurement – Loop Pattern1Notes: 1.DQS_t, DQS_c are V DDQ.2.BG1 is a "Don't Care" for x16 devices.3.DQ signals are V DDQ except when burst sequence drives each DQ signal by a READ com-mand.Table 147: I DD , I PP , and I DDQ Current Limits – Rev. B (0°C ≤ T C ≤ 105°C) (Continued)Notes: 1.Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperaturerange of operation (–40–85°C).2.Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-ture range of operation (–40–105°C).3.Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (–40–45°C).4.I DD6E , DD6R and I DD6A values are verified by design and characterization, and may not be subject to production test.5.When additive latency is enabled for I DD0, current changes by approximately 9%.6.When additive latency is enabled for I DD1, current changes by approximately +14% (x8),+14% (x16).7.When additive latency is enabled for I DD2N , current changes by approximately 0%.8.When DLL is disabled for I DD2N , current changes by approximately 1%.9.When CAL is enabled for I DD2N , current changes by approximately –34%.10.When gear-down is enabled for I DD2N , current changes by approximately 0%.11.When CA parity is enabled for I DD2N , current changes by approximately +15%.12.When additive latency is enabled for I DD3N , current changes by approximately +9%.13.When additive latency is enabled for I DD4R , current changes by approximately +6%.14.When read DBI is enabled for I DD4R , current changes by approximately –8%.15.When additive latency is enabled for I DD4W , current changes by approximately +6% (x8),+4% (x16).16.When write DBI is enabled for I DD4W , current changes by approximately 13%.17.When write CRC is enabled for I DD4W , current changes by approximately +4%.18.When CA parity is enabled for I DD4W , current changes by approximately +15% (x8),+10% (x16).19.When 2X REF is enabled for I DD5R , current changes by approximately –16%.20.When 4X REF is enabled for I DD5R , current changes by approximately –35%.21.I PP0 test and limit is applicable for I DD0 and I DD1 conditions.22.I PP3N test and limit is applicable for all I DD2x , I DD3x , I DD4x and I DD8 conditions; that is, test-ing I PP3N should satisfy the I PP s for the noted I DD tests.23.I PP6x is applicable to I DD6N , I DD6E , I DD6R and I DD6A conditions.4Gb: x8, x16 Automotive DDR4 SDRAM Current Specifications – Limits。

MEMORY存储芯片MT29F2G08ABAEAWP IT中文规格书

Dynamic ODTIn certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT R TT(WR)) enabled, the DRAM switches from nominal ODT R TT,nom ) to dy-namic ODT R TT(WR)) when beginning a WRITE burst and subsequently switches back to nominal ODT R TT,nom ) at the completion of the WRITE burst. This requirement is sup-ported by the dynamic ODT feature, as described below.Dynamic ODT Special Use CaseWhen DDR3 devices are architect as a single rank memory array, dynamic ODT offers a special use case: the ODT ball can be wired high (via a current limiting resistor prefer-red) by having R TT,nom disabled via MR1 and R TT(WR) enabled via MR2. This will allow the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur-ing write accesses.When enabling this special use case, some standard ODT spec conditions may be viola-ted: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this would appear to be a problem since R TT(WR) can not be used (should be disabled) and R TT(NOM) should be used. For Write leveling during this special use case, with the DLL locked, then R TT(NOM) maybe enabled when entering Write Leveling mode and disabled when exiting Write Leveling mode. More so, R TT(NOM) must be enabled when enabling Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via same MR1 load if R TT(NOM) is to be used.ODT will turn-on within a delay of ODTLon + t AON + t MOD + 1CK (enabling via MR1)or turn-off within a delay of ODTLoff + t AOF + t MOD + 1CK. As seen in the table below,between the Load Mode of MR1 and the previously specified delay, the value of ODT is uncertain. this means the DQ ODT termination could turn-on and then turn-off again during the period of stated uncertainty.Table 85: Write Leveling with Dynamic ODT Special CaseFunctional DescriptionThe dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic ODT is not supported during DLL disable mode so R TT(WR) must be disabled. The dy-namic ODT function is described below:•Two R TT values are available—R TT,nom and R TT(WR).–The value for R TT,nom is preselected via MR1[9, 6, 2].–The value for R TT(WR) is preselected via MR2[10, 9].4Gb: x4, x8, x16 DDR3L SDRAM Dynamic ODTReference Output LoadFigure 31 (page 75) represents the effective reference load of 25ȍ used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the out-put slew rate measurements. It is not intended to be a precise representation of a partic-ular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the tim-ing reference load to a system environment.Figure 31: Reference Output Load for AC Timing and Output Slew RateV TT = V DDQ /2V SSSlew Rate Definitions for Single-Ended Output SignalsThe single-ended output driver is summarized in Table 48 (page 72). With the reference load for timing measurements, the output slew rate for falling and rising edges is de-fined and measured between V OL(AC) and V OH(AC) for single-ended signals.Table 51: Single-Ended Output Slew Rate Definition4Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating ConditionsV DD Voltage SwitchingAfter the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 51 is main-tained.Figure 51: V DD Voltage SwitchingCKE R TT BA CK, CK#Command Don’t CareODT Th Ti Tj Tk RESET#Time break V DD , V V DD , V DDQ Note: 1.From time point Td until Tk, NOP or DES commands must be applied between MRS andZQCL commands.4Gb: x4, x8, x16 DDR3L SDRAM Voltage Initialization/Change。

MEMORY存储芯片MT29F4G08ABADAH4-I中文规格书

OTP DATA READ (00h-30h)To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not.To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column ad-dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages.R/B# goes LOW (t R) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP op-eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-tions).Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command.The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)command.Only data on the current page can be read. Pulsing RE# outputs data sequentially.Figure 68: OTP DATA READWE#CE#ALECLERE#R/B#I/OxNote: 1.The OTP page must be within the 02h–1Fh range.Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode)WE# CE# ALECLERE#R/B#I/OxDon’t CareNote: 1.OTP data is protected following a good status confirmation.Figure 69: OTP DATA READ with RANDOM DATA READ OperationWE#CE#ALECLERE#R/B#I/OxNote: 1.The OTP page must be within the range 02h–1Fh.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory One-Time Programmable (OTP) Operations。

MEMORY存储芯片MT29F2G08ABAEAH4_E中文规格书

NAND Flash MemoryMT29F2G08ABAEAH4, MT29F2G08ABAEAWP , MT29F2G08ABBEAH4MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4MT29F2G16ABBEAHC Features•Open NAND Flash Interface (ONFI) 1.0-compliant 1•Single-level cell (SLC) technology •Organization–Page size x8: 2112 bytes (2048 + 64 bytes)–Page size x16: 1056 words (1024 + 32 words)–Block size: 64 pages (128K + 4K bytes)–Plane size: 2 planes x 1024 blocks per plane –Device size: 2Gb: 2048 blocks •Asynchronous I/O performance –t RC/t WC: 20ns (3.3V), 25ns (1.8V)•Array performance –Read page: 25µs 3–Program page: 200µs (TYP: 1.8V , 3.3V)3–Erase block: 700µs (TYP)•Command set: ONFI NAND Flash Protocol •Advanced command set–Program page cache mode 4–Read page cache mode 4–One-time programmable (OTP) mode –Two-plane commands 4–Interleaved die (LUN) operations –Read unique ID–Block lock (1.8V only)–Internal data move•Operation status byte provides software method for detecting–Operation completion –Pass/fail condition –Write-protect status•Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion •WP# signal: Write protect entire device•First block (block address 00h) is valid when ship-ped from factory with ECC. For minimum required ECC, see Error Management.•Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-cles are less than 1000•RESET (FFh) required as first command after pow-er-on•Alternate method of device initialization (Nand_In-it) after power up (contact factory)•Internal data move operations supported within the plane from which data is read •Quality and reliability–Data retention: 10 years–Endurance: 100,000 PROGRAM/ERASE cycles •Operating voltage range –V CC : 2.7–3.6V –V CC : 1.7–1.95V•Operating temperature–Commercial: 0°C to +70°C –Industrial (IT): –40ºC to +85ºC–Automotive Industrial (AIT): –40°C to +85°C –Automotive (AAT): –40°C to +105°C •Package–48-pin TSOP type 1, CPL 2–63-ball VFBGANotes:1.The ONFI 1.0 specification is available at2.CPL = Center parting line.3.See Electrical Specifications – Program/EraseCharacteristics for t R_ECC and t PROG_ECC specifications.4.These commands supported only with ECCdisabled.质量等级领域:宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC ，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以深圳市美光存储技术有限公司提供的参数为例，以下为MT29F2G08ABAEAH4_E的详细参数，仅供参考Error ManagementEach NAND Flash die (LUN) is specified to have a minimum number of valid blocks(NVB) of the total available blocks. This means the die (LUNs) could have blocks thatare invalid when shipped from the factory. An invalid block is one that contains at leastone page that has more bad bits than can be corrected by the minimum required ECC.Additional blocks can develop with use. However, the total number of available blocksper die (LUN) will not fall below NVB during the endurance life of the product.Although NAND Flash memory devices could contain bad blocks, they can be usedquite reliably in systems that provide bad block management and error-correction algo-rithms. This type of software environment ensures data integrity.Internal circuitry isolates each block from other blocks, so the presence of a bad blockdoes not affect the operation of the rest of the NAND Flash array.NAND Flash devices are shipped from the factory erased. The factory identifies invalidblocks before shipping by attempting to program the bad block mark into every loca-tion in the first page of each invalid block. It may not be possible to program every loca-tion with the bad block mark. However, the first spare area location in each bad block isguaranteed to contain the bad block mark. This method is compliant with ONFI FactoryDefect Mapping requirements. See the following table for the first spare area locationand the bad block mark.System software should check the first spare area location on the first page of eachblock prior to performing any PROGRAM or ERASE operations on the NAND Flash de-vice. A bad block table can then be created, enabling system software to map aroundthese areas. Factory testing is performed under worst-case conditions. Because invalidblocks could be marginal, it may not be possible to recover this information if the blockis erased.Over time, some memory locations may fail to program or erase properly. In order toensure that data is stored properly over the life of the NAND Flash device, the followingprecautions are required:•Always check status after a PROGRAM or ERASE operation•Under typical conditions, use the minimum required ECC (see table below)•Use bad block management and wear-leveling algorithmsThe first block (physical block address 00h) for each CE# is guaranteed to be validwith ECC when shipped from the factory.Table 18: Error Management DetailsInternal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not ECC protected. During the busy time for PROGRAM operations, internal ECC generates parity bits when error detection is complete.During READ operations the device executes the internal ECC engine (5-bit detection and 4-bit error correction). When the READ operaton is complete, read status bit 0 must be checked to determine whether errors larger than four bits have occurred. Following the READ STATUS command, the device must be returned to read mode by issuing the 00h command.Limitations of internal ECC include the spare area, defined in the figures below, and ECC parity areas that cannot be written to. Each ECC user area (referred to as main and spare) must be written within one partial-page program so that the NAND device can calculate the proper ECC parity. The number of partial-page programs within a page cannot exceed four.。

MEMORY存储芯片MT29F2G08ABAGAWP-IT_G中文规格书

PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__1.fm -Rev. I 1/06 ENNAND Flash MemoryMT29F2G08AABWP/MT29F2G16AABWP MT29F4G08BABWP/MT29F4G16BABWP MT29F8G08FABWP Features•Organization:•Page size:x8: 2,112 bytes (2,048 + 64 bytes)x16: 1,056 words (1,024 + 32 words)•Block size: 64 pages (128K + 4K bytes)•Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;8Gb: 8,192 blocks •Read performance:•Random read: 25µs•Sequential read: 30ns (3V x8 only)•Write performance:•Page program: 300µs (TYP)•Block erase: 2ms (TYP)•Endurance: 100,000 PROGRAM/ERASE cycles •Data retention: 10 years•First block (block address 00h) guaranteed to be valid without ECC (up to 1,000 PROGRAM/ERASE cycles)•V CC : 2.7V–3.6V•Automated PROGRAM and ERASE •Basic NAND command set:•PAGE READ, RANDOM DATA READ, READ ID,READ STATUS, PROGRAM PAGE, RANDOM DATA INPUT, PROGRAM PAGE CACHE MODE, INTER-NAL DATA MOVE, INTERNAL DATA MOVE with RANDOM DATA INPUT, BLOCK ERASE, RESET •New commands:•PAGE READ CACHE MODE•READ UNIQUE ID (contact factory)•READ ID2 (contact factory)•Operation status byte provides a software method of detecting:•PROGRAM/ERASE operation completion •PROGRAM/ERASE pass/fail condition •Write-protect status•Ready/busy# (R/B#) pin provides a hardware method of detecting PROGRAM or ERASE cycle completion•PRE pin: prefetch on power up •WP# pin: hardware write protectFigure 1:48-Pin TSOP Type 1Options Marking•Density:2Gb (single die)MT29F2GxxAAB 4Gb (dual-die stack)MT29F4GxxBAB 8Gb (quad-die stack)MT29F8GxxFAB •Device width:x8MT29Fxx08x x16MT29Fxx16x •Configuration:# of die # of CE## ofR/B#111A 211B 422F•V CC : 2.7V–3.6VA •Second generation dieB •Package:48 TSOP type I (lead-free)WP 48 TSOP type I (NEW version,WA8Gb device only, lead-free)48 TSOP type I (contact factory)WG •Operating temperature:Commercial (0°C to 70°C)None Extended temperature (-40°C to +85°C)ETPower-On AUTO-READDuring power-on, with the PRE pin at V CC, 3V V CC devices automatically transfer thefirst page of the memory array to the data register without requiring a command oraddress-input sequence. As V CC reaches approximately 2.5V, the internal voltage detec-tor initiates the power-on AUTO-READ function.R/B# will stay LOW (t RPRE) while the first page of data is copied into the data register.See Table18 on page41for the t RPRE value. Once the READ is complete and R/B# goesHIGH, RE# can be pulsed to output the first page of data.The PRE function is not supported on extended-temperature devices.Figure 16: First Page Power-On AUTO-READ (3V V CC only)Notes:1.Verified per device characterization; not 100 percent tested on all devices.2.The PRE function is not supported on extended-temperature devices.Figure 17: AC Waveforms During Power TransitionsPROGRAM OperationsPROGRAM PAGE 80h-10hMicron NAND Flash devices are inherently page-programmed devices. Within a block,the pages must be programmed consecutively from the least significant bit (LSB) page ofthe block to most significant bit (MSB) pages of the block. Random page address pro-gramming is prohibited.Micron NAND flash devices also support partial-page programming operations. Thismeans that any single bit can only be programmed one time before an erase is required;however, the page can be partitioned such that a maximum of eight programming oper-ations are allowed before an erase is required.SERIAL DATA INPUT 80hPAGE PROGRAM operations require loading the SERIAL DATA INPUT (80h) commandinto the command register, followed by five ADDRESS cycles, then the data. Serial datais loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)command is written after the data input is complete. The internal write state machineautomatically executes the proper algorithm and controls all the necessary timing toprogram and verify the operation. Write verification only detects “1s” that are not suc-cessfully written to “0s.”R/B# goes LOW for the duration of array programming time, t PROG. The READ STATUSREGISTER (70h) command and the RESET (FFh) command are the only commands validduring the programming operation. Bit 6 of the status register will reflect the state ofR/B#. When the device reaches ready, read bit 0 of the status register to determine if theprogram operation passed or failed. (See Figure23.) The command register stays in readstatus register mode until another valid command is written to it.RANDOM DATA INPUT 85hAfter the initial data set is input, additional data can be written to a new column addresswith the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-mand can be used any number of times in the same page prior to issuing the PAGEWRITE (10h) command. See Figure24 for the proper command sequence.Figure 23: PROGRAM and READ STATUS OperationFigure 24: RANDOM DATA INPUTPROGRAM PAGE CACHE MODE 80h-15hCache programming is actually a buffered programming mode of the standard PAGEPROGRAM command. Programming is started by loading the SERIAL DATA INPUT(80h) command to the command register, followed by five cycles of address, and a full orpartial page of data. The data is initially copied into the cache register, and the CACHEWRITE (15h) command is then latched to the command register. Data is transferredfrom the cache register to the data register on the rising edge of WE#. R/B# goes LOWduring this transfer time. After the data has been copied into the data register and R/B#returns to HIGH, memory array programming begins.When R/B# returns to HIGH, new data can be written to the cache register by issuinganother CACHE PROGRAM command sequence. The time that R/B# stays LOW will becontrolled by the actual programming time. The first time through equals the time ittakes to transfer the cache register contents to the data register. On the second and sub-sequent programming passes, transfer from the cache register to the data register is heldoff until current data register content has been programmed into the array.Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h)command to determine when the cache register is ready to accept new data. The R/B#pin always follows bit 6.Bit 5 (R/B#) of the status register can be polled to determine when the actual program-ming of the array is complete for the current programming cycle.If just the R/B# pin is used to determine programming completion, the last page of theprogram sequence must use the PROGRAM PAGE (10h) command instead of theCACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is usedevery time, including the last page of the programming sequence, status register bit 5must be used to determine when programming is complete. (See Figure25.)Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of thestatus register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”(ready state). (See Figure25.)Figure 25: PROGRAM PAGE CACHE MODE ExampleNotes:1.See Note 3, Table19 on page41.2.Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW orpulse multiple times after a 70h command.。

MEMORY存储芯片MT29F1G08ABADAH4-ITE中文规格书

Figure 53: MRS to nonMRS Command Timing (t MOD)CK#CKCommand Address CKEIndicates breakin time scale Don’t CareNotes: 1.Prior to issuing the MRS command, all banks must be idle (they must be precharged, t RPmust be satisfied, and no data bursts can be in progress).2.Prior to Ta2 when t MOD (MIN) is being satisfied, no commands (except NOP/DES) may beissued.3.If R TT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis-fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 untilt MODmin is satisfied at Ta2.4.CKE must be registered HIGH from the MRS command until t MRSPDEN (MIN), at whichtime power-down may occur (see Power-Down Mode (page 187)).Mode Register 0 (MR0)The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modesof operation. These definitions include the selection of a burst length, burst type, CASlatency, operating mode, DLL RESET, write recovery, and precharge power-down mode(see Figure 54 (page 142)).Burst LengthBurst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM areburst-oriented, with the burst length being programmable to 4 (chop) mode, 8 (fixed)mode, or selectable using A12 during a READ/WRITE command (on-the-fly). The burstlength determines the maximum number of column locations that can be accessed fora given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITEcommand, if A12 = 0, then BC4 mode is selected. If A12 = 1, then BL8 mode is selected.Specific timing diagrams, and turnaround between READ/WRITE, are shown in theREAD/WRITE sections of this document.When a READ or WRITE command is issued, a block of columns equal to the burstlength is effectively selected. All accesses for that burst take place within this block,meaning that the burst will wrap within the block if a boundary is reached. The block isuniquely selected by A[i :2] when the burst length is set to 4 and by A[i :3] when the burstlength is set to 8, where A i is the most significant column address bit for a given config-uration. The remaining (least significant) address bit(s) is (are) used to select the start-4Gb: x4, x8, x16 DDR3L SDRAM Mode Register 0 (MR0)Input/Output CapacitanceTable 6: DDR3L Input/Output CapacitanceNotes: 1.V DD = 1.35V (1.283–1.45V), V DDQ = V DD , V REF = V SS , f = 100 MHz, T C = 25°C. V OUT(DC) = 0.5× V DDQ , V OUT = 0.1V (peak-to-peak).2.DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.3.Includes TDQS, TDQS#. C DDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.4.C DIO = C IO(DQ) - 0.5 × (C IO(DQS) + C IO(DQS#)).5.Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =A[n :0], BA[2:0].6.C DI_CTRL = C I(CTRL) - 0.5 × (C CK(CK) + C CK(CK#)).7.C DI_CMD_ADDR = C I(CMD_ADDR) - 0.5 × (C CK(CK) + C CK(CK#)).4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications。

MEMORY存储芯片MT29F2G08ABAFAH4-ITS中文规格书

RTT,nom Mode Restriction n/a
Note: 1. RZQ = 240˖. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
Table 88: Mode Registers for RTT(WR)
4Gb: x4, x8, x16 DDR3L SDRAM Commands
Figure 45: DLL Disable tDQSCK
T0
T1
T2
T3
T4
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
Address
Valid
DQS, DQS# DLL on DQ BL8 DLL on
DQS, DQS# DLL off DQ BL8 DLL disable
96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.
987
ห้องสมุดไป่ตู้
14 ±0.1 12 CTR
0.8 TYP
321
A B C D E F G H J K L M N P R T
Ball A1 ID (covered by SR)
DI b+1
DI b+2
DI b+3
DI b+4
DI b+5
DI b+6
DI b+7
DI
DI
DI
DI
b
b+1 b+2 b+3

MEMORY存储芯片MT29F2G08ABAEAH4-ITX中文规格书

ODT Timing DefinitionsDefinitions for t ADC, t AONAS, and t AOFAS are provided in the Table 131 (page 309) and shown in Figure 242 (page 310) and Figure 244 (page 311). Measurement reference set-tings are provided in the subsequent Table 132 (page 309).The t ADC for the dynamic ODT case and read disable ODT cases are represented by t ADC of Direct ODT Control case.Table 131: ODT Timing DefinitionsTable 132: Reference Settings for ODT Timing MeasurementsNotes: 1.MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for R TT(NOM) setting; MR5 hasA8 = 0, A7 = 0, A6 = 0 for R TT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for R TT(WR) setting.2.ODT state change is controlled by ODT pin.3.ODT state change is controlled by a WRITE command.4.Refer to Figure 242 (page 310).5.Refer to Figure 243 (page 310).6.Refer to Figure 244 (page 311).8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination CharacteristicsFigure 12: 96-Ball FBGA – x16 (LY)Ball A1 ID (covered by SR)1.8 CTRNonconductiveovermoldNotes: 1.All dimensions are in millimeters.2.Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).Data MaskThe DATA MASK (DM) function, also described as a partial write, has been added to thedevice and is supported only for x8 and x16 configurations (x4 is not supported). TheDM function shares a common pin with the DBI and TDQS functions. The DM functionapplies only to WRITE operations and cannot be enabled at the same time the write DBIfunction is enabled. Refer to the TDQS Function Matrix table for valid configurations forall three functions (TDQS/DM/DBI).CA Parity Persistent Error ModeNormal CA parity mode (CA parity persistent mode disabled) no longer performs CAparity checking while the parity error status bit remains set at 1. However, with CA pari-ty persistent mode enabled, CA parity checking continues to be performed when theparity error status bit is set to a 1.ODT Input Buffer for Power-DownThis feature determines whether the ODT input buffer is on or off during power-down.If the input buffer is configured to be on (enabled during power-down), the ODT inputsignal must be at a valid logic level. If the input buffer is configured to be off (disabledduring power-down), the ODT input signal may be floating and the device does not pro-vide R TT(NOM) termination. However, the device may provide R TT(Park) termination de-pending on the MR settings. This is primarily for additional power savings.CA Parity Error StatusThe device will set the error status bit to 1 upon detecting a parity error. The parity errorstatus bit remains set at 1 until the device controller clears it explicitly using an MRScommand.CRC Error StatusThe device will set the error status bit to 1 upon detecting a CRC error. The CRC errorstatus bit remains set at 1 until the device controller clears it explicitly using an MRScommand.CA Parity Latency ModeCA parity is enabled when a latency value, dependent on t CK, is programmed; this ac-counts for parity calculation delay internal to the device. The normal state of CA parityis to be disabled. If CA parity is enabled, the device must ensure there are no parity er-rors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16,CAS_n/A15, WE_n/A14, and the address bus including bank address and bank groupbits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.。

MEMORY存储芯片MT29F2G08ABBEAH4-ITX中文规格书

Write Timing ViolationsMotivationGenerally, if timing parameters are violated, a complete reset/initialization procedurehas to be initiated to make sure that the device works properly. However, for certain mi-nor violations, it is desirable that the device is guaranteed not to "hang up" and that er-rors are limited to that specific operation. A minor violation does not include a majortiming violation (for example, when a DQS strobe misses in the t DQSCK window).For the following, it will be assumed that there are no timing violations with regard tothe WRITE command itself (including ODT, and so on) and that it does satisfy all timingrequirements not mentioned below.Data Setup and Hold ViolationsIf the data-to-strobe timing requirements (t DS, t DH) are violated, for any of the strobeedges associated with a WRITE burst, then wrong data might be written to the memorylocation addressed with this WRITE command.In the example, the relevant strobe edges for WRITE Burst A are associated with theclock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5.Subsequent reads from that location might result in unpredictable read data; however,the device will work properly otherwise.Strobe-to-Strobe and Strobe-to-Clock ViolationsIf the strobe timing requirements (t DQSH, t DQSL, t WPRE, t WPST) or the strobe to clocktiming requirements (t DSS, t DSH, t DQSS) are violated, for any of the strobe edges asso-ciated with a WRITE burst, then wrong data might be written to the memory locationaddressed with the offending WRITE command. Subsequent reads from that locationmight result in unpredictable read data; however, the device will work properly other-wise with the following constraints:•Both write CRC and data burst OTF are disabled; timing specifications other than t DQSH, t DQSL, t WPRE, t WPST, t DSS, t DSH, t DQSS are not violated.•The offending write strobe (and preamble) arrive no earlier or later than six DQS tran-sition edges from the WRITE latency position.•A READ command following an offending WRITE command from any open bank isallowed.•One or more subsequent WR or a subsequent WRA (to same bank as offending WR)may be issued t CCD_L later, but incorrect data could be written. Subsequent WR andWRA can be either offending or non-offending writes. Reads from these writes mayprovide incorrect data.•One or more subsequent WR or a subsequent WRA (to a different bank group) may beissued t CCD_S later, but incorrect data could be written. Subsequent WR and WRAcan be either offending or non-offending writes. Reads from these writes may provideincorrect data.•After one or more precharge commands (PRE or PREA) are issued to the device afteran offending WRITE command and all banks are in precharged state (idle state), asubsequent, non-offending WR or WRA to any open bank will be able to write correctdata.8Gb: x4, x8, x16 DDR4 SDRAM Write Timing ViolationsMM PUDD =× 100R ONPU,max - R ONPU,minR ON,nomMM PDDD =× 100R ONPD,max - R ONPD,minR ON,nom 7.The lower and upper bytes of a x16 are each treated on a per byte basis.8.The minimum values are derated by 9% when the device operates between –40°C and0°C (T C ).Output Driver Temperature and Voltage SensitivityIf temperature and/or voltage change after calibration, the tolerance limits widen ac-cording to the equations and tables below.˂T = T - T(@calibration); ˂V = V DDQ - V DDQ (@ calibration); V DD = V DDQTable 125: Output Driver Sensitivity DefinitionsTable 126: Output Driver Voltage and Temperature SensitivityAlert DriverA functional representation of the alert output buffer is shown in the figure below. Out-put driver impedance, R ON , is defined as follows.8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac-teristicsFigure 69: V REF Step: Single Step Size Increment CaseVFigure 70: V REF Step: Single Step Size Decrement CaseV)8Gb: x4, x8, x16 DDR4 SDRAM V REFDQ Calibration。

MEMORY存储芯片MT29F4G08ABADAH4-IT中文规格书

Notes: 1.Speed Bin table is only valid with DLL enabled.2.When operating in 2t CK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable t CK range.3.The programmed value of CWL must be less than or equal to the programmed value of CL.4.This value applies to non-native t CK-CL-n RCD-n RP combinations.5.When calculating t RC in clocks, values may not be used in a combination that violate t RAS or t RP .6.This value exceeds the JEDEC requirement in order to allow additional flexibility, espe-cially for components. However, JEDEC SPD compliance may force modules to only sup-port the JEDEC defined value, please refer to the SPD documentation.8Gb: x4, x8, x16 DDR4 SDRAM Speed Bin TablesCCMTD-1725822587-98758gb_ddr4_dram.pdf - Rev. S 12/2020 ENNotes: 1.Speed Bin table is only valid with DLL enabled.2.When operating in 2t CK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable t CK range.3.The programmed value of CWL must be less than or equal to the programmed value of CL.4.This value applies to non-native t CK-CL-n RCD-n RP combinations.5.When calculating t RC in clocks, values may not be used in a combination that violate t RAS or t RP .6.This value exceeds the JEDEC requirement in order to allow additional flexibility, espe-cially for components. However, JEDEC SPD compliance may force modules to only sup-port the JEDEC defined value, please refer to the SPD documentation.8Gb: x4, x8, x16 DDR4 SDRAM Speed Bin TablesCCMTD-1725822587-98758gb_ddr4_dram.pdf - Rev. S 12/2020 EN。

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NAND Flash MemoryMT29F2G08ABAEAH4, MT29F2G08ABAEAWP , MT29F2G08ABBEAH4MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4MT29F2G16ABBEAHC Features•Open NAND Flash Interface (ONFI) 1.0-compliant 1•Single-level cell (SLC) technology •Organization–Page size x8: 2112 bytes (2048 + 64 bytes)–Page size x16: 1056 words (1024 + 32 words)–Block size: 64 pages (128K + 4K bytes)–Plane size: 2 planes x 1024 blocks per plane –Device size: 2Gb: 2048 blocks •Asynchronous I/O performance –t RC/t WC: 20ns (3.3V), 25ns (1.8V)•Array performance –Read page: 25µs 3–Program page: 200µs (TYP: 1.8V , 3.3V)3–Erase block: 700µs (TYP)•Command set: ONFI NAND Flash Protocol •Advanced command set–Program page cache mode 4–Read page cache mode 4–One-time programmable (OTP) mode –Two-plane commands 4–Interleaved die (LUN) operations –Read unique ID–Block lock (1.8V only)–Internal data move•Operation status byte provides software method for detecting–Operation completion –Pass/fail condition –Write-protect status•Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion •WP# signal: Write protect entire device•First block (block address 00h) is valid when ship-ped from factory with ECC. For minimum required ECC, see Error Management.•Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-cles are less than 1000•RESET (FFh) required as first command after pow-er-on•Alternate method of device initialization (Nand_In-it) after power up (contact factory)•Internal data move operations supported within the plane from which data is read •Quality and reliability–Data retention: 10 years–Endurance: 100,000 PROGRAM/ERASE cycles •Operating voltage range –V CC : 2.7–3.6V –V CC : 1.7–1.95V•Operating temperature–Commercial: 0°C to +70°C –Industrial (IT): –40ºC to +85ºC–Automotive Industrial (AIT): –40°C to +85°C –Automotive (AAT): –40°C to +105°C •Package–48-pin TSOP type 1, CPL 2–63-ball VFBGANotes:1.The ONFI 1.0 specification is available at2.CPL = Center parting line.3.See Electrical Specifications – Program/EraseCharacteristics for t R_ECC and t PROG_ECC specifications.4.These commands supported only with ECCdisabled.质量等级领域:宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC ，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以深圳市美光存储技术有限公司提供的参数为例，以下为MT29F2G08ABAEAH4-IT_E的详细参数，仅供参考Figure 15: Asynchronous Data Output Cycles (EDO Mode)CE#RE#I/OxRDYWrite Protect#The write protect# (WP#) signal enables or disables PROGRAM and ERASE operationsto a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. WhenWP# is HIGH, PROGRAM and ERASE operations are enabled.It is recommended that the host drive WP# LOW during power-on until V CC is stable toprevent inadvertent PROGRAM and ERASE operations (see Device Initialization for ad-ditional details).WP# must be transitioned only when the target is not busy and prior to beginning acommand sequence. After a command sequence is complete and the target is ready,WP# can be transitioned. After WP# is transitioned, the host must wait t WW before issu-ing a new command.The WP# signal is always an active input, even when CE# is HIGH. This signal shouldnot be multiplexed with other signals.Ready/Busy#The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-get is ready or busy. A target is busy when one or more of its die (LUNs) are busy(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because eachdie (LUN) contains a status register, it is possible to determine the independent statusof each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-tus Operations for details regarding die (LUN) status).This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when thetarget is ready, and transitions LOW when the target is busy. The signal's open-drainTable 5: Command Set (Continued)2Gb: x8, x16 NAND Flash MemoryCommand Definitions2Gb: x8, x16 NAND Flash Memory Parameter Page Data Structure TablesOTP DATA READ (00h-30h)To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not.To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column ad-dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages.R/B# goes LOW (t R) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP op-eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-tions).Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command.The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)command.Only data on the current page can be read. Pulsing RE# outputs data sequentially.Figure 66: OTP DATA READWE#CE#ALECLERE#R/B#I/OxNote: 1.The OTP page must be within the 02h–1Fh range.2Gb: x8, x16 NAND Flash MemoryOne-Time Programmable (OTP) Operations。