Asynchronous DesignEvaluation Methods for Hypertext Development
FA常用英文(供参考)
Proposal Design 方案设计[prəˈpəʊzl] Layout Design 布局设计Module Design 模块设计[ˈmɒdju:l] Parallel Design 并行设计[ˈpærəlel] Optimizing Design 优化设计['ɒptɪmaɪzɪŋ] Mechanical Design 机械设计Software Design 软件设计Top-Down Design 自顶向下设计Error-Proofing Design 防错设计['pru:fɪŋ] Feasibility 可行性[ˌfi:zə'bɪlətɪ]Plan 计划FMEA 失效模式分析Ergonomic 人机工程学[ˌɜ:gəˈnɒmɪk] Human Machine Interface 人机交互界面Schedule 进度表ˈʃedju:l]Safeguard 安全防护Cycle Time 生产节拍Technique Process 工艺流程英[tekˈni:k] [ˈprəʊses]Sequence 顺序[ˈsi:kwəns] Mechanism 机构[ˈmekənɪzəm] Structure 结构System 系统Orbit 轨迹[ˈɔ:bɪt]PDM 产品数据管理PLM 产品生命周期管理3D Drawing 三维图2D Drawing 二维图Part Drawing 零件图Assembly Drawing 装配图[əˈsembli] Bill of Material 材料清单（BOM）Cost Down 降低成本Qualified Part 合格品ˈkwɒlɪfaɪd] Rejected Part 不合格品[rɪˈdʒekt] Confirm 确认kənˈfɜ:m]Check 审核Approve 批准Flow Line 流水线Conveyor 传输装置[kənˈveɪə(r)] Orientation 定向[ɔ:riənˈteɪʃn] Location 定位Picking 抓取Sorting 排序Pallet 随行夹具[ˈpælət]Fixture 固定夹具Gripper 抓取夹具['grɪpə]Feeding 进给Loading 上料Offloading 卸料Machining 加工Manufacture 制造[ˌmænjuˈfæktʃə(r)]Assemble 装配[əˈsembl]Run 运行Dry Run 设备空运行Patent 专利[ˈpætnt]Automated inspection 自动化检验automatic assembly system 自动化装配系统applied biomechanics 应用生物力学CAD/CAM 计算机辅助设计与制造computer integrated manufacturing system 计算机整合制造系统data structure 数据结构data base management system 数据库管理系统decision analysis 决策分析engineering economy 工程经济engineering statistics 工程统计facilities planning 设施规划factory diagnoisis and improvement method 工厂诊断与改善方法financial and cost analysis 财务与成本分析fuzzy theory and application 模糊理论与应用human-computer interaction (HCI)人因工程与计算机系统human factors engineering 人因工程human information processing 人类讯息处理human-machine system design 人机系统设计human resource management 人力资源管理human system diagnosis and improvement 人体系统诊断与改善industrial environment evaluation 工业环境评估industrial organizations and management 工业组织与管理industrial safety 工业安全information technology 信息技术intellectual property laws 智慧财产权法knowledge engineering 知识工程linear algebra 线性代数manufacturing automation 制造自动化manufacturing engineering 制造工程manufacturing management 制造管理manufacturing process 制造程序manufacturing systems and management 制造系统与管理market and marketing 市场与行销material flows automation 物流自动化mathematical programming 数学规划multicriteria decision making 多目标规划multi-criteria decision methods 多准则决策分析network analysis 网络分析numerical analysis 数值分析organization and management 组织与管理product and technology development management 产品与技术开发管理production management 生产管理production planning and control 生产计划与管制quality control 质量管理quality engineering 品质工程quality management techniques and practice 品质管理queueing theory 等候线理论reliability engineering 可靠度工程research，development and innovation management 研究发展管理semiconductor production management 半导体生产管理sequencing and scheduling 排序与排程simulation 模拟分析statistical method 统计方法stochastic processes 随机系统strategic management of technology 技术策略system analysis and design in large scale 大型系统分析与设计system performance evaluation 系统绩效评估技术system quality assurance engineering 系统品质保证工程systems engineering 系统工程systems simulation 系统仿真vision and colors 视觉与色彩work physiology 工作生理学work study 工作研究集散控制系统——Distributed Control System（DCS）现场总线控制系统——Fieldbus Control System（FCS）监控及数据采集系统——Supervisory Control And DataAcqusition（SCADA）可编程序控制器——Programmable Logic Controller（PLC）可编程计算机控制器——Programmable Computer Controller（PCC）工厂自动化——Factory Automation（FA）过程自动化——Process Automation（PA）办公自动化——Office Automation（OA）管理信息系统——Management Information System（MIS）楼宇自动化系统——Building Automation System人机界面——Human Machine Interface （HMI）工控机——Industrial Personal Computer （IPC）单片机——Single Chip Microprocessor计算机数控（CNC）远程测控终端——Remote Terminal Unit （RTU）上位机——Supervisory Computer图形用户界面（GUI）人工智能——Artificial Intelligent（AI）智能终端——Intelligent Terminal模糊控制——Fuzzy Control组态——Configuration仿真——Simulation冗余——Redundant客户/服务器——Client/Server网络——Network设备网——DeviceNET基金会现场总线——foundation fieldbus（FF）现场总线——Fieldbus以太网——Ethernet变频器——Inverter脉宽调制——Pulse Width Modulation （PWM）伺服驱动器——Servo Driver软起动器——Soft Starter步进——Step-by-Step控制阀——Control Valver流量计——Flowmeter仪表——Instrument记录仪—— Recorder传感器——Sensor智能传感器——Smart Sensor智能变送器——Smart Transducer虚拟仪器——Virtual Instrument主站/从站——MasterStation/Slave station 操作员站/工程师站/管理员站——Operator Station/Engineer Station/Manager Station电力专业英语单词电力系统power system发电机generator励磁excitation励磁器excitor电压voltage电流current升压变压器step-up transformer母线bus变压器transformer空载损耗：no-load loss铁损：iron loss铜损：copper loss空载电流：no-load current无功损耗：reactive loss有功损耗：active loss输电系统power transmission system高压侧high side输电线transmission line高压: high voltage低压：low voltage中压：middle voltage功角稳定angle stability 稳定stability电压稳定voltage stability暂态稳定transient stability电厂power plant能量输送power transfer交流AC直流DC电网power system落点drop point开关站switch station调节regulation高抗high voltage shunt reactor 并列的：apposable裕度margin故障fault三相故障three phase fault分接头：tap切机generator triping高顶值high limited value静态static (state)动态dynamic (state)机端电压控制AVR电抗reactance电阻resistance功角power angle有功（功率）active power电容器：Capacitor电抗器：Reactor断路器：Breaker电动机：motor功率因数：power-factor定子：stator阻抗电压：阻抗：impedance功角：power-angle电压等级：voltage grade有功负载: active load/PLoad无功负载：reactive load档位：tap position电阻：resistor电抗：reactance电导：conductance电纳：susceptance上限:upper limit下限：lower limit正序阻抗：positive sequence impedance 负序阻抗：negative sequence impedance 零序阻抗：zero sequence impedance无功（功率）reactive power功率因数power factor无功电流reactive current斜率slope额定rating变比ratio参考值reference value电压互感器PT分接头tap仿真分析simulation analysis下降率droop rate传递函数transfer function框图block diagram受端receive-side同步synchronization保护断路器circuit breaker摇摆swing阻尼damping无刷直流电机：Brusless DC motor刀闸(隔离开关)：Isolator机端generator terminal变电站transformer substation永磁同步电机：Permanent-magnet Synchronism Motor异步电机：Asynchronous Motor三绕组变压器：three-column transformer ThrClnTrans双绕组变压器：double-column transformer DblClmnTrans固定串联电容补偿fixed series capacitor compensation双回同杆并架double-circuit lines on the same tower单机无穷大系统one machine - infinity bus system励磁电流：magnetizing current 补偿度degree of compensation电磁场Electromagnetic fields失去同步loss of synchronization装机容量installed capacity 无功补偿reactive power compensation故障切除时间fault clearing time极限切除时间critical clearing time强行励磁reinforced excitation并联电容器：shunt capacitor线路补偿器LDC(line drop compensation) 电机学Electrical Machinery自动控制理论Automatic Control Theory电磁场Electromagnetic Field微机原理Principle of Microcomputer电工学Electrotechnics Principle of circuits 电力系统稳态分析Steady-State Analysis of Power System电力系统暂态分析Transient-State Analysis of PowerSystem电力系统继电保护原理Principle of Electrical System's RelayProtection电力系统元件保护原理Protection Principle of Power System 'sElement电力系统内部过电压Past Voltage within Power system模拟电子技术基础Basis of AnalogueElectronic Technique数字电子技术Digital Electrical Technique 电路原理实验Lab. of principle of circuits电气工程讲座Lectures on electrical power production电力电子基础Basic fundamentals of power electronics高电压工程High voltage engineering电子专题实践Topics on experimental project ofelectronics电气工程概论Introduction to electrical engineering电子电机集成系统electronic machine system电力传动与控制Electrical Drive and Control 电力系统继电保护Power System Relaying ProtectionBOX 组件Plastic 塑胶cabinet 壳cover 上盖support 下盖top 上部bottom 底部cap (帽,杯)housing 壳insert(型,芯)Box 组件holder 支座roller 转子belt 皮带impeller风扇case 箱filter 滤网flex hose 软管metal 金属shaft 轴gear 齿轮washer 垫片die cast 铸件nut 螺母bush 轴套chuck 锁头screw 螺丝ring 垫圈spring 弹弓bit 铁嘴plate 片bar 杆spindle轴芯pin 小轴bearing 轴承thread 螺纹powder metal 粉末冶金key 锁匙pinion 小齿轮electric 电气件nameplate 铭牌cord 电线cable 电缆motor 电机switch 开关plug插头fuse 保险丝battery电池button 按钮cell电池adaptor 火牛socket插座P.C.B 电路板charger 充电座/器HI-POT高压测试timer定时器Power pack 电池组resistor电阻IC集成电路terms 术语toque 扭矩force 力speed 速度rating 额定值sampling 抽样fitting 装配futtonal 功能part line分型线aperance 外观testure 纹理vibration 振动finished 表面处理cavity 模腔model 型号part 零件assembly 部件accessory附件remark 注释mark 标记approve 认可defect 缺陷nonconformity 不合格comformity 合格sinkage 缩水burr 毛刺flash 披锋sharp edge 尖缘scratch刮花flow mark 流痕weld line 夹水纹rusty 铸跡hardness 硬度treatment 热处理cycle 循环freouency频数description名称inspection 检验check 检查dispose 处理injection注射revise 更改material 材料purchasing 采购gate 水口current 电流voltage电压power功率I.N.T接触不良rework 加工sort 拣货A.O.D 有偏差接收reject 退货Sketch 简图urgent 紧急Tolerance 公差fit配合Run-out跳动dimention 尺寸AQL 允收水准solenoid valve 电磁阀abort 中断,停止abnormal 异常abrader 研磨,磨石,研磨工具absence 失去Absence of brush 无(碳)刷Absolute ABS 绝对的Absolute atmosphere ATA 绝对大气压AC Lub oil pump 交流润滑油泵absorptance 吸收比,吸收率acceleration 加速accelerator 加速器accept 接受access 存取accomplish 完成,达到accumulator 蓄电池,累加器Accumulator battery 蓄电池组accuracy 准确,精确acid 酸性,酸的Acid washing 酸洗acknowledge 确认,响应acquisition 发现,取得action 动作Active power 有功功率actuator 执行机构address 地址adequate 适当的，充分的adjust 调整，校正Admission mode 进汽方式Aerial line 天线after 以后air 风，空气Air compressor 空压机Air duct pressure 风管压力Air ejector 抽气器Air exhaust fan 排气扇Air heater 空气加热器Air preheater 空气预热器Air receiver 空气罐Alarm 报警algorithm 算法Attempt 企图Attemperater 减温器，调温器Attention 注意Attenuation 衰減,减少,降低Auto reclose 自动重合闸Auto transfer 自动转移Autoformer 自耦变压器Automatic AUTO 自动Automatic voltage regulator 自动调压器Auxiliary AUX 辅助的Auxiliary power 厂用电Available 有效的,可用的Avoid 避免,回避Avometer 万用表,安伏欧表计Axial 轴向的Axis 轴,轴线Axis disp protection 轴向位移，保护Axle 轴，车轴，心捧BBack 背后，反向的Back pressure 背压Coil 线圈Coil pipe 蛇形管Cold 冷Cold air 冷风Cold reheater CRH 再热器冷段Cold reserve 冷备用（锅炉）Cold start 冷态启动Cold test 冷态试验Collect 收集Collecting pipe 集水管Collector 收集器Colour 颜色Colour library 颜色库Combin 合并、联合Combustion 燃烧Command 命令、指挥Commission 使投入、使投产Common 共同的、普通的Communication 联系、通讯Commutator 换向器Compensation 补偿Electrical machine 电机Electrical service 供电Electric power industry 电力工业Electrode 电极Electric power company 电力公司Electric power system 电力系统Electronic 电子的、电子学的Electrotechnics 电工学、电工技术Electrostaic precipitator 静电除尘器Electrostatic 静电的Extra-high voltage超高压Extend扩展、延伸Exteral外部的、表面的Extr press抽汽压力Extr temp抽汽温度Extraction EXTR抽汽Flexible 灵活的、柔性的Flexible joint 弹性联接器Furnace 炉膛Fuse 保险丝、熔断器Fuse holder 保险盒Fusible cutout 熔断开关Fw bypass 给水旁路GGAIN 增益Gang 班、组Gas 气体、烟气Gate 闸门Gate damper 闸门式挡板Gateway 入口、途径Gauge 仪表、标准Gauge float 水位、指示、浮标Gear 齿轮Gear pump 齿轮泵Gear shift housing 变速箱Gen main breaker 发电机出口总开关General control panel 总控制屏General vlv 总阀Generate 引起、产生Generator 发电机、发生器Gland 密封套Gland heater GLAND HTR 轴封加热器Gland seal 轴封Glass-paper 砂纸Goal 目的、目标Go on 继续Govern vlv GV 调速器、调节器Graphics 调节阀Grease 图形Green 绿色Grid 高压输电网、铅板Grid system 电网系统Performance 完成、执行、性能Performance calculation 性能计算Performance curve 性能曲线Periodic 周期的、循环的Periodic inspection 定期检查Peripheral 周围的Peripheral equipment 外围设备Permanent 永久的、持久的Permanent magneticgenerator永磁发电机Permit 允许Permit to work 允许开工Petrol 汽油Plunger 柱塞、滑阀Plunger pump 柱塞泵Plus 加Plyers 钳子、老虎钳Pneumatic 气动的Point 点Point database 测点数据库Point directory 测点目录Point name 测点名Point record 测点记录Point field 泡克区Phase voltage 相电压Pole 机、柱Policher 除盐装置Pollution 污染Pop valve 安全阀、突开阀Portion 一部分Position POS 位置Positive 确定的、正的、阳性的Potable water 饮用水Potential transformer PT 电压互感器Tank 箱Tap 抽头、分布Tape armour 钢带铠装Taper 锥体、楔销Taper key 斜键、楔键Taper pin 锥形销、斜销Target 目标T-beam 丁字梁Temperature 温度Temperature compensation 温度补偿Temperature liming relay 热继电器Tempered 热处理的Template 模板、样板Tensile 拉力的、张力的Total control unit TCU 总控单元T-junction 三通三、模具注塑模具injection mold 冲压模具Stamping tool 模架mold base定模座板Fixed clamp plate A板A plate B板B plate支承板 support plate 方铁 spacer plate 回位销 Return pin 导柱 Guide pin动模座板Moving clamp plate 顶针ejector pin单腔模具single cavity mold 多腔模具multi-cavity mold 浇口gate合模力clamping force锁模力locking force 开裂crack循环时间cycle time 老化aging 螺杆screw 镶件 Insert 主流道 sprue 分流道runner 浇口gate直浇口 direct gate 点浇口pin-point gate 测浇口edge gate潜伏浇口submarine gate 浇口套sprue bush 流道板runner plate 排气槽vent 分型线（面）parting line 定模Fixed mold 动模movable mold 型腔cavity凹模cavity plate，凸模core plate 斜销angle pin 滑块slide拉料杆sprue puller 定位环locating ring 脱模斜度draft 滑动型芯slide core 螺纹型芯threaded core热流道模具hot-runner mold 熔合纹weld line三板式模具three plate mold 脱模ejection 脱模剂release agent 注射能力shot capacity 注射速率injection rate 注射压力injection pressure 保压时间holding time 闭模时间closing time电加工设备Electron Discharge Machining 数控加工中心CNC machine center 万能铁床Universal milling machine 平面磨床Surface grinding machine万能摇臂钻床Universal radial movable driller立式钻床Vertical driller 倒角chamfer 键Key键槽keyway 间距pitch快速成型模Rapid prototype tool （RPT）四、品管SPC statistic process control品质保证Quality Assurance(QA) 品质控制Quality control(QC) 来料检验IQC Incoming quality control 巡检IPQC In-process quality control 校对calibration环境试验Environmental test 光泽gloss拉伸强度tensile strength 盐雾实验salt spray test 翘曲warp比重specific gravity 疲劳fatigue撕裂强度tear strength 缩痕sink mark 耐久性durability 抽样sampling样品数量sample sizeAQL Acceptable Quality level 批量lot size 抽样计划sampling plan 抗张强度 Tensile Strength 抗折强度 Flexural Strength 硬度 Rigidity色差 Color Difference涂镀层厚度 Coating Thickness 导电性能 Electric Conductivity 粘度 viscosity 附着力 adhesion耐磨 Abrasion resistance 尺寸 Dimension (喷涂)外观问题 Cosmetic issue 不合格品 Non-conforming product 限度样板 Limit sample五、生产注塑机injection machine冲床Punch machine 嵌件注塑 Insert molding双色注塑 Double injection molding 薄壁注塑 Thin wall molding膜内注塑 IMD molding ( In-mold decoration）移印 Tampo printing 丝印 Silk screen printing 热熔 Heat staking超声熔接 Ultrasonic welding (USW）尼龙nylon 黄铜 brass 青铜 bronze 紫(纯)铜 copper 料斗hopper 麻点pit配料compounding 涂层coating 飞边flash 缺料 Short mold 烧焦 Burn mark 缩水 Sink mark 气泡 Bubbles 破裂 Crack熔合线 Welding line 流痕 Flow mark 银条 Silver streak 黑条 Black streak表面光泽不良 Lusterless 表面剥离 Pelling 翘曲变形 Deformation 脏圬 Stain mark 油污 Oil mark蓝黑点 Blue-black mark 顶白 Pin mark 拉伤 Scratch限度样品 Limit sample 最佳样品 Golden sample 预热preheating再生料recycle material 机械手 Robot机器人 Servo robot试生产 Trial run; Pilot run (PR) 量产 mass production 切料头 Degate保质期shelf lifeABC分类法ABC Classification 装配Assembly平均库存Average Inventory 批号Batch Number批量生产Mass Production 提货单Bill of Lading 物料清单Bill of Material 采购员Buyer检查点Check Point 有效日期Date Available 修改日期Date Changed 结束日期Date Closed 截止日期Date Due 生产日期Date in Produced库存调整日期Date Inventory Adjust 作废日期D ate Obsolete 收到日期Date Received 交付日期Date Released 需求日期Date Required需求管理Demand Management 需求Demand工程变更生效日期Engineering Change Effect Date 呆滞材料分析Excess Material Analysis 完全跟踪Full Pegging在制品库存In Process Inventory 投入/产出控制Input/ Output Control 检验标识Inspection ID库存周转率Inventory Carry Rate 准时制生产Just-in-time (JIT) 看板Kanban人工工时Labor Hour最后运输日期Last Shipment Date 提前期Lead Time 负荷Loading仓位代码Location Code 仓位状况Location Status 批量标识Lot ID批量编号Lot Number 批量Lot Size 机器能力Machine Capacity 机器加载Machine Loading制造周期时间Manufacturing Cycle Time 制造资源计划Manufacturing Resource Planning (MRP II) 物料成本Material Cost物料发送和接收Material Issues and Receipts物料需求计划Material Requirements Planning (MRP) 现有库存量On-hand Balance 订单输入Order Entry 零件批次Part Lot零件编号Part Number (P/N) 零件Part领料单Picking List 领料/提货Picking 产品控制Product Control 产品线Production Line采购订单跟踪Purchase Order Tracking 需求量Quantity Demand 毛需求量Quantity Gross 安全库存量Safety Stock 在制品Work in Process 零库存Zero Inventories。
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Compariso
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer ComparisonsClifford E. Cummings Peter AlfkeSunburst Design, Inc. Xilinx, Inc.SNUG-2002San Jose, CAVoted Best Paper1st Place ABSTRACTAn interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper.To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the builtin binary ripple carry logic.The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #2) is included.This FIFO design paper builds on information already presented in another FIFO design paper where the FIFO pointers are synchronized into the opposite clock domain before running "FIFO full" or "FIFO empty" tests. The reader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method.Post-SNUG Editorial Comment (by Cliff Cummings)Although this paper was voted “Best Paper - 1st Place” by SNUG attendees, this paper builds off of a second FIFO paper listed as reference [1]. The first FIFO paper laid the foundation for some of the content of this paper; therefore, it is highly recommended that readers download and read the FIFO1 paper[1] to acquire background information already assumed to be known by the reader of this paper.1.0 IntroductionAn asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer using one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain, where the two clock domains are asynchronous to each other.One common technique for designing an asynchronous FIFO is to use Gray[4] code pointers that are synchronized into the opposite clock domain before generating synchronous FIFO full or empty status signals[1]. An interesting and different approach to FIFO full and empty generation is to do an asynchronous comparison of the pointers and then asynchronously set the full or empty status bits[6].This paper discusses the FIFO design style with asynchronous pointer comparison and asynchronous full and empty generation. Important details relating to this style of asynchronous FIFO design are included. The FIFO style implemented in this paper uses efficient Gray code counters, whose implementation is described in the next section.2.0 Gray code counter - style #2One Gray code counter style uses a single set of flip-flops as the Gray code register with accompanying Gray-to binary conversion, binary increment, and binary-to-Gray conversion[1].A second Gray code counter style, the one described in this paper, uses two sets of registers, one a binary counter and a second to capture a binary-to-Gray converted value. The intent of this Gray code counter style #2 is to utilize the binary carry structure, simplify the Gray-to-binary conversion; reduce combinational logic, and increase the upper frequency limit of the Gray code counter.The binary counter conditionally increments the binary value, which is passed to both the inputs of the binary counter as the next-binary-count value, and is also passed to the simple binary-to-Gray conversion logic, consisting of one 2-input XOR gate per bit position. The converted binary value is the next Gray-count value and drives the Gray code register inputs.Figure 1 shows the block diagram for an n-bit Gray code counter (style #2).This implementation requires twice the number of flip-flops, but reduces the combinatorial logic and can operate at a higher frequency. In FPGA designs, availability of extra flip-flops is rarely a problem since FPGAs typically contain far more flip-flops than any design will ever use. In FPGA designs, reducing the amount of combinational logic frequently translates into significant improvements in speed.The ptr output of the block diagram in Figure 1 is an n-bit Gray code pointer.Note: since the MSB of a binary sequence is equal to the MSB of a Gray code sequence, this design can be further simplified by using the binary MSB-flip-flop as the Gray codeMSB-flip-flop. The Verilog code in this paper did not implement this additional optimization. This would save one flip-flop per pointer.3.0 Full & empty detectionAs with any FIFO design, correct implementation of full and empty is the most difficult part of the design.There are two problems with the generation of full and empty:First, both full and empty are indicated by the fact that the read and write pointers are identical. Therefore,something else has to distinguish between full and empty. One known solution to this problem appends an extra bit to both pointers and then compares the extra bit for equality (for FIFO empty) or inequality (for FIFO full), along with equality of the other read and write pointer bits[1].Another solution, the one described in this paper, divides the address space into four quadrants and decodes the two MSBs of the two counters to determine whether the FIFO was going full or going empty at the time the two pointers became equal.If the write pointer is one quadrant behind the read pointer, this indicates a "possibly going full" situation as shown in Figure 2. When this condition occurs, the direction latch of Figure 4 is set.Figure 3 - FIFO is going empty because the rptr trails the wptr by one quadrantIf the write pointer is one quadrant ahead of the read pointer, this indicates a "possibly going empty" situation as shown in Figure 3. When this condition occurs, the direction latch of Figure 4 is cleared.When the FIFO is reset the direction latch is also cleared to indicate that the FIFO “is going empty” (actually, it is empty when both pointers are reset). Setting and resetting the direction latch is not timing-critical, and the direction latch eliminates the ambiguity of the address identity decoder.The Xilinx FPGA logic to implement the decoding of the two wptr MSBs and the two rptr MSBs is easily implemented as two 4-input look-up tables.The second, and more difficult, problem stems from the asynchronous nature of the write and read clocks. Comparing two counters that are clocked asynchronously can lead to unreliable decoding spikes when either or both counters change multiple bits more or less simultaneously. The solution described in this paper uses a Gray count sequence, where only one bit changes from any count to the next. Any decoder or comparator will then switch only from one valid output to the next one, with no danger of spurious decoding glitches.4.0 FIFO style #2For the purposes of this paper, FIFO style #1 refers to a FIFO implementation style that synchronizes pointers from one clock domain to another before generating full and empty flags [1].The FIFO style described in this paper (FIFO style #2) does asynchronous comparison between Gray code pointers to generate an asynchronous control signal to set and reset the full and empty flip-flops.The block diagram for FIFO style #2 is shown in Figure 5.To facilitate static timing analysis of the style #2 FIFO design, the design has been partitioned into the following five Verilog modules with the following functionality and clock domains:•fifo2.v - (see Example 1 in section 5.1) - this is the top-level wrapper-module that includes all clock domains. The top module is only used as a wrapper to instantiate all of the other FIFO modules used in the design. If this FIFO is used as part of a larger ASIC or FPGA design, thistop-level wrapper would probably be discarded to permit grouping of the other FIFO modules into their respective clock domains for improved synthesis and static timing analysis.fifomem.v - (see Example 2 in section 5.2) - this is the FIFO memory buffer that is accessed by both the write and read clock domains. This buffer is most likely an instantiated, synchronous dual-port RAM. Other memory styles can be adapted to function as the FIFO buffer.•async_cmp.v - (see Example 3 in section 5.3) - this is an asynchronous pointer-comparison module that is used to generate signals th at control assertion of the asynchronous “full” and “empty” status bits. This module only contains combinational comparison logic. No sequential logic is included in this module.•rptr_empty.v - (see Example 4 in section 5.4) - this module is mostly synchronous to the read-clock domain and contains the FIFO read pointer and empty-flag logic. Assertion of the aempty_n signal (an input to this module) is synchronous to the rclk-domain, sinceaempty_n can only be asserted when the rptr incremented, but de-assertion of the aempty_n signal happens when the wptr increments, which is asynchronous to rclk.•wptr_full.v - (see Example 5 in section 5.5) - this module is mostly synchronous to the write-clock domain and contains the FIFO write pointer and full-flag logic. Assertion of theafull_n signal (an input to this module) is synchronous to the wclk-domain, since afull_n can only be asserted when the wptr incremented (and wrst_n), but de-assertion of theafull_n signal happens when the rptr increments, which is asynchronous to wclk.5.0 RTL code for FIFO style #2The Verilog RTL code for the FIFO style #2 model is listed in this section.5.1 fifo2.v - FIFO top-level moduleThe fifo2 top-level module is a parameterized module with all sub-blocks instantiated following safe coding practices using named port connections.module fifo2 (rdata, wfull, rempty, wdata,winc, wclk, wrst_n, rinc, rclk, rrst_n);parameter DSIZE = 8;parameter ASIZE = 4;output [DSIZE-1:0] rdata;output wfull;output rempty;input [DSIZE-1:0] wdata;input winc, wclk, wrst_n;input rinc, rclk, rrst_n;wire [ASIZE-1:0] wptr, rptr;wire [ASIZE-1:0] waddr, raddr;async_cmp #(ASIZE) async_cmp(.aempty_n(aempty_n), .afull_n(afull_n),.wptr(wptr), .rptr(rptr), .wrst_n(wrst_n));fifomem #(DSIZE, ASIZE) fifomem(.rdata(rdata), .wdata(wdata),.waddr(wptr), .raddr(rptr),.wclken(winc), .wclk(wclk));rptr_empty #(ASIZE) rptr_empty(.rempty(rempty), .rptr(rptr),.aempty_n(aempty_n), .rinc(rinc),.rclk(rclk), .rrst_n(rrst_n));wptr_full #(ASIZE) wptr_full(.wfull(wfull), .wptr(wptr),.afull_n(afull_n), .winc(winc),.wclk(wclk), .wrst_n(wrst_n));endmoduleExample 1 - Top-level Verilog code for the FIFO style #2 design5.2 fifomem.v - FIFO memory bufferThe FIFO memory buffer could be an instantiated ASIC or FPGA dual-port, synchronous memory device. The memory buffer could also be synthesized to ASIC or FPGA registers using the RTL code in this module.If a vendor RAM is instantiated, it is highly recommended that the instantiation be done using named port connections.module fifomem (rdata, wdata, waddr, raddr, wclken, wclk);parameter DATASIZE = 8; // Memory data word widthparameter ADDRSIZE = 4; // Number of memory address bitsparameter DEPTH = 1<<ADDRSIZE; // DEPTH = 2**ADDRSIZEoutput [DATASIZE-1:0] rdata;input [DATASIZE-1:0] wdata;input [ADDRSIZE-1:0] waddr, raddr;input wclken, wclk;`ifdef VENDORRAM// instantiation of a vendor's dual-port RAMVENDOR_RAM MEM (.dout(rdata), .din(wdata),.waddr(waddr), .raddr(raddr),.wclken(wclken), .clk(wclk));`elsereg [DATASIZE-1:0] MEM [0:DEPTH-1];assign rdata = MEM[raddr];always @(posedge wclk)if (wclken) MEM[waddr] <= wdata;`endifendmoduleExample 2 - Verilog RTL code for the FIFO buffer memory array5.3 async_cmp.v - Asynchronous the full/empty comparison logicThe logic used to determine the full or empty status on the FIFO is the most distinctive difference between FIFO style #1 and FIFO style #2.Async_cmp is an asynchronous comparison module, used to compare the read and write pointers to detect full and empty conditions.module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);parameter ADDRSIZE = 4;parameter N = ADDRSIZE-1;output aempty_n, afull_n;input [N:0] wptr, rptr;input wrst_n;reg direction;wire high = 1'b1;wire dirset_n = ~( (wptr[N]^rptr[N-1]) & ~(wptr[N-1]^rptr[N]));wire dirclr_n = ~((~(wptr[N]^rptr[N-1]) & (wptr[N-1]^rptr[N])) |~wrst_n);always @(posedge high or negedge dirset_n or negedge dirclr_n)if (!dirclr_n) direction <= 1'b0;else if (!dirset_n) direction <= 1'b1;else direction <= high;//always @(negedge dirset_n or negedge dirclr_n)//if (!dirclr_n) direction <= 1'b0;//else direction <= 1'b1;assign aempty_n = ~((wptr == rptr) && !direction);assign afull_n = ~((wptr == rptr) && direction);endmoduleExample 3 - Verilog RTL code for the asynchronous comparator moduleThree of the last seven lines of the Verilog code of Example 3 have been commented out in this model. In theory, a synthesis tool should be capable of inferring an RS-flip-flop from the comment-removed code, but the LSI_10K library that is included with the default installation of the Synopsys tools did not infer a correct RS-flip-flop with this code when tested, so the always block immediately preceding the commented code was added to infer an RSflip-flop.5.3.1 Asynchronous generation of full and emptyIn the async_cmp code of Example 3, and shown in Figure 6, aempty_n and afull_n are the asynchronously decoded signals. The aempty_n signal is asserted on the rising edge of an rclk, but is de-asserted on the rising edge of a wclk. Similarly, the afull_n signal is asserted on a wclk and removed on an rclk.The empty signal will be used to stop the next read operation, and the leading edge of aempty_n is properly synchronous with the read clock, but the trailing edge needs to be synchronized to the read clock. This is done in a two-stage synchronizer that generates rempty.The wfull signal is generated in the symmetrically equivalent way.5.3.2 Resetting the FIFOThe first FIFO event of interest takes place on a FIFO-reset operation. When the FIFO is reset, four important things happen within the async_cmp module and accompanying full and empty synchronizers of the wptr_full and rptr_empty modules (the connections between the async_cmp, wptr_full and rptr_empty modules are shown in Figure 7):1. The reset signal directly clears the wfull flag. The rempty flag is not cleared by a reset.2. The reset signal clears both FIFO pointers, so the pointer comparator asserts that the pointers are equal.3. The reset clears the direction bit.4. With the pointers equal and the direction bit cleared, the aempty_n bit is asserted, which presets the rempty flag.5.3.3 FIFO-writes & FIFO fullThe second FIFO operational event of interest takes place when a FIFO-write operation takes place and the wptr is incremented. At this point, the FIFO pointers are no longer equal so the aempty_n signal is de-asserted, releasing the preset control of the rempty flip-flops. After two rising edges on rclk, the FIFO will de-assert the rempty signal. Because the de-assertion of aempty_n happens on a rising wclk and because the rempty signal is clocked by the rclk, the two-flip-flop synchronizer as shown in Figure 8 is required to remove metastability that could be generated by the first rempty flip-flop.The second FIFO operational event of interest takes place when the wptr increments into the next Gray code quadrant beyond the rptr (see section 3.0 for a discussion of Gray code quadrants). The direction bit is cleared (but it was already clear).The third FIFO operational event of interest occurs when the wptr is within one quadrant of catching up to the rptr as described in section 3.0. When this happens, the dirset_n bit of Figure 6 is asserted low, which sets the direction bit high. This means that the direction bit is set long before the FIFO is full and is not timingcritical to assertion of the afull_n signal. The fourth FIFO operational event of interest is when the wptr catches up to the rptr (and the direction bit is set). When this happens, the afull_n signal presets the wfull flip-flops. The afull_n signal is asserted on a FIFO-write operation and is synchronous to the rising edge of the wclk; therefore, asserting full is synchronous to the wclk. See section 5.3.6 for a discussion of the critical timing path associated with assertion of the wfull signal.The fifth FIFO operational event of interest is when a FIFO-read operation takes place and the rptr is incremented. At this point, the FIFO pointers are no longer equal so the afull_n signal is de-asserted, releasing the preset control of the wfull flip-flops. After two rising edges on wclk, the FIFO will de-assert the wfull signal. Because the de-assertion of afull_n happens on a rising rclk and because the wfull signal is clocked by the wclk, the two-flip-flop synchronizer, shown in Figure 8, is required to remove metastability that could be generated by the first wfull flip-flop capturing the inverted and asynchronously generated afull_n data input.During operation, wfull is generated synchronous to the write clock, in a similar way that rempty is generated synchronous to the read clock. The afull_n signal is asserted as a result of a write clock, and the leading (falling) edge is thus naturally synchronous to the write clock. The trailing (rising) edge is, however caused by the read clock, and must, therefore be synchronized to thewrite clock. The same timing issues related to the setting of the full flag also apply to the setting of the empty flag.5.3.4 FIFO-reads & FIFO emptyThe sixth FIFO operational event of interest takes place when the rptr increments into the next Gray code quadrant beyond the wptr. The direction bit is again set (but it was already set). The seventh FIFO operational event of interest occurs when the rptr is within one quadrant of catching up to the wptr. When this happens, the dirrst bit of Figure 6 is asserted high , which clears the direction bit. This means that the direction bit is cleared long before the FIFO is empty and is not timing critical to assertion of the aempty_n signal.The eighth FIFO operational event of interest is when the rptr catches up to the wptr (and the direction bit is zero). When this happens, the aempty_n signal presets the remptyflip-flops. The aempty_n signal is asserted on a FIFO-read operation and is synchronous to the rising edge of the rclk; therefore, asserting empty is synchronous to the rclk. See section 5.3.6 for a discussion of the critical timing path associated with assertion of the rempty signal. Finally, when a FIFO-write operation takes place and the wptr is incremented. At this point, the FIFO pointers are no longer equal so the aempty_n signal is de-asserted, releasing the preset control of the rempty flip-flops. After two rising edges on rclk, the FIFO will de-assert the rempty signal. Because the de-assertion of aempty_n happens on a rising wclk and because the rempty signal is clocked by the rclk, the two-flip-flop synchronizer as shown in Figure 8 is required to remove metastability that could be generated by the first rempty flip-flop.5.3.5 Alternate method to preset the full & empty flagsAnother method for setting the rempty or wfull flags is to use a self-timed differentiating circuit as shown in Figure 9. In this figure, the flip-flops are shown with high-true presets, similar to what is found on Xilinx FPGAs.(equivalent circuitry could also be designed using low-true presets). When the aempty signal goes high, the rempty output flip-flop is preset and assuming that the signal between the flip-flops was low, this signal combined with aempty-high will drive the output of the and gate high and set the first flip-flop. When the first flip-flop is set,the and gate will quit driving the preset signal to the first flip-flop. This is a self-timed preset signal that releases preset immediately after preset occurs, well before the aempty signal goes low.5.3.6 Full and empty critical timing pathsUsing the asynchronous comparison technique described in this paper, there are critical timing paths associated with the generation of both the rempty and wfull signals.The rempty critical timing path, shown in Figure 10, consists of (1) the rclk-to-q incrementing of the rptr, (2) comparison logic of the rptr to the wptr, (3) combining the comparator output with the direction latch output to generate the aempty_n signal, (4) presetting the rempty signal,(5) any logic that is driven by the rempty signal, and (6) resultant signals meeting the setup time of any down-stream flip-flops clocked within the rclk domain. This critical timing path has a symmetrically equivalent critical timing path for the generation of the wfull signal, also shown in Figure 10.5.3.7 Asynchronous concerns, questions and answersWhile writing this paper, the authors asked and answered numerous questions to address concerns over the highly asynchronous nature of the generation and removal of the full and empty bits for the FIFO style described in this paper. This section captures a number of the questions, concerns and answers that lead both authors to believe this coding style does indeed work. Generation of the aempty_n control signal is straightforward. Whenever the read pointer (rptr) equals the write pointer (wptr), and the direction latch is clear, the FIFO is empty. The empty flag is used only in the read clock domain and since the read pointer, incremented by a read clock,causes the empty flag to be set, assertion of the empty flag is always synchronous in the read clock domain. As long as the empty flag meets the critical empty-assertion timing path described in section 5.3.6, there is no synchronization problems associated with asserting the empty flag.The de-assertion of aempty_n is caused by the write clock incrementing the write pointer, and is thus unrelated to the read clock. The de-assertion of aempty_n must, therefore, be synchronized in a dual-flip-flop synchronizer, clocked by the read clock. The first flip-flop is subject to metastability but the second flip-flop is included to wait for the metastability to subside, just like any other multi-clock synchronizer[2].Since aempty_n is started by one clock and terminated by the other, it has an undefined duration,and might even be a runt pulse. A runt pulse is a Low-High-Low signal transition where the transition to High may or may not pass through the logic-“1” threshold level of the logic family being used.If the aempty_n control signal is a runt pulse, there are four possible scenarios that should be addressed:(1) the runt signal is not recognized by the rempty flip-flops and empty is not asserted. This is not a problem.(2) The runt pulse might preset the first synchronizer flip-flop, but not the second flip-flop. This is highly unlikely, but would result in an unnecessary, but properly synchronized rempty output, that will show up on the output of the second flip-flop one read clock later. This is not a problem.(3) The runt pulse might preset the second synchronizer flip-flop, but not the first flip-flop. This is highly unlikely,but would result in an unnecessary, but properly synchronized rempty output (as long as the empty critical timing is met), that will be set on the output of the second flip-flop until the next read clock, when it will be cleared by the zero from the first flip-flop. This is not a problem.(4) The most likely case is that the runt pulse sets both flip-flops, thus creating a properly synchronized rempty output that is two read-clock periods long. The longer duration is caused by the two-flip-flop synchronizer ( to avoid metastable problems as described below). This is not a problem.The runt pulse cannot have any effect on the synchronizer data-input, since an aempty_n runt pulse can only occur immediately after a read clock edge, thus long before the next read clock edge (as long as critical timing is met).The aempty_n signal might also stay high longer and go low at any moment, even perhaps coincident with the next read clock edge. If it goes low well before the set-up time of the first synchronize flip-flop, the result is like scenario (4) above. If it goes low well after the set-up time, the synchronizer will stretch rempty by one more read clock period.If aempty_n goes low within the metstability-catching set-up time window, the first synchronizer flip-flop output will be indeterminate for a few nanoseconds, but will then be either high or low. In either case, the output of the second synchronizer flip-flop will create the appropriate synchronized rempty output.The next question is, what happens if the write clock de-asserts the aempty_n signal coincident with the rising rclk on the dual synchronizer? The first flip-flop could go metastable, which is why there is a second flip-flop in the dual synchronizer.But the removal of the setting signal on the second flip-flop will violate the recovery time of the second flip-flop.Will this cause the second flip-flop to go metastable? The authors do not believe this can happen because the preset to the flip-flop forced the output high and the input to the same flip-flop is already high, which we believe is not subject to a recovery time instability on the flip-flop.Challenge: if anyone can prove that a flip-flop that is set high, and is also driven by ahigh-data-input signal, can go metastable if the preset signal is removed coincident with the rising edge of the clock to the same flip-flop, the authors would like to be made aware of any such claim. The authors believe that recovery time parameters are with respect to removing a preset when the data input value is zero. The authors could not find any published reference to discount the possibility of metastability on the output of the second flip-flop but we believe that metastabilityin this case is not possible.Last question. Can a runt-preset pulse, where the trailing edge of the runt pulse is caused by the wclk, preset the second synchronizer flip-flop in close proximity to a rising rclk, violate the preset recovery time and cause metastability on the output of the second flip-flop? The answer is no as long as the aempty_n critical timing path is met. Assuming that critical timing is met, the aempty_n signal going low should occur shortly after a rising rclk and well before the rising edge of the second flip-flop, so runt pulses can only occur well before the rising edge of an rclk.Again, symmetrically equivalent scenarios and arguments can be made about the generation of the wfull flag.5.4 rptr_empty.v - Read pointer & empty generation logicThis module encloses all of the FIFO logic that is generated within the read clock domain (except synchronizers).The read pointer is an n-bit Gray code counter. The FIFO rempty output is asserted when the aempty_n signal goes low and the rempty output is de-asserted on the second rising rclk edge after aempty_n goes high (a rare metastable state could cause the rempty output to be de-asserted on the third rising rclk edge). This module is completely synchronous to the rclk for simplified static timing analysis, except for the aempty_n input, which is de-asserted asynchronously to the rclk.module rptr_empty (rempty, rptr, aempty_n, rinc, rclk, rrst_n); parameter ADDRSIZE = 4;output rempty;output [ADDRSIZE-1:0] rptr;input aempty_n;input rinc, rclk, rrst_n;reg [ADDRSIZE-1:0] rptr, rbin;reg rempty, rempty2;wire [ADDRSIZE-1:0] rgnext, rbnext;//---------------------------------------------------------------// GRAYSTYLE2 pointer//--------------------------------------------------------------- always @(posedge rclk or negedge rrst_n)if (!rrst_n) beginrbin <= 0;rptr <= 0;endelse beginrbin <= rbnext;rptr <= rgnext;end//---------------------------------------------------------------// increment the binary count if not empty//--------------------------------------------------------------- assign rbnext = !rempty ? rbin + rinc : rbin;assign rgnext = (rbnext>>1) ^ rbnext; // binary-to-gray conversion。
网络教学和传统教学的对比英语作文
网络教学和传统教学的对比英语作文Answer in English.Thesis: Online learning and traditional face-to-face instruction are two distinct approaches to education, each with its own set of advantages and drawbacks.Introduction:In the realm of education, the emergence of online learning has sparked a significant debate, pitting it against the traditional brick-and-mortar model. While both approaches aim to impart knowledge and skills, they differ in their delivery methods and learning experiences. This essay will delve into a comprehensive comparison of online learning and traditional teaching, highlighting their respective strengths, weaknesses, and implications for the future of education.Body:Convenience and Accessibility:Online learning: Offers unparalleled convenience and accessibility, allowing students to learn from anywhere with an internet connection. This flexibility is particularly beneficial for working professionals, individuals with limited mobility, or those living in remote areas.Traditional teaching: Requires students to be physically present at a specific location and time, limiting accessibility for those with busy schedules or geographic constraints.Cost:Online learning: Typically involves lower tuition costs and fees compared to traditional education, as it eliminates the need for physical infrastructure and on-campus resources.Traditional teaching: Involves higher costs associated with campus facilities, faculty salaries, and other expenses, which can burden students with hefty tuition bills.Flexibility and Customization:Online learning: Allows for flexible scheduling and self-paced learning, enabling students to tailor their studies to their individual needs and preferences.Traditional teaching: Offers a more structured and fixed schedule, providing a consistent learning experience but with less flexibility.Interaction and Collaboration:Online learning: Can provide opportunities for asynchronous communication through discussion boards and virtual meetings but may limit real-time interactions and group work.Traditional teaching: Fosters face-to-face interactions, group discussions, and hands-on activities, enhancing collaboration and social connections.Technology and Resources:Online learning: Heavily relies on technology and digital resources, requiring students to have access to reliable devices and internet connections.Traditional teaching: Incorporates both technology and traditional resources (e.g., textbooks, library), providing students with a broader range of learning materials.Assessment and Evaluation:Online learning: Employs various online assessment tools, such as quizzes, assignments, and proctored exams, but may pose challenges in evaluating practical skills or subjective responses.Traditional teaching: Allows for a wider range ofassessment methods, including oral presentations, physical demonstrations, and written examinations, providing a more comprehensive evaluation.Conclusion:Online learning and traditional teaching present unique advantages and challenges for students. The choice between the two ultimately depends on individual needs, learning styles, and circumstances. While online learning offers convenience, accessibility, and flexibility, it may lack the same level of personal interaction and real-time collaboration found in traditional teaching. Traditional teaching provides a structured learning environment, fostering social connections and hands-on experiences, but it may not be as convenient or cost-effective for everyone. As technology continues to evolve and education adapts to meet new demands, it is likely that both online learning and traditional teaching will continue to coexist and complement each other, offering learners a diverse range of educational opportunities.Answer in Chinese.对比在线教学和传统教学，各自利弊。
在线学习与传统学习的差异英语作文
在线学习与传统学习的差异英语作文The rapid advancement of technology has revolutionized the way we approach education. In the past, traditional classroom-based learning was the predominant method, where students and teachers physically gathered in a dedicated learning environment. However, the emergence of online learning has introduced a new paradigm, presenting both advantages and challenges when compared to traditional learning. This essay will explore the key differences between online learning and traditional learning, delving into the various aspects that define the educational experience.One of the most significant differences lies in the mode of delivery. Traditional learning typically involves face-to-face interactions between students and instructors, fostering a sense of community and immediate feedback. Classrooms provide a structured environment where students can engage in discussions, ask questions, and receive real-time guidance from their teachers. This interactive dynamic can be particularly beneficial for subjects that require hands-on demonstrations, group collaborations, or in-depth discussions.In contrast, online learning relies on digital platforms and virtual environments to facilitate the educational process. Students access course materials, participate in discussions, and submit assignments through various online tools and learning management systems. While this approach offers flexibility and convenience, it can sometimes lack the personal touch and immediate feedback that characterizes traditional learning. Online learners may have to navigate self-paced modules, asynchronous communication, and rely more on their own discipline and self-motivation to stay engaged.Another key distinction is the aspect of social interaction. Traditional learning settings often foster a sense of community, where students can engage in face-to-face discussions, form study groups, and develop interpersonal relationships with their peers and instructors. This social dynamic can contribute to a deeper understanding of course material, as students can learn from each other's perspectives and experiences. Additionally, the physical presence of an instructor can provide a sense of accountability and motivation, as students may feel more compelled to participate and stay on track.On the other hand, online learning can sometimes feel more isolating, as students may not have the same level of direct social interaction. While online platforms may offer discussion forums, virtual group projects, and opportunities for collaboration, the lackof physical proximity can make it more challenging to build strong social connections. This can be particularly challenging for students who thrive in a more collaborative learning environment or those who require additional support and guidance from their peers and instructors.The accessibility and flexibility of online learning are often cited as significant advantages. Online courses allow students to learn at their own pace, from the comfort of their own homes, and often at a lower cost compared to traditional on-campus programs. This can be particularly beneficial for individuals with busy schedules, those living in remote areas, or those with physical disabilities that may make it difficult to attend in-person classes. Online learning also offers a broader range of course options, as students can access educational resources from institutions around the world, expanding the diversity of available programs.In contrast, traditional learning environments often have more structured schedules and fixed class times, which can be a drawback for students with competing responsibilities. However, this structure can also provide a sense of routine and discipline, which some learners may find beneficial for their academic success.The assessment and evaluation methods also differ between online and traditional learning. In traditional settings, assessments ofteninvolve in-class exams, presentations, and hands-on projects that can be directly observed and evaluated by instructors. This allows for a more comprehensive evaluation of a student's understanding and performance. Online learning, on the other hand, may rely more heavily on written assignments, quizzes, and virtual simulations, which can sometimes make it more challenging to assess certain skills, such as problem-solving or practical application.Additionally, the issue of academic integrity and the potential for cheating can be more prevalent in online learning environments, where it may be more difficult to verify the identity of the student and monitor their activities during assessments. Traditional learning settings often have more robust mechanisms in place to ensure academic integrity, such as proctored exams and direct observation of student work.It is important to note that the effectiveness of online learning and traditional learning can be influenced by various factors, including the subject matter, the individual learning styles and preferences of students, and the quality of the educational resources and instructional methods employed. In some cases, a blended or hybrid approach, combining elements of both online and traditional learning, may be the most effective solution, allowing students to benefit from the strengths of each modality.In conclusion, the differences between online learning and traditional learning are multifaceted and span various aspects of the educational experience. While online learning offers greater flexibility, accessibility, and a broader range of course options, traditional learning environments can provide a more structured, interactive, and socially engaging learning experience. Ultimately, the choice between online and traditional learning should be guided by the specific needs, learning preferences, and educational goals of the individual student, as well as the nature of the subject matter and the quality of the educational resources available.。
电驱系统设计流程
电驱系统设计流程1.电驱系统设计的第一步是确定系统的性能指标和需求。
1. The first step in the design of the electric drive system is to determine the performance indicators and requirements of the system.2.确定系统用途和工作环境，例如车辆、机械设备或工业生产线。
2. Determine the purpose and working environment of the system, such as vehicles, mechanical equipment, or industrial production lines.3.对于不同的应用领域，需要选择不同类型的电机和控制器。
3. Different types of motors and controllers need to be selected for different applications.4.根据功率需求和效率要求选择合适的电机类型，比如直流电机、异步电机或同步电机。
4. Choose the appropriate type of motor, such as DC motor, asynchronous motor, or synchronous motor, according to the power requirements and efficiency requirements.5.确定驱动系统的控制方式，可以是开环控制、闭环控制或者矢量控制。
5. Determine the control mode of the drive system, which can be open-loop control, closed-loop control, or vector control.6.设计电机的机械部分，包括轴承、结构和散热系统。
Altium_Designer中英文技术词汇对照
[检索词汇]altium designer中英文技术词汇对照PCB AD常用术语翻译对译protel单词Accept接受Accuracy精确度准确度Activate激活活动启动Add添加Address地址Advance高级Aide助手辅助Align排列对齐Alpha开端Analog模拟的Analyzer分析器测定仪Angle角度观点Annotate注解Aperture孔径光圈Applocation应用程序Approximation接近近似值Arc圆弧弧度Architecture结构体构造Array阵列数组Ascend登高上升Assembly集合装配Associate关联的辅助的Asynchronous异步的Automatical自动的Access存取通道接近Action行动作用Active积极的活泼的Adder加法器Administration管理员管理器Aggressor干扰源入侵者Alias别名化名混淆Allow允许Always总是永远Analysis分析研究Animation动画Applicable可应用的适用的Apply应用Arbiter仲裁器Architect设计者制造者Area面积范围Arrange安排排列调整Arrow箭形Assembler装配器汇编Assign分配分派指定Astable非稳态的多谐振荡的Attempt尝试Available有效的有用的Backup备用Bar标签Base基极基础基地Batch批处理批量Begin开始创建Behavior行为举止态度Bell铃钟Between两者之间Bidir允许双向Bidirectional双向性Bill清单Binary二进制二元的Bistable双稳Bit位Bitmap位图Black黑色黑色的Blind盲孔Blip标志信号Block框栏隔阻Board板子牌子委员会Body物体主干主体Boolean布尔值Border边线Bottom底部Bounce反弹抖动Breakpoint中断点断点Broken破裂的损坏的Browse浏览Buffer缓冲器Bullet锥形体Bury埋藏Bus总线Butterfly蝶形Button按钮Bypass省略Byte字节Cable电缆Calculation计算估计CAM(computer aided manufacturing)计算机辅助制造Cancel作废删除Capacitor电容Caption标题Capture捕获收集记录Case实情案例Category类目范畴部属Cathode阴极Center中心Centimeter厘米Chain链Change改变Channel通道Charge充电指责指示Check检测Chart制成图表Child子女Chip集成芯片Circuit电路Circular圆环弧形Class阶层等级Cleanup清扫工作Clear清除清零Clearance清除余地间隙Click单击点击Clipboard剪切板Clock时钟Close关闭结束Closure关闭闭幕Code编码代码Collector集电极Color彩色着色Colour颜色Column圆柱纵列栏目Combination组合Comma逗号Command命令Comparator比较器Community社区群落Compilation编辑物Compatible兼容的和谐的Component元器件组成成分Compile编辑收集汇编Computer计算机Composite合成的复合的综合的Condition条件Concurrent并发事件同行Configure配置Confidence置信度自信信赖Conflict冲突Confirm确认证实Connector连接端Connectivity连线Constraint约束限制因素Console主控台表盘托架Consumer用户使用者Construction构造Continue继续延伸Contract缩短Control控制Convert转化转变Coordinate坐标Copper铜Copy拷贝复制Core核Cord绳线索Corner角落拐角Corporation公司企业法人Counter计数器Courtyard天井庭院Create创建Cross十字符号混合Crosspoint插入测试点Crosstalk串扰CRTCrystal晶体Current电流当前的流行的Cursor光标游标指示器Custom惯例Customer用户客户Cutout切出划出挖空Cycle周期Comment注释发表评论说明书Dashed下划线Data数字数据Databse数据库资料库Date日期Daughtrer子系子插件派生Debug排错调试Dead死的Decimal十进制小数Decade十进制十年Default默认值缺省值弃权Decoder译码器Definition定义式限定分辨率Define定义下定义Delay延时Degree度等级Demo演绎演示版Delete删除Demote降级降低Deny否认Description描述Designator标识指示者Designer设计师Destination目标目的Detail细节零件Device装置设备图样器件Diagram示意图Dialog对话Diagonal对角线Difference差异查分差额Diamond菱形钻石Digital数字的Different不同的Dimension尺度Dim朦胧暗淡Direct指示指令Diode二极管Disable无能无效无用Director指南指导咨询Disk圆盘Discharge放点排出释放Distribution分配分布分发Display显示Dock停放连接接驳Divider分配分割Dot小点虚线点缀Donut环形Download下载Down下降Draw绘制描写冲压成型Drag拖拽Drop下拉滴落遗漏Drill钻Duplicate复制副本Dual双数的两倍Duty占空比Edge边缘Edit编辑Efficient高效的有能力的Electrical电气的电学的电力的Ellipse椭圆Embed潜入插入Emitter射极Emulate效法Enable使能激活有效Encoder编码器End结束Engineer设计建造工程师Enter进入参加Entity实体Entry入口Enum列举型别Error错误Evaluation评价评估鉴定Example例子Excel胜过优秀突出Execute执行实施签署Exist存在的现有的Expand扩大推广展开Expansion扩大扩展扩张Expiry终止期满Explode爆炸分解Exponent指数Export输出出品Explore探究查询Extra额外的附加的External外部的外面的外形Extrude压制突出Extract提取摘录Fabrication制造Frequency频率Failure无效毁坏的Function函数功能False虚假的伪造的Fail失败不足Fanout扇出Fall下降降落落差Favorite最爱的（sth sb）Famale凹的阴的Figure图形Fatal致命的Fill填充Field现场域范围Filter过滤器File文件Find建立发现Film胶片First第一首先Finally最终的Flash闪光闪烁曝光Finish完成结束Flatten弄平弄直Fit适合相配Flip-flop触发器Flat平的平坦的Floorplan层平面图Flip倒转Focus集中聚焦Float发行Footprint封装Flow流动源自Format格式Folder文件夹折叠Formula公式Force强制FPGAForum讨论论坛会Frame框图塑造Free自由Framework架构结构Form从····起由于Gate门Generate产生导致造成Graphic图形green绿色Grid栅格Ground地面基础Group组类集聚Guide引导指南手册Hard坚硬的困难的Hardware硬件设备五金Harmonic谐波谐振Harness束Hatch策划画影线舱口Hazard冒险Hazy模糊的混浊的Height高度Help帮助Hexadecimal十六进制Hide隐藏Hierarchy体系分层系列High高的高级的高尚的Hint暗示History历史记录Horizontal水平横向Hug拥抱紧靠Ideal理想的Identical相同的相等的恒等的Identifier识别符Identify识别标记IDF(integrated data file)综合资料文件IEEE电气电子工程师协会Impedance阻抗Ignore忽略Import输入导入Imperial英制的Include包含Incident事变入射Index索引Increment增量Inductor电感Indication指示表示Information信息Industry工业企业产业行业Innovation创新Initial最初的开始的Insert插入嵌入添Input输入Insight洞察顿悟Inside内部的里面的Install安装Inspector检查视察Instrument仪器Instance实例Integrate积分的集成使完成使结合Integer整数Interactive互动的交互的Integrity完整的Interface接口界面Interconnect互联器Internet因特网Internal内部的IPC(industry process control)工业过程控制Interrupt打断中断Isolate隔离Island孤岛岛屿Item项目条款ISP(In-system programmable)在线编程JTAG(joint test action group)联合测试行为组Job工作职业Joint联合的Jump跳跃Junctions结点接点Keep保持Key关键钥匙Kind种类Knowledge知识Label标签商标Lattice晶格点阵Landscape横向Layer层Latch锁存器锁扣LCD(liquid crystal display)液晶显示器Launch发射投掷出版LED(light emitting diode)发光二级管Layout布置布局Legacy老化遗留下Learn学习学会认知Length长度Left左边向左Less较少的Legend图例图注Library库图书馆Lens镜Line线条线路Level水平Link链接连接License注册Linear线性的直线的一次的Liquid液体流体不稳的Live激活Localize本地局部本地化定位Locate把···设置在位置场所Lock锁定Log记录Logarithmic对数的Logic逻辑逻辑学Logical逻辑的合理的Login登录Lookup查找查阅Loop循环环状物Low低的矮的Lot地段许多Laboratory实验室LPM(library of parameter modules)参数化模块库Language语言用语术语Machine机器机械Multivibrator多谐振荡器Maker制造者Magnitude幅值强度量值Manage管理操纵Male阳的Manual手册手动的Manager管理者经理主任Map图Manufacture制造制作加工Match匹配比赛Mask表面掩膜屏蔽Matrix矩阵混合物Material材料物质Maximum最大值最大量Maximize增加扩大Measure测量Meal粉状物膳食Medium中间的媒介Mechanical机械的Membership会员资格Mega许多非常强大Memory存储器内存Menu菜单Merge合并Message信息Meter米（长度单位）Metric公制的Microsoft微软Millimeter毫米Minimum最小值Miscellaneous混合杂项多样Miser钻探机Miss损失差错遗漏Miter斜接斜角Mix混合结合杂交Mode形状方式风格Model模型模特型号Modify更改修饰Module模块组件单元Moire网纹纹波龟纹Mold模块模型Monitor监控Monostable单稳状态Moor固定系住Mount安装Move移动Mult多种多元多路Magnify放大Name名称Nano十亿分之一纳Navigator领航导航Neck领口瓶颈Negative负的Net网络Netlable网络标号Netlist网络表New新的Next下一步再Nexus关系Node结点波峰Noise噪音None忽略一个也没Normal正常的常规的Number数字号码数量Object物体目标Octagon八边形Octal八进制Octave八行八度八位ODBC(ovject database connectivity)开放数据库互联Ohm欧姆（电阻单位）OLE DB(object lin king and embedding databse)目标链接及嵌入式数据库Online在线Opcode运算码Openbus开放总线公共总线Open开放的公开的Operate工作运转营业Operand操作数运算域Optimizer优化程序优化器Operator运算符Orange橙子桔子Option选择选项Orientation取向Order顺序Original原本的最初的Origin起源原点Outline外形略述概括Orthogonal直角的正交的Outside外部的外观Output输出Overlay覆盖层Overall全部的Owner物主所有者Overshoot过冲Package封装包装Pad焊盘基座垫料Page页码翻阅Pair成对成双Palette调色盘选盘控制板Panel面板画板嵌镶板Parallel并行并联Parameter参数系数因数Parent父系Parsing部析Part部件Passive无源的被动的Paste助焊贴敷铜Path路径轨迹PCBPeak峰值Peripheral周边的外围的Permission同意Persistent坚持不懈固执的Physical物理的Pickbox点选框取景框Pickup拾取收集Pin引脚管脚Place放置Placement布局Plane平板平面飞机Plugin插件栓Point点Plus十字记号加号Polygon多边形多角形Pole极极地Popup弹出Polyline折线Portable可移植的移动的Port端口Position位置Portrait竖向纵向Postpone延时搁置Positive正的Power电源功率Pour倾泻倒灌Preference偏好优先Predefined预先定义Preliminary预备的初步语言的Prefix前缀字首Preserve保护保藏维护Prepreg预浸料半固化品Preview预览预习排练Preset置数Primary主要的Previous以前的早先的Print打印Primitive原始的纯朴的Priority优先级优先权Printout打印输出Process进程步骤Probe探测调查Profile外形轮廓部面Processor处理器加工者Program程序设计Programmable可编程的Project工程项目Proper适当的恰当的Promote促进创办Provider提供者供应商Property性质特性Pull拉牵拖PSD(programmable system device)可编程的系统部件Pulse脉冲跳动Pullback障碍阻扰拉回Push推挤推进拓展Quality质量特性Query疑问质问问号Quiet静态的安静的Radix根基数RAMRange级别排行类别Raster光栅屏面Ray射线光线闪现Rebuild重建重构Recent最近的Record记录经历Rectangle矩形长方形Rectangular矩形的成直角的Red红色的Reference参考基准Reflect反射Region区域地带Register寄存器Remove删除移除Repeat重复Report报告Require需要需求Reserve储备保存Reset复位置零Reshape改造矫形变形Resistance电阻值Resistor店主Resource资源Restore恢复还原返回Restrict限制约束Result结果导致Retrieve取回恢复Revision修订本校正版Right右的右方Ring铃声环形物Rise上升起立增强ROMRoom房间空间位置Root根根源本质Rotation旋转自转Round圆的Routing走线布线Row成形排列Rule规则Run运转流行的趋势Server服务服务器Same相同的同样的Sans没有无Save保存Scalar标量数量Scale刻度调节Schematic图表示意图Scope范围域Score成绩计分Script脚本Scroll卷动Search搜索Secondary次要的从属的Section部分片断Seed原因种子Select挑选选拔Separate分离区别标识Sequential有顺序的相继的Serial串行的系列的序列的Serif细体字Series串联连贯成套Session学期期间Service服务检修劳务Shader材质Set设置置位Shadow阴影着色Shape造型形状Share共享Sheet图纸方块Shelve搁置暂缓考虑Shift移动变换Shortcut快捷方式Show显示展示Signal信号Sign签署有符号的征兆标志Silent沉默的Silkscreen丝印层Similar相似的类似的Simple简单的朴实的Simulation仿真Sitemap网站地图网站导航Situs地点位置Silce切片薄片Slider滑块滑动Slot槽Small小的细的微的Smart智慧灵气Snap跳转突然折断Snippet片断摘录Software软件Solder焊接Solid实心的固体的坚固的Sort分类Source电源根源Space间隔间隙Speaker扬声器Special特殊的Specification说明书明细表Specify具体指定详细指明列入清单Speed速度Split分离Spreadsheet电子表格试算表Square方形正直的Stack堆积层叠Standalone单板机Standard标准规范Standoff支架平淡Start起始Starve不足饥饿State状态形势州Static静止的Station平台地位Status地位资格身份Step步进踏步步骤Stimulus激励促进刺激Stop停止Storage储存器Strategy策略方案战略String字符串串条弦Structure构成结构组织Style风格文体作风Subversion颠覆Summary摘要概括总结Support支持Suppress压制抑制阻止Surface表面Suspend暂停挂起终止Swap交换Sweep扫描环视Switch开关Symbol符号Synchronous同步的Syntax语法Synthesis综合合成System系统Table表格True真实Target目标对象指标Tail末尾尾部Technology技术工艺Teardrop泪滴Template样板Temperature温度气温Terminal极限的末端的端子Tenting掩盖遮掩Terminator终端负载Terminate终结终止Text文本正本Test测试Themselves他们自己TFT触摸屏显示器Thruhole通孔Thermal热的热量的Time时间Tile铺排Timer定时器Timebase时基Toggle切换开关双稳Timing时序定时Tool工具Tolerance公差容限容差Top顶部Toolbar工具栏工具条Total总体的合计为Topic题目Track轨迹Touchscreen触摸屏Train培训Trail拖Transfer传递Trance恍惚Transistor三极管晶体管Transient暂态瞬态Transparency透明度Translate转变翻译Triangle三角Transport传输Trigonometry三角法Trigger触发器启动引起Tube真空管电子管试管Tune调谐曲调协调Tutorial指导导师Type类型Unassign未定义Uncouple解耦松开Undershoot下冲负尖峰Undo取消还原Uniform相同的一致的单调的Unique独特的唯一的Unit单位Universal普遍的全体的宇宙的Unspecified不规定不确定Up向上Update更新Usage用法习惯处理Utility实用的通用的Use实用Valid有效的确实的合法的Validate使生效Validation确认验证Value数值价值价格评价Variant变化派生Vector矢量向量Vendor供应商卖主Version版本翻译Vertical垂直纵向Vertex顶点制高点极点Very很非常甚至VHDLVia经由过孔Victim被干扰受害者Video视频录像View查看Violation违犯冲突Virtual实质上的虚拟的Visible可视的Voltage电压Wait等待延缓Walkaround环绕步行栈桥Warn警告提醒预告Wave波动起伏挥动Waveform波形图Where地点在哪里Wide宽的广泛的Window窗口Width宽度幅度带宽Wizard向导精灵Wire导线Workspace工作区工作空间Worksheet工作表单WOSA(windows open services architecture)开放服务结构Worst最差的最坏的Zero零Zone地段区域Zoom缩放陡升。
焊接专业英语词汇学习汇总
焊接方面的1. 保护气体shielding gas2. 变形deformation3. 波浪变形buckling distortion4。
补焊repair welding5。
残余应力residual-stress6。
层状撕裂Lamellar Tear7. 插销试验Implant Test8。
常规力学性能convention mechanics performance 9。
超声波探伤ultrasonic inspection10. 衬垫焊welding with backing11。
船形焊fillet welding in the flat position 12. 磁粉探伤magnetic particle inspection13。
粗滴过渡globular transfer14。
脆性断裂brittlement fracture15. 淬火vt。
quench n。
~ing16. 错边变形dislocating distortion17。
搭接lap welding18。
打底焊backing welding19. 单道焊single-pass welding20。
单面焊welding by one side21。
导电嘴wire guide ;contact tube22。
等离子弧焊plasma welding23. 低合金钢low alloy steel24. 点焊spot welding25。
电弧动特性dynamic characteristic26. 电弧焊electric arc welding27。
电弧静特性static characteristic28. 电极electrode29. 电流current30. 电压voltage31。
电源power supply；power source32. 电阻焊resistance welding33。
调修correct34。
定位焊tack welding35. 短路过渡short circuiting transfer36. 段焊tack37. 断续焊intermittent welding38. 堆焊surfacing；build up welding39. 对接butt welding40。
一汽大众汽车行业中英术语对照-08630
行业相关词汇（部分）：1.公司概况公司概况 company profile 2.主要/主营业务主营业务 main business 3.业务范围业务范围 business scope 4.核心价值核心价值 core value 5.核心竞争力核心竞争力 core competence/competitiveness 6.核心应用系统核心应用系统 core application system 7.成功案例成功案例 success story/case 8.典型案例典型案例 typical case 9.案例研究／分析案例研究／分析 case study 10.汽车配件/备件/零件零件 automotive (spare)parts 11.汽车附件汽车附件 automotive accessories 12.部件/元件/组件组件 components 13.汽车后市场汽车后市场 aftermarket 14.配件市场配件市场 parts market 15.经销商管理系统经销商管理系统 Dealer Management System(DMS) 16.英孚思为经销商协同管理系统英孚思为经销商协同管理系统 Infoservice Dealer Collaboration Management System (INFODCS) 17.英孚思为整车销售管理系统英孚思为整车销售管理系统 Infoservice Vehicle Sales Management System (INFOVSM) 18.英孚思为配件运作管理系统Service Parts Management System 英孚思为配件运作管理系统 Infoservice Spare/S ervice (INFOSPM) 19.英孚思为索赔管理系统英孚思为索赔管理系统 Infoservice Warranty Management System (INFOWS) 20.英孚思为技术资料发布系统英孚思为技术资料发布系统 Infoservice Technical –data Viewer ((INFOTDV) 21.英孚思为英孚商用数据交换平台英孚思为英孚商用数据交换平台 (INFOX) Infoservice B2B Data Exchange Platform 22.经销商订单管理系统经销商订单管理系统 dealer order management system 23.售后配件管理系统售后配件管理系统 Spare/Service Parts management system(SPM) 24.集成管理系统集成管理系统 integrated management system 25.数据分析系统数据分析系统 data analysis system 26.销售配额销售配额 sales quota 27.配额管理配额管理 quota management 28.配额式订单管理系统配额式订单管理系统 quota-based order management system 29.配额式订单管理模式配额式订单管理模式 quota-based order management mode 30.主数据管理主数据管理 master data management(MDM) 31.操作系统操作系统 operating system (OS) 32.应用系统应用系统 application system 33.实施服务实施服务 implementation service 34.一站式服务一站式服务 one-stop shop/one-stop services 35.综合性的一揽子服务（方案）综合性的一揽子服务（方案） a comprehensive package of services 36.现场服务现场服务 on-site service 37.现场培训现场培训 on-site training38.现场实施现场实施 on-site implementation 39.现场分析现场分析 on-site analysis 40.现场管理现场管理 field/on-site management 41.车厂/主机厂/整车制造商/车辆制造厂车辆制造厂 OEM/automaker 42.整车物流整车物流 (finished) vehicle logistics (FVL)／outbound logistics(注：整车以后可以一致翻为vehicle,如前加finished也可以) 43.先进的整车物流先进的整车物流 advanced (finished) vehicle logistics(AFVL) 44.整车配送整车配送 vehicle delivery 45.整车／车辆匹配整车／车辆匹配 vehicle matching 46.4S-整车销售（Sale）,零配件（Spare part）,售后服务（Service）,信息反馈等（Survey）47.线上车辆状态跟踪线上车辆状态跟踪 online vehicle status tracking 48.线上预配车模块线上预配车模块 online vehicle pre-allocation module 49.车辆滞留时间车辆滞留时间 vehicle holdup period 50.配车冻结配车冻结 vehicle allocation freezing 51.生产冻结期生产冻结期 production freezing time 52.提前分销/分配分配 pre-distribution 53.生产周排产计划生产周排产计划 weekly production schedule 54.管线内车辆管线内车辆 vehicles in the pipeline 55.（车辆）下线时间（车辆）下线时间 offline time/ off-production-line time 56.（车辆）上线时间（车辆）上线时间 online time 57.系统上线系统上线 system go-live 58.资源配置／分配资源配置／分配 resources allocation/distribution 59.产品推广产品推广 products deployment(注：本行业产品推广一般是系统推广部署之意，区别与一般产品的推广促销products promotion) 60.业务流程业务流程 business process 61.持续支持持续支持 on-going/continuous support 62.长期支持long-term support 63.订单查询订单查询 order inquiry/query(注：前者一般电话查询等，后者一般网上查询) 64.签收签收 •sign-in 65.软件外包软件外包 software outsourcing 66.服务站服务站 service station 67.服务中心service centre 68.功能模块功能模块 function/functional module 69.召回召回 recall 70.无缝连接无缝连接 seamless connection/joint 71.J2EE架构架构 J2EE architecture 72.J2EE 框架框架 J2EE framework 73.展厅管理showroom management 74.备件库存备件库存 spare parts inventory/stock 75.物料出入库物料出入库 material issuing and receiving 76.出库/仓库交货仓库交货 goods issuing/delivery/ex-warehouse 77.叉车厂叉车厂 forklift truck works 78.库存深度库存深度 stock depth 79.库存积压/压库压库 overstock 80.汽车配件厂汽车配件厂 auto parts plant 81.汽车维修厂汽车维修厂 automotive service shop 82.汽车修理厂汽车修理厂 automotive repair shop 83.汽车维修工程有限公司汽车维修工程有限公司 Auto maintenance engineering Co. Ltd 84.汽车养护有限公司汽车养护有限公司 car maintenance Co. Ltd 85.汽车美容护理中心汽车美容护理中心 Auto care centre 86.大客户销售经理大客户销售经理 Fleet Sales/Key Account Manager 87.订单处理订单处理 order processing/handling 88.延期交货订单/欠货订单欠货订单 back order 89.实时客户订单实时客户订单 real-time customer order 90.客户名单客户名单 customer list 91.客户跟进客户跟进 customer follow-up 92.潜在客户潜在客户 potential customer/prospect 93.客户服务满意（度）customer service satisfaction 94.客户满意度(指标)customer satisfaction index (CSI) 95.客户关怀客户关怀 customer care 96.客户忠诚度客户忠诚度 customer loyalty 97.授权及审批授权及审批 authorization and approval 98.保修/索赔申请索赔申请 warranty claim 99.回运件/返修件／旧件返修件／旧件 return parts 100.最佳实践最佳实践 best practice 101.同步传输同步传输 synchronous transmission 102.异步传输异步传输 asynchronous transmission 103.消息组播消息组播 message multicast 104.安全密码认证安全密码认证 Security Password Authentication 105.日志管理日志管理 log management 106.多重组网多重组网 domain based routing rules \ 107.批量数据上传批量数据上传 batch data upload 108.电子数据交换电子数据交换 electronic data interchange (EDI) 109.数据库连接池数据库连接池 database pool 110..数据源数据源 data source\ 111.线形图线形图 linear chart 112.柱形/条形图条形图 /直方图bar chart/histogram 113.饼图饼图 pie chart 114.托管/寄存服务 hosting service 寄存 服务115.绩效考核指标体系设计绩效考核指标体系设计 performance index design 116.绩效评价体系设计绩效评价体系设计 performance evaluation system design 117.绩效管理体系绩效管理体系 performance management system 118.关键业绩指标关键业绩指标 key performance index (KPI) 119.应用编程接口应用编程接口 application programming interface (API) 120.系统部署系统部署 system deployment 121.试运行试运行 pilot/ trial/test running(注：本行业常用pilot) 122.集中培训集中培训 centralized training 123.系统切换system cutover 124.无线接入无线接入 wireless access 125.办公自动化办公自动化 office automation (OA) 126.虚拟专用网虚拟专用网 virtual private network(VPN) 127.故障管理故障管理 fault management(FM) 128.故障模式与结果分析故障模式与结果分析 Fault Modes and Effect Analysis (FMEA) 129.故障率Failure Rate 130.故障记录Failure Record 131.三包服务三包服务 three-guarantee service/sanbao service 132.集中构架技术集中构架技术 integrated architecture technology 133.分布式构架技术分布式构架技术 distributed architecture technology 134.集中式服务组合集中式服务组合 centralized architecture 135.分布式服务组合分布式服务组合 decentralized architecture 136.国际商用机器公司International Business Machines Corporation (IBM) 137.硬件及安全网络中心硬件及安全网络中心 system support and network security centre 138.物流规划物流规划 logistics planning 139.数据转换数据转换 data conversion 140.数据移植／迁移数据移植／迁移 data migration 141.双边／双方承诺双边／双方承诺 bilateral /mutual commitment 142.项目启动会项目启动会 project kickoff meeting 143.售后服务after-sale service(ASS)/after service/service 144.质控质控 quality control (QC) 145.质量保证质量保证 quality assurance (QA) 146.价格管理价格管理 pricing management 147.终端市场终端市场 end-market 148.横向协作横向协作 horizontal collaboration 149.纵向支持纵向支持 vertical support 150.综合实力综合实力 comprehensive strength 151.良性循环良性循环 benign/virtuous cycle/circulation 152.前后台运作前后台运作 front and back-end operation 153.大/关键客户销售经理: Fleet Sales/Key Account Manager 154.产品责任产品责任 product liability 155.订单完成率订单完成率 order fulfillment/completion rate 156.汇报会汇报会 report／review meeting 157.双周总结／汇报会bi-weekly review meeting 158.根源分析根源分析 root cause analysis 159.滚动需求滚动需求 rolling demand 160.产供销链产供销链 production, supply & sales chain 161.供应链战略供应链战略 supply chain strategy 162.供应链管理供应链管理 supply chain management 163.连锁店管理连锁店管理 chain store management 164.经销商销售预测经销商销售预测 dealer sales forecast 165.销售支持与费用结算销售支持与费用结算 sales support & expense settlement 166.订单交付订单交付 Order to Delivery (OTD）167.刚性生产计划刚性生产计划 rigid production plan 168.订单管理流程订单管理流程 order management process 169.营销总部sales & marketing headquarter 170.量化管理量化管理 quantitative management 171.项目管理办公室项目管理办公室 project management office (PMO) 172.灾难恢复计划灾难恢复计划 disaster recovery plan(DRP) 173.电子配件目录电子配件目录 electronic parts catalogue(EPC) 174.企业资源计／规划enterprise resource Planning (ERP) 175.客户关系管理客户关系管理 customer relationship management (CRM) 176.业务流程重组／再造业务流程重组／再造 Business Process Reengineering(BPR) 177.战略业务单元/战略性事业单位/策略性事业单位策略性事业单位 strategic business unit (SBU) 。
三相异步变频电动机国标
三相异步变频电动机国标**三相异步变频电动机国标**The national standard for three-phase asynchronousvariable-frequency motors outlines the technical requirements, test methods, and evaluation criteria for these motors. It ensures the safety, reliability, and efficiency of the motors, promoting their widespread application in various industries.三相异步变频电动机国标详细规定了该类电动机的技术要求、试验方法和评价准则。
它确保了电动机的安全性、可靠性和效率，推动了其在各个行业的广泛应用。
The standard specifies the basic parameters of the motors, including rated voltage, rated frequency, rated power, and speed range. It also details the construction and material requirements, ensuring the motors are built with high-quality materials and designed for optimal performance.该标准规定了电动机的基本参数，包括额定电压、额定频率、额定功率和转速范围。
同时，它还详细说明了电动机的结构和材料要求，确保电动机采用高质量材料制造，并设计以达到最佳性能。
In terms of performance, the standard requires the motors to meet certain efficiency standards and have good thermal performance. This ensures that the motors can operate stably under various conditions and reduce energy consumption.在性能方面，标准要求电动机必须达到一定的效率标准，并具有良好的热性能。
混合研究方法：我国体育学博士论文适用情境与模型解析（2015—2019）
混合研究方法：我国体育学博士论文适用情境与模型解析（2015—2019）作者：张琦姚家新来源：《山东体育学院学报》2021年第02期摘要：采用文獻资料法，对2015—2019年体育学博士论文的研究范式进行深入分析，得出混合研究范式具有突起之势，是体育教育训练学、体育人文社会学和体育管理学论文中占比最高的研究范式。
借鉴国内外不同学科混合研究范式的研究成果及近5年本学科博士论文研究范式实际使用情况，归纳出混合研究的适用情境：（1）提高对复杂性研究问题的解释力;（2）开发新的测量工具实现数据验证;（3）定量降维为质性深入探讨做准备;（4）提升小群体研究成果的可转换性。
并提炼出混合研究多元借鉴适用设计模型：（1）同步三角校验设计;（2）异步嵌入式设计;（3）异步解释式设计;（4）异步探索式设计。
混合研究应用存在的问题：（1）缺少明晰的研究设计及描述;（2）谋求理论发展的源动力不足;（3）缺少对研究成果的严谨整合;（4）难于把握推论质量评价标准。
混合研究为体育学科开辟了一个全新的科研格局，促进了不同认识论、方法论及具体技术的辩证结合，同时也提出了诸如更高的方法素养要求、难以避免的信息损耗、方法的自限性问题以及对阶段性矛盾结果的处理等问题。
研究者应增加对混合方法研究理论的认识水平并提高实际应用能力，从方法论及实践层面同时提升该研究范式在体育学领域的严谨性和普及性。
关键词：研究范式;博士论文;混合研究;适用情境;设计模型中图分类号：G80-3 文献标识码：A 文章编号：1006-2076（2021）02-0062-09Abstract：By using the method of literature， this study makes an in-depth analysis of the research paradigm of doctoral dissertations in physical education from 2015 to 2019. It is concluded that the mixed research paradigm has a prominent trend and is of the highest proportion of research paradigms in sports education and training， sports humanities and sociology and sports management. Drawing on the research results of the mixed research paradigm of different disciplines at home and abroad and the actual application of the research paradigm of doctoral dissertations in this discipline in the past five years， the applicable situations of mixed research are summarized as follows：（1）Improving the explanatory power of complexity research issues; （2） Developing new measurement tools for data validation; （3） Quantitative dimension reduction prepares for in-depth qualitative discussion; （4） Improving the convertibility of small group research results. The multi-reference design model of hybrid research has been extracted：（1） Synchronous triangle calibration design ; （2） Asynchronous embedded design; （3） Asynchronous explanatory design; （4）Asynchronous exploratory design. And applicable problems of the mixed research application are summarized：（1） Lack of clear research design and description; （2） Lack of motivation for theoretical development; （3） Lack of rigorous integration of research results; （4） Difficult to grasp the evaluation standard of inference quality. Mixed research has opened up a new scientific research pattern for sports discipline， and promoted the dialectical combination of different epistemology， methodology and specific technology. At the same time， it also put forward such problems as higher methodological literacy requirements， unavoidable information loss， self-limitation of methods and the treatment of periodic contradictory results. The author believes that researchers should deepen their understanding of the mixed method research theory and improve theirpractical application ability， and increase the preciseness and popularity of this research paradigm in the field of sports science at the methodological and practical levels.Key words：research paradigm; doctoral thesis; mixed research; applicable situation; design model科学史表明，任何优秀科研成果的取得都依赖于正确的研究方法，没有研究方法就没有科学[1]。
Matlab的第三方工具箱全套整合(强烈推荐)
Complex- for estimating temporal and spatial signal complexities
Computational Statistics
Coral- seismic waveform analysis
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JMatLink- Matlab Java classes
Kalman- Bayesian Kalman filter
Kalman Filter- filtering, smoothing and parameter estimation (using EM) for linear dynamical systems
DMsuite- differentiation matrix suite
DMTTEQ- design and test time domain equalizer design methods
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英语作文克服网课缺点措施
英语作文克服网课缺点措施The COVID-19 pandemic has significantly transformed the landscape of education worldwide. With physical classrooms becoming inaccessible, online learning has emerged as the primary mode of instruction for students across all levels. While online courses have provided a viable solution to ensure the continuity of education during these unprecedented times, they have also exposed various shortcomings that need to be addressed.One of the primary challenges of online learning is the lack of face-to-face interaction between students and instructors. In a traditional classroom setting, students can engage in dynamic discussions, ask questions, and receive immediate feedback from their teachers. However, in an online environment, this personal connection can be lost, leading to a sense of isolation and disengagement among learners. To overcome this, educators should explore innovative ways to foster meaningful interactions and create a sense of community within their virtual classrooms.Strategies such as incorporating interactive virtual sessions, breakoutrooms for small group discussions, and regular one-on-one check-ins with students can help bridge the gap and maintain a sense of engagement. Additionally, providing opportunities for students to collaborate on group projects or participate in virtual study groups can enhance their social and communication skills, which are crucial for their overall development.Another significant drawback of online courses is the potential for distractions and lack of self-discipline. In a physical classroom, students are more likely to stay focused due to the structured environment and the presence of their peers and teachers. However, in the comfort of their own homes, students may find it challenging to maintain their attention and avoid the temptation of social media, gaming, or other digital distractions.To address this issue, educators should implement strategies to help students develop effective time management and self-regulation skills. This can include providing clear schedules, setting deadlines for assignments, and encouraging the use of productivity tools and apps. Additionally, educators can incorporate regular check-ins, progress reports, and accountability measures to ensure that students stay on track with their learning.Furthermore, the quality of online course content and delivery can also be a concern. While many institutions have made efforts totransition their courses to the digital realm, the sudden shift has revealed the need for more comprehensive training and support for both instructors and students. Educators should be equipped with the necessary skills and resources to create engaging and interactive online learning experiences, while students should be provided with clear guidance and support on navigating the online learning environment.To address this challenge, institutions should invest in professional development programs for their faculty, focusing on effective online teaching methodologies, the use of educational technology, and the creation of high-quality digital content. Additionally, students should be offered comprehensive onboarding and training sessions to familiarize themselves with the online learning platforms and strategies for effective self-directed learning.Another significant challenge of online courses is the potential for technical issues and connectivity problems. Reliable internet access and stable technological infrastructure are essential for a seamless online learning experience. However, not all students may have access to the necessary resources, particularly in areas with limited or inconsistent internet connectivity.To mitigate this challenge, institutions should explore ways to provide affordable or subsidized internet access and technologicaldevices to students in need. Additionally, they can develop contingency plans and alternative learning options, such as asynchronous content delivery or offline learning materials, to ensure that students can continue their education even in the face of technical difficulties.Finally, the issue of assessment and evaluation in online courses can also be a concern. Traditional assessment methods, such as in-person exams, may not be feasible in an online setting, and institutions must find alternative ways to evaluate student learning and ensure academic integrity.To address this challenge, educators should explore a variety of assessment methods, including online proctoring, project-based assignments, and portfolio-based evaluations. They should also implement robust academic integrity policies and utilize technological solutions to prevent cheating and plagiarism. Additionally, providing clear communication and guidelines to students regarding assessment expectations and academic integrity policies can help set the stage for a fair and transparent evaluation process.In conclusion, the COVID-19 pandemic has accelerated the adoption of online learning, and it is likely that this mode of education will continue to play a significant role in the future. To overcome theshortcomings of online courses, a multifaceted approach is necessary. Educators and institutions must prioritize the development of engaging and interactive online learning experiences, foster a sense of community and connection, provide comprehensive support and training, and implement robust assessment strategies. By addressing these challenges, we can ensure that online learning becomes a more effective and inclusive educational option for students worldwide.。
Method for modeling and processing asynchronous fu
专利名称：Method for modeling and processingasynchronous functional specification forsystem level architecture synthesis发明人：Rajiv Jain,Alan Peisheng Su,Chaitali Biswas申请号：US09947250申请日：20010905公开号：US07076417B2公开日：20060711专利内容由知识产权出版社提供专利附图：摘要：A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includesthe step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.申请人：Rajiv Jain,Alan Peisheng Su,Chaitali Biswas地址：Naperville IL US,Westlake Village CA US,Los Angeles CA US国籍：US,US,US更多信息请下载全文后查看。
微塞米Timberwolf音频处理器系列产品ZL38090说明书
DescriptionThe ZL38090 is part of Microsemi’s Timberwolf audio processor family of products that feature the company’s innovative AcuEdge acoustic technology,which is a set of highly-complex and integrated algorithms. These algorithms are incorporated into a powerful DSP platform that allow the user to extract intelligible information from the audio environment.The Microsemi AcuEdge Technology ZL38090 device is ideal for Universal Serial Bus (USB) Audio Accessories. The device is available in a 64 pin QFN or 56 ball WLCSP package. Its license-free, royalty-free intelligent audio Firmware (ZLS38090) provides Beamforming and a variety of other voice enhancements to improve both the intelligibility and subjective quality of audio.Microsemi offers the MiTuner™ ZLS38508LITE GUI software package allowing a user to interactively configure the ZL38090 device.Applications•Unified Communication Devices •USB Boom and Boomless Headsets •USB Beamforming Microphones •USB SpeakerphoneTypical USB Headset ApplicationZL38090FlashSPIMDAC2DMICs DAC1USBMIC1MIC2Microsemi AcuEdge Technology ZLS38090 Firmware Audio Features•Supports 1 stereo headset pair with play and record or just playback functions•Microphone Beamforming (2 microphones)•Standard Dynamic Range Compressor •Limiter •Expander•Send and receive path 8-band parametric equalizers•8kHz/16kHz/48 kHz audio streaming•14 General Purpose Input/Outputs (11 in the WLCSP package) with fixed function capability for:•Volume Up/Down, Mute Mic, and Hook-Switch On/Off•PWM outputs for LED controlCommon USB Features•USB Audio Class Device v1.0 compliant•Adaptive mode for playback, Asynchronous modefor record •USB Audio Class clock modes •Remote wake-up via fixed function GPIO •Common HID controls for volume, mute, equalizer, and audio source and destinations •A USB port enumerates with:•EP0 (Control)• 2 endpoints for Microphones and Speakers (both stereo)• 1 interrupt endpoint (for Status Reporting)•Skype/Lync CompatibleDocument ID# 153166Version 2May 2016Ordering InformationDevice OPNPackage PackingZL38090LDF1 64-pin QFN (9x9) Tape & Reel ZL38090LDG1 64-pin QFN (9x9) TrayZL38090UGB2 56-ball WLCSP(3.05x3.05) Tape & ReelThese packages meet RoHS 2 Directive 2011/65/EU of the European Council to minimize the environmental impact of electrical equipment.Designed for USB Audio AccessoriesZL38090Product Brief•Stand alone USB device (additional host processor not required for headphoneapplications)ZL38090 Common Hardware Features•DSP with Voice Hardware Accelerators•Dual 16-bit digital-to-analog converters (DAC) •Sampling up to 48kHz and internal output drivers•Headphone amplifiers capable of 32mW output drive power into 16ohms•Impulse pop/click protection• 2 Digital Microphone inputs•TDM port shared between PCM andInter-IC Sound (I2S)•General purpose UART port for debug•Boots from SPI or Flash•Master SPI port for serial Flash interface•Can run unattended (controllerless), self-booting into a configured operational stateFor ease of mounting, the ZL38090 is available in two packages. QFN Hardware Features•64-pin QFN•9mm by 9mm package size•Headphone amplifiers can be configured as2 differential or 4 single-ended outputs• 4 Fixed Function PWM pins for Vol Up, Vol Down, Mute, and Hook Switch control and status•14 General Purpose Input/Output (GPIO) pins •Internal +1.2V voltage regulatorWLCSP Hardware Features•56-ball Wafer Level Chip Scale Package • 3.05mm by 3.05mm package size •Headphone amplifiers can be configured as2 single-ended outputs• 4 Fixed Function PWM pins for Vol Up, Vol Down, Mute, and Hook Switch control and status•11 General Purpose Input/Output (GPIO) pinsTools•ZLK38000 Evaluation Kit•MiTuner™ ZLS38508LITE GUI software Designed for USB Boom and Boomless HeadsetsZL38090Product BriefZL38090 Audio Processor for USB HeadsetsTypical Headset ApplicationThe ZL38090 functions as a complete USB Audio device. The ZL38090 does not require a separate host processor to operate. It it is designed to meet the Skype Certification/Lync Logo specification for a headset. The USB port can be connected to any computer or gaming system. All device controls can be accessed through the USB port,including a subset of basic functions (preset modes) that can be wired to the GPIO pins to provide volume up/down,mute, or special programmable commands.The ZL38090 has two internal differential headphone speaker amplifiers that can drive stereo signals directly into 16/32ohm headphones.Digital microphones can be connected to the ZL38090 DMIC interface, providing a low noise audio pick-up. The ZL38090 can perform beamforming when two microphones are used. Analog microphones can be used with the addition of an electret microphone pre-amplifier device.The ZL38090 has a TDM port that can be used to route audio, or audio can be routed through the USB port. USB Headset Block DiagramNote: When using the WLCSP package option, the headphone speaker amplifiers (DAC1 and DAC2) have single-ended stereo drive.DAC1DAC2DMIC_IN1DMIC_IN2GPIOZLK38090 Evaluation KitThe ZLK38090 Evaluation Kit includes all the hardware necessary to operate the ZLE38090 Evaluation Board. The Evaluation Board provides a flexible platform to evaluate a ZL38090 Timberwolf Audio Processor device with AcuEdge™ Technology Firmware. Firmware Code for the ZL38090 can be downloaded into the Evaluation Board using the ZLS38000 Firmware Loader software. The ZLE38090 Evaluation Board can then be controlled using the MiTuner™ GUI Lite Software (ZLS38508LITE).Device Pinout (64-Pin QFN) Top ViewPackage Outline (64-Pin QFN)Device Pinout (56-Ball WLCSP) Top ViewStaggered Balls (56-Ball WLCSP) Bottom ViewPackage Outline (56-Ball WLCSP)Device PinoutQFN Pin #WLCSPBall Name Type Description15D6RESET Input Reset. When low the device is in its reset state and all tristate outputswill be in a high impedance state. This input must be high for normaldevice operation.A 10KΩ pull-up resistor is required on this node to DVDD33 if this pinis not continuously driven.Table 1 - Reset Pin DescriptionQFN Pin #WLCSPBall Name Type Description6-DAC1_M Output DAC 1 Minus Output. This is the negative output signal of thedifferential amplifier of the DAC 1.Not available on the WLCSP package.7C7DAC1_P DAC 1 Plus Output. This is the positive output signal of thedifferential amplifier of the DAC 1.9-DAC2_M DAC 2 Minus Output. This is the negative output signal of thedifferential amplifier of the DAC 2.Not available on the WLCSP package.8D7DAC2_P DAC 2 Plus Output. This is the positive output signal of thedifferential amplifier of the DAC 2.12F7CDAC DAC Reference. This node requires capacitive decoupling. 13G7CREF Common Mode Reference. This node requires capacitivedecoupling.Table 2 - DAC Pin DescriptionsQFN Pin #WLCSPBall Name Type Description18H6DMIC_CLK Output Digital Microphone Clock Output. Clock output for digitalmicrophones and digital electret microphone pre-amplifier devices. 19H3DMIC_IN1Input Digital Microphone Input 1. Stereo or mono digital microphoneinput.Tie to VSS if unused.20H2DMIC_IN2Input Digital Microphone Input 2. Stereo or mono digital microphoneinput.Tie to VSS if unused.Table 3 - Microphone Pin DescriptionsQFN Pin #WLCSPBall Name Type Description29E1PCLK/I2S_SCK Input/OutputPCM Clock (Input/Tristate Output). PCLK is equal to the bit rate ofsignals DR/DX. In TDM master mode this clock is an output and inTDM slave mode this clock is an input.I2S Serial Clock (Input/Tristate Output). This is the I2S bit clock. InI2S master mode this clock is an output and drives the bit clock inputof the external slave device’s peripheral converters. In I2S slave modethis clock is an input and is driven from a converter operating inmaster mode.After power-up, this signal defaults to be an input in I2S slave mode.A 100KΩ pull-down resistor is required on this pin to VSS. If this pin isunused, tie the pin to VSS.When driving PCLK/I2S_SCK from a host, one of the followingconditions must be satisfied:1.Host drives PCLK low during reset, or2.Host tri-states PCLK during reset (the 100KΩ resistor will keepPCLK low), or3. Host drives PCLK at its normal frequency30F1FS/I2S_WS Input/OutputPCM Frame Pulse (Input/Tristate Output). This is the TDM framealignment reference. This signal is an input for applications where thePCM bus is frame aligned to an external frame signal (slave mode). Inmaster mode this signal is a frame pulse output.I2S Word Select (Left/Right) (Input/Tristate Output). This is the I2Sleft or right word select. In I2S master mode word select is an outputwhich drives the left/right input of the external slave device’speripheral converters. In I2S slave mode this pin is an input which isdriven from a converter operating in master mode.After power-up, this signal defaults to be an input in I2S slave mode.Tie this pin to VSS if unused.31G1DR/I2S_SDI Input PCM Serial Data Stream Input. This serial data stream operates at PCLK data rates.I2S Serial Data Input. This is the I2S port serial data input.Tie this pin to VSS if unused.32H1DX/I2S_SDO Output PCM Serial Data Stream Output. This serial data stream operates at PCLK data rates.I2S Serial Data Output. This is the I2S port serial data output.Table 4 - TDM and I2S Pin DescriptionQFN Pin #WLCSPBall Name Type Description1A5SM_CLK Output Master SPI Port Clock (Tristate Output). Clock output for the MasterSPI port. Maximum frequency = 8MHz.2A6SM_MISO Input Master SPI Port Data Input. Data input signal for the Master SPI port. 3A7SM_MOSI Output Master SPI Port Data Output (Tristate Output). Data output signalfor the Master SPI port.64A4GPIO_9/SM_CSInput/OutputMaster SPI Port Chip Select (Input Internal Pull-Up/TristateOutput). Chip select output for the Master SPI port.Shared with GPIO_9.Table 5 - Master SPI Port Pin DescriptionsQFN Pin #WLCSPBall Name Type Description50B2UART_RX Input UART (Input). Receive serial data in. This port functions as aperipheral interface for an external controller and supports access tothe internal registers and memory of the device.49C2UART_TX Output UART (Tristate Output). Transmit serial data out. This port functionsas a peripheral interface for an external controller and supports accessto the internal registers and memory of the device.Table 6 - UART Pin DescriptionQFN Pin #WLCSPBall Name Type Description33, 34, 36F4, E4,F3GPIO_[0:2]Input/OutputGeneral Purpose I/O (Input Internal Pull-Down/Tristate Output).These pins can be configured as an input or output and are intendedfor low-frequency signalling.37, 38, 39F2, ,F6GPIO_[3:5]General Purpose I/O (Input Internal Pull-Down/Tristate Output).These pins can be configured as an input or output and are intendedfor low-frequency signaling.GPIO_4 is not available on the WLCSP package.64A4GPIO_9/SM_CSGeneral Purpose I/O (Input Internal Pull-Down/Tristate Output).This pin can be configured as an input or output and is intended for low-frequency signalling.Alternate functionality with SM_CS.Table 7 - GPIO Pin DescriptionsQFN Pin #WLCSPBall Name Type Description41E2GPIO_7Input/Output Hook Switch/Volume Down. Fixed function used to control the hook state and volume down with GPIO[10:13].43D3GPIO_8Microphone/Volume Up. Fixed function used to control the hookstate and volume down with GPIO[10:13].44E3GPIO_10Volume Control/Call State. Fixed function used to control the volumeand indicate the call state with GPIO[7:8].45C3GPIO_11Call Control/Volume State 1. Fixed function used to control the hookswitch (on/off) and control multicolor LEDs for volume indication withGPIO[7:8].47-GPIO_12Volume State 2. Fixed function used to control multicolor LEDs forvolume indication with GPIO[7:8].GPIO_12 is not available on the WLCSP package.48-GPIO_13Volume State 3. Fixed function used to control multicolor LEDs forvolume indication with GPIO[7:8].GPIO_13 is not available on the WLCSP package.Table 8 - Headset Control/IndicatorQFN Pin #WLCSPBall Name Type Description22H7XI Input Crystal Oscillator Input.23F5XO Output Crystal Oscillator Output.Table 9 - Oscillator Pin DescriptionQFN Pin #WLCSPBall Name Type Description25H5USB_DM Input/Output USB Data D- Signal. Carries USB data to/from USB 2.0.26G4USB_RTUNE Tx Resistor Tune. Connect to external 43.2 resistor to VSS.27H4USB_DP USB Data D+ Signal. Carries USB data to/from USB 2.0.40E5GPIO_6USB Resume. This pin is used to sense activity on USB Data D+ toresume from sleep or perform a USB reset. It can be configured asan input or output and are intended for low-frequency signaling.Table 10 - USB Pin DescriptionQFN Pin #WLCSPBall Name Type Description17-EXT_SEL Input VDD +1.2V Select. Select external +1.2 V supply. Tie to DVDD33 ifthe +1.2V supply is to be provided externally. Tie to VSS (0 V) if the+1.2 V supply is to be generated internally.Not available on the WLCSP package.16-VDD12_CTRL Output VDD +1.2 V Control. Analog control line for the voltage regulatorexternal FET when EXT_SEL is tied to VSS. When EXT_SEL is tiedto DVDD33, the VDD12_CTRL pin becomes a CMOS output whichcan drive the shutdown input of an external LDO.Not available on the WLCSP package.4, 14, 24, 42, 58B5, D1,G5, G6DVDD12Power Core Supply. Connect to a +1.2V ±5% supply.Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupledto the VSS plane.5, 21, 35, 46, 51, 59B3, B7,G3DVDD33Power Digital Supply. Connect to a +3.3V ±5% supply.Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupledto the VSS plane.28-DVDD33_XTAL Power Crystal Digital Supply. For designs using a crystal or external oscillator, this pin must be connected to a +3.3V supply sourcecapable of delivering 10mA.For designs that do not use a crystal or external oscillator this pincan be tied to VSS in order to save power.Not available on the WLCSP package.10, 11E7AVDD33Power Analog Supply. Connect to a +3.3V ±5% supply.Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupledto the VSS plane.54B4, B6,D2, D4,E6, G2VSS Ground Ground. Connect to digital ground plane.-ExposedGround Pad Ground Exposed Pad Substrate Connection. Connect to VSS. This pad is at ground potential and must be soldered to the printed circuit boardand connected via multiple vias to a heatsink area on the bottom ofthe board and to the internal ground plane.Not available on the WLCSP package.Table 11 - Supply and Ground Pin DescriptionsQFN Pin #WLCSPBall Name Type Description56, 57, 63A3, C1,C6NC No Connection. These pins are to be left unconnected, do not useas a tie point.Table 12 - No Connect Pin DescriptionsTable 13 - IN0 Pin DescriptionsQFN Pin #WLCSP Ball NameType Description 52, 53, 55, 60, 61, 62A1, A2,B1, C4,C5, D5IN0Input IN0. Tie these pins to Ground.Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi.This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request.For more information about all Microsemi productsvisit our website atTECHNICAL DOCUMENTATION – NOT FOR RESALE© 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductorsolutions for: aerospace, defense and security; enterprise and communications; and industrialand alternative energy markets. Products include mixed-signal ICs, SoCs, and ASICs;programmable logic solutions; power management products; timing and voice processingdevices; RF solutions; discrete components; and systems. Microsemi is headquartered in AlisoViejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996。
网络教学与传统教学的区别英语作文
网络教学与传统教学的区别英语作文英文回答：Differences between Online and Traditional Education.In the realm of education, the advent of online learning has sparked a paradigm shift, offering an alternative to traditional classroom-based instruction. While both modalities seek to impart knowledge and skills, they differ significantly in their delivery methods, learning environments, and implications for students and educators.Delivery Methods.Online education is characterized by its asynchronous nature, allowing learners to access course materials and complete assignments at their own pace and convenience. Students typically interact with content through online platforms, virtual classrooms, and video conferencing.Traditional education, on the other hand, is synchronous, requiring students to attend classes at specific times and locations.Learning Environments.Online learning fosters a self-paced and flexible learning environment, where learners can set their own study schedules and work from any location with an internet connection. This flexibility can be particularly beneficial for individuals with busy schedules or those who live far from educational institutions. Traditional education, in contrast, provides a structured and supervised learning environment, where students are expected to attend class regularly and participate in face-to-face interactions.Student Engagement.In online education, students have the advantage of accessing a wide range of resources and learning materials on demand. However, they also face the challenge of staying motivated and engaged in the absence of face-to-faceinteractions. Traditional education offers more opportunities for direct interaction with instructors and classmates, which can enhance engagement and foster a sense of community.Educator Roles.In online education, instructors primarily serve as facilitators and mentors, providing guidance and support to students through asynchronous communication channels. They design and deliver course materials, respond to student inquiries, and evaluate assignments. In traditional education, instructors play a more active role in the learning process, leading classroom discussions,facilitating in-person interactions, and providing immediate feedback.Assessment.Online education typically relies on a variety of assessment methods, including online quizzes, discussion forums, and written assignments. Traditional educationoften incorporates a combination of in-class exams, papers, and projects. The assessment methods in traditional education allow for more immediate evaluation and feedback, while online assessments provide greater flexibility and convenience.Advantages and Disadvantages.Online Education.Advantages: Flexibility, self-pacing, accessibilityfor remote learners.Disadvantages: Lack of face-to-face interactions, potential for isolation.Traditional Education.Advantages: Structured learning environment, direct instructor and peer interactions.Disadvantages: Limited flexibility, may not beaccessible for all learners.In summary, online and traditional education offer distinct approaches to learning, each with its own advantages and disadvantages. Online education provides flexibility, self-pacing, and accessibility, while traditional education offers a structured environment, direct interactions, and immediate feedback. The choice between the two modalities depends on individual needs, learning styles, and circumstances.中文回答：网络教学与传统教学的区别。
self-consistency evaluation method -回复
self-consistency evaluation method -回复自相一致性评估方法（self-consistency evaluation method）在社会科学研究中被广泛应用，用于评估调查问卷或实验研究的可靠性和一致性。
本文将一步一步回答关于自相一致性评估方法的问题，讨论其应用和重要性。
第一步：理解自相一致性评估方法自相一致性评估方法是一种统计技术，用于评估调查问卷或实验研究中测量的各个项目之间的一致性。
它可以帮助研究者确定测量工具的可靠性和准确性，从而增强研究结果的信心和可信度。
第二步：应用自相一致性评估方法的步骤a. 设计测量工具：在进行一项研究之前，必须准确定义研究变量，并设计合适的测量工具来收集数据。
这可以是一个调查问卷或一个实验任务。
b. 选择测量项目：选择需要评估自相一致性的测量项目。
通常，这些项目应该是测量同一个概念或变量的不同方面，例如，一份调查问卷中的多个问题可能涉及同一个主题。
c. 数据收集：使用设计好的测量工具，收集研究参与者的数据。
这可以通过在线调查、面对面访谈或实验研究等方式进行。
d. 计算自相一致性：使用适当的统计方法计算测量项目之间的自相一致性。
最常用的方法之一是Cronbach's alpha系数。
该系数的值介于0和1之间，越接近1表示项目之间的一致性越高。
e. 解释结果：根据自相一致性系数的结果，研究者可以判断测量工具的一致性和信度。
较高的自相一致性系数意味着测量工具是可靠且一致的，研究结果更具说服力。
第三步：自相一致性评估方法的重要性a. 可靠性评估：自相一致性评估方法为研究者提供了一种评估测量工具可靠性的方式。
如果测量工具不可靠，得出的研究结论可能不准确或不可靠。
b. 信度评估：通过评估测量工具的自相一致性，可以确保研究工具在同一概念的不同方面之间能够产生一致的结果。
这有助于确保研究结果的信度和稳定性。
c. 精确度提高：通过使用自相一致性评估方法，研究者可以确定测量工具中可能存在的问题，并加以纠正。
ADI ADPD4000(1)多模式传感器前端解决方案
ADI公司的ADPD4000是多模式传感器前端,有8 个输入通道, 具有多种工作模式以适应以下测量如PPG,ECG,EDA,阻抗和温度.有12 个可编程时隙,适用于同步传感器测量. 灵活的采样速率从0.004 Hz 至 9 kHz,片内集成了数字滤波,发射和接收信号链的SNR为90 dB,环境光抑制为60 dB 至 1 kHz,支持 SPI 和 I2C 通信, 256 字节 FIFO.主要用在可穿戴健康和健美监视器如心率监视仪(HRM),心律变异(HRV),应力,血压估计, SpO2,水化（合）作用,体躯成分.工业监测如CO,CO2,烟雾,气溶胶检测以及家庭病人监测.本文介绍了ADPD4000/1主要特性,功能框图, 模拟信号通路框图以及评估板EVAL-ADPD4000Z-PPG和EVAL-ADPDUCZ连接图,评估板EVAL-ADPD4000Z-PPG主要特性,电路图和PCB设计图.The ADPD4000/ADPD4001 operate as a complete multimodal sensor front end, stimulating up to eight LEDs and measuring the return signal on up to eight separate current inputs. Twelve time slots are available,enabling 12 separate measurements per sampling period.The data output and functional configuration utilize an I2C interface on the ADPD4001 or a serial port interface (SPI) on the ADPD4000. The control circuitry includes flexible LED signaling and synchronous detection. Thedevices use a 1.8 V analog core and 1.8 V/3.3 V compatible digitalinput/output (I/O).The analog front end (AFE) rejects signal offsets and corruption fromasynchronous modulated interference, typically from ambient light,eliminating the need for optical filters or externally controlled dccancellation circuitry.Multiple operating modes are provided, enabling the ADPD4000/ADPD4001 to be a sensor hub for synchronous measurements ofphotodiodes, biopotential electrodes, resistance, capacitance, andtemperature sensors.The ADPD4000/ADPD4001 are available in a 3.11 mm × 2.14 mm, 0.4 mm pitch, 33-ball WLCSP and 35-ball WLCSP.ADPD4000/1主要特性:Multimodal analog front end8 input channels with multiple operation modes to accommodate thefollowing measurements: PPG, ECG, EDA, impedance, and temperature Dual channel processing with simultaneous sampling12 programmable time slots for synchronized sensor measurements Flexible input multiplexing to support differential and single-ended sensor measurements 8 LED drivers, 4 of which can be driven simultaneously Flexible sampling rate from 0.004 Hz to 9 kHz using internal oscillators On-chip digital filteringSNR of transmit and receive signal chain: 90 dBAmbient light rejection: 60 dB up to 1 kHz400 mA total LED drive currentTotal system power dissipation: 50 μW (combined LED and AFE power),continuous PPG measurement at 75 dB SNR, 25 Hz ODR, 100 nA/mA CTRADI ADPD4000(1)多模式传感器前端解决方案SPI and I2C communications supported256-byte FIFOADPD4000/1应用:Wearable health and fitness monitors: heart rate monitors (HRMs), heart rate variability(HRV), stress, blood pressure estimation, SpO2, hydration, bodycompositionIndustrial monitoring: CO, CO2, smoke, and aerosol detectionHome patient monitoring图1:ADPD4000/1功能框图图2. ADPD4000/1模拟信号通路框图评估板EVAL-ADPD4000Z-PPGThe EVAL-ADPD4000Z-PPG evaluation board provides users with asimple means of evaluating the ADPD4000/ADPD4001 photometric front end.The EVAL-ADPD4000Z-PPG evaluation board implements a simplediscrete optical design for vital signs monitoring applica-tions, specifically wrist-based photoplethysmography (PPG).The EVAL-ADPD4000Z-PPG has three green light emitting diodes(LEDs), one infrared (IR), and one red LED, all separately driven. A single 7 mm2 photodiode (PD) is populated on the board. The PD has no optical filter coating. However, a pin for pin alternative device with an IR blockfilter is available.The full evaluation system includes the Wavetool Evaluation Software graphical user interface (GUI) that provides users with low level registeraccess and high level system configurability.Raw data streamed to this tool can be displayed in real time withlimited latency. Views are provided for both frequency and time domain analysis.A user datagram protocol (UDP) transfer capability from the Wavetool Evaluation Software (available for download on the EVAL-ADPD4000Z-PPG product page) allows data stream connections and register configurability to external analysis programs, such as LabVIEW® or MATLAB, in real time.The EVAL-ADPD4000Z-PPG board is powered by the EVAL-ADPDUCZ microcontroller board (obtained from the EVAL-ADPD4000Z-PPG product page). In addition to the power requirements, serial port interface (SPI) (default) or I2C data streams are received from the ADPD4000 by the microcontroller. A ribbon cable connects the two boards. Themicrocontroller repackages the data, sending it to a virtual serial port over the USB to the PC, displayed on the Wavetool Evaluation Software. The EVAL-ADPD4000Z-PPG can also be connected directly to themicrocontroller development system of the user, using the SPI for the ADPD4000 (or I2C for the ADPD4001).The ADPD4000/ADPD4001 data sheet, available at , provides full specifications for the ADPD4000/ADPD4001. Consult the ADPD4000/ADPD4001 data sheet in conjunction with this user guide whenusing the EVAL-ADPD4000Z-PPG.评估板EVAL-ADPD4000Z-PPG 主要特性:Board supports ADPD4000 and ADPD4001 population ADPD4000 (SPI) is the default board population All inputs and outputs are accessible to the user 3 separately driven green LEDs included 1 red and 1 IR LED includedMetal baffle to block optical crosstalkWorks with the Wavetool Evaluation Software allowing Time domain graphing and logging Frequency domain graphing Statistical analysisData streaming to other applications评估板EVAL-ADPD4000Z-PPG 包括:EVAL-ADPD4000Z-PPG evaluation board Ribbon cableWrist strap, with hook and loop fastener图3:评估板EVAL-ADPD4000Z-PPG 外形图(顶视)。
Tcl与DesignCompiler（十三）——DesignCompliler中常用到的命。。。
Tcl与DesignCompiler（⼗三）——DesignCompliler中常⽤到的命。
本⽂将描述在Design Compliler中常⽤到的命令，这些命令按照流程的顺序进⾏嵌套讲解，主要是列举例⼦；⼤概的讲解布局如下所⽰：⼤概有11个部分，下⾯我们逐个部分进⾏（简单的）介绍的举例。
1、tcl的命令和结构tcl的命令和结构请参照第⼆节的内容：--> 设置变量命令： set PER 2.0 显⽰变量命令： echo $PER # Result: 2.0--> 表达式操作： set MARG 0.95 expr $PER * $MARG # expr: *, /, +, >, <, =, <=, >= set PCI_PORTS [get_ports A] set PCLPORTS [get_ports “Y??M Z*”]-->命令嵌套，显⽰命令中嵌套表达式命令： echo “Effctv P = [expr $PERIOD * $MARGIN]” # Result with soft quotes: “Effctv P = 1.9”等价于： echo {Effctv P = [expr $PERIOD * $MARGIN]} # Result with hard quotes: # “Effctv P = [expr $PERIOD * $MARGIN]”-->tcl的注释⾏：# Tcl Comment line set COMMENT injine ; # Tel inline comment-->设置tcl中的列表变量： set MY_DESIGNS “A.v B.v Top.v”查看列表变量： foreach DESIGN $MY_DESIGNS { read_verilog $DESIGN}-->for循环： for { set i 1} { $i < 10 } { incr i} { read_verilog BLOCK_$i.v }2、获取帮助-->在dc_shell 中能⽤的命令： pwd 、 cd 、 Is、history、 !l 、 !7 、 Ireport 、 sh <LINUX_command> ：加上sh后，可以执⾏在linux中执⾏的命令，如sh gvim xxx.v & (&是后台运⾏)、 printenv、 get_linux_variable <LINUX_variable>-->在dc_shell中寻求帮助： 下⾯的这些man、printvar命令都只能在dc_shell中运⾏： help -verbose *clock ：列出与*clock有关的选项 create_clock -help ：查看create_clock这个命令的简单⽤法 man create_clock ：查看create_clock这个命令的详细信息 printvar Mibrary ：查看 Mibrary这个变量的内容 man target_library ：查看target_library这个命令的详细信息-->linux关联DC中的帮助，获取更多的帮助 为了能够在linux中使⽤dc_shell中的man命令，或者说能在linux中查看某些dc的命令，可以使⽤关联（alias）： $ alias dcman “/usr/bin/man -M $SYNOPSYS/doc/syn/man” 然后我们就可以使⽤dcman来参看dc中的命令了，例如： $dcman targetjibrary3、tcl语法的检查当在DC可以执⾏tcl⽂件，在运⾏之前，我们要检查这个tcl⽂件是否有语法错误，可以使⽤下⾯的命令： $dcprocheck xxx.tcl4、设计对象的操作关于设计对象的内容（⽐如上⾯是设计对象等），请查看前⾯的章节，这⾥我们只进⾏说对设计对象操作的⼀些命令（这些命令可以在dc_shell 中执⾏，或者写在tcl⽂件中）。
eLearning术语
电子化学习（ e-Learning ）常有术语AICCAICC [Aviation Industry CBT [Computer-Based Training] Committee]这套标准合用于对经过技术手段进行的培训进行开发、流传和评估。
航空工业计算机培训委员会（ AICC ）是一个航空工业领域的计算机培训专家们构成的国际协会。
APIAPI [An Application Program Interface]应用程序界面是一种语言及信息格式，能让一种计算机应用和操作系统或其余计算机程序，如数据管理程序、ERP 应用等进行交流交流。
应用程序界面供给了一种让不一样的计算机相互交流、共同工作并共享数据和函数的方式。
ARCSARCS [attention, relevance, confidence, and satisfaction.]Keller 的激励理论，包含：惹起注意、供给有关性、成立自信和获取知足。
ASPASP [Application Service Provider]应用服务供给商（ ASP）是供给经过互联网接入软件应用的公司，不然那些应用软件就要安装在客户自己的计算机里。
因为该应用位于应用服务供给商服务器上，使用该应用的公司得免得除软件安装和升级的成本和辛苦。
Asynchronous异步学习[Asynchronous]人们不可以进行同步交流时的学习就称为异步学习。
异步学习的例子包含自定步骤学习课程、和导师互换电子邮件信息、在议论组上张贴信息。
异步学习的优势是方便、易靠近，同时它也的确由个人自定学习步骤。
异步学习的劣势是：学生们会感觉被孤立或因为缺少人际及时互动而不那么踊跃。
此外，异步电子学习不可以供给对学生的表现的及时反应，对培训的调整在评估达成以后。
Authoring Tool编写工具[Authoring Tool]一种软件应用，主要由被非程序员应用，它利用比喻（书或许流程图）来创立在线课程。
编程中常用到的单词
Examine 检查、调查、考试Detail 详情、详述Expansion 扩大，扩，扩展Interpretation 解释、说明Interval 时间间隔Lap 膝盖，折叠Material 材料、原料Emphasize 强调、着重Chipset 芯片组Removeable 可移动的、可删除的Dock 码头Housing 外壳Dimension 尺寸、大小Solder 焊接DDR (double data rate)双精度数据速率Round 圆的、大约VGA (video graphics Adapter)视频图形适配器Central process unit 中央处理单元（CPU）Confuse 困惑、糊涂Slot 槽、缝Module 模块、组件Detect 查明、发现Snap 捕捉Socket 插座、灯座Visible 明显、看得见Grid 栅格Invalid 无效的Capture 引起、获取Impact 冲击、碰撞Walk 走入、步入Accuracy 正确的、精确Rank 排序、分类Retain 保留、保持Primary 主要的Retain 保留Part 部分、分解Preface 序言Index 索引Content 目录、容Impact 冲击、碰撞Remainder 余数Sequence 序列Role 作用、地位、角色Debugger 调试Attempt 尝试、试图Procedure 过程Performance 性能、表现Balance 平衡Quality 质量、品质Assigned 指定、赋值Discard 丢弃Modify 修改、改变Extra 额外、改变Octal 进制Declaration 描述、说明Hook 钩、钩住Track 跟踪、追踪、小道Conflict 冲突Usage 使用、用法Installation 安装、装置Blink 闪烁、闪亮Volatile 易变的（C语言中寄存器操作的关键字）Risk 冒险、风险、危险Retain 保留、保持Frame 框架、结构Horizontal 水平Vertical 垂直Pixel 像素Comfortable 舒服、舒适Scheme 计划，组合Compare 比较Feature 特点、特性Illustrate 说明Giant 巨大的、特大的Evolved 使发展、使进步Variety 多样的、种类Router 路由器Implement 执行、工具Protocol 协议Preset 预先布置、设定Measurement 测量Correct 正确的、合适的、纠正Desire 希望、渴望Final 最后的Steady 稳定的、不变的Reference 参考点Command 命令、指挥Pattern 模式、样品、花样Dynamic 动态的Static 静态的Remote 原理Regard 尊重、问候Mainframe 主机、大型机Composed of 由什么组成Embed 把……嵌入Parallel 并行Neural network 神经网络Advent 到来Reach 到达、到来Current directory 当前路径Scale 规模、比例Science 科学Theory 理论、原理、学说Engineer 工程师Modify 修改Revise 修订、改变Reduce 减少Expand 扩Experiment 尝试、体验、实验Evaluate 评价、估价、求值Traditional 传统的Branch 树枝、分支Unify 使联合、统一Higher performance 高性能Low cost 低功耗Search 检索、查找Mobile 移动的、变幻的Tap 开发、插头、抽头Region 地球、地区Fireware 固件Sofeware 软件Hardware 硬件Flat 平的Cathode 阴极Slot 槽PCI (peripheral component Interconnect)外部控制器接口Bank 库、储存器Kernel 核Extension 扩展、扩充Kernel 核、核程序Slash 斜杠Grant 授予Reference 引用、参考Unique 独特的Status 状态Generic 类别、一般的Customize 定制Process 进程Each 各自Scheduler 调度Entry 进入Arrival 到达Attention 注意、照料、照顾Among 经过Procedure 程序、工序Time slice 时间片Preempt 占先、取代Illegal 不合法的Time 时间Calendar 日历Alarm 闹钟Motorola 摩托罗拉Merge 合并Accession 增减、正式加入Term 学期、术语、条款Explosion 爆炸、爆发、扩Associative 联想、联合Intensive 强烈Handle 处理Extend 延伸、扩大FTP file transfer protocolAvailable 可用的Packet 包，信息包Adapter 适配器Bundle 一批、一捆Modem 调制解调器Flat 平滑的、单调的Tier 层Abstract 抽象Image/figure 形象Editor 编辑器Schema 模式Redundancy 冗余Inconsistency 不一致Query 查询SQL structured query language 结构化查询语言Arise 产生，出现Available 可用的，有空的Recovery 恢复Portable 可移植的Filestore 文件储存器Slove 解决，解答Exhibit 证明，呈现Roughly 粗糙的Certain 某一、必然的Typical 典型的，特有的Instance 例子，实例Restore 归还，交换，恢复Procedure 手续，工序，过程Refer 提到，本质Treat 招待，处置With 和RTOS real time operation system 实时操作系统Action 行动，活动Instead 代理Expression 表现Function 函数Conditiona statement 条件语句Threshold 如么、入口Bulk 大块、大量Exec (execute) 执行Pending 直到，未解决的、等待Wrapper 包装、封装Immutable 不可变的、不可改变的Emerge 浮现，出现Reliable 可靠性，可信赖的Flexible 灵活Together 一起，一同Packet 小包detectFormat 格式化，形式Pervious 可行的，同名的Evolve 进化，推出Deploy 展开，配置Split 分开，分为Conference 会议，讨论Phrase 短语，说法Bundle 捆，批Detect 洞察，检波，检测Analog 模拟的Suggest 建议，提议Complex 复杂，分成Ground 地面，土地Route 路，路线Station 站，车站Instant 瞬间，此刻Account 账户，账目Initiate 开始，初始化Alert 警觉，报警，闹钟Validated 证实，生效，验证Perform 执行，履行Course 科目，进程，方针Billion 十亿Million 百万Thousand 千Removable 可移动的Dial 钟Motor 马达Simulator 模拟器Graph 图表，图形Track 小道，监测Weight 权重，重任，重量Workstation 工作站Visual 视觉的，视力Whatever 无论如何，无论怎么样Below 在下面，到下面Manage 使用，完成Resolution 分辨率，解决Refresh 刷新Vary 变化，不同Landscape 风景画，横版Portrait 肖像画，竖版Default 未履行的，默认的Distribute 分配，分立，分布Switch 开关，转换Relay 继电器，中继Node 节点，结点Trap 陷阱Abort 终止Fault 故障Exceptions 异常Encode 编码Decode 解码Volume 大量的，体积的Research 研究Untruly 人性，不守规矩Role 作用，地位Volatile 异变的Storage 贮藏Handle 处理Vary 变换，变异，违反Mechanism 机制，机器，性能Exploit 开发，开拓，开采Configure 配置Common 通俗，通常Synchronous 同步Asynchronous 串行Serial Port 串口Parallel 平行Accurate 精确的Elapse 消逝，时间Evaluation 评鉴，平菇，估值Determine 决定，制度Branch 分支，树枝Efficient 高效的Count 计算Arrange 安排，排列Reload 重装，再装Otherwise 否则，另外Timing 定时，调速Crystal 结晶，水晶Role角色，任务Complex 复杂的，复合的Sink 下沉，消遣，（heat sink 散热片）Simplest 最简单的Preset 事先装置Socket 插座Wise 明智，智慧Screw 旋，拧Within 部，里面Dominate 支配，控制Entire 全部，整个，全体Resolve 决定Belong 属于，应归于Issue 发生，发布Order 命令，秩序Reside 居住，存在Confusion 混乱的，令人迷惑的Toggle 切换Formula 公式，趋势Slide 滑动，幻灯片Remote 遥远的，远程Encounter 遭遇，遇到Dim 暗淡，不光明Array 数组，阵列Assign 分配，指定Available 有用，有效Begin 开始，创建Batch 批处理，批量Bill 清单Blip 标志CAM computer aided manufacturing 计算机辅助制造Capture 捕捉，收集Check 检测Circuit 电路Construction 构造CRT cathode ray Tube 阴极射线管Anode 阳极Cathode 阴极Calculation 计算，估计Current 当前Previous 过去Future 将来Demo 演示，示威Shot 射击Attach 附带的Zoom 放大Almost 几乎完美的Trigger 扳机，触发Successive 连续Period 时期，周期Desire 希望，期望SDK software development deck 软件开发工具包Latency 潜在Parallel 并联Premium 额外Electromechanical 机电的Append 附加，贴上Virtual 确实的，事实的【计算机】虚拟的Shake 动摇，摇头Dumb 哑的，无声的Layout 布局Peer 对等Forward 向前，提前Coupler ，配合，耦合Response 反应，响应Console 控制台Extension 分机Syntax 语法Authenticate 认证，证实Revision 修改Pattern 样品，模式Equation 方程式，等式Signal 信号Single 单一的，唯一的Cable 电缆Application 应用Request 请求，需求Response 响应，回应Indicate 表明Frame 框架Arrow 箭头Audio 音讯Assign 指定，指派Binary 二进制Decimal 十进制Hexadecimal 十六进制Octal 八进制Block 块，区Boolean 布尔值Breakpoint 断点Character 字符Template 模版Client 客户，客户端Equal 相等Enum 枚举Feature 特性Database 数据库Reference 引用，参考Export 引出，汇出Inline 联Heap 堆Menu 菜单Import 导入，汇入Message 信息，消息Module 模组，模块Mouse 鼠标Option 选项Package 套件Prefix 前方，前序Random 随机Protocol 协议SPI serial peripheral interface 串行外围接口Fraction 分数Vivid 形象，生动Drag 拖动Drop 放弃Site 站点SQL structured query language 结构化查询语言Professional 专业，专业性的Implemented 实现，执行，最初Inherit 继承Consume 消耗Significant 重要的，有意义的Parity 同等，对等Construct 修建,构建，创立Brace 支撑，准备好，支持Entire 全部，全体Corresponds 相一致，相当Surrogate 代表，代理Usage 使用，用法Available 有空，可获得的，通用Implicit 绝对的，暗含，隐含Inherent 固有，天生，先天Inheritance 继承Storing 保管，入库，储存Raw 未加工，生的Instead 代替，顶替Obsolete 废弃的，老式的，淘汰的Distinction 区别，物质Margin 边缘，围Sector 扇区Density 密度Delve 探索Quote 引用，引述Daemon 守护，守护进程Delve 探索Clarity 清晰URL uniform resource locator 在Internet的WWW服务程序上用于指定信息位置的表示方法Flaw 瑕疵，缺点Dialog box 对话框Thread 线程，线索Release 版本，发布Imagine 想，设想Duration 持续Reference 参考Native code 本机代码Duration 持续，期间，连续Acceptable 可接受的Designate 指明Ordinal 顺序Construct 修建，建造Bracket 括号Notation 记号Rather 稍微，相当Scope 围，见识，眼界Concept 观念，概念Discuss 谈论，讨论Assembler 汇编程序，汇编，汇编器Execute 执行Interpreter 解释器，解释Slow 慢Fast 快Professional 专业的，专业性的Debugger 调试程序Subroutine 子程序Routine 例程system call 系统调用graft 移植，嫁接precede 处于。
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Hypertext ‘89 Proceedings
e2
November 1989
experimental hypertext development. Because of the iterative nature of system design, the flow of information in this system is non-linear, so Figure 1 will require a detailed explanation. First, the purpose, inputs, and outputs of processes will be described. Then, all the stores used by these processes will be described (in alphabetical order). After this introduction, a second pass through the processes will show how the model can help organize the asynchronous design evaluation process, as applied to NaviText’” systems. In the discussion, the following special fonts will be used to refer to processes, and data stores. Process I. Task Ana/vsis. Task Analysis is used to determine the information processing PURPOSE: needs of users. These needs depend on (1) the type of user, (2) the tasks being performed by the user, and to some degree, (3) the technology available to the user. Since the user changes over time, by gaming knowledge or becoming fatigued, another important factor is (4) time. INPUT: The inputs to task analysis come from interaction with users and knowledge of their tasks, from the Local Empirical Base (e.g., usage data), from experiences with locally developed systems (Local Systems), and from task-specific analysis of documents (Text Technology Base). OUTPUT: The outputs from task analysis can go into a Local Empirical Base or directly into a Local Design Base. Process 2. Document AnahMs. Document analysis is used to determine the information content, PURPOSE: structure, and format of a (potential) hypertext. The importance of the analysis of logical vs. physical structure, identifying “natural” units of information, and the linking of this information has been discussed in detail in [GlusSS] and [Glus89]. INPUT: The inputs to document analysis can be an analysis of particular texts, or a summary of understood text technology from a Text Technology Base (e.g., the uses of multiple hierarchical organizations or ways of representing multiple versions). OUTPUT: The output of document analysis is an increased understanding of the structure of documents, stored in the Text Technology Base. Process 3. Literature Sufvev and Svstems Evaluation. PURPOSE: Literature survey and systems evaluation builds on the lessons learned by other researchers. The article by [Conk871 not only surveyed many research and commercial hypertext systems, but Such also compared these systems along many dimensions. dimensions can be used to help organize the structure of design support bases. INPUT: The inputs to literature survey and systems evaluation are (1) published research results and (2) local evaluations of existing systems. OUTPUT: The outputs of literature survey and systems evaluation add to the Text Technology Base and to the knowledge of other systems Empirical results and (Other Systems Technology Base). experiences from external research and systems must also be considered by an evaluative process (Interpretation of Data).
A Data Flow Model of Systems Development Research
Each of the processes, flows, and stores in Figure 1 represent an activity or result of hypertext research. The structure of the diagram is a reusable organizer for
INTRODUCTION
The development of new hypertext systems is a candidate for some of the development techniques that have been successful in other dynamic fields. The iterative design and evaluation prototyping lifecycle used in user interface development and the experimental programming strategy used in artificial intelligence provide us with paradigms for exploring new possibilities for the online delivery of information. Figure 1 shows a data flow diagram of a process model of an asynchronous design and evaluation method I have used for developing systems, most recently hypertext systems. In this paper, I will illustrate this model of system development, discussing the model both in terms of my own work on the NaviText’” family of hypertext browsers (per187], [PerlSS], [Per189b]), and in terms of other research. For each process in the model, there are issues in the methodology of developing a new technology that will also be addressed. This document is based on a data flow diagram (see the primer below) that has been flattened out for presentation. The original document was built in the “Software Through Pictures” system [IDE86]. The numbered sections in this document are keyed to the activity numbers in the diagram. Being asynchronous, the actual order of activities may not match the order of the activity numbers. This document will begin with a description of a data flow model of hypertext systems development research, including the processes and data (knowledge) stores. Then, experiences and results with NaviText’” SAM will be discussed in terms of the processes involved in its development. Ideally, the descriptions of the data flow elements would be popup notes, accessible during reading, but instead, some background on the data flow model must be covered. On a first reading, the rest of the introduction can be skimmed.