FPGA可编程逻辑器件芯片XCZU21DR-2FFVD1156I中文规格书

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FPGA可编程逻辑器件芯片XCKU040-1FFVA1156I中文规格书

General DescriptionXilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of system requirements with a focus on lowering total power consumption through numerous innovative technological advancements.Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic andnext-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of various system-level functions.Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Zynq® UltraScale+ MPSoCs : Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's firstprogrammable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leadingprogrammable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.Family ComparisonsUltraScale Architecture and Product Data Sheet: OverviewDS890 (v3.14) September 14, 2020Product SpecificationTable 1:Device ResourcesKintex UltraScale FPGAKintex UltraScale+FPGA Virtex UltraScale FPGA Virtex UltraScale+FPGA Zynq UltraScale+MPSoCZynq UltraScale+RFSoCMPSoC Processing System ✓✓RF-ADC/DAC ✓SD-FEC✓System Logic Cells (K)318–1,451356–1,843783–5,541862–8,938103–1,143489–930Block Memory (Mb)12.7–75.912.7–60.844.3–132.923.6–94.5 4.5–34.622.8–38.0UltraRAM (Mb)0–8190–3600–3613.5–45.0HBM DRAM (GB)0–16DSP (Slices)768–5,5201,368–3,528600–2,8801,320–12,288240–3,5281,872–4,272DSP Performance (GMAC/s)8,1806,2874,26821,8976,2877,613Transceivers12–6416–7636–12032–1280–728–16Max. Transceiver Speed (Gb/s)16.332.7530.558.032.7532.75Max. Serial Bandwidth (full duplex) (Gb/s)2,0863,2685,6168,3843,2681,048Memory Interface Performance (Mb/s)2,4002,6662,4002,6662,6662,666I/O Pins312–832280–668338–1,456208–2,07282–668152–408Virtex UltraScale+ HBM Device-Package Combinations and Maximum I/OsTable 11:Virtex UltraScale+ HBM FPGA Feature SummaryVU31PVU33P VU35P VU37P VU45P VU47P VU57P System Logic Cells 961,800961,8001,906,8002,851,8001,906,8002,851,8002,851,800CLB Flip-Flops 879,360879,3601,743,3602,607,3601,743,3602,607,3602,607,360CLB LUTs439,680439,680871,6801,303,680871,6801,303,6801,303,680Max. Distributed RAM (Mb)12.512.524.636.724.636.736.7Block RAM Blocks 6726721,3442,0161,3442,0162,016Block RAM (Mb)23.623.647.370.947.370.970.9UltraRAM Blocks 320320640960640960960UltraRAM (Mb)90.090.0180.0270.0180.0270.0270.0HBM DRAM (GB)4888161616CMTs (1 MMCM and 2 PLLs)4481281212Max. HP I/O (1)208208416624416624624DSP Slices 2,8802,8805,9529,0245,9529,0249,024System Monitor1123233GTY Transceivers 32.75Gb/s (2)32326496649632GTM Transceivers 58.0Gb/s 00000032100G / 50G KP4 FEC 00000016/32Transceiver Fractional PLLs 16163248324832PCIE4 (PCIe Gen3 x16) 0012120PCIE4C (PCIe Gen3 x16 /Gen4 x8 / CCIX)(3)4444444150G Interlaken––24244100G Ethernet w/RS-FEC22585810Notes:1.HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V .2.GTY transceivers in the FLGF1924 package support data rates up to 16.3Gb/s. See Table 12.3.This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale+ Devices Integrated Block for PCI Express Product Guide , for details on compatibility mode.Table 12:Virtex UltraScale+ HBM Device-Package Combinations and Maximum I/OsPackage(1)(2)(3)(4)PackageDimensions(mm)VU31P VU33P VU35P VU37P VU45P VU47P VU57PHP, GTY HP, GTYHP, GTYHP, GTYHP, GTYHP, GTYHP, GTY, GTMFSVH192445x45208,32FSVH210447.5x47.5208,32416,64416,64FSVH289255x55416,64624,96416,64624,96FSVK289255x55624, 32, 32Notes:1.Go to Ordering Information for package designation details.2.All packages have 1.0mm ball pitch.3.Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See the UltraScale Architecture Product Selection Guide for details on inter-family migration.4.Consult UG583, UltraScale Architecture PCB Design User Guide for specific migration details.Package(1)(2)(3)(4)Package Dimensions(mm)ZU4EV ZU5EV ZU7EV HD, HP GTH, GTY HD, HP GTH, GTY HD, HP GTH, GTYSFVC784(5)23x2396, 1564, 096, 1564, 0FBVB90031x3148, 15616, 048, 15616, 048, 15616, 0FFVC115635x3548, 31220, 0FFVF151740x4048, 41624, 0In FPGAs and the PL of the MPSoCs and RFSoCs, sensor outputs and up to 17 user-allocated external analog inputs are digitized using a 10-bit 200 kilo-sample-per-second (kSPS) ADC, and the measurements System MonitorThe System Monitor blocks in the UltraScale architecture are used to enhance the overall safety, security, and reliability of the system by monitoring the physical environment via on-chip power supply and temperature sensors and external channels to the ADC.All UltraScale architecture-based devices contain at least one System Monitor. The System Monitor in UltraScale+ FPGAs and the PL of Zynq UltraScale+ MPSoCs and RFSoCs is similar to the Kintex UltraScale and Virtex UltraScale devices but with additional features including a PMBus interface.Kintex UltraScaleVirtex UltraScaleKintex UltraScale+Virtex UltraScale+Zynq UltraScale+ PLZynq UltraScale+ PSADC 10-bit 200kSPS 10-bit 200kSPS 10-bit 1MSPSInterfacesJTAG, I2C, DRPJTAG, I2C, DRP , PMBusAPB。

FPGA可编程逻辑器件芯片XCKU060-2FFVB1156I中文规格书

Pin DefinitionsTable1-5 lists the pin definitions used in UltraScale and UltraScale+ device packages.Table 1-5:Pin DefinitionsPin Name Type Direction DescriptionUser I/O PinsIO_L[1to24][P or N]_T[0to3] [U or L]_N[0to12]_ [multi-function]_[bank number] orIO_T[0to3][U or L]_N[0to12]_[multi-function]_[bank number]Dedicated Input/Output Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:•IO indicates a user I/O pin.•L[1to24] indicates a unique differential pair with P (positive) and N (negative) sides. User I/O pins without the L indicator are single-ended.•T[0 to 3][U or L] indicates the assigned byte group and nibble location (upper or lower portion) within that group for the pin.•N[0 to 12] the number of the I/O within its byte group.•[multi-function] indicates any other functions that the pin can provide. If not used for this function, the pin can be a user I/O.•[bank number] indicates the assigned bank for the user I/O pin.User I/O Multi-Function PinsGC or HDGC Multi-function Input/OutputFour global clock (GC) pin pairs are in each bank. HDGCpins have direct access to the global clock buffers. GC pinshave direct access to the global clock buffers, MMCMs,and PLLs that are in the clock management tile (CMT)adjacent to the same I/O bank. GC and HDGC inputsprovide dedicated, high-speed access to the internalglobal and regional clock resources. GC and HDGC inputsuse dedicated routing and must be used for clock inputswhere the timing of various clocking features isimperative. GC or HDGC pins can be treated as user I/Owhen not used as input clocks.Up-to-date information about designing with the GC(or HDGC) pin is available in the UltraScale ArchitectureClocking Resources User Guide (UG572) [Ref6].VRP(1)Multi-function N/A This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).Die Level Bank Numbering OverviewBanking and Clocking Summary•For each device, not all banks are bonded out in every package.GTH/GTY/GTM Columns•One GTH/GTY Quad=Four transceivers=Four GTHE3 or GTYE3 primitives.•One GTM Dual=Two transceivers=Two GTME3 primitives•Not all GT Quads/Duals are bonded out in every package.•Also shown are quads/duals labeled with RCAL. This specifies the location of the RCAL masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device.•The XY coordinates shown in each quad/dual correspond to the transceiver channel number found in the pin names for that quad/dual, as shown in Figure1-1.•An alphabetic designator is shown in each quad/dual. Each letter corresponds to the columns in Table1-7 and Table1-9.•The power supply group is shown in brackets [] for each quad/dual.I/O Banks•Each user I/O bank has a total of 52 I/Os where 48 can be used as differential (24differential pairs) or single-ended I/Os. The remaining four function only assingle-ended I/Os. All 52 pads of a bank are not always bonded out to pins.• A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as partial.•Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock resources.•Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.•Banks are arranged in columns and separated into rows which are pitch-matched with adjacent PHY, clock regions, and GT blocks.•An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table1-7 and Table1-9.。

FPGA可编程逻辑器件芯片XC6VSX315T-L1FFG1156I中文规格书

Packaging OverviewSummaryThis chapter covers the following topics:•Introduction•Device/Package Combinations and Maximum I/Os•Pin DefinitionsIntroductionThis section describes the pinouts for Virtex®-5 devices in the 1.00mm pitch flip-chip fine-pitch BGA packages.Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages thatare optimally designed for improved signal integrity and jitter. Package inductance isminimized as a result of optimal placement and even distribution as well as an increasednumber of Power and GND pins.All of the devices supported in a particular package are pinout compatible and are listed inthe same table (one table per package). Pins that are not available for the smaller devicesare listed in the “No Connects” column of each table.For Virtex-5Q devices, the EF package is offered. The only difference between an EF and anFF package is that the discrete substrate capacitors on the EF package are coated withepoxy. The coating is comprised of an undercoat epoxy that is dispensed under thecapacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All otherpackage construction characteristics of the EF matches that of the FF package. The EFpackage changes are noted in Chapter4, “Mechanical Drawings.”Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/Ostandards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG,configuration, and power/ground pins, are listed at the end of each table. Table1-7provides definitions for all pin types.For information on package electrical characteristics and how the characteristics aremeasured, refer to UG112: Device Package User Guide found on the Xilinx website.For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updatesto this document.Pin DefinitionsDedicated Configuration Pins (1)CCLK_0Input/Output Configuration clock. Output and input in Master mode or Input in Slave mode.CS_B_0Input In SelectMAP mode, this is the active-low Chip Select signal. D_IN_0Input In bit-serial modes, D_IN is the single-data input.DONE_0Input/OutputDONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence.D_OUT_BUSY_0OutputIn SelectMAP mode, BUSY controls the rate at which configuration data is loaded.In bit-serial modes, DOUT gives preamble and configuration data to down-stream devices in a daisy chain.HSWAPEN_0InputEnable I/O pullups during configurationINIT_B_0Bidirectional(open-drain)When Low, this pin indicates that the configuration memory is being cleared.When held Low, the start of configuration is delayed. During configuration, aLow on this output indicates that a configuration data error has occurred.M0_0, M1_0, M2_0Input Configuration mode selectionPROGRAM_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor.RDWR_B_0Input In SelectMAP mode, this is the active-low Write Enable signal.TCK_0Input Boundary-Scan Clock.TDI_0Input Boundary-Scan Data Input.TDO_0Output Boundary-Scan Data Output.TMS_0Input Boundary-Scan Mode Select.DXP_0, DXN_0 N/ATemperature-sensing diode pins (Anode: DXP; Cathode: DXN).Reserved Pins RSVD N/A Reserved pins—must be tied to ground.FLOAT N/ADo not connect this pin to the board. Leave floating.Other Pins GND N/A Ground.VBATT_0N/A Decryptor key memory backup supply; this pin should be tied to V CC or GND.VCCAUX N/A Power-supply pins for auxiliary circuits.VCCINT N/A Power-supply pins for the internal core logic.VCCO_#(2)N/APower-supply pins for the output drivers (per bank).Table 1-7:Virtex-5 FPGA Pin Definitions (Continued)Pin NameDirectionDescriptionFF323 Package—LX20T and LX30T17IO_L8P_CC_17P1017IO_L8N_CC_17(2)N1017IO_L9P_CC_17U1617IO_L9N_CC_17(2)U1517IO_L10P_CC_17V1817IO_L10N_CC_17(2)V1717IO_L11P_CC_17R10Table 2-1:FF323 Package—LX20T and LX30T (Continued)BankPin DescriptionPin NumberNo Connect (NC)Chapter 2:Pinout TablesFF324 Package—LX30 and LX50Table 2-2:FF324 Package—LX30 and LX50Bank Pin Description Pin Number No Connect (NC)0DXP_0L100DXN_0L90AVDD_0H100AVSS_0H90VP_0J100VN_0K90VREFP_0K100VREFN_0J90VBATT_0T180PROGRAM_B_0U180HSWAPEN_0T170D_IN_0R70DONE_0P80CCLK_0N80INIT_B_0M80CS_B_0R160RDWR_B_0P150RSVD(3)R140RSVD(3)P140TCK_0M90M0_0N120M2_0N130M1_0L110TMS_0V50TDI_0U50D_OUT_BUSY_0T60TDO_0U61IO_L0P_A19_1F111IO_L0N_A18_1 G111IO_L1P_A17_1 G101IO_L1N_A16_1 F9FF324 Package—LX30 and LX50Table 2-2:FF324 Package—LX30 and LX50 (Continued)Bank Pin Description Pin Number No Connect (NC) 18IO_L11P_CC_18 N618IO_L11N_CC_18(2)P518IO_L12P_VRN_18 T218IO_L12N_VRP_18 T118IO_L13P_18 N718IO_L13N_18 P718IO_L14P_18 V118IO_L14N_VREF_18 U118IO_L15P_18 P418IO_L15N_18 R418IO_L16P_18 V218IO_L16N_18 V318IO_L17P_18 R518IO_L17N_18 R618IO_L18P_18 U318IO_L18N_18 T318IO_L19P_18 T418IO_L19N_18 U4NA GND D1NA GND J1NA GND P1NA GND B2NA GND M2NA GND U2NA GND E3NA GND R3NA GND H4NA GND V4NA GND A5NA GND L5NA GND D6NA GND K6NA GND P6。

FPGA可编程逻辑器件芯片XCZU11EG-2FFVC1156E中文规格书

120 M12 1
15
4
-
-
-
121 M16 1
15
5
-
-
-
122 K14 1
15
6
-
-
-
123 L16 1
15
7
-
-
-
-
-
-
15
8
-
-
-
-
-
-
15
9
-
-
-
-
-
-
15
10
-
-
-
-
-
-
15
11 58 K13 85 125 K15 1
15
12 59 K14 86 126 L12 1
15
13 60 J12 87 127 K16 1
Used/Tot
40/64(62%) 64/224(29%) 61/160(38%) 26/64(41%) 23/33(70%)
CoolRunner-II Data Sheets and Application Notes
The LCD Interface presented in this application note is simple and straightforward. Additionally, CoolRunner-II devices are ideal candidates for driving LCDs due to their low cost, low power and ease of use.
14
5
49 N11 -
100 N13 1
14
6
- P11 68

FPGA可编程逻辑器件芯片XCZU15EG-2FFVB1156I中文规格书

Table 1‐4:Pin DefinitionsPin Name Type Direction Description User I/O PinsIO_L[1to24][P or N]_T[0to3] [U or L]_N[0to12]_ [multi-function]_[bank number] orIO_T[0to3][U or L]_N[0to12]_[multi-function]_[bank number]Dedicated Input/Output Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:•IO indicates a user I/O pin.•L[1to24] indicates a unique differential pair with P (positive) and N (negative) sides. User I/O pins without the L indicator are single-ended.•T[0 to 3][U or L] indicates the assigned byte group and nibble location (upper or lower portion) within that group for the pin.•N[0 to 12] the number of the I/O within its byte group.•[multi-function] indicates any other functions that the pin can provide. If not used for this function, the pin can be a user I/O.•[bank number] indicates the assigned bank for the user I/O pin.User I/O Multi-Function PinsGC or HDGC Multi-function Input Four global clock (GC or HDGC) pin pairs are in each bank. HDGC pins have direct access to the global clock buffers. GC pins have direct access to the global clock buffers and the MMCMs and PLLs that are in the clock management tile (CMT) adjacent to the same I/O bank. GC and HDGC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC and HDGC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative.Up-to-date information about designing with the GC (or HDGC) pin is available in the UltraScale Architecture Clocking Resources User Guide (UG572) [Ref7]VRP(1)Multi-function N/A This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司Other Dedicated PinsDXNDedicatedN/ATemperature-sensing diode pins (Anode: DXP; Cathode: DXN). The thermal diode is accessed by using the DXP and DXN pins. When not used, tie to GND.To use the thermal diode an appropriate external thermal monitoring IC must be added. Consult the external thermal monitoring IC data sheet for usage guidelines.DXPTable 1‐4:Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionFootprint Compatibility between PackagesZynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices with the same number of package pins and the same preceding alphabetic designator. For example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the XCZU9EG-FFVC900. Pins that are available in one device but are not available in another device are labeled as No Connects in the other device's package file.compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packagessection of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref14].Table1-5 shows the footprint compatible devices available for each package. See theZynq UltraScale+ MPSoC Overview (DS891) [Ref1] for specific package letter code options.All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.Table 1‐5:Footprint CompatibilityPackages Footprint Compatible DevicesSBVA484 SFRA484XCZU2CG, XCZU2EG,XAZU2EGXCZU3CG, XCZU3EG,XAZU3EG, XQZU3EGSFVA625XCZU2CG, XCZU2EG,XAZU2EG XCZU3CG, XCZU3EG, XAZU3EGSFVC784 SFRC784XCZU2CG, XCZU2EG,XAZU2EGXCZU3CG, XCZU3EG,XAZU3EG, XQZU3EGXCZU4CG, XCZU4EG,XCZU4EV, XAZU4EVXCZU5CG, XCZU5EG,XCZU5EV, XAZU5EV,XQZU5EVFBVB900 FFRB900XCZU4CG, XCZU4EG,XCZU4EVXCZU5CG, XCZU5EG,XCZU5EV, XQZU5EVXCZU7CG, XCZU7EG,XCZU7EV, XAZU7EV,XQZU7EVFFVC900 FFRC900XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG,XQZU9EGXCZU15EG, XQZU15EGFFVB1156 FFRB1156XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG,XQZU9EGXCZU15EG, XQZU15EGFFVC1156 FFRC1156XCZU7CG, XCZU7EG,XCZU7EV, XQZU7EVXCZU11EG, XQZU11EGFFVD1156XCZU21DR, XQZU21DRFFVE1156 FSVE1156XCZU25DR XCZU27DR, XCZU43DR,XCZU47DR, XCZU49DRXCZU28DR, XQZU28DRFFVB1517XCZU11EG XCZU17EG XCZU19EG, XQZU19EGDie Level Bank Numbering OverviewBanking and Clocking Summary•For each device, not all banks are bonded out in every package.GTH/GTY Columns•One GT Quad=Four transceivers=Four GTHE4 or GTYE4 primitives.•Not all GT Quads are bonded out in every package.•Also shown are quads labeled with RCAL. This specifies the location of the RCAL masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device.•The XY coordinates shown in each quad correspond to the transceiver channel number found in the pin names for that quad, as shown in Figure1-2.•An alphabetic designator is shown in each quad. Each letter corresponds to the columns in Table1-6 and Table1-7.•The power supply group is shown in brackets [ ] for each quad.I/O Banks•Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential (24differential pairs) or single-ended I/Os. The remaining four function only assingle-ended I/Os. All 52 pads of a bank are not always bonded out to pins.• A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are labeled as partial.•Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12 differential pairs) or single-ended I/Os.•Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock resources.•Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.•Banks are arranged in columns and separated into rows which are pitch-matched with adjacent PHY, clock regions, and GT blocks.•An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table1-6 and Table1-7.。

FPGA可编程逻辑器件芯片XCKU025-2FFVA1156I中文规格书

Virtex™-E 1.8 V Field Programmable Gate ArraysDS022-2 (v3.0) March 21, 2014Production Product SpecificationUseful Application ExamplesThe Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available Standard Usage The circuit shown in Figure 27 resembles the B UFGDLL macro implemented to provide access to the RST andLOCKED pins of the CLKDLL.Board Level Deskew of Multiple Non-Virtex-E DevicesThe circuit shown in Figure 28 can be used to deskew a system clock between a Virtex-E chip and other non-Vir-tex-E chips on the same board. This application is com-monly used when the Virtex-E device is used in conjunction with other standard products such as SRAM or DRAM devices. While designing the board level route, ensure that the return net delay to the source equals the delay to the other chips involved.Board-level deskew is not required for low-fanout clock net-works. It is recommended for systems that have fanout lim-itations on the clock network, or if the clock distribution chip cannot handle the load.Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of theLOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement.The dll_mirror_1 files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit.Deskew of Clock and Its 2x MultipleThe circuit shown in Figure 29 implements a 2x clock multi-plier and also uses the CLK0 clock output with a zero ns skew between registers on the same chip. Alternatively, a clock divider circuit can be implemented using similar con-nections.Figure 27: Standard DLL ImplementationFigure 28: DLL Deskew of Board Level Clock Figure 29: DLL Deskew of Clock and 2x MultipleDS022-4 (v3.0) March 21, 2014Production Product SpecificationHQ240 High-Heat Quad Flat-Pack Packages XCV600E and XCV1000E devices in High-heat dissipation Quad Flat-pack packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless device-dependent as indicated in the footnotes. If the pin is not used as V REF , it can be used as general I/O. Immedi-ately following Table 8, see Table 9 for Differential Pair infor-mation.486P56P57√-496P52P532-506P49P503VREF 516P46P474VREF 526P41P42√-536P38P392-546P35P364VREF 556P33P345VREF 567P27P28√-577P23P244VREF 587P20P212-597P17P18√-607P12P134VREF 617P9P103VREF 627P6P72-637P4P56VREF Notes: 1.AO in the XCV50E.2.AO in the XCV50E, 100E, 200E, 300E.3.AO in the XCV50E, 200E, 300E, 400E.4.AO in the XCV50E, 300E, 400E.5.AO in the XCV100E, 200E, 400E.6.AO in the XCV100E, 400E.7.AO in the XCV50E, 200E, 400E.8.AO in the XCV100E.Table 7: PQ240 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E, XCV400EPairBank P Pin N Pin AO Other Functions Table 8: HQ240 — XCV600E, XCV1000E Pin #Pin Description Bank P240VCCO 7P239TCK NA P238IO 0P237IO_L0N 0P236IO_VREF_L0P 0P235IO_L1N_YY 0P234IO_L1P_YY 0P233GND NA P232VCCO 0P231IO_VREF 0P230IO_VREF 0P229IO_VREF_L2N_YY 0P228IO_L2P_YY 0P227GND NA P226VCCO 0P225VCCINT NA P224IO_L3N_YY 0P223IO_L3P_YY 0P222IO_VREF 01P221IO_L4N_Y 0P220IO_L4P_Y 0P219GND NA P218IO_VREF_L5N_Y 0P217IO_L5P_Y 0P216IO_VREF 0P215IO_LVDS_DLL_L6N 0P214VCCINT NA P213GCK30P212VCCO 0P211GND NA。

FPGA可编程逻辑器件芯片XCKU040-2FFVA1156I中文规格书

SummaryThe Xilinx® Kintex® UltraScale™ FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. The -1L devices can operate at either of two V CCINT voltages, 0.95V and 0.90V and are screened for lower maximum static power. When operated at V CCINT = 0.95V, the speed specification of a -1L device is the same as the -1 speed grade. When operated at V CCINT = 0.90V, the -1L performance and static and dynamic power is reduced.DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.This data sheet, part of an overall set of documentation on the UltraScale architecture-based devices, is available on the Xilinx.DC CharacteristicsKintex UltraScale FPGAs Data Sheet:DC and AC Switching CharacteristicsDS892 (v1.19) September 22, 2020Product SpecificationTable 1:Absolute Maximum Ratings (1)Symbol Description Min Max UnitsFPGA LogicV CCINT Internal supply voltage–0.500 1.100V V CCINT_IO (2)Internal supply voltage for the I/O banks –0.500 1.100V V CCAUX Auxiliary supply voltage–0.500 2.000V V CCBRAM Supply voltage for the block RAM memories –0.500 1.100V V CCOOutput drivers supply voltage for HR I/O banks –0.500 3.400V Output drivers supply voltage for HP I/O banks –0.500 2.000V V CCAUX_IO (3)Auxiliary supply voltage for the I/O banks –0.500 2.000V V REFInput reference voltage–0.500 2.000V V IN (4)(5)(6)I/O input voltage for HR I/O banks–0.400V CCO +0.550V I/O input voltage for HP I/O banks–0.550V CCO +0.550V I/O input voltage (when V CCO = 3.3V) for V REF and differential I/O standards except TMDS_33(7)–0.4002.625VProduction Silicon and Software StatusIn some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases.Table22 lists the production released Kintex UltraScale FPGAs, speed grade, and the minimum corresponding supported speed specification version and Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.Table 22:Kintex UltraScale FPGAs Production Software and Speed Specification Release(1)DeviceSpeed Grade, Temperature Ranges, and V CCINT Operating Voltages1.0V0.95V0.90V -3E-2E, -2I-1C, -1I-1M-1LI-1LI(3)XCKU025(2)N/A Vivado Tools 2015.3 v1.23N/A N/A N/AXCKU035(2)Vivado Tools 2015.2.1v1.23 for FBVA676 andFFVA1156 packagesVivado Tools 2015.1 v1.23 forFBVA676 and FFVA1156 packages N/A Vivado Tools 2015.3 v1.23 Vivado Tools 2015.3 v1.23 for FBVA900N/AVivado Tools 2015.4 v1.23 for SFVA784N/A Vivado Tools 2015.4 v1.23 forSFVA784XCKU040(2)Vivado Tools 2015.2.1v1.23 for FBVA676 andFFVA1156 packagesVivado Tools 2015.1 v1.23 forFBVA676 and FFVA1156 packages N/A Vivado Tools 2015.3 v1.23 Vivado Tools 2015.3 v1.23 for FBVA900N/AVivado Tools 2015.4 v1.23 for SFVA784N/A Vivado Tools 2015.4 v1.23 forSFVA784XCKU060(2)Vivado Tools 2015.4 v1.23Vivado Tools 2015.2 v1.23N/A Vivado Tools2015.3 v1.23Vivado Tools 2015.4 v1.23XCKU085(2)Vivado Tools 2015.4 v1.24Vivado Tools 2015.3 v1.24N/A Vivado Tools 2016.1 v1.24 XCKU095N/A Vivado Tools 2015.3 v1.24N/A N/A N/A XCKU115(2)Vivado Tools 2015.4 v1.24Vivado Tools 2015.2.1 v1.24N/A Vivado Tools 2016.1 v1.24 XQKU040N/A Vivado Tools 2016.4 v1.23N/A N/A XQKU060N/A Vivado Tools 2016.4 v1.23N/A N/A XQKU095N/A Vivado Tools 2016.4 v1.24N/A N/A XQKU115N/A Vivado Tools 2016.4 v1.24N/A N/A N/A Notes:1.For designs developed using Vivado tools prior to 2016.4, see the design advisory answer record AR68169: DesignAdvisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs—New minimum production speed specification version (Speed File) required for all designs.2.Designs with these devices that use the dedicated System Monitor I2C (I2C_SCL and I2C_SDA) or PCIe reset (PERSTN0or PERSTN1) I/O where the bank 65 V CCO=3.3V must use Vivado Design Suite 2015.4 or later.3.The lowest power -1L devices, where V CCINT=0.90V, are listed in the Vivado Design Suite as -1LV.DescriptionI/OBankTypeSpeed Grade and V CCINT Operating VoltagesUnits1.0V0.95V0.90V-3-2-1/-1L-1LMin Max Min Max Min Max Min MaxLVDS TX DDR (TX_BITSLICE 4:1, 8:1)HP3001600300160030014003001400Mb/s HR3001250300125030012503001250Mb/sLVDS TX SDR (TX_BITSLICE 2:1, 4:1)HP150800150800150700150700Mb/s HR150625150625150625150625Mb/sLVDS RX DDR (RX_BITSLICE 1:4, 1:8)(2)HP3001600(3)3001600(3)3001400(3)3001400(3)Mb/s HR3001250300125030012503001250Mb/sLVDS RX SDR (RX_BITSLICE 1:2,1:4)(2)HP 150800150800150700150700Mb/s HR150625150625150625150625Mb/sDescriptionI/O Bank TypeSpeed Grade and V CCINT Operating VoltagesUnits1.0V 0.95V 0.90V-3-2-1/-1L-1L MinMaxMinMaxMinMaxMinMaxQDR II+(6)All All Single rank component 633600600550550QDRIV-XPHPAllSingle rank component800800800667667(7)Table 26:Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and PackageMemory StandardI/O Bank TypePackageDRAM TypeSpeed Grade, Temperature Ranges, and V CCINT Operating VoltagesUnits1.0V 0.95V0.90V-3E-2E-2I-1C/I -1M -1LI-1LI。

FPGA可编程逻辑器件芯片XQ6VLX130T-L1FFG1156I中文规格书

Chapter3:About Design ElementsCBD16CEMacro:16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous ClearSupported ArchitecturesThis design element is supported in the following architectures:CoolRunner™-IIIntroductionThis element is an asynchronously clearable,cascadable dual edge triggered binary counter.The asynchronous clear(CLR)input,when High,overrides all other inputs and forces the Q outputs,terminal count(TC),and clock enable out(CEO)to logic level zero,independent of clock transitions.The Q outputs increment when the clock enable input(CE)is High during the Low-to-High and High-to-Low clock(C)transition.The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.Create larger counters by connecting the CEO output of each stage to the CE input of the next stage and connecting the C and CLR inputs in parallel.CEO is active(High)when TC and CE are High.The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(t CE-TC),where n is the number of stages and the time t CE-TC is theCE-to-TC propagation delay of each stage.When cascading counters,use the CEO output if the counter uses the CE input or use the TC output if it does not.This counter is asynchronously cleared,outputs Low,when power is applied.For CPLD devices,you can simulate power-on by applying a High-level pulse on the PRLD global net.Logic TableInputs OutputsCLR CE C Qz:Q0TC CEO1X X00000X No change No change001↑Inc TC CEO01↓Inc TC CEOz=bit width-1TC=Qz•Q(z-1)•Q(z-2)•...•Q0CEO=TC•CEDesign Entry MethodThis design element is only for use in schematics.CPLD Libraries GuideUG606(v14.7)October2,2013Chapter2:Functional CategoriesDesign Element DescriptionSR8RLED Macro:8-Bit Shift Register with Clock Enable andSynchronous ResetSRD16CE Macro:16-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Asynchronous Clear SRD16CLE Macro:16-Bit Loadable Serial/Parallel-In Parallel-OutDual Edge Triggered Shift Register with Clock Enable andAsynchronous ClearSRD16CLED Macro:16-Bit Dual Edge Triggered Shift Register withClock Enable and Asynchronous ClearSRD16RE Macro:16-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Synchronous ResetSRD16RLE Macro:16-Bit Loadable Serial/Parallel-In Parallel-OutDual Edge Triggered Shift Register with Clock Enable andSynchronous ResetSRD16RLED Macro:16-Bit Dual Edge Triggered Shift Register withClock Enable and Synchronous ResetSRD4CE Macro:4-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Asynchronous Clear SRD4CLE Macro:4-Bit Loadable Serial/Parallel-In Parallel-Out DualEdge Triggered Shift Register with Clock Enable andAsynchronous ClearSRD4CLED Macro:4-Bit Dual Edge Triggered Shift Register with ClockEnable and Asynchronous ClearSRD4RE Macro:4-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Synchronous ResetSRD4RLE Macro:4-Bit Loadable Serial/Parallel-In Parallel-Out DualEdge Triggered Shift Register with Clock Enable andSynchronous ResetSRD4RLED Macro:4-Bit Dual Edge Triggered Shift Register with ClockEnable and Synchronous ResetSRD8CE Macro:8-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Asynchronous Clear SRD8CLE Macro:8-Bit Loadable Serial/Parallel-In Parallel-Out DualEdge Triggered Shift Register with Clock Enable andAsynchronous ClearSRD8CLED Macro:8-Bit Dual Edge Triggered Shift Register with ClockEnable and Asynchronous ClearSRD8RE Macro:8-Bit Serial-In Parallel-Out Dual Edge TriggeredShift Register with Clock Enable and Synchronous ResetSRD8RLE Macro:8-Bit Loadable Serial/Parallel-In Parallel-Out DualEdge Triggered Shift Register with Clock Enable andSynchronous ResetSRD8RLED Macro:8-Bit Dual Edge Triggered Shift Register with ClockEnable and Synchronous ResetCPLD Libraries GuideUG606(v14.7)October2,2013。

FPGA可编程逻辑器件芯片XCZU6CG-2FFVB1156I中文规格书

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching CharacteristicsLVDS DC Specifications (LVDS_25)The LVDS_25 standard is available in the HD I/O banks. See the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.Table 18: LVDS_25 DC SpecificationsSymbol DC Parameter Min Typ Max Units V CCO1Supply voltage 2.375 2.500 2.625VV IDIFF Differential input voltage:1003506002mV (Q – Q), Q = High(Q – Q), Q = HighV ICM Input common-mode voltage0.300 1.200 1.425V Notes:1.LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no V CCO requirements. Any V CCO can bechosen as long as the input voltage levels do not violate the Recommended Operating Condition (Table 2) specification for the V IN I/O pin voltage.2.Maximum V IDIFF value is specified for the maximum V ICM specification. With a lower V ICM, a higher V DIFF is tolerated only when therecommended operating conditions and overshoot/undershoot V IN specifications are maintained.LVDS DC Specifications (LVDS)The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.Table 19: LVDS DC SpecificationsSymbol DC Parameter Conditions Min Typ Max Units V CCO1Supply voltage 1.710 1.800 1.890VR T = 100Ω across Q and Q signals247350454mVV ODIFF2Differential output voltage:(Q – Q), Q = High(Q – Q), Q = HighV OCM2Output common-mode voltage R T = 100Ω across Q and Q signals 1.000 1.250 1.425V1003506003mVV IDIFF3Differential input voltage:(Q – Q), Q = High(Q – Q), Q = HighV ICM_DC4Input common-mode voltage (DC coupling)0.300 1.200 1.425VV ICM_AC5Input common-mode voltage (AC coupling)0.600– 1.100V Notes:1.In HP I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the V CCO levels are different from thespecified level only if internal differential termination is not used. In this scenario, V CCO must be chosen to ensure the input pin voltage levels do not violate the Recommended Operating Condition (Table 2) specification for the V IN I/O pin voltage.2.V OCM and V ODIFF values are for LVDS_PRE_EMPHASIS = FALSE.3.Maximum V IDIFF value is specified for the maximum V ICM specification. With a lower V ICM, a higher V DIFF is tolerated only when therecommended operating conditions and overshoot/undershoot V IN specifications are maintained.4.Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).5.External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2,EQ_LEVEL3, EQ_LEVEL4.DS922 (v1.17) February 16, 2021Product SpecificationKintex UltraScale+ FPGAs Data Sheet: DC and AC Switching CharacteristicsAC Switching CharacteristicsAll values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as outlined in the following table.Table 20: Speed Specification Version By Device2020.2.2Device1.28XCKU3P, XCKU5P, XCKU9P, XCKU11P, XCKU13P, and XCKU15PXQKU5P, XQKU15P1.32XCKU19PSwitching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:•Advance Product Specification: These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation areconsidered relatively stable and conservative, some under-reporting might still occur.•Preliminary Product Specification: These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a betterindication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.•Product Specification: These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formalnotification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades.Testing of AC Switching CharacteristicsInternal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions.For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex UltraScale+ FPGAs.Speed Grade DesignationsSince individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 21 correlates the current status of the Kintex UltraScale+ FPGAs on a per speed grade basis.DS922 (v1.17) February 16, 2021Product Specification。

FPGA可编程逻辑器件芯片XCKU035-2FFVA1156I中文规格书

Chapter1 Packaging OverviewIntroduction to the UltraScale ArchitectureThe Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enablemulti-hundred gigabit-per-second levels of system performance with smart processing,while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth, high-utilization system requirements by using industry-leading technical innovations, including next-generation routing, ASIC-likeclocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new powerreduction features. The devices share many building blocks, providing scalability acrossprocess nodes and product families to leverage system-level investment across platforms.Virtex® UltraScale+™ devices provide the highest performance and integration capabilities in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and data center and fully integrated radar/early-warning systems.Virtex UltraScale devices provide the greatest performance and integration at 20nm,including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the 20nm process node, this family is ideal for applications including 400G networking, large scale ASIC prototyping, and emulation.Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET node, delivering the most cost-effective solution for high-end capabilities, includingtransceiver and memory interface line rates as well as 100G connectivity cores. Our newest mid-range family is ideal for both packet processing and DSP-intensive functions and is well suited for applications including wireless MIMO technology, Nx100G networking, and data center.Kintex UltraScale devices provide the best price/performance/watt at 20nm and include the highest signal processing bandwidth in a mid-range device, next-generationtransceivers, and low-cost packaging for an optimum blend of capability andcost-effectiveness. The family is ideal for packet processing in 100G networking and data centers applications as well as DSP-intensive processing needed in next-generation medical imaging, 8k4k video, and heterogeneous wireless infrastructure.Zynq® UltraScale+ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Integrating an Arm®-based system for advanced analytics and on-chip programmable logic for task acceleration creates unlimited possibilities for applications including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.This packaging and pinout specification user guide is part of the UltraScale Architecture documentation suite available.Introduction to UltraScale and UltraScale+ FPGAs Packaging and PinoutsThis section describes the packages and pinouts for the UltraScale architecture-based FPGAs in various organic flip-chip 0.8mm and 1.0mm pitch BGA packages.•Kintex UltraScale and Kintex UltraScale+ devices are offered in low-cost, space-saving flip-chip and bare-die flip-chip packages that are optimally designed for highperformance-to-price ratio.•Virtex UltraScale and Virtex UltraScale+ devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for highest system capacity, bandwidth and signal performance. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of power and GND pins.•Zynq UltraScale+ MPSoCs are further described in the Zynq UltraScale+ MPSoC Packaging and Pinouts User Guide (UG1075) [Ref4].particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref5].UltraScale and UltraScale+ device’s flip-chip assembly materials are manufactured using ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than 0.002 alpha-particles per square centimeter per hour.FSVA3824SSI, flip-chip, fine-pitch, lidless with stiffener ring BGA 1.065x 65FSVB3824SSI, flip-chip, fine-pitch, lidless with stiffener ringBGA1.065x 65Notes:1.FFV, FLV, and FLG packages are footprint compatible when the package code letter designator and pin count are identical.See UltraScale Architecture and Product Overview (DS890) [Ref 1] for specific letter codes and ordering code information.2.These 52.5x 52.5 packages have the same PCB ball footprint as the 47.5x 47.5 packages and are footprint compatible.Table 1-1:Package Specifications (Cont’d)Packages (1)DescriptionPackage SpecificationsPackage Type Pitch (mm)Size (mm)XQVU3P FFRC1517040XQVU7P FLRA2104052XQVU7P FLRB2104076XQVU11PFLRC210496Table 1-3:Serial Transceiver Channels (GTH/GTY/GTM) by Device/PackageDevicePackageGTH Channels GTY Channels GTM ChannelsVirtex UltraScale+ DevicesXCVU27P FIGD210401630XCVU29P 01630XCVU27P FSGA257703248XCVU29P3248Table 1-2:Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)Device PackageGTH ChannelsGTY Channels。

FPGA可编程逻辑器件芯片XCKU040-L1FFVA1156I中文规格书

Spartan and Spartan-XL FPGA Families Data SheetDS060 (v2.0) March 1, 2013Product SpecificationSpartan Family Pin-to-Pin Output Parameter GuidelinesAll devices are 100% functionally tested. Pin-to-pin timingparameters are derived from measuring external and inter-nal test patterns and are guaranteed over worst-case oper-ating conditions (supply voltage and junction temperature).Listed below are representative values for typical pin loca-tions and normal clock loading. For more specific, more pre-cise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static tim-ing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays,provided as a guideline, have been extracted from the static timing analyzer report.Spartan Family Output Flip-Flop, Clock-to-Out Symbol DescriptionDevice Speed GradeUnits -4-3Max Max Global Primary Clock to TTL Output using OFFT ICKOF Fast XCS055.38.7ns XCS105.79.1ns XCS206.19.3ns XCS306.59.4ns XCS406.810.2ns T ICKO Slew-rate limited XCS059.011.5ns XCS109.412.0ns XCS209.812.2ns XCS3010.212.8ns XCS4010.512.8ns Global Secondary Clock to TTL Output using OFF T ICKSOF Fast XCS05 5.89.2ns XCS10 6.29.6ns XCS20 6.69.8ns XCS307.09.9ns XCS407.310.7ns T ICKSO Slew-rate limited XCS059.512.0ns XCS109.912.5ns XCS2010.312.7ns XCS3010.713.2ns XCS4011.014.3ns Delay Adder for CMOS Outputs Option T CMOSOF Fast All devices 0.8 1.0ns T CMOSO Slew-rate limited All devices1.52.0ns Notes:1.Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and where all accessible IOB and CLB flip-flops are clocked by the global clock net.2.Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. For different loads, see Figure 34.3.OFF = Output Flip-FlopDS060 (v2.0) March 1, 2013Product Specification Spartan Family IOB Input Switching Characteristic GuidelinesAll devices are 100% functionally tested. Internal timingparameters are derived from measuring internal test pat-terns. Listed below are representative values. For morespecific, more precise, and worst-case guaranteed data,use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing ana-lyzer report. All timing parameters assume worst-case oper-ating conditions (supply voltage and junction temperature).SymbolDescription Device Speed GradeUnits -4-3Min MaxMin Max Setup Times - TTL Inputs (1)T ECIK Clock Enable (EC) to Clock (IK), no delay All devices 1.6-2.1-ns T PICK Pad to Clock (IK), no delay All devices 1.5-2.0-ns Hold Times T IKEC Clock Enable (EC) to Clock (IK), no delay All devices 0.0-0.9-ns All Other Hold Times All devices 0.0-0.0-ns Propagation Delays - TTL Inputs (1)T PID Pad to I1, I2All devices - 1.5- 2.0ns T PLI Pad to I1, I2 via transparent input latch, no delay All devices - 2.8- 3.6ns T IKRI Clock (IK) to I1, I2 (flip-flop)All devices - 2.7- 2.8ns T IKLI Clock (IK) to I1, I2 (latch enable, active Low)All devices - 3.2- 3.9ns Delay Adder for Input with Delay Option T Delay T ECIKD = T ECIK + T Delay T PICKD = T PICK + T Delay T PDLI = T PLI + T Delay XCS05 3.6-4.0-ns XCS10 3.7-4.1-ns XCS20 3.8-4.2-ns XCS30 4.5-5.0-ns XCS40 5.5-5.5-ns Global Set/Reset T MRW Minimum GSR pulse width All devices 11.5-13.5-ns T RRI Delay from GSR input to any Q XCS05-9.0-11.3ns XCS10-9.5-11.9ns XCS20-10.0-12.5ns XCS30-10.5-13.1ns XCS40-11.0-13.8ns Notes:1.Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.2.Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.3.Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.。

FPGA可编程逻辑器件芯片XCKU040-2FFVA1156I中文规格书

Table 1-1:Package SpecificationsPackages (1)DescriptionPackage SpecificationsPackage Type Pitch (mm)Size (mm)FBVA676Bare-die, flip-chip, fine-pitch BGA1.027x 27FFVA676Flip-chip, fine-pitchFFVB676FFRB676Ruggedized, flip-chip, fine-pitch RBA676SFVA784Flip-chip, super-fine-pitch0.823x 23SFVB784SFRB784Ruggedized, flip-chip, super-fine pitch FBVA900Bare-die, flip-chip, fine-pitch 1.031x 31FFVD900Flip-chip, fine-pitch FFVE900FFVA1156Flip-chip, fine-pitch35x 35FFRA1156Ruggedized, flip-chip, fine-pitchRFA1156FFVA1517Flip-chip, fine-pitch40x 40FFVC1517FFVD1517FFVE1517FFRC1517Ruggedized, flip-chip, fine-pitch FFRE1517RLD1517Ruggedized, SSI, flip-chip, fine-pitch FLVA1517SSI, flip-chip, fine-pitchFLVD1517找FPGA 和CPLD 可编程逻辑器件，上深圳宇航军工半导体有限公司Gigabit Transceiver Channels by Device/PackageTable 1-2 lists the quantity of gigabit transceiver channels for the UltraScale andUltraScale+ devices. In all devices, a gigabit transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins. For transceiver data rate limitations on specific device/package combinations, see the specific UltraScale and UltraScale+ device data sheets [Ref 4].FSVA3824SSI, flip-chip, fine-pitch, lidless with stiffener ring BGA 1.065x 65FSVB3824SSI, flip-chip, fine-pitch, lidless with stiffener ringBGA1.065x 65Notes:1.FFV, FLV, and FLG packages are footprint compatible when the package code letter designator and pin count are identical.See UltraScale Architecture and Product Overview (DS890) [Ref 1] for specific letter codes and ordering code information.2.These 52.5x 52.5 packages have the same PCB ball footprint as the 47.5x 47.5 packages and are footprint compatible.Table 1-1:Package Specifications (Cont’d)Packages (1)DescriptionPackage SpecificationsPackage Type Pitch (mm)Size (mm)Table 1-2:Serial Transceiver Channels (GTH/GTY) by Device/PackageDevicePackageGTH ChannelsGTY ChannelsKintex UltraScale DevicesXCKU035FBVA676160XCKU040160XCKU035SFVA78480XCKU04080XCKU035FBVA900160XCKU040160XCKU025FFVA1156120XCKU035160XCKU040200XCKU060280XCKU095208XCKU060FFVA1517320XCKU085FLVA1517480XCKU115480XCKU095FFVC15172020XCKU115FLVD1517640XCKU095FFVB17603216DBCQBC Multi-functionInputByte lane clock (DBC and QBC) input pin pairs are clock inputs directly driving source synchronous clocks to the bit slices in the I/O banks. In memory applications, these are also known as DQS. For more information, consult the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 5].PERSTN[0 to 1]Multi-functionInputDefault reset pin locations for the integrated block for PCI Express.Pin NameTypeDirectionDescriptionMGTAVTT_[L or R][N, UC, C, LC, or S](5)Dedicated Input Analog power-supply pin for the transmit driver.MGTVCCAUX_[L or R][N, UC, C, LC, or S](5)Dedicated Input Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers.MGTREFCLK[0 or 1][P or N]Dedicated Input Differential reference clock for the transceivers.MGTAVTTRCAL_[L or R][N, UC, C, LC, or S](5)Dedicated N/A Precision reference resistor pin for internal calibration termination.MGTRREF_[L or R][N, UC, C, LC, or S](5)DedicatedInputPrecision reference resistor pin for internal calibration termination.Notes:Pin NameTypeDirectionDescription。

FPGA可编程逻辑器件芯片XCZU21DR-2FFVD1156E中文规格书

Figure 4 has been translated into a table, as follows.Table 6: Inter-byte and Inter-nibble Clocking in an XPIO BankXPHY Nibble Can Route To (ThroughInter-nibble Clocking)Can Route To (ThroughInter-byte Clocking)Can Route To (Through Inter-byte,Inter-nibble, or a Combination of theTwo)01-110-0230, 40, 1, 3, 4, 5, 6, 7, 8321, 50, 1, 2, 4, 5, 6, 7452, 60, 1, 2, 3, 5, 6, 7, 8543, 70, 1, 2, 3, 4, 6, 76787, 876-68---As shown in the clocking figures, within a bank there are two types of clock inputs that serve two different purposes:•Global Clock (GC): Clock input with dedicated clock routing designed to have low skew, low duty cycle distortion, and improved jitter resistance. As such, it is recommended for externalclocks to enter through GC pins. For interfaces that use XPHY, the GC pins are typically usedas the clock source for the XPLLs, which in turn clock the XPHY. GCs can reach all XPLLs in anXPIO bank as well as XPLLs in the adjacent banks.•XCC: Strobe input for XPHY receive interfaces•Both GC and XCC: These pins can act as GCs and/or XCCsNote: If a GC, XCC, or GC/XCC input is not used to receive a clock or strobe, it can be used as a regular I/O pin.Refer to Versal ACAP Clocking Resources Architecture Manual (AM003) for a more detailedexplanation of GC and XCC pins.The following figure shows the XCC and GC pins that can accept a clock and the NIBBLESLICEs with which they are associated. Clocks entering on GC or XCC inputs (as opposed to dataentering on those pins), regardless of whether single-ended or differential, must enter the I/O pin associated with NIBBLESLICE[0]. If the clock is differential, the complementary side of the clock (incoming on the I/O pin associated with NIBBLESLICE[1]) should be connected to the samedifferential buffer as the signal incoming to the I/O pin of NIBBLESLICE[0]. BecauseNIBBLESLICE[0] is the only NIBBLESLICE that is capable of connecting to the strobe circuitry,Chapter 2: XPHY ArchitectureAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture ManualRevision HistoryAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture Manual。

FPGA可编程逻辑器件芯片XCZU21DR-2FFVD1156I中文规格书

Introduction to the RocketIO GTX TransceiverOverviewThe RocketIO™ GTX transceiver is a power-efficient transceiver for Virtex®-5 FPGAs. TheGTX transceiver is highly configurable and tightly integrated with the programmable logicresources of the FPGA. It provides the following features to support a wide variety ofapplications:•Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.•Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.•Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.•Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.•Fixed latency modes for minimized, deterministic datapath latency.•Beacon signaling for PCI Express® designs and Out-of-Band signaling includingCOM signal support for SATA designs.•RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.•Receiver eye scan:♦Vertical eye scan in the voltage domain for testing purposes♦Horizontal eye scan in the time domain for testing purposesThe first-time user is recommended to read High-Speed Serial I/O Made Simple[Ref1], whichdiscusses high-speed serial transceiver technology and its applications.Table1-1 lists some of the standard protocols designers can implement using the GTXtransceiver. The Xilinx® CORE Generator™ tool includes a Wizard to automaticallyconfigure GTX transceivers to support one of these protocols or perform customconfiguration (see Chapter2, “RocketIO GTX Transceiver Wizard”).The GTX_DUAL tile offers a data rate range and features that allow physical layer supportfor various protocols as illustrated in Table1-1.Chapter 1:Introduction to the RocketIO GTX TransceiverFigure1-3 shows a diagram of a GTX_DUAL tile, containing two GTX transceivers and ashared resources block. The GTX_DUAL tile is the HDL primitive used to operate GTXtransceivers in the FPGA.Notes:1.CLKIN is a simplification for a clock source. See Figure5-3, page97 for details on CLKIN.Figure 1-3:GTX_DUAL Tile Block DiagramPorts and AttributesTable 1-3 lists alphabetically the signal names, clock domains, directions, and descriptions for the GTX_DUAL ports, and provides links to their detailed descriptions.MGTRREF_R In (Pad)TXT only: Reference resistor input for the X1 column. Analog Design Guidelines (page 254)MGTRREF_L In (Pad)TXT only: Reference resistor input for the X0 column. Analog Design Guidelines (page 254)MGTRXN0MGTRXP0MGTRXN1MGTRXP1In (Pad)Differential complements forming adifferential receiver input pair foreach transceiver.RX Termination andEqualization (page 162)MGTTXN0MGTTXP0MGTTXN1MGTTXP1Out (Pad)Differential complements forming a differential transmitter output pair for each transceiver.RX Termination and Equalization (page 162)Table 1-2:GTX_DUAL Analog Pin Summary (Cont’d)PinDir DescriptionSection (Page)Table 1-3:GTX_DUAL Port Summary PortDir Domain DescriptionSection (Page)CLKINInAsyncReference clock input to the shared PMA PLL.Shared PMA PLL (page 87), Clocking (page 98),Power Control (page 110)DADDR[6:0]In DCLK DRP address bus.Dynamic Reconfiguration Port (page 117)DCLK In N/A DRP interface clock.Dynamic Reconfiguration Port (page 117)DENIn DCLK Enables DRP read or write operations.Dynamic Reconfiguration Port (page 117)DFECLKDLYADJ0[5:0]DFECLKDLYADJ1[5:0]In RXUSRCLK2DFE clock delay adjust control for each transceiver.Decision Feedback Equalization (page 167)DFECLKDLYADJMONITOR0[5:0]DFECLKDLYADJMONITOR1[5:0]Out RXUSRCLK2DFE clock delay adjust monitor for each transceiver.Decision Feedback Equalization (page 167)DFEEYEDACMONITOR0[4:0]DFEEYEDACMONITOR1[4:0]Out RXUSRCLK2Vertical Eye Scan for each transceiver (voltage domain).Decision Feedback Equalization (page 167)DFESENSCAL0[2:0]DFESENSCAL1[2:0]OutRXUSRCLK2DFE calibration status.Decision Feedback Equalization (page 167)DFETAP10[4:0]DFETAP11[4:0]In RXUSRCLK2DFE tap 1 weight value control for each transceiver (5-bit resolution).Decision Feedback Equalization (page 167)DFETAP1MONITOR0[4:0]DFETAP1MONITOR1[4:0]Out RXUSRCLK2DFE tap 1 weight value monitorfor each transceiver (5-bitresolution).Decision FeedbackEqualization (page 167)RXCHARISCOMMA0[3:0] RXCHARISCOMMA1[3:0]Out RXUSRCLK2Asserted when RXDATA is an8B/10B comma.RXCHARISCOMMA isinfluenced by the setting of theseattributes:DEC_MCOMMA_DETECT_0DEC_MCOMMA_DETECT_1DEC_PCOMMA_DETECT_0DEC_PCOMMA_DETECT_1Configurable 8B/10BDecoder (page200)RXCHARISK0[3:0] RXCHARISK1[3:0]Out RXUSRCLK2Asserted when RXDATA is an8B/10B K character.Configurable 8B/10BDecoder (page200)RXCHBONDI0[3:0] RXCHBONDI1[3:0]In RXUSRCLKFPGA channel bonding control.Used only by slaves.Configurable ChannelBonding (Lane Deskew)(page219)RXCHBONDO0[3:0] RXCHBONDO1[3:0]Out RXUSRCLK FPGA channel bonding control.Configurable ChannelBonding (Lane Deskew)(page219)RXCLKCORCNT0[2:0] RXCLKCORCNT1[2:0]Out RXUSRCLK2Reports the status of the elasticbuffer clock correction.Configurable ClockCorrection (page212)RXCOMMADET0 RXCOMMADET1Out RXUSRCLK2Asserted when the commaalignment block detects acomma.Configurable CommaAlignment and Detection(page192)RXCOMMADETUSE0 RXCOMMADETUSE1In RXUSRCLK2Activates the comma detectionand alignment circuit.Configurable CommaAlignment and Detection(page192)RXDATA0[31:0] RXDATA1[31:0]Out RXUSRCLK2Receive data bus of the receiveinterface to the FPGA.FPGA RX Interface(page236)RXDATAVALID0RXDATAVALID1Out RXUSRCLK2Data valid for RX Gearbox.RX Gearbox (page231)RXDATAWIDTH0[1:0] RXDATAWIDTH1[1:0]In RXUSRCLK2Selects the width of the RXDATAreceive data connection to theFPGA.Configurable 8B/10BDecoder (page200), FPGARX Interface (page236)RXDEC8B10BUSE0 RXDEC8B10BUSE1In RXUSRCLK2Enables the 8B/10B decoder.Configurable 8B/10BDecoder (page200)RXDISPERR0[3:0] RXDISPERR1[3:0]Out RXUSRCLK2Indicates if RXDATA wasreceived with a disparity error.Configurable 8B/10BDecoder (page200)RXELECIDLE0 RXELECIDLE1Out AsyncIndicates the differential voltagebetween RXN and RXP droppedbelow the minimum threshold.RX OOB/Beacon Signaling(page174)RXENCHANSYNC0 RXENCHANSYNC1In RXUSRCLK2Enables channel bonding.Configurable ChannelBonding (Lane Deskew)(page219)Table 1-3:GTX_DUAL Port Summary (Cont’d)Port Dir Domain Description Section (Page)。

FPGA可编程逻辑器件芯片XCZU15EG-LFFVB1156I中文规格书

Chapter 2: XPHY Architecture •When RX_DATA_WIDTH = 4 or 8, RX_GATING = ENABLE, and CONTINUOUS_DQS = FALSE, set the following bits of PHY_RDEN to 1 to accept the strobe or 0 to reject the strobe.PHY_RDEN is synchronized to PLL_CLK for this attribute combination. Each bit of PHY_RDENcontrols two UI worth of data:○If RX_DATA_WIDTH = 8: [3:0]○If RX_DATA_WIDTH = 4: [2][0]○If RX_DATA_WIDTH = 2: not supported•When RX_GATING = DISABLE the gate is always open, regardless of the value of RX_DATA_WIDTH, CONTINUOUS_DQS, or PHY_RDEN. In this scenario (RX_GATING =DISABLE), the strobe starts the deserialization in the RX datapath. Because of this, the strobemust be stable to ensure XPHY alignment.•When SERIAL_MODE = TRUE, tie all four bits of PHY_RDEN HighPHY_WREN is set up and used to control TX datapath gating as follows:•When TX_GATING = ENABLE, PHY_WREN gates the TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5]. NIBBLESLICE[1]cannot be gated. Set the following bits of PHY_WREN to 0 to gate transmit data or 1 to notgate transmit data:○If TX_DATA_WIDTH = 8: [3:0]○If TX_DATA_WIDTH = 4: [2][0]○If TX_DATA_WIDTH = 2: not supported•Note that PHY_WREN can be used to control both TX datapath gating (if TX_GATING = ENABLE) and tristating (if TBYTE_CTL_# = PHY_WREN). However, only when PHY_WREN isused for tristating is it inverted and serialized prior to its use. When used for gating,PHY_WREN is serialized but is not inverted. Thus, when used for gating, PHY_WREN shouldbe set to 1 to open the gate and 0 to close the gate. When used for tristating, PHY_WRENshould be set to 0, which is then inverted to 1 to tristate the buffer. It follows that settingPHY_WREN to 1 for tristating results in the buffer not being tristated. See Controlling TristateControl for more information on tristating.Other important points to keep in mind:•When turning the bus around, toggle the BS_RESET_CTRL.clr_gate bit then toggle the BS_RESET_CTRL.bs_reset bit. T oggling BS_RESET_CTRL.clr_gate clears the strobe path gatinglogic, helping to ensure proper alignment when combined with the NIBBLESLICE resetperformed through the toggling of BS_RESET_CTRL.bs_reset. Continue reading this sectionfor the bs_reset/clr_gate sequence. See Register Interface Unit for more information onBS_RESET_CTRL. After the write to bs_reset is completed, data can be transmittedimmediately. For receivers, however, the first FIFO_EMPTY deassertion should be used toknow when receiving valid data.•Before performing a bs_reset, set PHY_WREN and PHY_RDEN to 0 regardless of the TX_GATING or RX_GATING settings.AM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture ManualIMPORTANT! The DELAY_VALUE_x attribute and VTC are not supported if REFCLK_FREQUENCY is lessthan 500 MHz. In this scenario, EN_VTC should be tied to 0.The steps before/after changing delays differ if PHY_RDY was asserted for the first time, asdescribed in the following sequences. If not using VTC, refer to the Controlling Delays section for how to change delay values.The following sequence and figure show the before/after steps of changing delay values onNIBBLESLICE[x] after PHY_RDY is asserted for the first time:1.Start with EN_VTC, RX_EN_VTC, and TX_EN_VTC asserted.2.Deassert RX_EN_VTC and TX_EN_VTC.3.After RX_EN_VTC and TX_EN_VTC have been deasserted, wait ten CTRL_CLK cycles.4.Modify delay values (see Controlling Delays).5.Wait another ten CTRL_CLK cycles, then reassert RX_EN_VTC and TX_EN_VTC.6.The XPHY is ready to undergo VTC and can be operated normally.Figure 18:Changing Delay Values After PHY_RDY is Asserted for the First Time The following sequence and figure show the before/after steps of changing delay values onNIBBLESLICE[x] before PHY_RDY is asserted for the first time:1.Start with EN_VTC deasserted, and RX_EN_VTC and TX_EN_VTC asserted.2.After DLY_RDY asserts, deassert RX_EN_VTC and TX_EN_VTC.3.After the relevant RX_EN_VTC and TX_EN_VTC is deasserted, wait ten CTRL_CLK cycles.4.Modify delay values (see Controlling Delays).5.Wait another ten CTRL_CLK cycles, then assert EN_VTC, RX_EN_VTC, and TX_EN_VTC.6.After PHY_RDY asserts, the XPHY is ready to undergo VTC and can be operated normally.Figure 19:Changing Delay Values Before PHY_RDY is Asserted for the First TimeChapter 2: XPHY ArchitectureAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture Manual。

FPGA可编程逻辑器件芯片XCZU11EG-L1FFVC1156I中文规格书

DS300 (v3.3) June 25, 2014Product SpecificationFeaturesPlatform Cable USB has these features:•Supported on Windows and Red Hat Enterprise Linux •Automatically senses and adapts to target I/O voltage •Interfaces to devices operating at 5V (TTL), 3.3V (LVCMOS), 2.5V , 1.8V , and 1.5V •LED Status Indicator •CE, USB-IF , and FCC compliant •Intended for development — not recommended for production programming •Pb-free (RoHS-compliant)•Configures all Xilinx devices ♦All Virtex® FPGA families ♦All Spartan® FPGA families ♦XC9500 / XC9500XL / XC9500XV CPLDs ♦CoolRunner™ XPLA3 / CoolRunner-II CPLDs ♦XC18V00 ISP PROMs ♦Platform Flash XCF00S/XCF00P/XL PROMs ♦XC4000 series FPGAs •Programs serial peripheral interface (SPI) flash PROMs Platform Cable USB DescriptionPlatform Cable USB (Figure 1) is a high-performancedownload cable attaching to user hardware for the purpose ofprogramming or configuring any of the following Xilinx devices:•ISP Configuration PROMs •CPLDs •FPGAs Platform Cable USB attaches to the USB port on a desktopor laptop PC with an off-the-shelf Hi-Speed USB A-B cable.It derives all operating power from the hub port controller.No external power supply is required. A sustained slave-serial FPGA configuration transfer rate of 24Mb/s ispossible in a Hi-Speed USB environment. Actual transferrates can vary if bandwidth of the hub is being shared withother USB peripheral devices.Device configuration and programming operations usingPlatform Cable USB are supported by iMP ACT downloadsoftware using Boundary-Scan (IEEE 1149.1 / IEEE 1532),slave-serial mode, or serial peripheral interface (SPI). PlatformCable USB supports indirect (via an FPGA IEEE 1149.1[JT AG] port) programming of select flash memories includingthe Platform Flash XL configuration and storage device. T argetclock speeds are selectable from 750kHz to 24MHz.Platform Cable USB attaches to target systems using a14-conductor ribbon cable designed for high-bandwidth datatransfers. An optional adapter that allows attachment of aflying lead set is included for backward compatibility with target systems that do not use the ribbon cable connector.Note:The next generation, Platform Cable USB II, is now available. Please refer to the DS593, Platform Cable USB II , for details.Platform Cable USBDS300 (v3.3) June 25, 2014Product SpecificationPlatform Cable USBDS300 (v3.3) June 25, 2014Product SpecificationIn Boundary-Scan mode, iMPACT 7.1i (and later) queries the BSDL file of each device in a target Boundary-Scan chain to determine the maximum Boundary-Scan clock (JT AG TCK) frequency. iMPACT 7.1i (and later)automatically restricts the available TCK_CCLK_SCKselections to frequencies that are less than or equal to the slowest device in the chain. By default, iMPACT 7.1i (or later) selects either 6MHz or the highest commonfrequency when any device in the Boundary-Scan chain is not capable of 6MHz operation. Table 2 shows themaximum supported JTAG TCK frequency for a variety of Xilinx devices. See the device data sheet or BSDL file for maximum JT AG TCK specifications.Note:iMP ACT versions earlier than 7.1i do not restrict the TCK_CCLK_SCK selections in Boundary-Scan mode.Accordingly, users should take care to select a TCK_CCLK_SCK frequency that matches the JTAG TCK specifications for the slowest device in the target Boundary-Scan chain.A Status bar on the bottom edge of the iMPACT GUI provides useful information about operating conditions. If the host port is USB 1.1, Platform Cable USB connects atfull-speed, and the Status bar shows "usb-fs." If the host port is USB 2.0, Platform Cable USB connects at Hi-Speed and the Status bar shows "usb-hs."The active TCK_CCLK_SCK frequency is shown in the lower right-hand corner of the Status bar (see Figure 10).The command log also includes information aboutcommunication with the cable. When the cable is selected using the Cable Communication Setup dialog box, the command log indicates:Firmware version = 1CPLD file version = 0004h CPLD version = 0004h Cable Connection Established Note:The actual revision number can be expected to change with new software releases.Status Indicator Platform Cable USB uses a bi-color Status LED to indicate the presence of target voltage. When the ribbon cable is connected to a mating connector on the target system, the Status LED is illuminated as a function of the voltage present on pin 2 (V REF ).Users must design their system hardware with pin 2 attached to a voltage plane that supplies the JT AG, SPI, or slave-serial pins on the target device(s). Some devices have separate power pins for this purpose (VAUX), while others have a common supply for both VCCIO and the JTAG pins (TCK, TMS, TDI, and TDO). Refer to the target device Data Sheet for details on slave-serial or JTAG pins.The Status LED is amber (see Figure 11) when any one or more of the following conditions exist:•The ribbon cable is not connected to a target system •The target system is not powered •The voltage on the V REF pin is < +1.5V The Status LED is green when all of the following conditions exist:•The ribbon cable is connected to a target system •The target system is powered •The voltage on the V REF pin is ≥ +1.5V The Status LED is Off whenever Platform Cable USB enters a Suspend state, or is disconnected from a powered USB port.Table 2:Maximum JTAG Clock Frequencies Device FamilyMaximum JTAG Clock Frequency Units XC9500/XL/XV10MHz XPLA310MHz CoolRunner-II33MHz XC18V0010MHz XCF00S/XCF00P15MHz Virtex33MHz Virtex-II33MHz Virtex-II Pro33MHz Virtex-433MHz Virtex-533MHz Spartan5MHz Spartan-II33MHz Spartan-333MHz Spartan-3A10MHz Spartan-3E 10MHz Figure 10:iMPACT Status Bar DS300_10_111904Active CableIdentificationFull-Speed or High-Speed Connection Active TCK_CCLK Frequency Command LogText Display。

FPGA可编程逻辑器件芯片XCKU060-2FFVA1156I中文规格书

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FPGA可编程逻辑器件芯片XCZU6EGL-1FFVB1156I中文规格书

2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
TPSFD_KU3P TPHFD_KU3P
Global clock input and input flip-flop (or latch) without MMCMSetupBiblioteka XCKU3P1.98
2.28
2.38
3.55
3.83
ns
Hold
–0.36
–0.36
–0.36
–1.04
–1.04
ns
TPSFD_KU5P
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS922 (v1.17) February 16, 2021 Product Specification
–0.60
ns
TPSFD_KU11P
Setup
XCKU11P
1.99
2.28
2.38
3.54
3.79
ns
TPHFD_KU11P
Hold
–0.38
–0.38
–0.38
–1.05
–1.05
ns
TPSFD_KU13P
Setup

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