FPGA可编程逻辑器件芯片5AGXBA3D4F31C4N中文规格书

Active Serial Configuration (Serial Configuration Devices)
Figure7–15.In-System Programming of Serial Configuration Devices
Notes to Figure7–15:
(1)Connect these pull-up resistors to 3.3-V supply.
(2)Power up the ByteBlaster II cable's V CC with a 3.3-V supply.
(3)If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table7–11
for more details.
You can program serial configuration devices with the Quartus II
software with the Altera programming hardware (APU) and the
appropriate configuration device programming adapter. The EPCS1 and
EPCS4 devices are offered in an eight-pin small outline integrated circuit
(SOIC) package.
In production environments, serial configuration devices can be
programmed using multiple methods. Altera programming hardware or
other third-party programming hardware can be used to program blank
serial configuration devices before they are mounted onto printed circuit
boards (PCBs). Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system using C-based
software drivers provided by Altera.
Stratix II Device Handbook, Volume2
PLLs in Stratix II and Stratix II GX Devices Figure1–3.Stratix II and Stratix II GX Enhanced PLL
Notes to Figure1–3:
(1)Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2)PLLs 5, 6, 11, and 12 each have six single-ended dedicated clock outputs or three differential dedicated clock
outputs.
(3)If the design uses external feedback input pins, you will lose one (or two, if f BIN is differential) dedicated output
clock pin. Every Stratix II and Stratix II GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
(4)The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Stratix II Device Handbook, Volume2
External Memory Interfaces in Stratix II and Stratix II GX Devices to any of Stratix II and Stratix II GX I/O pins in the same bank as the DQ
pins of the FPGA. There is one DM pin per DQS/DQ group in a DDR or
DDR2SDRAM device.
You can also use I/O pins in banks 1, 2, 5, or 6 to interface with DDR and
DDR2 SDRAM devices. These banks do not have dedicated circuitry,
though, and can only support DDR SDRAM at speeds up to 150MHz and
DDR2 SDRAM at speeds up to 200MHz. DDR2 SDRAM interfaces using
these banks are supported using the SSTL-18 Class I I/O standard.
f For more information, see AN 327: Interfacin
g DDR SDRAM with
Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II
Devices.
If the DDR or DDR2 SDRAM device supports error correction coding
(ECC), the design will use an extra DQS/DQ group for the ECC pins.
You can use any of the user I/O pins for commands and addresses to the
DDR and DDR2 SDRAM. You may need to generate these signals from
the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK# pins. Use any of
the user I/O pins via the DDR registers to generate the CK and CK#
signals to meet the DDR SDRAM or DDR2 SDRAM device’s t DQSS
requirement. The memory device’s t DQSS specification requires that the
write DQS signal’s positive edge must be within 25% of the positive edge
of the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/O
pins for CK and CK# also ensures that any PVT variations on the DQS
signals are tracked the same way by these CK and CK# pins. Figure3–2
shows a diagram that illustrates how to generate these clocks.
Stratix II Device Handbook, Volume2。