Exploring ESD Challenges

In this work, the ESD characterization of bulkFinFET technology with a layout compatible with the sub-20 nm generation nodes is presented. In addition, Silicon Controlled Rectifiers (SCRs), which have high unit area ESD robustness, have been considered as a promising ESD protection device in several specific applications. The impact of narrow fin configurations on the ESD robustness of SCRs is presented for the first time. In Section II, the specific process changes towards sub-20 nm nodes are together with its impact on ESD protection. The experiments and measurement results are described in Section III and IV. More detailed discussion and TCAD device simulation are included in the following Section V to
imec, Kapeldreef 75, B-3001 Leuven, Belgium tel.: +32 16 28 11 24, fax: +32 16 28 17 06, e-mail: Shih-Hung.Chen@imec.be (1) also with Vrije Universiteit Brussels, Dept. ELEC, Brussels, Belgium
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further explain the observed effects. This paper is concluded in Section VI.
device types and design splits are presented in the next section.
Exploring ESD Challenges in Sub-20-nm Bulk FinFET CMOS Technology Nodes
Shih-Hung Chen, Geert Hellings, Steven Thijs, Dimitri Linten, Mirko Scholz (1), and Guido Groeseneken (2)
(2) also with Electrical Engineering Dept., K.U. Leuven, B-3001 Leuven, Belgium
50 Words Abstract - Bulk FinFET is the main technology option for sub 20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic ESD performance. In this work, the impact on ESD performance induced by the process options beyond 20 nm nodes is explored on different ESD devices. Furthermore, experimental results of SCR devices in bulk FinFET technology are demonstrated for the first time. between planar and fin. The fin width can be varied from several-ten nm to hundreds µm.
III. Test Structure Description
Based on an existing mature bulk FinFET technology, the impact from the process changes can be more reliably evaluated. It is helpful to forecast the ESD characteristics in next generation sub-20 nm FinFET technologies. Different types of ESD protection devices were included in this work.
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Figure 1: Illustrated cross-sectional views of (a) SOI FinFET and (b) bulk FinFET.
II. Impact of Process Changes toward the Next Generation
When research of bulk FinFET technology moved into sub-20 nm nodes, several process features have been modified in order to further shrink the transistor footprint and reinforce its characteristics during normal operation. For example, the lithography process with double patterning technique [9] and the epitaxial growth of source and drain (S/D) [10] are the most significant changes. However, the impact of these advanced processes on ESD characteristics is still remained to be studied. First, due to the double patterning technique, the fin width would be fixed, approaching 10 nm in sub-20 nm FinFET technology. Fin widths have been proven as an essential parameter of ESD characteristics [6]. According to Ref. [8], wide fin devices are more suitable than narrow fin devices for ESD protection. Unfortunately, wide fin devices might not be available in these advanced FinFET technologies. Second, because of the fixed narrow fins and epitaxially grown S/D, there will be no wide diffusion area, also named landing pad (LP), for the contact plugs (or strips) landing, which connects directly with the bulk. Instead, all narrow fins are connected together by the epitaxially grown S/D, as shown in Figure 2, and these S/D areas are now only connected to the substrate bulk through the narrow fin structures.
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I. Introduction
As CMOS field-effect transistors (FETs) shrink from 32 nm to 22 nm or beyond, the need for short channel effect (SCE) control and the increase of driving current have forced CMOS device technologies to move from “planar” to “FinFET” device architecture [1], [2]. SOI (Silicon on Insulator) FinFET, which is only a thin Si film built on a buried oxide layer, was firstly proposed and it has demonstrated excellent transistor IV characteristics. Unfortunately, the buried oxide layer in SOI FinFET deteriorates thermal dissipation and device reliability [1]-[3]. A second type of FinFET technology without buried oxide layer is bulk FinFET [3]-[5]. Here, fin structures are fabricated on a bulk Si substrate and the fins are directly connected to Si substrate, as shown in Figure 1. This does not only improve the thermal dissipation and the device reliability [3]-[6], but also reduces manufacturing cost. Recently, the bulk FinFET technology has been implemented in commercial CPU IC chips [7]. Since 2009, ESD characteristics of bulk FinFET have been investigated. The ESD related comparisons between SOI and bulk FinFET have been shown in the prior works [6], [8]. However, the bulk FinFETs used in these prior works were based on 45 nm (or 32 nm) technology node which is a “hybrid” architecture