STREAM PROCESSOR WITH LOW POWER PARALLEL MATRIX MU

专利名称：STREAM PROCESSOR WITH LOW POWER
PARALLEL MATRIX MULTIPLY PIPELINE
发明人：Jiasheng Chen,Yunxiao Zou,Michael J.
Mantor,Allen Rush
申请号：US15855637
申请日：20171227
公开号：US20190171448A1
公开日：
20190606
专利内容由知识产权出版社提供
专利附图：
摘要：Systems, apparatuses, and methods for implementing a low power parallel
matrix multiply pipeline are disclosed. In one embodiment, a system includes at least first
and second vector register files coupled to a matrix multiply pipeline. The matrix multiply pipeline comprises a plurality of dot product units. The dot product units are configured to calculate dot or outer products for first and second sets of operands retrieved from the first vector register file. The results of the dot or outer product operations are written back to the second vector register file. The second vector register file provides the results from the previous dot or outer product operations as inputs to subsequent dot or outer product operations. The dot product units receive the results from previous phases of the matrix multiply operation and accumulate these previous dot or outer product results with the current dot or outer product results.
申请人：Advanced Micro Devices, Inc.
地址：Sunnyvale CA US
国籍：US
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