可测性DFT

Design
Wafer
Class
Fabrication Probe
Die Sort Probe
Die
Final
Assembly Test
Reliability Stress
Parameter Coverage
• VtP
• leakage
• VtN
• memory
• IgS
• Core
• IdS
• ...
Scan
Fault Coverage
• Fault coverage
The percentage of total faults for which test patterns have = 100 X
Number of Detected Faults Total Number of Faults in the CUT
to manufacturing.
• Responsible for
quality of design.
Test
• Verifies correctness of
manufactured hardware.
• Two-part process:
1. Test generation: software process executed once during design
compiler tool. (STIL - Standard Test Interface Language for Digital Test Vectord, IEEEStd. 1450.01999)
• Check DRC and make any necessary corrections • Prepare design for ATPG, setup fault list, analyze
problem
E.g. system functional failure
Example
a
c
b
• Defect: short to the grand • Fault: signal b stuck at logic 0 • Error: happens when a=1 b=1
Fault Models
2. Test application: electrical tests applied to hardware
• Test application
performed on every manufactured device.
• Responsible for quality of
devices.
Testing Principle
• Three basic element
A known input Stimulus
A known state A known expected
response
Automatic Test Equipment (ATE)
Overview of IC Testing
Outlines
Transition Delay Fault
• Model large transition delay
slow to rise or slow to fall transition an interconnect signal has a greater than normal
propagation delay associated with it
• Increase the defect coverage
How many function test patterns can cover all the devices?
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
OR Bridging 1 1 Transition / 0 0 Reset Coupling 1 0 Inversion Coupling 1 0
0 Passive Neighborhood 1 1 1 Pattern Sensitive
1
1 Stuck-AT- 1
0 0 AND Bridging 1 Transition / 1
Stuck-AT Faults
• What is stuck-at fault?
Applicable to any physical defect manifesting as a signal that is stuck at a fixed logic level
One stuck-at fault can model more than one kind of defect
E.g. input stuck-at ‘1’, output slow-to-rise
• Error: machine failure due to a fault
E.g. system functional failure
• Bug – functional failure caused by design
• Automatic test pattern generation
With the build-in DFT circuit, test vectors are generated automatically
Vector Generation Using ATPG Tool
• Read in netlist with scan chain connected • Read in IP and standard-cell library model • Read in STIL test protocol file, generated by DFT
buses for contention and set the ATPG options
• Generate vectors • Review the test coverage and re-run ATPG if
necessary
• Compress the vectors • Convert vector to ATE vector format • Save test vectors and fault list
(ATPG)
• Design-for-test (DFT) techniques
Types of Test Vector Sets
• Exhaustive
Apply every possible input vector A long time!
• Functional
Test every function of the device How to guarantee the coverage?
• Fault coverage is influenced by
Testability of the circuit Quality of applied patterns
Test Generation Definitions
Test vectors
An input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary output
• Neighborhood pattern sensitive fault
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
(ATPG)
• Design-for-test (DFT)
• The model behaves as stuck at fault for a
certain period of time
Path Delay Fault
• It models defects in circuit path • Unlike transition delay fault, path delay
faults do not have localized fault sites.
• Associated with testing the AC performance
of specific paths
Typically critical path
Memory Faults
Stuck-AT- 0 0
1 1 Set Coupling 0 1 Inversion Coupling
1 Active
1 0 0 Neighborhood
1
Pattern Sensitive
Various Faults With Address Decoder AdrE AdrE AdrE AdrE AdrE
Memory Fault – cont.
• Fault Model Derived
Find a test for every “modeled” fault Industry practice currently
Why Model Faults?
• Fault model identifies target faults • Fault model makes analysis possible • Effectiveness measurable by
• Fault models are typically defined
on a structure basis
Different fault models for digital logic, memories and analog circuit
• Typical fault models
Single stuck-at faults Transistor open/short faults Bridging faults Delay faults Memory faults Analog faults
第十章
可测试性设计
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
(ATPG)
• Design-for-test (DFT) techniques
Scan chain technique MBIST Boundary Scan
experiments
Defect & Fault Modeling Definition
• Defect: Physical abnormally fabricated die
E.g. missing/extra material
• Fault: behavior difference due to a defect
• Leff
• Weff
• Res
• ...
Package • BGA • QFP • PGA • TAB • CSP • SIP • MCM • ...
Coverage • DC • AC • Digital • Analog • Speed • Temp • Power • ...
Qualification • Burn-in • Temp-Cycle • HVST • ESD • Latch-up • ...
Verification vs. Test
Verification
• Verifies correctness of
design.
• Performed by
simulation, hardware emulation, or formal verification, etc.
• Performed once prior
Test Challenges
• Reduce the cost of test
Reduce the vector data size Reduce the tester sequencing complexity Reduce the cost of test equipment Reduce the test time