IDM-SBC Schematic Rev A(TI原厂开发板原理图)

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Lab 2 二与非门电路原理图设计

Lab 2 二与非门电路原理图设计1.实验目的1.1了解Schematic设计环境1.2掌握二与非门电路原理图输入方法1.3掌握逻辑符号创建方法2.实验原理2.1Schematic设计环境启动Schematic Editor后，在命令解释窗口CIW中，打开任意库与单元中的Schematic视图，浏览Schematic Editing窗口如图2.1所示，顶部为菜单栏（Menu），左侧为图标栏（Icon Bar），具体介绍如下：图2.1 Schematic Editing窗口2.1.1菜单栏菜单栏中可选菜单有Tool、Design、Window、Edit、Add、Check、Sheet、Options等项。

其中常用菜单有：Tool菜单提供设计工具以及辅助命令。

比如，lab4、lab5所使用的仿真工具ADE，就在Tool下拉菜单中。

Window菜单中的各选项有调整窗口的辅助功能。

比如，Zoom选项对窗口放大（Zoom in）与缩小（Zoom out），fit选项将窗口调整为居中，redraw选项为刷新。

Edit菜单实现具体的编辑功能，主要有取消操作（Undo）、重复操作（Redo）、拉伸（Stretch）、拷贝（copy）、移动（Move）、删除（Delete）、旋转（Rotate）、属性（Properties）、选择（Select）、查找（Search）等子菜单，在以下实验中将大量应用。

Add菜单用于添加编辑所需要的各种素材，比如元件（Instance）或输入输出端点（pin）等。

2.1.2图标栏图标栏内的所有命令都可以在菜单栏实现，图标栏提供使用频率较高的一些菜单为快捷方式，旨在提高设计效率。

从上至下的图标共有：检查错误并存档（Check and Save）、放大（Zoom in）、缩小（Zoom out）、图形拉伸（Stretch）、拷贝（copy）、删除（Delete）、重复操作（Redo）、属性（Properties）、添加元件（Add Instance）、细连线（Wire Narrow）、粗连线（Wire Wide）、连线命名（Wire Label）、添加输入输出端点（Add pin）、命令选择（Command Options）等。

EP1C3T144 FPGA develop board manual(开发板原理图)

FPGA develop board manual ALTERA Cyclone EP1C3T144ALTERA Cyclone 系列的fpga是altera 公司针对底端用户推出的一个系列的fpga。

具有成本低，使用的方便的优点，规模从3000到20000LE。

这一块实验板用的EP1C3T144的芯片，有3000LE逻辑资源，另外还有13条M4K RAM （共6.5Kbyte），另外还有还有一个数字锁相环。

这些资源能够足够应付电子设计竞赛和日常教学的需要，也可以作为初学者入门学习fpga的工具。

1. 开发板介绍1.1. 总体介绍开发板的电路图，如附录所示，电路图一共可分为9个部分：电源部分、按键和LED、下载配置部分、复位部分、外部时钟、滤波电容、用户扩展接口、5 1单片机接口、FPGA 芯片。

1.2. 具体介绍1.2.1. 电源部分板子由外部提供5V电源，使用的圆头插座的封装，可以直接用5V的电源适配器插上使用，不需要直流稳压电源，FPGA的IO的电源是3.3V，内核的电压是1.5V，所以用上两个LEO，一个将5V转到3.3V，另一个将3.3V转到1.5V，加上一些滤波电容，板上的其他外设的电源均是3.3V，另外有3.3V的电源指示灯，表示电源是否正常，还有防反插二极管，防止电源反插，对器件造成损坏。

1.2.2. 按键和LED板上提供4个拨码按键和4个led，分别接到fpga的8个IO引脚上，具体的引脚可以参看电路图或者丝印。

对于初学者，按键和led可以用外当成最简单的外设，用和来控制这些外设。

对于用该板作开发的用户来说，可以把按键当成键盘控制，而把led当成提示来用。

1.2.3. 下载配置部分大家都知道fpga是sram型的可编程逻辑器件，不像rom型可编程器件cpld那样，通过jtag就可以直接把代码固化片子里面。

Fpga随便也可以通过jtag下载代码到片子里面运行。

Fpga下载到片子里面代码是存放在ram里，所以断电后这些代码马上就没有了。

AM335x BeagleBoneBlack Schematic 原理图,A5A版本

42 2
R7 0,1%
VRTC
10uF,10V C15 10uF,10V
3 1
VLDO1
R5 0,1% R8 0,DNI C16 DGND DGND DGND 2.2uF,6.3V
AGND
PPAD
VDD_3V3B VDD_3V3AUX SYS_5V U4 DGND 470K,1% R10 280K,1% R11 TPS65217C
DDR_VTP
C26 18pF,50V
OSC0_IN OSC0_OUT VSS_OSC0 OSC1_IN OSC1_OUT VSS_RTC DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_BA0 DDR_BA1 DDR_BA2 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_CK DDR_NCK DDR_CKE DDR_CSN0 DDR_CASN DDR_RASN DDR_WEn DDR_DQM0 DDR_DQS0 DDR_DQSN0 DDR_DQM1 DDR_DQS1 DDR_DQSN1 DDR_ODT DDR_RESETN DDR_VTP VREFSSTL
B B
This schematic is *NOT SUPPORTED* and DOES NOT constitute a reference design. Only “community” support is allowed via resources at /discuss. THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE DESIGN “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.

LPC2214的原理图

PHILIPS单片32位ARM微控制器－LPC2212/LPC2214( ARM嵌入式系统产品订制)概述LPC2212/LPC2214是一款基于16/32位ARM7TDMI-S，并支持实时仿真和跟踪的CPU,并带有128/256 k字节(kB)嵌入的高速Flash存储器。

128位宽度的存储器接口和独特的加速结构使32位代码能够在最大时钟速率下运行。

对代码规模有严格控制的应用可使用16位Thumb模式将代码规模降低超过30%，而性能的损失却很小。

LPC2212/LPC2214采用144脚封装、极低的功耗、多个32位定时器、8路10位ADC、PWM输出以及多达9个的外部中断，这款微控制器特别适合工业控制、医疗系统、收款机控制等应用领域。

其可用GPIO 范围为76脚(外部存储区)到112脚(单片).由于内置了宽范围的串行通信接口，它们也非常适合于通信网关、协议转换器、嵌入式软件调制解调器以及其它各种类型的应用。

特性16/32位ARM7TDMI-S核，LQFP144封装；16 kB片内SRAM；128/256 kB片内Flash程序存储器，128位宽度接口/加速器可实现高达60 MHz工作频率；可加密：全球首个实现可加密的ARM微控制器；多个串行接口，包括双UART(16C550)，高速I2C(400kbits/s)和双SPI；通过片内boot装载程序实现在系统编程(ISP)和在应用编程(IAP)。

512字节行编程时间为1ms。

单扇区或整片擦除时间为400ms；Embedded ICE-RT可实现断点和观察点。

当使用片内RealMonitor软件对前台任务进行调试时，中断服务程序可继续运行；8路10位A/D转换器，转换时间低至2.44μs；2个32位定时器(带4路捕获和4路比较通道)、PWM单元(6路输出)、实时时钟和看门狗；向量中断控制器。

可配置优先级和向量地址；可设置的外部存储区(寻址最大范围为16MB,支持8/16/32位数据宽度)；多达112个通用I/O口(可承受5V电压)，9个边沿或电平触发的外部中断引脚；CPU工作晶振最大为60MHz，并内嵌片内可编程锁相环PLL；片内晶振频率范围：1~30 MHz；两种低功耗模式，空闲/掉电；通过外部中断将处理器从掉电模式中唤醒；外设功能可单独使能/禁止，实现功耗最优化；双电源－CPU操作电压范围：1.65~1.95 V(1.8 V± 0.15 V)；－I/O操作电压范围：3.0~3.6 V(3.0 V± 10%)，可承受5V电压。

Proteus原理图元器件库详细说明

Analog ICs Capacitors CMOS 4000 series
Connectors Data Converters Debugging Tools
Diodes ECL 10000 Series
Electromechanical Inductors Laplace Primitives Mechanics
535 832 233
104 227 19
1623 28
10 258 48 2
232 523 14 197 1490 158 14 12 681 26
5 342 333 25
19 1677 262 198 138 112 303 213 347 139
运算放大器，端稳压器等电容
4060 14 级二进制串行计数 /分频器等 4035 于 4 通用移位寄存器连接器
LOGIC ANALYSER 逻辑分析器 LOGICPROBE 逻辑探针
LOGICPROBE[BIG] 逻辑探针用来显示连接位置的逻辑状态 LOGICSTATE 逻辑状态用鼠标点击 ,可改变该方框连接位置的逻辑状态 LOGICTOGGLE 逻辑触发 MASTERSWITCH 按钮手动闭合 ,立即自动打开 MOTOR 马达 OR 或门 POT-LIN 三引线可变电阻器 POWER 电源 RES 电阻 RESISTOR 电阻器 SWITCH 按钮手动按一下一个状态 SWITCH-SPDT 二选通一按钮 VOLTMETER 伏特计 VOLTMETER-MILLI mV 伏特计 VTERM 串行口终端 Electromechanical 电机 Inductors 变压器 Laplace Primitives 拉普拉斯变换 Memory Ics Microprocessor Ics Miscellaneous 各种器件 AERIAL- 天线； ATAHDD ；ATMEGA64 ； BATTERY ；CELL ；CRYSTAL- 晶振； FUSE ；METER- 仪表； Modelling Primitives 各种仿真器件是典型的基本元器模拟，不表示具体型号，只用于仿真，没有 PCB Optoelectronics 各种发光器件发光二极管， LED ，液晶等等 PLDs & FPGAs Resistors 各种电阻 Simulator Primitives 常用的器件 Speakers & Sounders Switches & Relays 开关，继电器，键盘 Switching Devices 晶阐管 Transistors 晶体管（三极管，场效应管） TTL 74 series TTL 74ALS series TTL 74AS series TTL 74F series TTL 74HC series TTL 74HCT series TTL 74LS series TTL 74S series Analog Ics 模拟电路集成芯片 Capacitors 电容集合 CMOS 4000 series Connectors 排座，排插 Data Converters ADC,DAC Debugging Tools 调试工具 ECL 10000 Series 各种常用集成电路

ep ce 官方原理图

CONTENTCover Page, Placement,TOPSDRAM, EEPROMCLOCK, LED, BUTTON,SW, GPIOs, 2X13 HEADER, G-SENSOR, ADC POWER 1.2V, 2.5V, 3.3VCyclone IV EP4CE22 BANK1..BANK8 , POWER , CONFIGTitle Size Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved.BTitle Size Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved.BDRAM_DQ[15..0]DRAM_DQ[15..0]DRAM_ADDR[12..0]DRAM_DQM[1..0]KEY[1..0]SW[3..0]LED[7..0]DRAM_BA0DRAM_BA1DRAM_CAS_N DRAM_RAS_N DRAM_WE_N DRAM_CS_N DRAM_CKE DRAM_CLK JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO NSTATUS CONF_DONE NCONFIG NCEI2C_SCLK I2C_SDAT G_SENSOR_CS_N G_SENSOR_INTI2C_SDATI2C_SCLK I2C_SDAT G_SENSOR_CS_N G_SENSOR_INT ADC_SDAT ADC_CS_N ADC_SADDR ADC_SCLKCLOCK_50GPIO_0_IN[1..0]GPIO_0[33..0]GPIO_1_IN[1..0]GPIO_1[33..0]GPIO_2_IN[2..0]GPIO_2[12..0]TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B PAGE 4 - 802 EP4CE22NSTATUS NCENCONFIGTDI TMS TDOTCK CONF_DONELED[7..0]SW[3..0]ADC_SCLK KEY[1..0]CLOCK_50DRAM_BA0DRAM_BA1DRAM_CKE DRAM_CLK DRAM_ADDR[12..0]DRAM_DQ[15..0]DRAM_DQM[1..0]G_SENSOR_INT DRAM_CAS_N ADC_SADDR DRAM_WE_N DRAM_CS_N ADC_CS_N G_SENSOR_CS_N ADC_SDAT DRAM_RAS_N I2C_SDATI2C_SCLK GPIO_1_IN[1..0]GPIO_0[33..0]GPIO_2_IN[2..0]GPIO_1[33..0]GPIO_0_IN[1..0]GPIO_2[12..0]DRAM_DQ[15..0]I2C_SDATPAGE 1405 POWERPAGE 9 - 1103 IN/OUT G_SENSOR_INT ADC_SADDR G_SENSOR_CS_N I2C_SDATI2C_SCLK GPIO_1_IN[1..0]GPIO_0[33..0]GPIO_2_IN[2..0]GPIO_0_IN[1..0]GPIO_1[33..0]GPIO_2[12..0]BANK 1BANK 2KEY1DRAM_DQ3DRAM_DQ6DRAM_DQ5DRAM_DQ4DRAM_DQ15DRAM_ADDR0DRAM_ADDR12DRAM_ADDR11DRAM_ADDR9DRAM_ADDR8DRAM_ADDR10LED5SW0LED7G_SENSOR_CS_N LED[7..0]G_SENSOR_INT KEY[1..0]DRAM_ADDR[12..0]DRAM_DQ[15..0]SW[3..0]DRAM_RAS_N DRAM_CAS_N Size Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.TitleDate:No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B U1AEP4CE22F17DQS2L/CQ3L,CDPCLK0DIFFIO_L3p DIFFIO_L4N IO1_0G5DIFFIO_L5p DIFFIO_L5nDIFFIO_L6p/DQS0L/CQ1L,DPCLK0DIFFIO_L6nCLK1/DIFFCLK_0nE1IO/VREFB1N0F3U1BEP4CE22F17DIFFIO_L7p/DQ1L J2DIFFIO_L7n/DQ1L J1DIFFIO_L10p K2DIFFIO_L10n/DQ1L K1DIFFIO_L11p/DQS1L/CQ1L#,DPCLK1L2DIFFIO_L11n/DQ1L L1DIFFIO_L13p/DQ1L N2DIFFIO_13n/DQ1L N1DIFFIO_L15p/DQ1LP2DIFFIO_L15n/DM1L/BWS#1L P1IO2_0/DQS3L/CQ3L#,CDPCLK1R1RUP1/DQ1L K5RDN1/DQ1L L4IO/VREFB2N0L3CLK2/DIFFCLK_1pM2CLK3/DIFFCLK_1nM1BANK 3BANK 4DRAM_DQ8DRAM_DQ9GPIO_114GPIO_112GPIO_111GPIO_16GPIO_19GPIO_18GPIO_14GPIO_13GPIO_15GPIO_12GPIO_11GPIO_17SW1CLOCK_50DRAM_CLK DRAM_DQ[15..0]DRAM_DQM[1..0]GPIO_1[33..0]GPIO_1_IN[1..0]DRAM_BA1DRAM_CKEDRAM_CS_N TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B U1CEP4CE22F17DIFFIO_B1p DIFFIO_B1n/DM3B/BWS#3B DIFFIO_B2p/DQ3B DIFFIO_B2nIO3_0/DQS1B/CQ1B#,CDPCLK2T2PLL1_CLKOUTp R4PLL1_CLKOUTn T4DIFFIO_B4p/DQ3B DIFFIO_B4n/DQ3BIO3_1/DQ3B M6IO/VREFB3N0P6DIFFIO_B5p/DQS3B/CQ3B#,DPCLK2DIFFIO_B6p/DQ3B DIFFIO_B6nDIFFIO_B7p/DQ3B DIFFIO_B7n IO3_2/DQ3B L7DIFFIO_B8p/DQ3BDIFFIO_B8n/DQS5B/CQ5B#,DPCLK3DIFFIO_B9n/DQ3BDIFFIO_B10n/DM5B/BWS#5B DIFFIO_B11p/DQ5B DIFFIO_B12n/DQ5BCLK14/DIFFCLK_6n T8CLK15/DIFFCLK_6p R8U1DEP4CE22F17DIFFIO_B14n/DQ5B N9DIFFIO_B16p/DQ5BR10DIFFIO_B16n/DQS4B/CQ5B,DPCLK4T10DIFFIO_B17p/DQ5B R11DIFFIO_B17n T11DIFFIO_B18p/DQ5B R12DIFFIO_B18n/DQ5B T12IO4_0/DQS2B/CQ3B,DPCLK5P9IO/VREFB4N0P11DIFFIO_B20pR13DIFFIO_B20n/DQ5B T13RUP2M10RDN2N11DIFFIO_B23p/DQ5BT14DIFFIO_B23n/DQS0B/CQ1B,CDPCLK3T15DIFFIO_B24p N12PLL4_CLKOUTpP14PLL4_CLKOUTnR14CLK12/DIFFCLK_7nT9CLK13/DIFFCLK_7p R9BANK 5BANK 6GPIO_2_IN2GPIO_24GPIO_23GPIO_28GPIO_29GPIO_212GPIO_211GPIO_127GPIO_120GPIO_126SW3GPIO_1[33..0]KEY[1..0]GPIO_2_IN[2..0]GPIO_2[12..0]SW[3..0]TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B EP4CE22F17RUP3/DM1R/BWS#1R N14RDN3/DQ1R P15DIFFIO_R15n/DQS3R/CQ3R#,CDPCLK4DIFFIO_R15p/DQ1R DIFFIO_R13n/DQ1R DIFFIO_R13p/DQ1R IO/VREFB5N0L14DIFFIO_R12p/DQ1R DIFFIO_R11n/DQ1R DIFFIO_R11p DIFFIO_R10n/DQ1R DIFFIO_R10p/DQS1R/CQ1R#,DRCLK6DIFFIO_R9n/DEV_OE DIFFIO_R9p/DEV_CLRn DIFFIO_R8n/DQ1R DIFFIO_R7n/DQ1RCLK6/DIFFCLK_3p M15CLK7/DIFFCLK_3nM16U1FEP4CE22F17DIFFIO_R5n/INIT_DONE G16DIFFIO_R5p/CRC_ERROR G15IO6_0DIFFIO_R4n/nCEO F16DIFFIO_R4p/CLKUSRF15IO6_1/DQS0R/CQ1R,DPCLK7IO/VREFB6N0IO6_2IO6_3/PADD23DIFFIO_R1n/PADD20/DQS2R/CQ3R,CDPCLK5C16DIFFIO_R1pC15CLK4/DIFFCLK_2p CLK5/DIFFCLK_2nBANK 7BANK 8GPIO_027GPIO_026GPIO_028GPIO_020GPIO_021GPIO_016GPIO_010GPIO_013GPIO_014GPIO_07GPIO_08GPIO_011GPIO_05GPIO_06GPIO_02GPIO_03GPIO_017GPIO_012GPIO_20SW2GPIO_2[12..0]LED[7..0]SW[3..0]ADC_SCLK ADC_SDATGPIO_0[33..0]GPIO_0_IN[1..0]TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B U1HEP4CE22F17DIFFIO_T11p/PADD17/DQS5T/CQ5T#,DPCLK10C8IO8_0/DQ3T DIFFIO_T10n/DATA2/DQ3T E8DIFFIO_T10p/DATA3F8DIFFIO_T9n/PADD18/DQ3T A7DIFFIO_T9p/DATA4/DQ3T B7IO/VREFB8N0DIFFIO_T7n/DATA14/DQS3T/CQ3T#,DPCLK11A6DIFFIO_T7p/DATA13/DQ3T B6IO8_1/DATA5/DQ3T DIFFIO_T6p/DATA6/DQ3T E6DIFFIO_T5n/DATA7/DQ3T A5DIFFIO_T5p/DATA8/DQ3T B5DIFFIO_T4n/DATA9D6DIFFIO_T3n/DATA10/DM3T/BWS#3T A4DIFFIO_T3p/DATA11B4DIFFIO_T2n A2DIFFIO_T2pA3IO8_2IO8_3/DATA12PLL3_CLKOUTp PLL3_CLKOUTn CLK11/DIFFCLK_4p CLK10/DIFFCLK_4nEP4CE22F17DIFFIO_T24n DIFFIO_T24p/DQ5T DIFFIO_T23nDIFFIO_T23p/DQS0T/CQ1T,CDPCLK6DIFFIO_T22nDIFFIO_T22p/DQ5T PLL2_CLKOUTn A14PLL2_CLKOUTp B14RUP4E11RDN4E10DIFFIO_T21n/DQ5T DIFFIO_T21p/DQ5T DIFFIO_T20n/DQ5TDIFFIO_T20p/PADD0/DQ5T IO/VREFB7N0C11DIFFIO_T19n/PADD1DIFFIO_T17p/PADD4/DQS2T/CQ3T,DPCLK8DIFFIO_T16n/PADD5/DQ5T DIFFIO_T16p/PADD6/DQ5T DIFFIO_T15n/PADD7/DQ5T DIFFIO_T15p/PADD8/DM5T/BWS#5TDIFFIO_T13p/PADD12/DQS4T/CQ5T,DPCLK9CLK9/DIFFCLK_5p B9CLK8/DIFFCLK_5nA9POWER & GNDCONFIGURATIONAS Fast POR configuration at 3.0- or 2.5-VTDOTCKDCLK ASDO NCSO DATA0NSTATUS NCENCONFIG TDI TMS TDO TCK CONF_DONEVCC1P2VCCD_PLL VCC2P5VCCA VCCD_PLLVCCA VCC3P3VCC3P3VCCAVCCAVCC3P3TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B U1JEP4CE22F17TCK H3TMS J5TDI H4TDO J4DCLK H1nSTATUS F4nCONFIG H5nCE J3ASDO C1nCSO D2DATA0H2CONF_DONEH14MSEL0H13MSEL1H12MSEL2G12R100DNIC200.1uR90C260.1uC320.1uR4TBD DNIC190.1uC240.1uC890.1uC220.1uC210.1uC3510uC280.1uL2BEADL1BEADC310.1uC300.1uEP4CE22F17G N D G N D L 9G N D L 10G N D L 11G N D K 12G N D G 11G N D B 2G N D B 15G N D C 5G N D C 12G N D D 7G N DD 10GND E4GND E13GND G4GND G13GND K4GND K13GND M4GND M13GND N7GND N10GND P5GND P12GND R2GND R15GND E2GND H16GND H15GNDA1M5GNDA2E12GNDA3E5GNDA4M12V C C I O 4V C C I O 5V C C I O 5V C C I O 6V C C I O 6V C C I O 7V C C I O 7V C C I O 7V C C I O 8V C C I O 8V C C I O 8C3610uC290.1uC37TBDDNIR71KR80DNIC230.1uC330.1uC18100uR20DNIC250.1uR10C340.1uR111KDNIC270.1uR30LED2LED1LED3LED0LED4LED7LED6LED5KEY0KEY1CLOCK_50KEY[1..0]VCC2P5VCC2P5VCC3P3VCC2P5VCC2P5TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B R132KLED3LEDGY150MHZVCC 4OUT3GND 2EN 1C401nRN212012345678U2SN74AUC171A 12A 33A 54A 95A 116A131Y 22Y 43Y 64Y 85Y 106Y 12GND7VCC 14ETP 15C410.1uLED7LEDGKEY0TACK_SW_RA4321RN112012345678C380.1uR12100KR152K KEY1TACK_SW_RA4321R14100KLED6LEDGLED5LEDG LED4LEDG C391nLED2LEDG ON1SW1SW-DIP812348765LED1LEDGGPIO - 0GPIO - 1GPIO - 2GPIO_032GPIO_031GPIO_07GPIO_012GPIO_0_IN1GPIO_0_IN0GPIO_011GPIO_016GPIO_014GPIO_020GPIO_019GPIO_010GPIO_022GPIO_026GPIO_030GPIO_017GPIO_015GPIO_06GPIO_00GPIO_024GPIO_013GPIO_09GPIO_021GPIO_033GPIO_029GPIO_025GPIO_023GPIO_02GPIO_018GPIO_028GPIO_08GPIO_05GPIO_04GPIO_027GPIO_03GPIO_132GPIO_131GPIO_17GPIO_112GPIO_1_IN1GPIO_1_IN0GPIO_111GPIO_116GPIO_114GPIO_120GPIO_119GPIO_110GPIO_122GPIO_126GPIO_130GPIO_117GPIO_115GPIO_16GPIO_10GPIO_124GPIO_113GPIO_19GPIO_121GPIO_133GPIO_129GPIO_125GPIO_123GPIO_12GPIO_118GPIO_128GPIO_18GPIO_15GPIO_14GPIO_127GPIO_13GPIO_2_IN1GPIO_20GPIO_22GPIO_24GPIO_26GPIO_28GPIO_210GPIO_212GPIO_2_IN0GPIO_2_IN2GPIO_21GPIO_23GPIO_25GPIO_27GPIO_29GPIO_211GPIO_01GPIO_11Analog_In0Analog_In4Analog_In6Analog_In3Analog_In5Analog_In7Analog_In1Analog_In2GPIO_0[33..0]GPIO_0_IN[1..0]GPIO_2[12..0]GPIO_2_IN[2..0]GPIO_1[33..0]GPIO_1_IN[1..0]VCC_SYSVCC3P3VCC_SYSVCC3P3VCC3P3Analog_In[7..0]TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B JP21122334455667788991010111112121313141415151616171718181919202021212222232324242525262627272828292930303131323233333434353536363737383839394040JP32X13 HEADER11223344556677889910101111121213131414151516161717181819192020212122222323242425252626JP11122334455667788991010111112121313141415151616171718181919202021212222232324242525262627272828292930303131323233333434353536363737383839394040Digital AccelerometerADC_IN0ADC_IN1ADC_IN2ADC_IN3ADC_IN4ADC_IN5ADC_IN6ADC_IN7ADC_IN1Analog_In1ADC_IN2Analog_In2ADC_IN3Analog_In3ADC_IN4Analog_In4ADC_IN5Analog_In5ADC_IN6Analog_In6ADC_IN7Analog_In7ADC_IN0Analog_In0G_SENSOR_INTI2C_SCLK I2C_SDATVCC_VSAGNDAGND AGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDVCC3P3Analog_In[7..0]TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B ADXL345INT18INT29NC 10RESERVED_111SDO_ALT_ADDRESS12SDA_SDI_SDIO 13SCL_SCLK 14R2622R2222C541n C421uR620DNIC530.1uC481nR212.2KDNIR2422C571nR1722R2722C551n R2022R2522C501n C511nR2822C461nC561n R1910KC524.7uDRAM_ADDR3DRAM_ADDR0DRAM_ADDR2DRAM_ADDR1DRAM_ADDR10DRAM_DQM0DRAM_DQ5DRAM_DQ0DRAM_DQ7DRAM_DQ6DRAM_DQ3DRAM_DQ2DRAM_DQ4DRAM_DQ1DRAM_ADDR12DRAM_ADDR5DRAM_ADDR7DRAM_ADDR6DRAM_ADDR8DRAM_ADDR11DRAM_ADDR4DRAM_ADDR9DRAM_DQM1DRAM_DQ8DRAM_DQ15DRAM_DQ11DRAM_DQ9DRAM_DQ10DRAM_DQ13DRAM_DQ14DRAM_DQ12DRAM_DQM[1..0]DRAM_ADDR[12..0]DRAM_CLK DRAM_CKE DRAM_BA0DRAM_BA1DRAM_WE_N DRAM_CAS_N DRAM_RAS_N DRAM_CS_N VCC3P3TitleCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.U5SDRAM 16Mx16A023A124A225A326A429A530A631A732A833A934nCAS 17nRAS 18LDQM 15nWE 16nCS 19CKE 37CLK 38UDQM 39D02D14D25D37D48D510D611D713D842D944D1045D1147D1248D1350D1451D1553A1236BA020V D D 1V D D27V S S 28V S S 41A1022V D D Q 3V D D Q 9V D D Q 43V D D Q49V S S Q 6V S S Q 12V S S Q 46V S S Q52A1135BA121V S S54V D D 14C620.1uC630.1uC580.1uC640.1uC590.1uC600.1uC610.1uI2C ADDRESS W/R = 0xA0/0xA1I2C_SCLK I2C_SDATVCC3P3VCC3P3VCC3P3VCC3P3TitleCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.R351KR30R34C650.1uR332K R310DNIA1A0VSS A2VCC SDASCL WP U624LC02B456871239R361K R322KVCC_SYS Range: 3.3 ~ 5.5 V2.5V/150mA1.2V/1.5AInput Power Range: VCC2P5VCC3P3VCC3P3VCC1P2VCC_SYSVCC3P3VCC1P2TitleSize Date:Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.B 10uC7210uR450DNIFID6REG2LP5900SD-2.5VIN6G N D3VOUT 1VEN 4P A D7NC12NC25C690.47uC7310uD7PMEG2010AEBFID7R381.2KR494.99KREG3LP38500SD-ADJIN 2IN 3IN4G N D 1OUT 5OUT 6OUT 7ADJ8D A P9C740.1uC700.47uFID5J2SIP2DNI12FID8R484.99KLP38500SD-ADJG N D 1ADJD A P90.1u10uR4710K5.36KD6PMEG2010AEBSIP2DNIR46C710.1uR610D8PMEG2010AEB。

LPC2148开发板原理图

5
P119 P118 P117 P116 P120 P123 P122 P121
C1 2 22pF 1 X1 32.768KHz 5 49 RTCX2 VBAT
4
TRACE_CN/NC
VDD3V3 VREF 1 2 1 1 1 1 1 1
3
R1 1
100R 2 GND
23 43 51 6 18 25 42 50 63
B
1N4148SMD D9 k 2 1 a R32 1 1.5K 2
2
VDD3V3 U4 1 2 3 4 RO VCC RE A B DE DI GND MAX485-SO8 R35 1 0R 2 2 e 8 6 7 5
VDD5V
R31 100R 1 CN8 1 2 3 RES
R30 1 D10 2 k D11 2 k R34 1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
4.7K 2 1N4148SMD a 1 1N4148SMD a 1 4.7K 2
P0.14/BSL
R33 1
0R/NC 2
VDD5V R36 1
A
1K 2 0R/NC 2 2K 2 GND
3
3
c
R37 1 R38 1
Q2 S9013SMD Title
b
RS232 & RS485
Size A Date: Document Number

EDACS 接口 TUAI для SIMULCAST 维护手册说明书

LBI-38948A MAINTENANCE MANUALEDACS®INTERFACETUAI FOR SIMULCAST19C852339G1SPECIFICATIONS*FUNCTIONS TUAI CH01 thru CH25TUAI TU01 thru TUO5 CONNECTORSJ1thruJ5Modular Telephone jack: 6 positionJ9andJ10Two 25 Pair Telco ConnectorsPARTS LISTTUAI For Simulcast Module 19C852339G1*These specifications are intended primarily for the use of the service technician. Refer to the appropriate Specifications Sheet in the applicable maintenance manual for the complete specifications.1DESCRIPTIONT est U nit A larm I nterface (TUAI ) Module 19C852219G1 is used to collect and route Test Unit Alarm Interface data throughout an E nhanced D igital A ccess C ommunication S ystem (EDACS ) through a common 25pair cable. This module mounts on EDACS Interface Panel 19D904009 (refer to Maintenance Manual LBI38812) when associated with Simulcast Station and Simulcast Common Equipment cabinets. The TUAI Module consists of five (5)telephone type modular (RJ12) jacks J1 through J5, and two 25 pair Telco connectors J9 and J10.Connectors J1 through J5 connect to the common con-nections between connectors J9 and J10 (refer to Schematic Diagram 19D904471). Through printed circuit wiring, con-nector J1, Pins 1 through 5 connect to TUAI channels 1through 5 (CH01 through CH05), respectively. Connector J1, Pin 6 connects to Test Unit #1 (TUO1) through J9, Pin 28.Connector J2, Pins 1 through 5 connects to TUAI chan-nels 6 through 10 (CH06 through CH10). Connector J2,Pin 6 connects to Test Unit #2 (TU02) through J9, Pin 14.Connector J3, Pins 1 through 5 connect to TUAI chan-nels 11 through 15 (CH11 through CH15). Connector J3,Pin 6 connects to Test Unit #3 (TU03) through J9, Pin 39.Connector J4, Pins 1 through 5 connects to TUAI chan-nels 16 through 20 (CH16 through CH20). Connector J4,Pin 6 connects to Test Unit #4 (TU04) through J9, Pin 15.Connector J5, Pins 1 through 5 connects to TUAI chan-nels 21 through 25 (CH21 through CH25).CIRCUIT ANAL YSISThe Test Unit Alarm Interface Module maps up to twenty five (25) TUAI channels, and five (5) Test Units to five (5) modular telephone jacks. These modular jacks con-nect to the various input/outputs within an EDACS System (refer to Schematic Diagram 19D904471). The TUAI Inter-face Module wiring arrangement is apparent when looking into the end of the common cable connecting J9 to J10 and having the channel and test unit connections designated in this pattern (refer to Figure 1).Printed in U.S.A.Copyright© October 1993, Ericsson GE Mobile Communications Inc.Figure 1 - Pin Assignments Looking Into ConnectionsBetween J9 and J10LBI-389482LBI-38948 TABLE OF TUAI INTERFACE MODULE CONNECTIONS3TUAI MODULE FOR SIMULCAST (19C852339, Rev. 4)OUTLINE DIAGRAMLBI-38948 4LBI-38948 SCHEMATIC DIAGRAM ArrayTUAI MDOULE FOR SIMULCAST(19D904471, Rev. 2)5。