AT24c04 的datasheet
AT24C04的原理与应用
4.2 I2C器件AT24C04的原理与应用I2C(Inter－Integrated Circuit)总线是一种由PHILIPS公司开发的两线式串行总线，用于连接微控制器及其外围设备。
I2C总线产生于上世纪80年代，最初为音频和视频设备开发，如今主要在服务器管理中使用，其中包括单个组件状态的通信。
I2C总线最主要的优点是其简单性和有效性。
由于接口直接在组件之上，因此I2C 总线占用的空间非常小，减少了电路板的空间和芯片管脚的数量，降低了互联成本。
总线的长度可高达25英尺，并且能够以10Kbps的最大传输速率支持40个组件。
I2C总线的另一个优点是，它支持多主控(multimastering)，其中任何能够进行发送和接收的设备都可以成为主总线。
一个主控能够控制信号的传输和时钟频率。
当然，在任何时间点上只能有一个主控。
4.2.21 I2C总线的构成和信号类型一、I2C总线的构成I2C总线是由数据线SDA和时钟SCL构成的串行总线，可发送和接收数据。
在CPU 与被控IC之间、IC与IC之间进行双向传送，最高传送速率100kbps，采用7位寻址，但是由于数据传输速率和应用功能的迅速增加，I2C总线也增强为快速模式（400Kbits/s）和10位寻址以满足更高速度和更大寻址空间的需求。
各种被控制电路均并联在这条总线上，但就像电话机一样只有拨通各自的号码才能工作，所以每个电路和模块都有唯一的地址。
在信息的传输过程中，I2C总线上并接的每一模块电路既是主控器（或被控器），又是发送器（或接收器），这取决于它所要完成的功能。
CPU发出的控制信号分为地址码和控制量两部分，地址码用来选址，即接通需要控制的电路，确定控制的种类；控制量决定该调整的类别（如对比度、亮度等）及需要调整的量。
这样，各控制电路虽然挂在同一条总线上，却彼此独立，互不相关。
二、I2C总线的信号类型I2C总线在传送数据过程中共有三种类型信号，它们分别是：起始信号、终止信号和应答信号。
24C04中文资料
ST24C04, ST25C04 ST24W04, ST25W044 Kbit Serial I 2C Bus EEPROMwith User-Defined Block Write ProtectionFebruary 19991/16AI00851E2E1-E2SDAV CCST24x04ST25x04MODE/WC*SCLV SSPRE Figure 1. Logic Diagram1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE:–3V to 5.5V for ST24x04 versions –2.5V to 5.5V for ST25x04 versionsHARDWARE WRITE CONTROL VERSIONS:ST24W04 and ST25W04PROGRAMMABLE WRITE PROTECTION TWO WIRE SERIAL INTERFACE, FULLY I 2C BUS COMPATIBLEBYTE and MULTIBYTE WRITE (up to 4BYTES)PAGE WRITE (up to 8 BYTES)BYTE, RANDOM and SEQUENTIAL READ MODESSELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCESDESCRIPTIONThis specification covers a range of 4 Kbits I 2C bus EEPROM products, the ST24/25C04 and the ST24/25W04. In the text, products are referred to as ST24/25x04, where "x" is: "C" for Standard version and "W" for hardware Write Control ver-sion.PRE Write Protect Enable E1-E2Chip Enable InputsSDA Serial Data Address Input/Output SCL Serial ClockMODE Multibyte/Page Write Mode (C version)WC Write Control (W version)V CC Supply Voltage V SSGroundTable 1. Signal Names81SO8 (M)150mil Width81PSDIP8 (B)0.25mm FrameNote: WC signal is only available for ST24/25W04 products.The ST24/25x04 are 4 Kbit electrically erasable programmable memories (EEPROM), organized as 2 blocks of 256 x8 bits. They are manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees an endur-ance of one million erase/write cycles with a data retention of 40 years.Both Plastic Dual-in-Line and Plastic Small Outline packages are available.The memories are compatible with the I 2C stand-ard, two wire serial interface which uses a bi-direc-tional data bus and serial clock. The memoriescarry a built-in 4 bit, unique device identification code (1010) corresponding to the I 2C bus defini-tion. This is used together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices may be attached to the I 2C bus and selected individually.The memories behave as a slave device in the I 2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.SDAV SSSCL MODE/WC E1PRE V CCE2AI00852EST24x04ST25x0412348765Figure 2A. DIP Pin Connections 1AI01107E2348765SDAV SSSCL MODE/WC E1PRE V CCE2ST24x04ST25x04Figure 2B. SO Pin ConnectionsDESCRIPTION (cont’d)Symbol ParameterValue Unit T A Ambient Operating Temperature –40 to 125 °C T STG Storage Temperature –65 to 150°C T LEAD Lead Temperature, Soldering (SO8 package)(PSDIP8 package)40 sec 10 sec215260°C V IO Input or Output Voltages –0.6 to 6.5 V V CC Supply Voltage–0.3 to 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) (2)4000V Electrostatic Discharge Voltage (Machine model) (3)500VNotes:1.Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute MaximumRating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.-STD-883C, 3015.7 (100pF, 1500 Ω).3.EIAJ IC-121 (Condition C) (200pF, 0 Ω).Table 2. Absolute Maximum Ratings (1)2/16ST24/25C04, ST24/25W04ModeRW bit MODE Bytes Initial SequenceCurrent Address Read ’1’X 1START, Device Select, RW = ’1’Random Address Read ’0’X1START, Device Select, RW = ’0’, Address,’1’reSTART, Device Select, RW = ’1’Sequential Read ’1’X 1 to 512Similar to Current or Random Mode Byte Write ’0’X 1START, Device Select, RW = ’0’Multibyte Write (2)’0’V IH 4START, Device Select, RW = ’0’Page Write’0’V IL8START, Device Select, RW = ’0’Notes:1.X = V IH or V IL2.Multibyte Write not available in ST24/25W04 versions.Table 4. Operating Modes (1)Device CodeChip EnableBlock Select RW Bitb7b6b5b4b3b2b1b0Device Select11E2E1A8RWNote: The MSB b7 is sent first.Table 3. Device Select CodeWhen writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are termi-nated with a STOP condition.Power On Reset: V CC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the V CC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command.In the same way, when V CC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable V CC must be applied before applying any logic signal.SIGNAL DESCRIPTIONSSerial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to V CC to act as a pull up (see Figure 3).Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory.It is an open drain output that may be wire-OR’edwith other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to V CC to act as pull up (see Figure 3).Chip Enable (E1 - E2). These chip enable inputs are used to set the 2 least significant bits (b2, b3)of the 7 bit device select code. These inputs may be driven dynamically or tied to V CC or V SS to establish the device select code.Protect Enable (PRE). The PRE input pin, in ad-dition to the status of the Block Address Pointer bit (b2, location 1FFh as in Figure 7), sets the PRE write protection active.Mode (MODE). The MODE input is available on pin 7 (see also WC feature) and may be driven dynami-cally. It must be at V IL or V IH for the Byte Write mode, V IH for Multibyte Write mode or V IL for Page Write mode. When unconnected, the MODE input is internally read as V IH (Multibyte Write mode). Write Control (WC). An hardware Write Control feature (WC) is offered only for ST24W04 and ST25W04 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control sig-nal is used to enable (WC = V IH ) or disable (WC =V IL ) the internal write protection. When uncon-nected, the WC input is internally read as V IL and the memory area is not write protected.3/16ST24/25C04, ST24/25W04AI01100V CCC BUSSDA R LMASTERR LSCLC BUS10020030040048121620C BUS (pF)R L m a x (k Ω)V CC = 5VFigure 3. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2C BusThe devices with this Write Control feature no longer support the Multibyte Write mode of opera-tion, however all other write modes are fully sup-ported.Refer to the AN404 Application Note for more de-tailed information about Write Control feature.DEVICE OPERATION I 2C Bus BackgroundThe ST24/25x04 support the I 2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for syn-chronisation. The ST24/25x04 are always slave devices in all communications.Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x04 con-tinuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi-nates communication between the ST24/25x04and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.Data Input. During data input the ST24/25x04sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device opera-tion the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low.Memory Addressing. To start communication be-tween the bus master and the slave ST24/25x04,the master must initiate a START condition. Follow-ing this, the master sends onto the SDA bus line 8bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.SIGNAL DESCRIPTIONS (cont’d)4/16ST24/25C04, ST24/25W04Symbol ParameterTest ConditionMinMax Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance (ST24/25W04)V IN ≤ 0.3 V CC 520k ΩZ WCH WC Input Impedance (ST24/25W04)V IN ≥ 0.7 V CC500k Ωt LPLow-pass filter input time constant (SDA and SCL)100nsNote: 1. Sampled only, not 100% tested.Table 5. Input Parameters (1) (T A = 25 °C, f = 100 kHz )Symbol ParameterTest Condition MinMax Unit I LI Input Leakage Current 0V ≤ V IN ≤ V CC ±2µA I LO Output Leakage Current 0V ≤ V OUT ≤ V CC SDA in Hi-Z ±2µA I CCSupply Current (ST24 series)V CC = 5V, f C = 100kHz (Rise/Fall time < 10ns)2mA Supply Current (ST25 series)V CC = 2.5V, f C = 100kHz 1mA I CC1Supply Current (Standby)(ST24 series)V IN = V SS or V CC ,V CC = 5V 100µA V IN = V SS or V CC , V CC = 5V, f C = 100kHz 300µA I CC2Supply Current (Standby) (ST25 series)V IN = V SS or V CC , V CC = 2.5V 5µA V IN = V SS or V CC , V CC = 2.5V, f C = 100kHz50µA V IL Input Low Voltage (SCL, SDA)–0.30.3 V CC V V IH Input High Voltage (SCL, SDA)0.7 V CC V CC + 1V V IL Input Low Voltage(E1-E2, PRE, MODE, WC)–0.30.5V V IH Input High Voltage(E1-E2, PRE, MODE, WC)V CC – 0.5V CC + 1V V OLOutput Low Voltage (ST24 series)I OL = 3mA, V CC = 5V 0.4V Output Low Voltage (ST25 series)I OL = 2.1mA, V CC = 2.5V0.4VTable 6. DC Characteristics(T A = 0 to 70°C, –20 to 85°C or –40 to 85°C; V CC = 3V to 5.5V or 2.5V to 5.5V)5/16ST24/25C04, ST24/25W04The 4 most significant bits of the device select codeare the device type identifier, corresponding to the I 2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 2 bits identify the specific memory on the bus. They are matched to the chip enable signals E2, E1. Thus up to 4 x 4K memories can be connected on the same bus giving a memory capacity total of 16 Kbits. After a START condition any memory on the bus will iden-tify the device code and compare the following 2bits to its chip enable inputs E2, E1.The 7th bit sent is the block number (one block =256 bytes). The 8th bit sent is the read or write bit (RW), this bit is set to ’1’ for read and ’0’ for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time.Input Rise and Fall Times ≤ 50nsInput Pulse Voltages0.2V CC to 0.8V CCInput and Output Timing Ref. Voltages 0.3V CC to 0.7V CCAC MEASUREMENT CONDITIONSAI008250.8V CC0.2V CC0.7V CC 0.3V CCFigure 4. AC Testing Input Output WaveformsDEVICE OPERATION (cont’d)Symbol Alt ParameterMinMax Unit t CH1CH2t R Clock Rise Time 1µs t CL1CL2t F Clock Fall Time 300ns t DH1DH2t R Input Rise Time 1µs t DL1DL1t F Input Fall Time300ns t CHDX (1)t SU:STA Clock High to Input Transition 4.7µs t CHCL t HIGH Clock Pulse Width High4µs t DLCL t HD:STA Input Low to Clock Low (START)4µs t CLDX t HD:DAT Clock Low to Input Transition 0µs t CLCH t LOW Clock Pulse Width Low4.7µs t DXCX t SU:DAT Input Transition to Clock Transition 250ns t CHDH t SU:STO Clock High to Input High (STOP) 4.7µs t DHDL t BUF Input High to Input Low (Bus Free) 4.7µs t CLQV (2)t AA Clock Low to Next Data Out Valid 0.3 3.5µs t CLQX t DH Data Out Hold Time 300ns f C f SCL Clock Frequency 100kHz t W (3)t WRWrite Time10msNotes:1.For a reSTART condition, or following a write cycle.2.The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions.3.In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) themaximum programming time is doubled to 20ms.Table 7. AC Characteristics(T A = 0 to 70°C, –20 to 85°C or –40 to 85°C; V CC = 3V to 5.5V or 2.5V to 5.5V)6/16ST24/25C04, ST24/25W04SCL SDA INSCL SDA OUTSCL SDA INtCHCLtDLCLtCHDXSTARTCONDITIONtCLCHtDXCXtCLDXSDAINPUTSDACHANGEtCHDHtDHDLSTOP &BUS FREEDATA VALIDtCLQV tCLQXDATA OUTPUTtCHDHSTOPCONDITIONtCHDXSTARTCONDITIONWRITE CYCLEtWAI00795BFigure 5. AC WaveformsWrite OperationsThe Multibyte Write mode (only available on the ST24/25C04 versions) is selected when the MODE pin is at V IH and the Page Write mode when MODE pin is at V IL. The MODE pin may be driven dynami-cally with CMOS input levels.Following a START condition the master sends a device select code with the RW bit reset to ’0’. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides ac-cess to one block of 256 bytes of the memory. After receipt of the byte address the device again re-sponds with an acknowledge.For the ST24/25W04 versions, any write command with WC = 1 will not modify the memory content. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independant of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either V IH or V IL, to minimize the stand-by current.7/16ST24/25C04, ST24/25W04SCL SDASCL SDASDASTARTCONDITIONSDAINPUTSDACHANGEAI00792STOPCONDITION 123789MSB ACKSTARTCONDITIONSCL123789MSB ACKSTOPCONDITION Figure 6. I2C Bus ProtocolMultibyte Write. For the Multibyte Write mode, the MODE pin must be at V IH. The Multibyte Write mode can be started from any address in the memory. The master sends from one up to 4 bytes of data, which are each acknowledged by the mem-ory. The transfer is terminated by the master gen-erating a STOP condition. The duration of the write cycle is t W = 10ms maximum except when bytes are accessed on 2 rows (that is have different values for the 6 most significant address bits A7-A2), the programming time is then doubled to a maximum of 20ms. Writing more than 4 bytes in the Multibyte Write mode may modify data bytes in an adjacent row (one row is 8 bytes long). However, the Multibyte Write can properly write up to 8 consecutive bytes as soon as the first address of these 8 bytes is the first address of the row, the 7 following bytes being written in the 7 following bytes of this same row.Page Write. For the Page Write mode, the MODE pin must be at V IL. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same ’row’in the memory: that is the 5 most significant mem-8/16ST24/25C04, ST24/25W04ory address bits (A7-A3) are the same inside one block. The master sends from one up to 8 bytes of data, which are each acknowledged by the mem-ory. After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory pro-gram cycle. All inputs are disabled until the comple-tion of this cycle and the memory will not respond to any request.Minimizing System Delays by Polling On ACK.During the internal write cycle, the memory discon-nects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (t W ) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re-duced by an ACK polling sequence issued by the master.WRITE Cycle in ProgressAI01099BNext Operation is Addressing the MemorySTART Condition DEVICE SELECT with RW = 0ACK ReturnedYESNOYESNOReSTARTSTOPProceedWRITE OperationProceedRandom Address READ OperationSend Byte AddressFirst byte of instruction with RW = 0 already decoded by ST24xxxFigure 8. Write Cycle Polling using ACKAI00855B1FFhb7b3b2XX100hBlock 1Block 0Protect Flag Enable = 0Disable = 18 byte boundary address Protect Location Figure 7. Memory Protection9/16ST24/25C04, ST24/25W04The sequence is as follows:–Initial condition: a Write is in progress (see Figure 8).–Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction).–Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will re-spond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1).Write Protection. Data in the upper block of 256bytes of the memory may be write protected. The memory is write protected between a boundary address and the top of memory (address 1FFh)when the PRE input pin is taken high and when the Protect Flag (bit b2 in location 1FFh) is set to ’0’.The boundary address is user defined by writing it in the Block Address Pointer. The Block Address Pointer is an 8 bit EEPROM register located at the address 1FFh. It is composed by 5 MSBs Address Pointer, which defines the bottom boundary ad-dress, and 3 LSBs which must be programmed atDEVICE OPERATION (cont’d)’0’. This Address Pointer can therefore address a boundary in steps of 8 bytes.The sequence to use the Write Protected feature is:–write the data to be protected into the top of the memory, up to, but not including, location 1FFh;–set the protection by writing the correct bottom boundary address in the Address Pointer (5MSBs of location 1FFh) with bit b2 (Protect flag)set to ’0’. Note that for a correct fonctionality of the memory, all the 3 LSBs of the Block Address Pointer must also be programmed at ’0’.The area will now be protected when the PRE input pin is taken High. While the PRE input pin is read at ’0’ by the memory, the location 1FFh can be used as a normal EEPROM byte.Caution: Special attention must be used when using the protect mode together with the Multibyte Write mode (MODE input pin High). If the Multibyte Write starts at the location right below the first byte of the Write Protected area, then the instruction will write over the first 3 bytes of the Write Protected area. The area protected is therefore smaller than the content defined in the location 1FFh, by 3 bytes.This does not apply to the Page Write mode as the address counter ’roll-over’ and thus cannot go above the 8 bytes lower boundary of the protected area.S T O PS T A R TBYTE WRITEDEV SELBYTE ADDR DATA INS T A R TMULTIBYTE ANDPAGE WRITEDEV SEL BYTE ADDR DATA IN 1DATA IN 2AI00793S T O PDATA IN NACKACKACKR/W ACKACKACKR/WACKACKFigure 9. Write Modes Sequence (ST24/25C04)10/16ST24/25C04, ST24/25W04S T O PS T A R TBYTE WRITEDEV SELBYTE ADDR DATA INWCS T A R TPAGE WRITEDEV SELBYTE ADDR DATA IN 1WCDATA IN 2AI01101BPAGE WRITE (cont'd)WC (cont'd)S T O PDATA IN NACKACKACKR/WACKACKACKR/WACKACKFigure 10. Write Modes Sequence with Write Control = 1 (ST24/25W04)Read OperationsRead operations are independent of the state of the MODE pin. On delivery, the memory content is set at all "1’s" (or FFh).Current Address Read. The memory has an inter-nal byte address counter. Each time a byte is read,this counter is incremented. For the Current Ad-dress Read mode, following a START condition,the master sends a memory address with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented.The master does NOT acknowledge the byte out-put, but terminates the transfer with a STOP con-dition.Random Address Read. A dummy write is per-formed to load the address into the address counter, see Figure 11. This is followed by another START condition from the master and the byte address is repeated with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed. The master have to NOT acknowledge the byte output, but terminates the transfer with a STOP condition.Sequential Read. This mode can be initiated with either a Current Address Read or a Random Ad-dress Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in se-quence. To terminate the stream of bytes, the master must NOT acknowledge the last byte out-11/16put, but MUST generate a STOP condition. The output data is from consecutive byte addresses,with the internal byte address counter automat-ically incremented after each byte output. After a count of the last memory address, the addresscounter will ’roll- over’ and the memory will continue to output data.Acknowledge in Read Mode. In all read modes the ST24/25x04 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25x04 terminate the data transfer and switches to a standby state.S T A R TDEV SEL *BYTE ADDRS T A R TDEV SELDATA OUT 1AI00794CDATA OUT NS T O PS T A R TCURRENT ADDRESS READDEV SELDATA OUTRANDOM ADDRESS READS T O PS T A R TDEV SEL *DATA OUTSEQUENTIAL CURRENT READS T O P DATA OUT NS T A R TDEV SEL *BYTE ADDR SEQUENTIAL RANDOM READS T A R TDEV SEL *DATA OUT 1S T O PACKR/WNO ACKACKR/WACKACK R/WACKACK ACK NO ACKR/WNO ACKACKACKR/WACK ACKR/WACK NO ACKFigure 11. Read Modes SequenceNote:*The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.DEVICE OPERATION (cont’d)12/16ORDERING INFORMATION SCHEMENotes: 3 * Temperature range on special request only.Parts are shipped with the memory content set at all "1’s" (FFh).For a list of available options (Operating Voltage, Range, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.Operating Voltage ST24C04 3V to 5.5V ST24W04 3V to 5.5V ST25C04 2.5V to 5.5V ST25W04 2.5V to 5.5VRangeStandardHardware Write Control StandardHardware Write ControlPackage B PSDIP80.25mm Frame MSO8 150mil WidthTemperature Range 10 to 70 °C 5–20 to 85 °C 6–40 to 85 °C 3 *–40 to 125 °COption TRTape & Reel PackingExample: ST24C04 M 1 TR13/16PSDIP-aA2A1A Le1DE1EN1CeA eBB1BSymbmm inches TypMin Max TypMin Max A 3.90 5.900.1540.232A10.49–0.019–A2 3.30 5.300.1300.209B 0.360.560.0140.022B1 1.15 1.650.0450.065C 0.200.360.0080.014D 9.209.900.3620.390E 7.62––0.300––E1 6.00 6.700.2360.264e1 2.54––0.100––eA 7.80–0.307–eB –10.00–0.394L 3.00 3.800.1180.150N88Drawing is not to scalePSDIP8 - 8 pin Plastic Skinny DIP , 0.25mm lead frame14/16SO-aENCPBe ADCLA1α1Hh x 45˚Symbmm inches TypMin Max TypMin Max A 1.35 1.750.0530.069A10.100.250.0040.010B 0.330.510.0130.020C 0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h 0.250.500.0100.020L 0.400.900.0160.035α0°8°0°8°N 88CP0.100.004Drawing is not to scaleSO8 - 8 lead Plastic Small Outline, 150 mils body width15/16Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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I2C之AT24C04总结
I2C之AT24C04总结济南职业学院电子工程系朱志强1、AT24C04介绍2、AT24C04之准备工作3、AT24C04之小试牛刀4、对应源程序2010年7月28日1、AT24C04介绍关于I2C的介绍，这里就不用说了，直接介绍24C04了。
24C04是4K位串行CMOS E2PROM。
引脚的认识：SCL 串行时钟引脚SDA 串行数据/地址A0、A1、A2 器件地址输入端WP 写保护（WP 管脚连接到Vcc，所有的内容都被写保护（只能读）。
当WP 管脚连接到Vss 或悬空，允许器件进行正常的读/写操作。
）2、AT24C04之准备工作首先，我们先查看一下实验板上面的接线图。
如图1所示。
图1 24c04连接图我们要注意的第一点是器件地址全部是0，即接地处理。
第二点是读写保护WP接地，意味着我们可以随意存取。
第三点是我们要用到的引脚连接到了P3^6和P3^7上。
在这里还要提醒一下，就是引脚上一定要有上拉电阻！阻值在470~1k 都可以的，具体的数值可以参考相关的手册。
在程序里我们需要先做以下定义：sbit AT24C04_SCL=P3^7;sbit AT24C04_SDA=P3^6;在写这个程序的时候，要使用到键盘，不用太多按键，我们暂时只用四个。
把实验板上面的跳线JP8接到“-”端上，使第一行的按键变为独立键盘就可以了。
线路图如图2所示。
图2 键盘部分电路图键盘这部分我就不说了吧，直接附上我用到的这部分程序，在我的程序中，并没有判断按键是否松开，而是使用的延时，这样的好处是一直按着按键，数据会一直在变化，要不然，频繁的按真的很累人。
转到按键程序对于里面用到的延时函数，一个是US级延时函数，一个是ms级延时函数，分别调用一下是延时2us和1ms。
对于显示部分吧，使用的就是LCD1602显示了。
这部分程序参见这里。
显示程序说完了这些，准备的就差不多了，我们可以对着PDF写AT24C04程序了。
3、AT24C04之小试牛刀我们打破PDF中的介绍顺序，按照实际写程序时的顺序分开分析。
I2C之AT24C04总结
I2C之AT24C04总结济南职业学院电子工程系朱志强1、AT24C04介绍2、AT24C04之准备工作3、AT24C04之小试牛刀4、对应源程序2010年7月28日1、AT24C04介绍关于I2C的介绍，这里就不用说了，直接介绍24C04了。
24C04是4K位串行CMOS E2PROM。
引脚的认识：SCL 串行时钟引脚SDA 串行数据/地址A0、A1、A2 器件地址输入端WP 写保护（WP 管脚连接到Vcc，所有的内容都被写保护（只能读）。
当WP 管脚连接到Vss 或悬空，允许器件进行正常的读/写操作。
）2、AT24C04之准备工作首先，我们先查看一下实验板上面的接线图。
如图1所示。
图1 24c04连接图我们要注意的第一点是器件地址全部是0，即接地处理。
第二点是读写保护WP接地，意味着我们可以随意存取。
第三点是我们要用到的引脚连接到了P3^6和P3^7上。
在这里还要提醒一下，就是引脚上一定要有上拉电阻！阻值在470~1k 都可以的，具体的数值可以参考相关的手册。
在程序里我们需要先做以下定义：sbit AT24C04_SCL=P3^7;sbit AT24C04_SDA=P3^6;在写这个程序的时候，要使用到键盘，不用太多按键，我们暂时只用四个。
把实验板上面的跳线JP8接到“-”端上，使第一行的按键变为独立键盘就可以了。
线路图如图2所示。
图2 键盘部分电路图键盘这部分我就不说了吧，直接附上我用到的这部分程序，在我的程序中，并没有判断按键是否松开，而是使用的延时，这样的好处是一直按着按键，数据会一直在变化，要不然，频繁的按真的很累人。
转到按键程序对于里面用到的延时函数，一个是US级延时函数，一个是ms级延时函数，分别调用一下是延时2us和1ms。
对于显示部分吧，使用的就是LCD1602显示了。
这部分程序参见这里。
显示程序说完了这些，准备的就差不多了，我们可以对着PDF写AT24C04程序了。
3、AT24C04之小试牛刀我们打破PDF中的介绍顺序，按照实际写程序时的顺序分开分析。
单片机学习项目 (11) I2C总线器件AT24C04及其应用
单片机学习项目项目11-I2C总线器件AT24C04及其应用一：电路原理电路在LED流水灯电路基础上设计，单片机的P2.6连接AT24C04的SDA端口，P3.7连接SCL，为保证数据传输正确，端口接上拉电阻。
电路见5-8所示。
二：程序设计主程序调用AT24C04子程序，在程序运行之前，需对AT24C04初始化。
程序清单如下：/*预处理*/#include<reg51.h>#include”AT24C04.c” //主程序包含AT24C04子程序/*延时函数*/void delay(unsigned int x){while(x--);}/*主函数*/void main(void){init_24c04();while(1){write_add_dat_24c04(1,0x0f); //地址1保存数据0x0fdelay(300);write_add_dat_24c04(2,0xf0); //地址2保存数据0xf0delay(300);P0 = read_add_dat_24c04(1); //读地址1保存数据0x0f，并在P0口显示 delay(50000);P0 = read_add_dat_24c04(2); //读地址2保存数据0xf0，并在P0口显示 delay(50000);}}/*结束*/三、24C04驱动#include<intrins.h>#define uchar unsigned char#define nop _nop_()sbit sda = P1^7;sbit scl = P1^1;/*I2C总线启动*/void start_24c04(void){sda = 1;nop;scl = 1;nop;sda = 0;nop;scl = 0;}/*I2C总线停止*/void stop_24c04(void){sda = 0;nop;scl = 1;nop;sda = 1;nop;}/*应答程序*/void ack_24c04(void){uchar i = 255;scl = 1;nop;while(sda && i--);scl = 0;nop;}/*I2C总线初始化*/void init_24c04(void)//该函数可以省去{sda = 1;nop;//常态scl = 0;nop;//常态}/*读取一个字节*/uchar read_onebyte_24c04(void){uchar i,dat;sda = 1; // 释放总线for(i = 0;i < 8;i++){scl = 1;dat = dat << 1;if(sda)dat = dat | 0x01;//先读取数据的高位，放到dat的低位 scl = 0;}sda = 1;scl = 0;return(dat);}/*写入一个字节*/void write_onebyte_24c04(uchar dat){uchar i;for(i = 0;i < 8;i++){sda = (bit)(dat & 0x80);//先发送数据的高位dat = dat << 1;scl = 1;scl = 0;}sda = 1;scl = 0;}/*对某个地址写一个字节的数据*/void write_add_dat_24c04(uchar add,uchar dat){start_24c04();write_onebyte_24c04(0xa0);ack_24c04();write_onebyte_24c04(add);ack_24c04();write_onebyte_24c04(dat);ack_24c04();stop_24c04();}/*读取某个地址一个字节的数据*/uchar read_add_dat_24c04(uchar add){uchar dat;start_24c04();write_onebyte_24c04(0xa0);ack_24c04();write_onebyte_24c04(add);ack_24c04();start_24c04();write_onebyte_24c04(0xa1);ack_24c04();dat = read_onebyte_24c04();stop_24c04();return(dat);}/*结束*/四、仿真运行本例程序Proteus仿真结果见图5-9所示，图中LED连接采用网络标号。
AT24Cxx中文数据手册
AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位，以及由每8位组成一个字节的可编程只读存储器（EEPROM），其分别提供128/256/512/1024/2048个字节。
该设备适用在许多低功耗和低电压操作的工业和商业应用中。
1引脚描述1.1串行时钟(SCL)SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。
1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。
该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或。
1.3设备/页地址(A2,A1,A0)对于AT24C01A和AT24C02，A2、A1和A0引脚是配置器件的硬件地址输入。
一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）。
AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。
A0引脚没有连接。
AT24C08A只使用A2引脚作为硬件地址输入，在一根总线上有2个8K 的设备可用来寻址。
A0和A1引脚没有连接。
AT24C16A不使用设备地址引脚，这限制了一根总线上只能挂一个设备。
A0、A1和A2引脚没有连接。
1.4写保护(WP)AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。
写保护引脚允许正常读/写操作时连接到GND。
当写保护引脚连接到VCC，写保护功能启用和操作如下表所示。
2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高。
SDA引脚上的数据只能在SCL低时间段内更改，而启动条件或停止条件在SCL为高时进行。
2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。
2.3停止条件SDA由低变为高，且SCL为高。
在读取序列之后，执行停止命令后EEPROM进入备用电源模式。
2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。
EEPROM I2C操作说明知识讲解
E E P R O M I2C操作说明I2C协议2条双向串行线，一条数据线SDA，一条时钟线SCL。
SDA传输数据是大端传输，每次传输8bit，即一字节。
支持多主控(multimastering)，任何时间点只能有一个主控。
总线上每个设备都有自己的一个addr，共7个bit，广播地址全0.系统中可能有多个同种芯片，为此addr分为固定部分和可编程部份，细节视芯片而定，看datasheet。
1.1 I2C位传输数据传输：SCL为高电平时，SDA线若保持稳定，那么SDA上是在传输数据bit；若SDA发生跳变，则用来表示一个会话的开始或结束（后面讲）数据改变：SCL为低电平时，SDA线才能改变传输的bit1.2 I2C开始和结束信号开始信号：SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据。
结束信号：SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据。
1.3 I2C应答信号Master每发送完8bit数据后等待Slave的ACK。
即在第9个clock，若从IC发ACK，SDA会被拉低。
若没有ACK，SDA会被置高，这会引起Master发生RESTART或STOP流程，如下所示：1.4 I2C写流程写寄存器的标准流程为：1. Master发起START2. Master发送I2C addr（7bit）和w操作0（1bit），等待ACK3. Slave发送ACK4. Master发送reg addr（8bit），等待ACK5. Slave发送ACK6. Master发送data（8bit），即要写入寄存器中的数据，等待ACK7. Slave发送ACK8. 第6步和第7步可以重复多次，即顺序写多个寄存器9. Master发起STOP写一个寄存器写多个寄存器1.5 I2C读流程读寄存器的标准流程为：1. Master发送I2C addr（7bit）和w操作1（1bit），等待ACK2. Slave发送ACK3. Master发送reg addr（8bit），等待ACK4. Slave发送ACK5. Master发起START6. Master发送I2C addr（7bit）和r操作1（1bit），等待ACK7. Slave发送ACK8. Slave发送data（8bit），即寄存器里的值9. Master发送ACK10. 第8步和第9步可以重复多次，即顺序读多个寄存器读一个寄存器读多个寄存器1.前言对于大多数工程师而言，I2C永远是一个头疼的问题。
HC24C04数据手册_v0.01
此时器件进入内部定时的写周期（非易失性寄存器的写时间），TWR。所有的输入操作在该 写周期内均无效，而且只有在写周期结束后，器件才会对操作指令做出应答。（参见图 7）
图7 SCL：串行时钟输入，DSA：串行数据输入/输出
注：写周期TWR是指一个写序列最后一个有效停止命令到内部擦/写周期结束的时间。
一旦时钟将读/写位为高的器件地址送入，并得到器件应答后，就会串行输出当前地址的数 据。主控器件不对器件返回应答信号，而是产生一个紧随的停止命令。（参见图9）
图9 当前地址读
自由地址读：自由读需要通过假的字节写操作来获得数据地址。一旦器件地址和数据地址 字节被时钟送入并得到器件的应答后，主控器件必须产生另一个起始命令。主控器件通过发送 一个读/写选择位为高的器件地址来开启一次当前地址读。器件对器件地址做出应答后由时钟串 行输出数据。主控器件不对数据传输返回应答信号，而是产生一个紧随的停止命令。（参见图 10）
单位
kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Write Cycles
图 1 总线时序
-6-
HC24C04
器件操作
时钟及数据传输：SDA 引脚通常被外围器件拉高。SDA 引脚的数据应在 SCL 为低时变化（参 见图 2）；当数据在 SCL 为高时变化，将视为下文所述的一个起始或停止命令。
0.4
1.0
mA
2.0
3.0
mA
—
1.0
μA
—
3.0
μA
0.05
3.0
μA
—
VCC×0.3 V
— VCC＋0.3 V
—
0.4
V
AT24C04在电子设计中的作用
AT24C04在电子设计中的作用【摘要】本文介绍了EEPROM器件AT24C04的基本使用方式，通过51单片机与AT24C04建立I2C串行通信方式，实现AT24C04的读、写操作。
以AT24C04为例，详细说明了EERPOM 在电子设计中的实际应用价值。
【关键词】EEPROM；I2C通信；单片机控制；掉电存储1前言EEPROM，即电可擦可编程只读存储器，是一种掉电后数据不丢失的存储器件。
它常用于存放硬件设置数据和保存记录设备数据，防止掉电后数据丢失。
本文介绍了AT24C04，作为一种串行总线存储器，它具有体积小、引脚少、功耗低等特点，是EEPROM器件在电子设计中的应用价值体现。
2AT24C04的基本介绍AT24C04是Atmel公司的一款I2C串行EEPROM，其工作电压范围宽，VCC工作在1.7-5.5伏，兼容51单片机的TTL电平。
芯片引脚分布图如图2-1所示：A1、A2为芯片的引脚地址，SCL和SDA为I2C总线接口的串行时钟线与数据线。
WP为写保护引脚，当芯片写保护时，WP为高电平，智能对器读操作，不能改写内部数据，从而起到硬件保护作用，当WP为低电平时，才能实现对器件的写操作。
芯片引脚少，外围电路简单，减少了布局布线空间。
3AT24C04的控制过程使用STC89C51单片机实现对AT24C04的控制，实质是建立单片机与EEPROM芯片的I2C通信。
相比RS232和SPI通信而言，I2C的时序要复杂一些。
SCL与SDA的建立关系是，在SCL高电平时，SDA数据保持，在SCL低电平时，SDA数据变化。
AT24C04的操作可分为写单字节，写多字节，读单字节和读多个存储字节。
以写单一字节为例，起始信号完成后输入器件地址和读写状态。
“1”表示读操作，“0”表示写操作。
等待从设备（AT24C04）的应答信号。
接收到应答信号后主设备（单片机）向从设备（AT24C04）发送所写地址（8位），等待应答信号，写入地址对应数据（8位），等待应答信号，以停止信号终止本次写操作。
24c04a中文介绍
24c04a资料一、概述1.1 特征•低功率CMOS技术•硬件写保护* 两线串行接口总线，与I2CTM兼容•5V电源条件下，系统正常工作•自定时写周期（包括自动擦除）•自定时写周期（包含自动擦除）•16个字节的页面写缓冲器•1,000,000擦/写周期（典型值）•8脚DIP/SOIC封装•提供很宽的温度适用范围商用：0℃~+70℃工业用：-40℃~+85℃汽车：-40℃~+125℃2.1描述Microchip公司的24c04a是4K位可擦除PROM。
芯片由2个或4个256*8位存储器块构成，并具有标准的两线串行接口。
可在电源电压低到2.5V的条件下工作，等待电流和额定电流分别仅为5uA和1mA。
24c04a具有8B页面写能力。
的24c04a已经一4页写能力高到八字节，和了到四24c04a设备也许连接到相同的两线总线。
2.2 引脚排列引脚说明1.SDA串行地址/数据输入/输出端这是一个双向传输端，用于传送地址和数据进入器件或从器件发出数据。
它是一个漏极开路端，因此要求接一个上拉电阻到Vcc端（典型值如下：100kHz时为10KΩ，400kHz 时为1KΩ）这对一般的数据传输，只有在SCL为低电平期间，SDA才允许变化。
在SCL为高电平期间SDA的变化，留给指示开始和停止条件。
2. SCL串行时钟端次输入端用于同步传输进入和发出器件的数据3. WP端此端必须接到Vss或者Vcc如果此端接到Vss，一般存储器操作使能（读/写整个存储器）如果此端接到Vcc，写操作禁止。
整个存储器是写保护的。
读操作不受到影响。
当WP被使能（连接到Vcc），允许用户可将24c04a用作串行ROM4.A0、A1、A2端这些端没有被24c04a使用。
它们可以不用连接，或者连接到Vss、Vcc2.3电子特性Vcc——————————————————7.0V输入和输出关于VSS———-0.6V ~ VCC + 1.0V存储温度———————————-65℃~ + 150℃使用环境温度—————————-65℃~ +1 25℃焊接口通导温度————————————+300℃引脚的ESD保护————————————4kV 名称功能A0A1、A2 Vss SDA SCL WP Vcc 不工作（必须与Vcc、Vss连接）芯片地址输入接地串行地址/数据I\O串行时钟写保护输入端+5V电源端三、功能说明24c04a支持双向两线总线和数据传输规程。
(完整word版)AT24Cxx中文数据手册
AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位,以及由每8位组成一个字节的可编程只读存储器（EEPROM）,其分别提供128/256/512/1024/2048个字节.该设备适用在许多低功耗和低电压操作的工业和商业应用中。
1引脚描述1.1串行时钟（SCL）SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。
1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。
该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或.1.3设备/页地址（A2,A1，A0）对于AT24C01A和AT24C02,A2、A1和A0引脚是配置器件的硬件地址输入。
一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）.AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。
A0引脚没有连接。
AT24C08A只使用A2引脚作为硬件地址输入,在一根总线上有2个8K 的设备可用来寻址.A0和A1引脚没有连接。
AT24C16A不使用设备地址引脚,这限制了一根总线上只能挂一个设备。
A0、A1和A2引脚没有连接。
1.4写保护(WP）AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。
写保护引脚允许正常读/写操作时连接到GND。
当写保护引脚连接到VCC,写保护功能启用和操作如下表所示.2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高.SDA引脚上的数据只能在SCL低时间段内更改,而启动条件或停止条件在SCL 为高时进行。
2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。
2.3停止条件SDA由低变为高，且SCL为高。
在读取序列之后,执行停止命令后EEPROM进入备用电源模式.2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。
AT24C04中文资料
Maplead MCU Development Board24. AT24C04 芯片的 I2C 总线读写4K（512×8）AT24C04 E2PEOMAT24C04 是 ATMEL 公司生产的 4K bit（512Bytes）E2PROM 芯片，该芯片 采用 I2C 总线设计，主要性能指标与 AT24C02 类似，不同点为： 容量为 AT24C02 的两倍，分为两部分存储空间，每部分 256bytes。
有 2 个器件地址选择脚，一个 I2C 总线最多能够挂接 4 个 AT24C04 器件。
32 页，每页 16 字节，每次可连续写入 16 字节数据。
WP 引脚为高电平时，AT24C04 的 0~255 地址空间的数据被写保护。
需要 9 位的地址进行数据寻址。
AT24C04 的引脚定义图 24-1 AT24C02 引脚定义 表 24-1 AT24C02 引脚定义引脚定义 1. A0 2. A1,A2 3. GND 4. SDA 5. SCL 6. WP 7. VCC 空引脚。
器件地址设定引脚。
电源地。
数据口。
同步时钟口。
写保护口。
电源。
说明A0 为空引脚，A1,A2 口为器件地址设定口，通过 A1,A2 口来设定 AT24C04 的器件地址 WP 口接低电平时，可以对整个 AT24C04 器件的 512 个字节进行读写操作。
当 WP 口接高电平后，器件前 256 个地址的数据被保护，只能读，不可写入，后 256 个字节数据可进行读写操作。
172Maplead MCU Development BoardAT24C04 的从器件寻址图 24-2 AT24C04 的器件及数据空间地址 AT24C04 的器件地址由两个引脚决定，分别为 A1,A2 引脚。
AT24C04 的数据空间由 P0 位决定，如图 24-2 所示，当 P0 为“0”时，将对 AT24C04 的 0~255 空间的数据进行操作；当当 P0 为“1”时，将对 AT24C04 的 256~511 空间的数据进行操作。
C51读写AT24C04(源代码)
C51读写AT24C04（源代码）/*=============================================*//*;***********************************//*;起动24C01时序*/void Start(){SCL=1;SDA=1;SDA=0;SCL=0;}/*;************************************//*;停止24C01时序*/void Stop(){SDA=0;SCL=1;SDA=1;}/*;**************************************//*;检测24C01的响应信号*/bit ACK(){bit c;SDA=1;SCL=1;c=SDA;SCL=0;return c;}/*;************************************/ /*;往24C01发一8位数据*/void SendChar(unsigned char ch){unsigned char i;i=8;do{SDA=(ch&0x80);SCL=1;SCL=0;ch<<=1;}while(--i!=0);}/*;**************************************/ /*;从24C01接收一8位数据*/unsigned char RecChar(){unsigned char i,j;i=8;do{SCL=1;j=(j<<1)|SDA;SCL=0;}while(--i!=0);return j;}//;**************************************/*;********************************//*;往24C01写一字节*/void WriteChar(unsigned int addr,unsigned char ch) {unsigned char c;c=((*((unsigned char *)&addr))<<1)&0x02;Start();SendChar(0xa0|c);ACK();SendChar(addr);ACK();SendChar(ch);ACK();Stop();// for(addr=4;addr!=0;addr--)for(ch=0xff;ch!=0;ch--) ;}//;**************************************/*;********************************//*;往24C01写多字节*/void WriteBuf(unsigned int addr,unsigned char idata *buf,unsigned char count) {unsigned char c;c=((*((unsigned char *)&addr))<<1)&0x02;Start();SendChar(0xa0|c);ACK();SendChar(addr);ACK();do{SendChar(*buf++);ACK();if(count!=1){if(((++addr)&0x7)==0){Stop();for(c=0xff;c!=0;c--) ;c=((*((unsigned char *)&addr))<<1)&0x02;Start();SendChar(0xa0|c);ACK();SendChar(addr);ACK();}}else{Stop();for(c=0xff;c!=0;c--) ;}}while(--count!=0);}/*;**********************************//*;从24C01读一字节*//*;入口:R0中为要读出内容的地址*//*;出口:A中为读到的内容*/unsigned char ReadChar(unsigned int addr) {unsigned char ch;ch=((*((unsigned char *)&addr))<<1)&0x02;Start();SendChar(0xa0|ch);ACK();SendChar(addr);ACK();Start();SendChar(0xa1|ch);ACK();ch=RecChar();Stop();return ch;}/**********************************//*至少读2字节*/void ReadBuf(unsigned int addr,unsigned char idata *buf,unsigned char count) {unsigned char ch;ch=((*((unsigned char *)&addr))<<1)&0x02;Start();SendChar(0xa0|ch);ACK();SendChar(addr);ACK();Start();SendChar(0xa1|ch);ACK();count--;do{*buf++=RecChar();SDA=0;SCL=1;SCL=0;SDA=1;}while(--count!=0); *buf=RecChar();Stop();}。
AT24C1024 中文说明书
AT24C10242线串行EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8位=1M2线串行接口施密特触发器，噪声抑制滤波输入双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V)硬件写保护引脚和软件数据保护256字节页写模式(允许部分页面写入)随机和顺序读写模式自定义写周期(5ms)高可靠性：耐久力：写周期/页100,000次数据保留：40年8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装描述AT24C1024提供1,048,567位的串行可电擦除和可编程只读存储器（EEPROM），它的每8位组成一个字节，共131,072个字节。
该设备的级联功能允许多达2个设备共亨同一条2-线总线。
该设备适合用于许多工业和商业，应用必要的低功耗和低电压的操作。
该器件可提供节省空间的8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装。
另外，这一系列产品允许在2.7V（2.7V~5.5V）下工作。
绝对最大额定值：工作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最大工作电压：6.25V直流输出电流：5.0mA注意：强制高出“绝对最大额定值”可能导致设备的永久损坏。
设备的压力等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间工作在绝对最大额定值的条件下可能影响设备的可靠性。
引脚描述：：引脚描述串行时钟（SCL）：SCL的输入是在时钟的上升沿数据进入每个EEPROM设备和下降沿数据输出每个设备。
串行数据（SDA）：SDA引脚是双向串行数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/页地址（A1）：A1引脚是设备的输入地址，它能够通过导线与不兼容的设备AT24C128/256/512连接。
当A1通过硬件连接时，2个以上的1024K设备可以在同一条系统总路线上寻址（下面会详细谈论设备的地址选择）。
常用EEPROM存储器
常用EEPROM存储器电路EEPROM存储器AT24C01低压和标准电压工作(Vcc=1.8V—5.5V)，128x8（1k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。
Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。
，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。
8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP等四种封装形式。
AT24C01数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C02低压和标准电压工作(Vcc=1.8V—5.5V)，256x8（2k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。
Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。
，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。
8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP 等四种封装形式。
AT24C02数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C04低压和标准电压工作(Vcc=1.8V—5.5V)，512x8（4k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。
Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。
，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。
8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP 等四种封装形式。
AT24C04数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C08低压和标准电压工作(Vcc=1.8V—5.5V)，1024x8（8k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。
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1Features•Medium-voltage and Standard-voltage Operation –5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•100 kHz (2.7V) and 400 kHz (5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes are Allowed •Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•8-lead PDIP and 8-lead JEDEC SOIC PackagesDescriptionThe AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-trically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential.The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NCNo Connect2AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.Absolute Maximum RatingsOperating Temperature ......................................−55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature .........................................−65°C to +150°C Voltage on Any Pinwith Respect to Ground ........................................−1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08/163256F–SEEPR–10/04The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.The AT24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects.WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown see Table 2.Table 2. Write ProtectNotes:1.This device is not recommended for new designs. Please refer to A T24C08A.2.This device is not recommended for new designs. Please refer to A T24C16A.Memory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,the 8K requires a 10-bit data word address for random word addressing.AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin StatusPart of the Array Protected24C01A 24C0224C0424C08(1)24C16(2)At V CCFull (1K) ArrayFull (2K) ArrayFull (4K) ArrayNormal Read/Write OperationUpper Half (8K) ArrayAt GND Normal Read/Write Operations4AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This parameter is characterized and is not 100% tested.Notes:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T A = −40°C to +125°C, V CC = +2.7V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 2.7 5.5V V CC2Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB2Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)−0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08/163256F–SEEPR–10/04Notes:1.The A T24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on thetopside of the package), guarantees 400 kHz (2.5V , 2.7V).2.This parameter is characterized and is not 100% tested (T A = 25°C).3.This parameter is characterized and is not 100% tested.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 7).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.Table 5. AC CharacteristicsApplicable over recommended operating range from T A = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).Symbol ParameterAT24C01A/02/04/08,2.7VAT24C16, 2.7V AT24C01A/02/04/08/16,5.0V Units Min Max MinMax MinMax f SCL Clock Frequency, SCL 400(1)400400kHz t LOW Clock Pulse Width Low 1.2 1.2 1.2µs t HIGH Clock Pulse Width High 0.60.60.6µst I Noise Suppression Time (2)505050ns t AA Clock Low to Data Out Valid 0.10.90.10.90.10.9µs t BUF Time the bus must be free before a new transmission can start (3) 1.2 1.2 1.2µs t HD.STA Start Hold Time 0.60.60.6µs t SU.STA Start Set-up Time 0.60.60.6µs t HD.DAT Data In Hold Time 000µs t SU.DA T Data In Set-up Time 100100100nst R Inputs Rise Time (3)300300300ns t F Inputs Fall Time (3)300300300ns t SU.STO Stop Set-up Time 0.60.60.6µs t DH Data Out Hold Time 505050nst WRWrite Cycle Time 555ms Endurance5.0V , 25°C1M1M1MWrite Cycles6AT24C01A/02/04/08/163256F–SEEPR–10/04STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.7AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 4. Data ValidityFigure 5. Start and Stop DefinitionFigure 6.Output Acknowledge8AT24C01A/02/04/08/163256F–SEEPR–10/04Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7on page 9).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-9AT24C01A/02/04/08/163256F–SEEPR–10/04ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 10).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 11).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condi-tion (see Figure 12 on page 11).Figure 7.Device Address10AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)Figure 10.Current Address Read11AT24C01A/02/04/08/163256F–SEEPR–10/04Figure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read12AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C01A Ordering InformationOrdering Code Package Operation Range A T24C01A-10P A-5.0C A T24C01A-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C01A-10P A-2.7C A T24C01A-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)13AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C02 Ordering InformationOrdering Code Package Operation Range A T24C02-10P A-5.0C A T24C02N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C02-10P A-2.7C A T24C02N-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)14AT24C01A/02/04/08/163256F–SEEPR–10/04AT24C04 Ordering InformationOrdering Code Package Operation Range A T24C04-10P A-5.0C A T24C04N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C04-10P A-2.7C A T24C04N-10SA-2.7C8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)15AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This device is not recommended for new designs. Please refer to A T24C08A.AT24C08(1) Ordering InformationOrdering Code Package Operation Range A T24C08-10P A-5.0C A T24C08N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C08-10P A-2.7C A T24C08N-10SA-2.7C 8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)16AT24C01A/02/04/08/163256F–SEEPR–10/04Note:1.This device is not recommended for new designs. Please refer to A T24C16A.AT24C16(1) Ordering InformationOrdering Code Package Operation Range A T24C16-10P A-5.0C A T24C16N-10SA-5.0C 8P38S1Automotive (−40°C to 125°C)A T24C16-10P A-2.7C A T24C16N-10SA-2.7C 8P38S1Automotive (−40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Options−5.0Standard Operation (4.5V to 5.5V)−2.7Low-voltage (2.7V to 5.5V)17AT24C01A/02/04/08/163256F–SEEPR–10/04Packaging Information8P3 – PDIP18AT24C01A/02/04/08/163256F–SEEPR–10/048S1 – JEDEC SOIC3256F–SEEPR–10/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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