Units specified don't exist, SHSUCDX can't install
Quartus II 报错
1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。
而时钟敏感信号是不能在时钟边沿变化的。
其后果为导致结果不正确。
措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋…0‟，便会被接地，赋…1‟接电源。
如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins ing as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。
三极管正压电源 CJ7805 数据手册说明书
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7.2
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INPUT VOLTAGE VIN (V)
Current Cut-off Grid Voltage
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0.043
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To-252(4R)-2L Tape and Reel
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FEATURES
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1 23
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0.000
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0.031
0.055
0.028
0.032
0.018
0.022
0.018
0.022
0.256
0.264
0.202
0.215
0.236
0.244
0.090 TYP.
0.170
0.186
0.070REF.
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0.386
HCC40108B
HCC40108B HCF40108BSeptembe r 19884x 4MULTIPORT REGISTEREY(Plastic Package)DESCRIPTIONORDER CODES :HCC40108BF HCF40108BM1HCF40108BEY HCF40108BC1F(Ceramic Package)M1(Micro Package)C1(Chip Carrier)PIN CONNECTIONSThe HCC40108B (extended temperature range)and HCF40108B (intermediate temperature range)are monolithic integrated circuits,available in 24lead dual in line plastic or ceramic packageand plas-tic micropackage.The HCC/HCF40108B is a 4X 4multiport register containing four 4-bit register,write address decoder,two separate read address decoder s,and two 3-state output buses.When the ENABLE input is low,the corresponding output bus is switched,independently of the clock,to a high im-pedance state.The high impedance third state pro-vides the outputs with the capability of being connected to the bus lines in a bus organized sys-tem without the need for interface or pull-up compo-nents.When the WRITE ENABLE input is high,all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines.When WRITE ENABLE is low,the CLOCK is inhibited and.FOUR 4-BIT REGISTERS.ONE INPUT AND TWO OUTPUT BUSES.UNLIMITED EXPANSION IN BIT AND WORD DIRECTION.DATA LINES HAVE LATCHED INPUTS .3-STATE OUTPUTS.SEPARATE CONTROL OF EACH BUS,ALLOWING SIMULTANEOUS INDEPENDET READING AND ANY OF FOUR REGISTERS ON BUS A AND BUS B AND INDEPENDENT WRITING INTO ANY ANY OF THE FOUR REG-ISTERS.40108B IS PIN COMPATIBLE WITH INDUSTRY TYPE MC14580.STANDARDIZED,SYMMETRICAL OUTPUT CHARACTERISTICS.QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE.5V,10V AND 15V PARAMETRIC RATINGS .INPUT CURRENTOF 100nA AT 18V AND 25oC FOR HCC DEVICE.100%TESTED FOR QUIESCENT CURRENT .MEETS ALL REQUIREMENTS OF JEDECTEN-TATIVE STANDARD No 13a,”STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES”no new data is netered.In either case,the contents of any word may be accessed via the read address lines indepe ndent of the state of the CLOCK input.1/14HCC/HCF40108 FUNCTIONAL DIAGRAMLOGIC DIAGRAM2/14ABSOLUTE MAXIMUM RATINGSymbol Parameter Value UnitV DD*Supply Voltage:HCC TypesHCF Types -0.5to+20-0.5to+18VVV i Input Voltage-0.5to V DD+0.5V I I DC Input Current(any one input)±10mAP tot Total Power Dissipation(per package)Dissipation per Output Transistorfor Top=Full Package Temperature Range 200100mWmWT op Operating Temperature:HCC TypesHCF Types -55to+125-40to+85o Co CT stg Storage Temperature-65to+150o C Stresses abov e those listedunder”Absolute Maximum Ratings”may cau se permanen t damage to thedevice.This is a stress ratingonly and functional opera tion of the device at thes e or any other cond itions above those indicated in the ope rational sections of this specification is not implied.Exposure to absolute maximum rating conditions for external periods may affect device reliability.*All voltage values are referred to V SS pin voltage.RECOMMENDED OPERATING CONDITIONSSymbol Parameter Value UnitV DD Supply Voltage:HCC TypesHCF Types 3to183to15VVV I Input Voltage0to V DD VT op Operating Temperature:HCC TypesHCF Types -55to+125-40to+85o Co CTRUTH TABLECLOCKWriteEnableWrite1Write2Read1ARead0ARead1BRead0BEnableAEnableBD n Q nA Q nB1S1S2S1S2S1S211111 1S1S2S1S2S1S210000X X X X X X X X0X Z Z Z100011011D n toword0Word1OutWord2Out000011011Word0notalteredWord1OutWord2OutX X X X10011X X Word2OutWord1OutX X X X X X X11X NC NC1=HIGH LEVEL,0=LOW LEVEL,X=DON’T CARE,Z=HIGH IMPEDANCES1and S2refer to input strates of either1or0HCC/HCF401083/14HCC/HCF40108 SCHEMATIC DIAGRAM4/14STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)Symbol Parameter Test ConditiosValue UnitV I(V)V O (V)|I O |(µA)V DD (V)T LOW *25o C T HIGH *Min.Max.Min.Typ.Max.Min.Max.I LQuiescent CurrentHCC Types0/5550.045150µA0/1010100.04103000/1515200.04206000/20201000.081003000HCFTypes 0/55200.04201500/1010400.04403000/1515800.0480600V OHOutput High Voltage 0/5<15 4.95 4.95 4.95V0/10<1109.959.959.950/15<11514.9514.9514.95V OLOutput Low Voltage 5/0<150.050.050.05V10/0<1100.050.050.0515/0<1150.050.050.05V IHInput High Voltage 0.5/4.5<15 3.5 3.53.5V1/9<1107771.5/13.5<115111111V ILInput Low Voltage 4.5/0.5<15 1.5 1.5 1.5V9/1<11033313.5/1.5<115444I OHOutput Drive CurrentHCC Types0/5 2.55-2-1.6-3.2-1.15mA0/5 4.65-0.64-0.51-1-0.360/109.510-1.6-1.3-2.6-0.90/1513.515-4.2-3.4-6.8-2.4HCF Types0/5 2.55-1.53-1.36-3.2-1.10/5 4.65-0.52-0.44-1-0.360/109.510-1.3-1.1-2.6-0.90/1513.515-3.6-3.0-6.8-2.4I OLOutput Sink CurrentHCC Types 0/50.450.640.5110.36mA0/100.510 1.6 1.3 2.60.90/15 1.515 4.2 3.4 6.8 2.4HCF Types0/50.450.520.4410.360/100.510 1.3 1.1 2.60.90/151.515 3.63.06.8 2.4I IH ,I ILInput Leakage Current HCCTypes 0/18Any Input18±0.1±10-5±0.1±1µAHCFTypes 0/1515±0.3±10-5±0.3±1I OH ,I OL**3-Sate Output Leakage CurrentHCCTypes 0/180/1818±0.4±10-4±0.4±12µAHCFTypes0/150/1515±1.0±10-4±1.0±7.5C I Input CapacitanceAny Input57.5pF*T LOW =-55oC for HCC device:-40oC for HCF device.*T HIGH =+125o C for HCC device:+85o C for HCF device.The Noise Margin for both ”1”and ”0”level is:1V min.with V DD =5V,2V min.with V DD =10V,2.5V min.withV DD =15V **Forced output disableHCC/HCF401085/14DYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25o C,C L =50pF,R L =200K Ω,typical temperature coefficent for all V DD values is 03%/oC,all input rise and fall times=20ns)Symbol ParameterTest ConditionsValue UnitV DD (V)Min.Typ.Max.t PLH t PHLPropagation Delay Time Clock or Write Enable to Q 5360720ns1014028015100200Propagation Delay Time Read or Write Address to Q5300600101202401585170t PZH t PHZ 3-State Disable Delay Time5100200ns1050100154080t PZL t PLZ 3-State Display Delay Time5130260ns10601201550100t TLH t THL Output Transition Time5100200ns1050100154080t setupSetup TimeData to Clock t s(D)50-95ns100-35150-20Setup TimeWrite Enable to Clock t s(WE)52501251010050157035Setup TimeWrite Address to Clock t s(WA)52501251010050157035t r ,t s Clock Rise and Fall Time515µs105155t holdHold TimeData to Clock t s(D)5220110ns1010050158040Hold TimeWrite Enable to Clock t s(WE)52701351013065158040Hold TimeWrite Address to Clock t s(WA)53301651014070159045t WClock Pulse WidthClock or Write Enable t W(CL)5350175ns1013065159045Clock Pulse Width Write Address t W(WA)53001501015075159045f CL Maximum Clock Input Frequency5 1.53MHz10 3.57154.59HCC/HCF401086/14Output Low(sink)Current Characteristics Typical Propagation Delay Time vs Load Capa-citance(CL or WE to Q)Typical Dynamic Power Dissipation vs Input Fre-quency Output High(source)Current Characteristics Typical Transition Time vs Load CapacitanceHCC/HCF401087/14HCC/HCF40108TIMING DIAGRAMTEST CIRCUITSOutput Enable Delay Times and Waveforms 8/14HCC/HCF40108 Power Dissipation and WaveformsQuiescent Device Current.Noise Immunity.Input Leakage Current.9/14HCC/HCF40108Plastic DIP24(0.25)MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.a10.630.025b0.450.018b10.230.310.0090.012 b2 1.270.050D32.2 1.268 E15.216.680.5980.657e 2.540.100e327.94 1.100F14.10.555I 4.4450.175L 3.30.130P043A 10/14Ceramic DIP24MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX. A32.3 1.272 B13.0513.360.5140.526 C 3.9 5.080.1540.200 D30.118E0.5 1.780.0200.070 e327.94 1.100F 2.29 2.790.0900.110 G0.40.550.0160.022 I 1.17 1.520.0460.060 L0.220.310.0090.012 M 1.52 2.490.0600.098 N14°(min.),15°(max.)P15.415.80.6060.622 Q 5.710.225P058CSO24MECHANICAL DATADIM.mm inch MIN.TYP.MAX.MIN.TYP.MAX.A 2.650.104a10.100.200.0040.007a2 2.450.096b 0.350.490.0130.019b10.230.320.0090.012C 0.500.020c145°(typ.)D 15.2015.600.5980.614E 10.0010.650.3930.420e 1.270.05e313.970.55F 7.407.600.2910.299L 0.50 1.270.190.050S8°(max.)FCLEa 1b 1Ae De3b 2413112c1sa 2PLCC20MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX. A9.7810.030.3850.395 B8.899.040.3500.356 D 4.2 4.570.1650.180 d1 2.540.100d20.560.022E7.378.380.2900.330 e 1.270.050e3 5.080.200F0.380.015G0.1010.004 M 1.270.050M1 1.140.045P027AInformation furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.©1994SGS-THOMSON Microelectronics-All Rights ReservedSGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia-Brazil-France-Germany-Hong Kong-Italy-Japan-Korea-Malaysia-Malta-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A。
Quartus常见错误警告分析
Quartus常见错误警告分析Quartus常见错误分析ErrorWarning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode outcannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"-------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s)analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as bufferInfo: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holdsits previous in every path with no new assignment, whichmay create a combinational loop in the currentdesign.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuckGND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" withclock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" withclock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated withformal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name"class_sig[2]" indesign.------没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component ---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does nothold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source filenode.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binaryoperator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。
VMware常见问题及解决办法
VMware常见问题及解决办法Ø简介本⽂介绍使⽤ VMware 虚拟机时常见的问题及解决办法，主要包括：1.虚拟机操作系统装好后，每次进⼊虚拟机还进⼊安装程序2.虚拟机不能与主机复制粘帖3.解决错误："Output error file the following locafion:"4.解决错误："Units specified don't exist. shsucdx can't install"5.解决错误："NTLDR is missing Press Ctrl+Alt+Del to restart"6.解决错误："Operating System not found"7.解决虚拟机声⾳滋滋声（例如：Windows XP Professional 开机或关机声⾳）8.VMware Player 不可恢复错误: (vcpu-0) vcpu-0:VERIFY vmcore/vmm/main/cpuid.c:386 bugNr=10365219.VMware Workstation 与 Device/Credential Guard 不兼容...1.虚拟机操作系统装好后，每次进⼊虚拟机还进⼊安装程序解决办法：将"CD-ROM Drive"（光盘驱动器）改为"Hard Drive"（硬盘驱动器）改为2.虚拟机不能与主机复制粘帖解决办法：安装VMare Tools程序，并且选择“完整安装”3.解决错误："Output error file the following locafion:"（输出错误⽂件下⾯的定位：）A:\GHOSTERR.TXT，如图：解决办法：这是因为没有分区导致，返回安装界⾯选择如“PM分区⼯具”分区即可4.解决错误："Units specified don't exist. shsucdx can't install"（单位指定不存在。
ansys常见错误
ansys常见错误ansys分析出现问题NO.0052some contact elements overlap with the other contact element which can cause over constraint. 这是由于在同一实体上，即有绑定接触（MPC）的定义，又有刚性区或远场载荷（MPC）的定义，操作中注意在定义刚性区或远场载荷时避免选择不必要的DOF自由度，以消除过约束NO.0053Shape testing revealed that 450 of the 1500 new or modified elements violate shape warning limits.是什么原因造成的呢？单元网格质量不够好尽量，用规则化网格，或者再较为细密一点NO.0054在用Area Fillet对两空间曲面进行倒角时出现以下错误：Area 6 offset could not fully converge to offset distance 10. Maximum error between the two surfaces is 1% of offset distance.请问这是什么错误？怎么解决？其中一个是圆柱接管表面，一个是碟形封头表面。
ansys的布尔操作能力比较弱。
如果一定要在ansys里面做的话，那么你试试看先对线进行倒角，然后由倒角后的线形成倒角的面。
建议最好用UG、PRO/E这类软件生成实体模型然后导入到ansysNO.0055There are 21 small equation solver pivot terms.; SOLID45 wedges are recommended only in regions of relatively lowstress gradients.第一个问题我自己觉得是在建立contact时出现的错误，但自己还没有改正过来；第二个也不知道是什么原因。
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这个信息跟随在输入语句后面， 这个信息跟随在输入语句后面，该语句中元件 的节点数与规定不符。例如，程序对于MOSFET规 的节点数与规定不符。例如，程序对于 规 定为4个节点 除了将衬底与地连接的情况外， 个节点， 定为 个节点，除了将衬底与地连接的情况外，都要 定义第四个节点。 定义第四个节点。
互感的偶合系数超过了1.0，程序继续分析，自动 互感的偶合系数超过了 ，程序继续分析， 将系数设置为1.0。 将系数设置为 。
*ERROR*: ZO MUST BE SPECIFIED
传输线的阻抗特性值必须给出． 传输线的阻抗特性值必须给出．这是一个致命 错误。 错误。
*ERROR*: EITHER TD OR F MUST BE SPECIFIED
线性折线电源(PWL)的时间值系列必须是增长的。 的时间值系列必须是增长的。 线性折线电源 的时间值系列必须是增长的
§ 10. 3. 4 元器件模型错误
*ERROR*: VALUE IS MISSING OR IS NONPOSITIVE
这个信息跟随在元件定义语句之后， 这个信息跟随在元件定义语句之后，指出元件 没有赋值或元件值是负数。 没有赋值或元件值是负数。Spice程序对下列元件值 程序对下列元件值 规定必须是正数：电阻、电容、电感、 规定必须是正数：电阻、电容、电感、互感和受控 半导体器件的某些几何参数（如面积、宽度w、 源。半导体器件的某些几何参数（如面积、宽度 、 长度L等 出现负值时，也会引出这一错误信息。 长度 等）出现负值时，也会引出这一错误信息。
*WARNING*: IN DIODE MODEL MODname IBV INCREASED TO value TORESOLVE INCOMPATIBILITY WITH SPECIH IED IS
quartus常见警告
1、Warning (10227): Verilog HDL Port Declaration warning at PRESS_MODELE.v(29): data type declaration for "iR" de clares packed dimensions but the port declaration declarati on does not.解释：2、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sd ram_PLL:sdram_pll1|altpll:altpll_component|pll" output por t clk[0] feeds output pin "DRAM1_CLK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance解释：PLL的输出用在了非专属的PLL_OUT措施：设计电路板的时候最好将PLL_OUT用在相关的时钟信号上，如果没有使用，则这个警告不理会也可。
3、Warning: Using design file cpu.v, which is not specified as a design file for the current project, but contains defini tions for 25 design units and 25 entities in project解释：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序生成的，不是用QUARTUS将文件添加进本项目措施：无须理会，不影响使用4、Warning (10240): Verilog HDL Always Construct warning at I2C_V_Config.v(153): inferring latch(es) for variable "L UT_DATA", which holds its previous value in one or more paths through the always construct解释：信号被综合成了latch，锁存器的EN和数据输入端口存在一个竞争的问题措施：将计数器从里面抽出来5、Warning: 12 hierarchies have connectivity warnings - see the Connectivity Checks report folder解释：实例化的时候，有一些端口没用，让没用的端口的位置空着，措施：不用理会6、Warning: Synthesized away the following node(s)解释：以下节点被综合优化掉措施：不用理会7、Warning:Found xx output pins without output pin load c apacitance assignment解释：没有给输出管教指定负载电容措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Edi tor中为相应的输出管脚指定负载电容，以消除警告8、Warning: The following nodes have both tri-state and no n-tri-state drivers解释：该用三态逻辑驱动的信号，被用非三态逻辑驱动了措施：在子信息中定位到警告所在，改用三态逻辑驱动9、Warning: Latch DE2_TV:inst1|I2C_V_Config:I2C_AV_Conf ig|LUT_DATA[8] has unsafe behaviorWarning: Ports D and ENA on the latch are fed by the sam e signal DE2_TV:inst1|I2C_V_Config:I2C_AV_Config|LUT_I NDEX[4]解释：产生了latch措施：用时序代替组合电路，或者是用完备的if/else，和case语句10、Warning: TRI or OPNDRN buffers permanently enabled 解释：输出要加三态控制11、Warning: Output pins are stuck at VCC or GND解释：这几个输出管脚直接接地了措施：如果这符合你的设计要求这种警告可以不管12、Warning (15400): WYSIWYG primitive "DE2_TV:inst1|S dram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo: dcfifo_component|dcfifo_21m1:auto_generated|altsyncram_ 1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a15 " has a port clk1 that is stuck at GND解释：这里是采用的SDRAM的读写方式为1入2出的模式，将fifo2的输入信号给接GND了措施：不用理会。
重装系统,出现：Units specified don't exist SHSUCDX can't install
?
解决方案1：
首先是你的硬盘分区不对吧
先用PQ格成ntfs或far32
进PE把C盘格式化成FAT32
BIOS里面硬盘模式ACHI改为IDE~
要到BIOS将硬盘的模式改成compatiST xp光盘，设置为光驱启动，出现界面后，选择xp pe（老毛桃），回车。笔记本就启动了。然后利用桌面上的GHOST安装，就不会出现问题，也只是安装在c盘中，不会影响其他盘的。祝你好运！
解决方案3：
笔记本电脑安装GHOST系统提示Units specified don't exist SHSUCDX can't install 。
朋友买了个联想笔记本电脑要重装XP，在安装GHOST系统提示Units specified don't exist SHSUCDX can't install 。
在一些thinkpad或联想的，预装WIN7或VISTA的品牌机上，如果用户想安装XP系统，往往会出现蓝屏、死机等错误。原因XP系统并不包含SATA 的驱动，造成错误。要想使用XP，请把BIOS中serial ata模式改成compatibility模式，即兼容模式。这样就可以正常使用XP,但这是以牺牲一定的磁盘性能为代价的。
对于这个错误提示是由于硬盘的格式错误造成，一般可通过三种途径来解决：
1。在BIOS里面硬盘模式ACHI改为IDE~
要到BIOS将硬盘的模式改成compatibility模式 就可以装，但我进入BIOS却找不到这个项，只好改用第二种方法：
LM7805三极管正压电源数据手册说明书
3-TERMINAL POSITIVE VOLTAGE REGULATOR LM7805 TO-220Plastic PackageThe Voltages Available allow these Regulators to be used in Logic Systems, Instrumentation, Hi-Fi Audio Circuits and other Solid State Electronic Equipment ABSOLUTE MAXIMUM RATINGS UNIT V W W ºC ºC ºCELECTRICAL CHARACTERISTICS (T j =25ºC unless specified otherwise)VI =10V, I O =500mA DESCRIPTION SYMBOLMINTYPMAXUNIT Output VoltageV OT j =25ºC4.805.20V I O =5mA ~ 1AV I =7V ~ 20V, P< 15W Line Regulation R EGV V I =7.0 ~ 25V T j =25ºC 100mV V I =8.0 ~ 12V50mV Ripple Rejection R R V I =8.0 ~ 18V, f=120HzT j =0 ~ 125ºC 62dB Load RegulationR EGL I O =5mA ~ 1.5A T j =25ºC100mV I O =250mA ~ 750mA50mV Output Resistance R O f=1KHz T j =0 ~ 125ºC 0.017ΩOutput Voltage Drift ∆V O /∆T I O =5mA T j =0 ~ 125ºC - 1.1mV/ºC Output Noise Voltage V NO f=10Hz ~ 100KHzT j =25ºC40µV Dropout Voltage V d I O =1AT j =25ºC 2.0V Quiescent CurrentI Q T j =25ºC8.0mA Quiescent Current Change ∆I Q V I =7.0 ~ 25V T j =0 ~ 125ºC 1.3mA I O =5mA ~ 1A0.5mA Short Circuit Output Current I SC T j =25ºC 750mA Peak Output CurrentI PKT j =25ºC2.2ATEST CONDITIONV T j =0 ~ 125ºC4.755.25Storage Temperature RangeT stg - 65 to +150Lead Temperature 1.6mm (1/16 inch) from Case for 10 seconds T L260Continuous Total Dissipation at T c =25ºC case TemperatureP D 15Operating free-air, case, or Virtual Junction Temperature Range T OPR 0 to 150DESCRIPTION SYMBOL VALUE Input VoltageV IN 35Continuous Total Dissipation at T a =25ºC free air TemperatureP D2.0Continental Device India LimitedAn ISO/TS 16949, ISO 9001 and ISO 14001 Certified CompanyTO-220Leaded PlasticPackageMRegulatorsPin 1: In Pin 2: Ground Pin 3: OutPackaging dimensions, tube dimensions and quantity/tube are approximate and subject to change.TO-220 Series Packaging TubeLM7805 TO-220Plastic PackageCustomer Notes LM7805TO-220Plastic PackageDisclaimerThe product information and the selection guides facilitate selection of the CDIL's Semiconductor Device(s)best suited for application in your product(s)as per your requirement.It is recommended that you completely review our Data Sheet(s)so as to confirm that the Device(s)meet functionality parameters for your application.The information furnished in the Data Sheet and on the CDIL Web Site/CD are believed to be accurate and reliable.CDIL however,does not assume responsibility for inaccuracies or incomplete information.Furthermore,CDIL does not assume liability whatsoever,arising out of the application or use of any CDIL product;neither does it convey any license under its patent rights nor rights of others.These products are not designed for use in life saving/support appliances or systems.CDIL customers selling these products(either as individual Semiconductor Devices or incorporated in their end products),in any life saving/support appliances or systems or applications do so at their own risk and CDIL will not be responsible for any damages resulting from such sale(s).CDIL strives for continuous improvement and reserves the right to change the specifications of its products without prior notice.CDIL is a registered Trademark ofContinental Device India LimitedC-120 Naraina Industrial Area, New Delhi 110 028, India.Telephone + 91-11-2579 6150, 4141 1112 Fax + 91-11-2579 5290, 4141 1119*****************。
quartus ii 中常见warning 及解决方法(转载)(Quartus II中常见警告及解决方法(转载))
quartus ii 中常见warning 及解决方法(转载)（Quartus II中常见警告及解决方法（转载））Support original! I reprinted, you can download free1.Found clock-sensitive, change, during, active, clock, edge, at, time, <time>, on, register, <name>"Reason: vector, source, file, clock sensitive signals (such as data, allowing, clearing, synchronization, loading, etc.) change simultaneously on the edge of the clock. A clock sensitive signal cannot change at the edge of the clock. The consequence is that the result is incorrect.Measures: edit vector source file2.Verilog, HDL, assignment, warning, at, <location>: truncated, value, with, size, <number>, to, match,, size, of, target (<number>Reason: in HDL design, the number of targets is set, such as: reg[4:0] a, and default to 32 bits, the number of digits to the right sizeMeasure: if the result is correct, it needs no correction. If you don't want to see this warning, you can change the number of settings3.All, reachable, assignments, to, data_out (10), assign,'0', register, removed, by, optimizationReason: after the optimizer has been optimized, the output port is no longer functional4.Following 9, pins, have, nothing, GND, or, VCC, driving, datain, port - changes, to, this,, connectivity, may, change, results, fittingReason: ninth feet, empty or grounded or connected to the power supplyMeasures: sometimes the output port is defined, but the output is directly assigned to '0', which will be grounded and assigned '1' to the power supply. If these ports are used in your design, you can ignore these warning5.Found, pins, functioning, as, undefined, clocks, and/or, memory, enablesReason: you have no constraint information as the PIN of the clock. You can set the settings for the corresponding PIN. Mainly refers to some of your pin in the circuit played a role in the clock tube, such as the flip-flop CLK pin, and this pin has no clock constraint, so QuartusII CLK as undefined clock.Measures: if CLK is not a clock, can add "not clock" constraint; if it is, can be added in clock setting; in some of the clock requirements are not very high, you can ignore this warning or modified here: Assignments>Timing analysis settings... Individual clocks > >.....6.Timing, characteristics, of, device, EPM570T144C5, are,preliminaryReason: because MAXII is a relatively new component, the timing in QuartusII is not a formal version. Wait for Service PackMeasure: only affects Quartus's Waveform7.Warning:, Clock, latency, analysis, for, offsets, is, supported, for, the, current, device, family, but, is, PLL, not, enabledMeasure: change the on in setting, Requirements&Option-->More, Timing, Setting-->setting-->Enable, Clock, Latency, timing to OFF8.Found, clock, high, time, violation, at,, NS, on, register, |counter|lpm_counter:count1_rtl_0|dffs[11]"Reason: violated the steup/hold time, should be after the simulation, to see whether the waveform settings and the clock edge in line with steup/hold timeMeasure: adding a register in the middle can solve the problem9.warning:, circuit, may, not, operate.detected,non-operational,, paths, clocked, by, clock, clk44, with, clock,, skew, larger, delay, than, dataReason: clock jitter is greater than data delay, when the clock is very fast, and if and other classes of excessive levels of this problem will occur, but this problem is mostly in thedevice's highest frequency will appear措施：设置-->选项-->需要定时要求和改小一些违约，如改到50mhz10。
系统 技术篇 Units specified don't stall
Units specified don’t exist.shsucdxcan’t install翻译过来意思是：特定分区（单元）不存在，shsucdx不能安装SHSUCDX(.CDM)为dos下的光驱扩展程序，安装SATA光驱的程序。
导致出现这个问题的可能原因：1、硬盘分区没有被激活（可使用fdisk或diskgen查看，diskgen查看被激活的分区为红色标志）2、硬盘坏道3、硬盘不能被正常识别（比如一些SATA硬盘不能被没有加载SATA驱动的Dos系统识别）。
诊断与解决过程：1、首先使用diskgen工具产看系统分区是否被激活（重新激活将要进行系统安装的分区），以及分区的文件系统格式（比如ntfs或fat32）。
然后问题还是没有解决，接着下面操作。
2、重启进入Bios（按F2），恢复出厂设置（loadmanufacture defaults），设置光盘引导（Boot——>cd/dvd drives）,设置硬盘模式为兼容模式Advanced——>IDE configuration——>SATA Mode(大概是这样)——>compatible)。
3、然后保存，重启，开始使用Ghost系统盘进行系统安装。
问题解决。
Ps：若是不想这么麻烦，那就用一张纯净的系统盘进行安装，或者换个高版本（SATA 光驱驱动的）的Ghost系统盘进行安装。
还有就是可以使用Ghost系统盘带的PE系统进行安装（进入PE系统，在桌面上可看到“GHOST安装“系统）。
更新：若硬盘有坏道，可检测出坏道位置，然后为坏道建立单独分区，隐藏坏道分区！解决方案解决方案1：首先是你的硬盘分区不对，用PE格式化成ntfs或FAT32BIOS 里面硬盘模式ACHI改为IDE~要到BIOS将硬盘的模式改成compatibility模式就可以装解决方案2：插入GHOST xp光盘，设置为光驱启动，出现界面后，选择xp pe（老毛桃），回车。
RAPID PROTOTYPING THROUGH OCTREE DECOMPOSITION OF 3D GEOMETRIC MODELS
DFM-2004-57769 RAPID PROTOTYPING THROUGH OCTREE DECOMPOSITION OF 3DGEOMETRIC MODELSH. MedellínMechanical Engineering, Heriot-Watt University, Edinburgh, EH14 4AS, Scotlande-mail: him1@J. CorneyMechanical Engineering, Heriot-Watt University, Edinburgh EH14 4AS, Scotlande-mail: j.r.corney@J. B. C. DaviesMechanical Engineering, Heriot-Watt University, Edinburgh EH14 4AS, Scotlande-mail: b.j.davies@T. LimMechanical Engineering, Heriot-Watt University,Edinburgh EH14 4AS, Scotlande-mail: t.lim@J.M. RitchieMechanical Engineering, Heriot-Watt University, Edinburgh EH14 4AS, Scotland e-mail: j.m.ritchie@ABSTRACTThis paper presents the integration of an Octree modeller, an assembly planning system, and a robotic cell to build approximate prototypes directly from 3D model data. The integration demonstrates the feasibility of an assembly based rapid prototyping approach referred to as OcBlox, which approximates Octree representations of 3D models with “Blox”. These cuboid units are automatically assembled to obtain a physical prototype. After detailing the algorithms used to generate the Octree’s assembly sequence, a single resolution example of a prototype built with this automated system is presented. The paper ends with a discussion of the potential of the approach to support post build machining and complex overhanging geometry.Keywords:Rapid prototyping, OcBlox, Octree representation, Octant, Blox.1.0 INTRODUCTION AND BACKGROUNDThe need for the rapid construction of physical models before full-scale production has emerged as a consequence of the constant drive to reduce cost whilst increasing the speed and quality of final products. In this context, Rapid Prototyping (RP) refers to the physical construction of 3D models directly from digital data using special equipment. Current RP techniques are all based on a layer-by-layerconstruction process, where a series of horizontal cross sections is obtained from a sliced CAD model.Considerable research in RP is oriented towards the development of new materials with improved properties [1-4].However, despite these advancements, there remain many limitations to the performance of current RP processes. As these technologies have become established, and their limitations understood, there have been increasing efforts to apply similar methodologies to the production of parts with “traditional” manufacturing processes. Indeed researchers have reported that comparing shape, materials, accuracy, batch size, production time, and cost, machining can potentially be a better route to rapid prototyping [2]. The following paragraphs briefly review a number of research projects motivated by similar observations.A rapid prototyping method using a 3-axis machine with aprogrammable 4th axis was proposed in [5]. The method required the generation of multiple NC programs for different rotations about a fixturing axis. Although successful application of the approach was demonstrated on a number of shapes, there are inherent limitations to the range of geometries the system could handle. A proposal for a new RP method combining LOM and CNC machining was presented in [6]. A CNC machine is used to control three heads that are used for modeling (to create layers of material), milling (to eliminate the staircase effect), and masking (to apply masking material to act as the support). The use of STL files, theProceedings of DETC’04 ASME 2004 Design Engineering Technical Conferences and Computers and Information in Engineering Conference September 28-October 2, 2004, Salt Lake City, Utah, USADET C20 04-5 7769variation of the material homogeneity, and the separation of masking material represent some limitations of the proposed method. A robot arm holding a milling tool for a layer-based construction of prototypes based on STL or SLC formats was presented in [7], and a hybrid-RP process combining deposition and machining was proposed in [3]. This hybrid process is based on extracting machining features from a 3D model, which are machined in layers of material and the component is built by stacking the machined layers. Recently, a dual-robot workcell was proved to be a more flexible and efficient tool for rapid prototyping of complex parts than the single–robot methods of machining [8].In this paper the integration of an Octree modeller, an assembly planning system, and a robotic cell is presented as a proof of concept for an assembly based rapid prototyping technique. The approach described here is a development of the method outlined in [9] and is motivated by a desire to increase the speed and decrease the cost of prototype production. The system has a unified interface that works directly with the 3D model data to generate instructions for the robotic assembly cell.The rest of this paper is organised as follows: Section two describes the algorithms and hardware that have been created to support this automated assembly system. Section three describes the implementation of the proposed method and in section four a discussion of the results is given. Finally, conclusions and an overview of future research work are detailed in section five.2.0 OCBLOX OVERVIEWThe OcBlox process is considered as the integration of three main components (Fig. 1):1. A Blox generation system via Octree decomposition,2. An assembly planning system, and3. A robotic assembly system.Although the production of a rough prototype shape is the current focus of the work, longer term of researchers are also motivated by the idea of creating a system for rapid production of “near shape” stock material. The machining of a part requires rough machining to remove large amounts of unwanted material, and finish machining to obtain the final surface finished. By constructing approximate physical models, the rough machining work and the material required to produce a component will be reduced considerably and thusthe manufacture time and cost will also decrease.ModelAssemblyMachined3DPlanningRoboticAssemblysystemPrototypeFinalPrototypeFigure 1: General overview of OcBlox.The following subsections give an overview of theOcBlox system’s components.2.1 OCTREE GENERATIONOctree representation is a form of tessellation in which thevolume occupied by a 3D solid CAD model is subdivided intocubes of varying sizes. Each of the cubes has a locational code(see Fig. 2a) that gives the exact location of each cube in theOctree. The relationship between each octant can also beviewed by means of a tree structure (see Fig. 2b) where eachbranch is identified by the relative position of the octant in itsparent node, and according to the orientations R (right), L(left), U (up), D (down), F (front), and B (back), [12, 20].Thus, octants are labeled as LDF, LDB, LUF, LUB, RDF,RDB, RUF, and RUB, (see Fig. 2c).(a) (b) (c)Figure 2: (a) octants, (b) Octree structure, (c) octantidentification.The first step in creating an Octree representation is togenerate a bounding box around the model. This box is thensubdivided into eight octants by halving the bounding box ineach axis direction, the resulting octants are known as level-one octants. Each octant is classified as full, empty or partiallyfull depending on its location in the model, inside, outside orpartially inside, respectively. Normally only partially fulloctants are divided further into smaller octants. In principlethe whole process can be repeated until all the octants in thebounding box are either full or empty with no partially fulloctants, at which stage, the boundary of the object is obtained.However, the continuation of the subdivision process canequally well be determined by other criteria (i.e. maximumlevel). Regardless of how it is controlled, at the end of theprocess the list of octants will form an approximaterepresentation of the 3D model (Fig. 24).The main use of Octrees has been to provide a compactrepresentation of a complex 3D image, or object. In this workwe exploit the Octree representation to approximate complexshapes with units of regular geometry whose size can bepredetermined, these units are referred as Blox and theycorrespond to leaf octants in the Octree. Further more itshierarchical data structure is easy to navigate (algorithms forneighbor finding are detailed in [10-12]).Only after the Octree has been generated (i.e. the locationof the leaf nodes specified) are the kernel modeller’s booleanAPI’s used to label each octant with the percentage of materialthey contain, thus:Content 0 %: An empty octant (located outside the solid model).Content 0 → 100%: An octant that only partially contains the model.Content 100 %: An octant located inside the solid model.For the single resolution implementation described insection 3, an Octree representation is generated by recursivelysub-dividing the assembly model’s bounding box until apredetermined resolution is reached (regardless of the octanttype). The level of subdivision of a model is determined according to the sizes of Blox available for assembling it.2.2 ASSEMBLY PLANNINGGiven an Octree model, the assembly planning system uses the properties of the Octree structure to plan the assembly sequence of the Blox set. The placing of each Blox in the assembly workspace is done in three moves, Fig. 3. Move 1 (m1) picks up a Blox from the feeder and moves it to a projected position outside the model’s bounding box (Fig. 3a). Move 2 (m2) moves it until it is directly above its final location (Fig. 3b). The last move3 (m3) lowers it into location (Fig. 3c). Direct vertical insertion is not considered because the high accuracy that it requires to avoid collisions between the Blox being assembled and the subassembly state.Figure 3: Assembly sequence for individual Blox. (a) move 1 (m1), (b) move 2 (m2), (c) move 3 (m3).The next two subsections describe the two algorithms that have been developed for the generation of assembly sequences. The first, called the “scan-line” algorithm, is designed to support the current single resolution implementation, while the second, “adaptive-scan-line” procedure handles the additional complications of true multi-resolution Octrees.2.2.1 Scan-line assembly algorithmThis algorithm uses the relative location of each Blox and a preferential ordering of assembly trajectories in the robotic cell, to generate the assembly sequence. The Octree structure is used to identify the initial Blox, while the assembly trajectory is used to select the direction to find the next adjacent Blox to be assembled. The algorithm initially selects the Blox in the farthest left-down-front (LDF) corner of the Octree (this is found by traversing each LDF link from root to leaf node, Fig. 4b) to start the assembly planning. The corner of this initial Blox is made the origin of the coordinate system associated with the assembly area (Fig. 4c). The assembly trajectory preference is defined by specifying the order in which the three assembly axes X (R), Y (B) and Z (U) are used during the assembly process.A flow chart of the scan algorithm is shown in Fig. 5 and the assembly sequence generation process for the model of Fig. 4 is represented in Fig. 6. As shown, the first Blox to be assembled is the farthest octant located in the extreme LDF of the Octree (Fig. 4b) while subsequent Bloxes are identified by examining their relative positions as determined by the assembly trajectory, and by using a neighbor finding algorithm similar to that reported in [12]. Bloxes are firstly assembled in the X (R) direction until no more Bloxes are located in this direction, then model construction progresses in the Y (B) direction by selecting a new adjacent Blox to start a row (Row-start). Finally when both X and Y are exhausted, the Z (U) trajectory is used to continue the assembly from a new Blox located in a higher Z level (Level_start).(a) (b) (c) Figure 4: Octree decomposition of a box. (a) Actual model,(b) Traversing each LDF octant in the Octree, (c)Octree representation and initial Blox.Figure 5: The scan-line algorithm flowchart.Figure 6: Scan-line ordering of an Octree model of a box.All the octants in an Octree are used to create the assembly sequence; however before a Blox is added to the assembly list its material content is checked. Currently empty Bloxes (0%) are not added, full Bloxes (100%) are added, and partially full Bloxes are added if they exceed a user defined tolerance (i.e. threshold). If this tolerance is set to zero then a maximal prototype will be generated (i.e. it will be bigger than the final shape) because all full and partially full Bloxes will be included to the build. The potential role of “empty” Bloxes in supporting overhanging structures is considered in Section 4.The scan-line algorithm has been implemented in the OcBlox interface as shown in Fig. 7. The obtained assembly sequence of an Octree model is presented as a list on the right-hand-side of the screen.sequenceFirst BloX in thefirst BloXlast BloXassembly LDF cornerFigure 7: Implementation of the scan-line algorithm.If an Octree has different sizes of Blox (i.e. multi-resolution) the assembly sequence generated with the scan-line algorithm could cause collisions. Figure 8 shows an example in which the scan-line method (progressing in the X direction) has created an assembly sequence of {1, 2, 3, 4}. This sequence would cause collisions of Blox 4 with the large Blox 3, which lies adjacent to the Blox 2. To overcome this problem the “adaptive-scan-line” algorithm detailed in the next section has been developed.Figure 8: Potential collision during the assembly of Blox 4.2.2.2 Adaptive-scan-line algorithmAs in the scan-line algorithm assembly proceeds in a number of preferred directions, but now prior to adding a current Blox to the assembly list, its trajectory is checked for collisions. If none is found, and the material content is above the threshold, the current Blox is added into the assembly list. On the other hand, if a current Blox is found to interfere with a Blox already in the assembly list, then the Blox which itclashed with and everything subsequent to it in the assembly list, is deleted and the current Blox is inserted at the end of the assembly list. Two modifications to the identification of the next Blox to be assembled are:1) When the current Blox has more than one adjacentBlox in the assembly direction (in this case R ), then it is the lowest, front adjacent Blox, not yet included in the assembly list which is selected as the next Blox to be evaluated for assembly (Fig. 9).2) After a scan-line iteration the “row start” Blox is onlyincremented if all the adjacent Bloxes in that particular row have been included in the assembly list. Otherwise the scan-line procedure starts again using the same “row start”. This process is also used for the increment of the “level start” Blox.Figure 9: Selection of the next Blox to be assembled in Rdirection (three different cases).Figure 10: Generation of the assembly sequence for a two-resolution Octree representation.Figure 10 illustrates the assembly sequence generation of a two-resolution Octree representation using the adaptive-scan-line algorithm. For this particular case three scan-line iterations using the same “row start” (Blox 1) are needed. In the first iteration Blox 2, which is the lowest front Blox, was selected as the adjacent to Blox 1. Similarly Blox 3 was located as being adjacent to Blox 2, and likewise Blox 4 is found to be adjacent to Blox 3. Thus the assembly sequence in the first iteration is {1, 2, 3, 4}. Because not all the adjacent Bloxes in the row were considered in the first iteration (for instance Blox 5 adjacent to Blox 1), it is necessary to do another scan line iteration. In this second iteration Blox 5 is the next unconsidered adjacent to Blox 1, however because Blox 4, which is already in the assembly list, interferes withthe assembly of Blox 5, Blox 4 is deleted from the assembly list and Blox 5 is added instead, {1, 2, 3, 5}. As the process continues Blox 6 is located adjacent to Blox 5 and then Blox 4 is found to be adjacent to Blox 6. Thus the assembly sequence after the second scan line iteration is {1, 2, 3, 5, 6, 4}. A third scan-line iteration is needed for Blox 7 (the next unconsidered adjacent Blox to Blox 1). Blox 4 obstructs the assembly of Blox 7 and therefore Blox 4 is again removed from the assembly list and Blox 7 is inserted instead, {1, 2, 3, 5, 6, 7}. Detecting that Blox 8 is adjacent to Blox 7 and that Blox 4 is adjacent to Blox 8, the final assembly sequence is obtained after three iterations using the same row start Blox, {1, 2, 3, 5, 6, 7, 8, 4}.(a)(b) (c)Figure 11: Assembly clash detection using ray firing. (a) Ray firing from a normal plane to the assemblytrajectory, (b) Array of rays to be fired, c) Ray firing including the preassembly position.The adaptive-scan-line algorithm has been implemented byusing a ray testing operation to detect potential collisions. The ray test is carried out as shown in Fig. 11 where the Bloxbeing tested is located in its final position and rays are fired in a reverse direction to the assembly trajectory (Fig. 11a) tosearch potential collisions with Bloxes already assembled, i.e. Bloxes already added in the assembly list. The number of raysfor the test is determined as follows: 2min .⎟⎟⎠⎞⎜⎜⎝⎛=s s Rays Nowhere s is the size of the Blox being tested and s min the minimum size of Blox in the Octree. The rays are fired in asquare array (Fig. 11b) from a normal plane to the assembly direction and located as shown in Fig. 11a. With this array ofrays it is guaranteed that any interference of the Blox being evaluated and the assembly state will be detected. Considering the physical assembly process of Fig. 3, it is envisaged that therobotic arm will not assemble a Blox directly to its final location (Fig. 3b and Fig. 3c) but to a position located just above its final location. This fact may cause collisions that cannot be detected with the normal array of rays of Fig. 11b. The solution to this problem is the increment of a row and a column in the array of rays as shown in Fig. 11c. In this way the geometric test is made to match the physical reality of the assembly process and the location of the preassembly position relative to the final position is (s min /2, s min /2, s min /2).Figure 12 presents the pseudo code of the adaptive-scan-line algorithm, and Fig. 13 shows a flowchart of the process. Figure 12: The adaptive-scan-line algorithm pseudo code.Figure 13: The adaptive-scan-line algorithm flowchart.The adaptive-scan line algorithm has been implemented and the results have shown to behave as anticipated.2.2.3 Analysis of the algorithmsCorrectness and completeness of the scan-line algorithm The correctness of the scan-line algorithm is immediate. Since the leaf octants in the Octree are considered to have the same level of subdivision, i.e. same size, the relative location of adjacent Bloxes according to the assembly preferences, (see Fig. 6) will guarantee that a feasible assembly sequence will be always obtained as no collisions will occur. However it is necessary a correct selection of the initial Blox or octant to start the analysis (see Fig. 4), which is correct when the farthest LDF octant is selected. Correct adjacent octant identification is guaranteed if the leaf octants have the same size and if the direction for adjacency is selected according to the assembly preferences. Since the neighbor finding method used in the scan line algorithm goes over all leaf octants in the Octree, all Bloxes are evaluated for assembly and therefore the completeness of the algorithm is guaranteed.Correctness and completeness of the adaptive-scan-line algorithmThe correctness of the adaptive-scan-line algorithm depends on the ray based test to detect potential collisions and on the correct updating of the assembly list. Each Blox is evaluated for potential collisions with the current subassembly state (Bloxes in the assembly list) before it is added into the assembly list. Thus if the assembly list is properly updated, a feasible assembly sequence is always guaranteed. The assembly list is updated in two ways: when a collision-free Blox is added at the end of it, and when a clashing Blox is inserted in a specific location. Bloxes that are added into the assembly list are labeled as “assembled” and Bloxes that are deleted from the assembly list are labeled as “no-assembled”. The adaptive-scan-algorithm automatically updates the Bloxes and the assembly list, and therefore a correct assembly sequence is guaranteed.By using identifiers the Bloxes are labeled as “visited” or “no-visited”, “assembled” or “no-assembled”. The algorithm goes over all octants in the Octree until there are no octant that have not been visited (i.e. no octants are missed). In this way a complete assembly sequence is guaranteed as all octants are evaluated.Performance of the scan-line algorithmAs shown in the flowchart of Fig. 5, the scan-line algorithm starts from an initial Blox (LDF) and it continues evaluating and searching adjacent octants until all the Bloxes are added into the assembly list. The time taken to do this is therefore proportional to the number of leaf nodes in the Octree and the execution time of the function to find adjacent Bloxes. The number of octants depends on the geometry of the model and the level of subdivision used in the Octree decomposition. Adjacent octants are found by traversing the Octree structure, and the execution time to find an adjacent octant can be measured in terms of the number of nodes in the Octree that must be visited. This time can be decomposed in two stages according to [12]. The first stage is to locate the nearest common ancestor of an octant (ascending the Octree time, T a), and then the second to locate the desired neighbor (descending the Octree time, T d)). Therefore the overall timefor assembly planning can be expressed as the function ),,(da TTNO where N is the number of leaf octants in the Octree. Some results of time performance for different components are presented in section 4.1.Performance of the adaptive-scan-line algorithmAccording to the flowchart of Fig. 13, it can be seen that the time required to generate an assembly sequence using the adaptive algorithm depends on the number of octants in the Octree, the required time to check for potential collisions, and the time required to find adjacent octants. As before, the number of octants in the Octree (N) depends on the geometryof the model and the level of subdivision used in the Octree decomposition. The collision detection function uses ray firing and the number of rays varies according to equation (1). Every ray is fired against every octant in the assembly list; therefore the time for the collision test is proportional to number of rays (N rays) and the number of octants in the assembly list (N AL),),(ALrays NNO. Finding adjacent Bloxes is more complex when different sizes of octants are present in the assembly. Traditional neighbor finding algorithms [12] only consider octant neighbors of same or bigger size. The neighbor finding function developed for the adaptive algorithm considers adjacency between octants of any size (bigger, smaller or same) and the time to find an adjacent Blox (T adj) depends on the number of nodes to be visited in the Octree. Therefore the time required to plan the assembly using the adaptive algorithm can be defined as a function),,,(adjALrays TNNNO. Experimental results of the performance of the algorithm are presented in section 4.1.2.3 ROBOTIC ASSEMBLY SYSTEMThe assembly sequence is used to automatically generate robot instructions and construct the prototype.2.3.1 Robot instruction generationAn Epson SCARA Robot ES653S is used for the assembly of the prototype. This robot has a nominal repeatability of ±0.02 mm and can be programmed directly from C++ using the SPEL API.The OcBlox application is written in C++ and uses the ACIS geometric modelling kernel [13] to support the geometric operations required. The system’s user interface allows:- Solid model manipulation- Octree subdivision for Blox generation- Manual modification of subdivision and assignment of physical material properties- Automatic assembly planning and manual modification- Assembly sequence visualisation- Robot instruction generation2.3.2 Assembly processA brief description of the main components of the system for creating the physical assembly are described in the following sections:Storage and feederThe feeder system stores the Bloxes and controls their orientation for robotic manipulation. Currently only one size of Blox is used for the assembly (i.e. one resolution of the Octree representation). Figure 14 shows the initial design of a 15 mm square Blox with a central hole for gripper pick-up and smaller corner holes used to locate small alignment pins. Several re-designs of the gripper have allowed the pickup holeto become significantly smaller; Fig. 19 shows the current dimension.Figure 14: Single size of Blox for building prototypes.A simple but effective feeder consisting of a long horizontal rail that stores and locates 50 Bloxes (15 mm) for the robot to collect has been designed. The Bloxes are moved into position by a gravity-pulley system (see Fig. 15).GripperThe handling system consists of a novel gripper designedto minimize any potential interference with the assembly process whilst providing a compliant grip. The ‘proboscis’ of the gripper uses the expansion of a pressurized silicon tube to create the friction needed for lifting a Blox (see Fig. 16). This design allows Bloxes to be placed without the need of any external gripping. Thus Bloxes can be placed next to each other without the possibility of clashes between gripper and assembly.Blox Bloxat the pickfeedergravity feeder beingup position picked upFigure 15: Feeder system at the pick up location.gripperproboscisFigure 16:Binding systemThe system glues the Bloxes when they have beenassembled into the correct position. The binding system (Fig.17) uses a pneumatic syringe adhesive dispenser coupled to a controller to place measured amounts of cyanoacrylic adhesive on the surface of each Blox during the build process.pneumatic glue gunFigure 17:Glue system for binding Bloxes.Build areaThe prototypes are assembled on a base plate located in the robot workspace. This base plate allows accurate Blox location by means of an array of positioning/locating holes. The aluminium base plate (Fig. 18) has the capacity to locate 20 x 13, 15 mm cubes on a single level.of BloxandprototypesBlox locationFigure 18: The assembly base plate.(a) 3D model (b) Octree representation (c)Assembly planning(d) Picking up a Blox from the feeder (e) Adhesive application (f) Assembly of BloxesFigure 19: Automated construction of prototypes process.3.0 IMPLEMENTATIONThe integration of the Octree decomposition, theassembly planning, and the robotic cell has allowed severalprototypes to be successfully constructed. These physical trialshave allowed the engineering challenges of the proposedapproach to be investigated in detail. Figure 19 shows the basicsteps involved during the construction of a model of a castle.The Octree decomposition generated 26 Bloxes which wereordered in an assembly sequence using an assembly trajectoryin X. Then robot instructions and assembly settings are createdbefore starting the automatic assembly. During the assemblyprocess, a Blox is picked up from the feeder and positioned intothe assembly area. The adhesive is automatically appliedaccording to the adjacency of the Blox being assembled.Finally the Blox is assembled in its final position and theprocess continues until the entire prototype is complete.The performance of the integrated system in theconstruction of the model castle is shown in Table 1. Thegeneration of Bloxes and the assembly sequence are relativelyfast and represent approximately the 5.54% of the overall buildtime of 446.46 seconds (7.44 minutes).No. Component Time(seconds)1 Blox generation (Octree) 24.062 Assembly planning (scan-line) 0.683 Assembly process 421.72Total time 446.46Table 1: Performance in building the castle.The above results were obtained using a computer with a950 MHz processor, and the robotic system described before.4.0 DISCUSSIONThe Blox generation algorithm includes the manualmanipulation of the Octree resolution, which means that theuser can specify and control the Blox dimensions according tothe features of the robotic cell and the sizes of Blox availablefor the construction.4.1 RESULTSThe results of building prototypes directly from singleresolution Octree models and using a robotic assembly cellhave been satisfactory. The experiment suggests that it takesapproximately 16.22 seconds to pick–up, glue, and place oneBlox. This unit value can be used to determine the assemblytime of Octree models when the number of Bloxes in the modelis known.Three different models were analyzed using the scan-linealgorithm. The three components were subdivided into differentnumber of octants. The results of the time performance analysisare shown in Fig. 20, where an assembly plan for an Octreemodel with around 300 octants is created in less than 40seconds. From these results it can be said that the scan-linealgorithm is a fast and effective method to generate assemblysequences of one-resolution Octree models. This is becausewhen a single resolution Octree is analyzed, the octants can beadded to the assembly list on the basis of assembly trajectorypreferences alone, and without carrying out a collision test.The computation of assembly sequences takes longer withthe adaptive-scan-line algorithm. Figure 21 shows the timeperformance for the same three components but using theadaptive-scan-line algorithm. In this case the assembly plan ofan Octree model with around 300 octants is created inapproximately 50 seconds, which is still relatively fastcompared with other assembly planners (e.g. [15, 21]).。
niosii和quartusi开发常见问题
N I O S I I和Q u a r t u s I开发常见问题-CAL-FENGHAI-(2020YEAR-YICAI)_JINGBIANNIOS II 开发常见问题-1Builder/Nios II 编译过程中遇到的一些问题与解决方法 (I)couldn't read file "stratix_pin_assign.tcl": no such file or directorysolution:From the Tools menu select Tcl Scripts, and then from the project folder choose the setup script for your particular development board, and click Run.下载时出现错误：Error: Can't configure device. Expected JTAG ID code 0x020010DD for device 1, but found JTAG ID code 0x020B40DD.solution:SOPC所选器件和开发板上的不一致。
solution:提示LED_PIO_BASE没有声明，这是因为名字不一致引起的。
比如，在生成SOPC时，双击系统PIO(Parallel I/O)(在Avalon Modules -> Other下），为系统添加输出接口,你没有把该组件改名成LED_PIO,而是保留了原始的名字：PIO_0；但你又通过IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, led); 来向该组件写入数据，就会导致上述错误。
解决办法：1.可以修改sopc系统，为该PIO改名为LED_PIO ;2.在hello_led.c的前面给LED_PIO_BASE赋值，如#define LED_PIO_BASE 0x00001800，后面的这个地址要与SOPC 中的地址对应。
单晶Checkcif所有检测内容汇总及解释以及解决方法
Checkcif所有检测内容汇总以下内容均基于IUCr官方网站的说明，同Platon软件有少许差别，请注意分辨。
ABSTY02_ALERT_1_C An _exptl_absorpt_correction_type has been given without a literature citation. This should be contained in the _exptl_absorpt_process_details field. Absorption correction given as multi-scan.警告原因：采用了吸收校正，但是没有给出吸收校正细节和参考文献。
解决方法：在_exptl_absorpt_process_details项下给出吸收校正文献和细节。
如果没做吸收校正_exptl_absorpt_correction_type后面改成none。
CHEMW03_ALERT_2_A ALERT: The ratio of given/expected molecular weight as calculated from the _atom_site* data lies outside。
警告原因：分子式和Z值没有给对。
解决方法：在ins里给对分子式和Z值重新精修生成cif。
CRYSC01_ALERT_1_C The word below has not been recognised as a standard identifier.警告原因：cif中使用的单词无法被识别。
解决方法：检查单词拼写是否有错误，是否为cif可识别的单词。
CRYSC01_ALERT_1_C No recognised colour has been given for crystal colour.警告原因：晶体颜色描述无法被cif识别。
解决方法：检查单词拼写是否有错误，是否为cif可识别的单词。
quartus之warning
quartus之warning1. Warning: Tri-state node(s) do not directly drive top-levelTri-state, not, directly, drive, top-levelWarning: Tri-state node(s) do not directly drive top-level pin(s)Warning: Converted tri-state buffer "cpu_top:inst|timer:m1|u15" feeding internal logic into a wire Warning: Converted tri-state buffer "cpu_top:inst|timer:m1|u16" feeding internal logic into a wire Warning: Converted tri-state buffer "cpu_top:inst|timer:m1|u18" feeding internal logic into a wire 方法：FPGA内部的信号不能出现被赋值为高阻，只有顶层的信号才可以。
2.Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.方法：是关于时间精度的，将SETTING中精度设置由1ns改为原本的1ps，警告消失，警告的大致意思是在EDA第三方仿真工具下仿真PLL设计，就要求时间精度为1ps3.Warning: Found pins functioning as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock方法：是没设定全局时钟，选择Assignment > Setting命令，在Timing Analysis Settings下选择的Classic Timing Analyzer SettingsDefault required fmax中填入时钟频率，点击下面的Indicidual Clocks按钮点击New点击Applies to node后面的“...”按钮，并在弹出的Node finder中加入相应的CLK信号填上clock settings name（即为程序中CLK），设置时钟频率和占空比，点击OK然后一路OK下去，再编译的时候这个警告就会没有了4. Warning: The Reserve All Unused Pins setting has not been specified, and will defaultto 'As output driving ground'.方法：setting里面，点击device，里有个对话框device and pin options，打开后里面有个unused pins，把里面的选项由原来的接地改成三态5. Warning: Feature LogicLock is only available with a valid subscription license. Pleasepurchase a software subscription to gain full access to this feature方法6.Warning (10240): Verilog HDL Always Construct warning atI2C_V_Config.v(153): inferring latch(es) for variable"LUT_DATA", which holds its previous value in one or more paths through the always construct解释：信号被综合成了latch，锁存器的EN和数据输入端口存在一个竞争的问题措施：将计数器从里面抽出来7.Warning: Design contains 2 input pin(s) that do not drivelogic解释：有2个输入没有驱动任何逻辑，也就是说，只定义了2个输入管脚，但在逻辑中并没有使用这2个输入信号措施：将这2个输入管脚的定义去掉即可8.Warning: Ignored locations or region assignments to thefollowing nodesWarning: Node "FIELD" is assigned to location or region, but does not exist in design解释：有些引脚做了分配，但是在设计中没有使用措施：可以不用理会9.解決在Quartus II无法使用ModelSim的问题如果想在Quartus II中使用ModelSim 编译的时候却出现了类似下面的错误 Error: Can't launch the ModelSim-Altera software -- the path to the loc executables for the ModelSim-Altera software were not specified or the executables were not found at specified path.Error: You can specify the path inthe EDA Tool Options page of the Options dialog box or using the Tcl command set_user_option.Error: NativeLink simulation flow was NOT successful 解决的办法：在Quartus II中正确设置ModelSim的路径Tools -> Options -> General -> EDA 在出现的对话框中设置安装ModelSim的路径一定要指向找到能有ModelSim.exe文件的文件夹10. error：current module quartus_asm ended unexpectedly 出现这个错误时，可能是软件崩溃了，或系统内存不足，或在编译时，软件出现警告和病毒提示时，阻止了从而意外删除了某些文件措施：可以换系统，可以把软件卸了再重装，可以换低版本的quartus软件，一般推荐quartus9.0的，另外在编译时出现警告和病毒提示时，选全部信任或同意操作。
SII50N12资料
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K/W ZthJC
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T j=125°C
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450 W Ptot 350 300
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Units specified don't exist，SHSUCDX can't
install
今天重装一富士通笔记本的操作系统，原系统 VistaHome Basic，C盘70G，NTFS格式,系统及其他文件占23G。
开始用GHOST 的WINXP光盘安装，提示：Units specified don't exist， SHSUCDX can't install。
上网搜索解决方法：
1.说硬盘的模式不对，在BIOS将硬盘的模式改成compatibility（兼容）模式就可以装，但我进入BIOS，根本就找不到这个选项，硬盘选项只有Enabled及Disabled。
NND!关掉干哈捏？
再搜：
2.说用Winpe（老毛桃）来安装可以成功。
找一张带有老毛桃的Winxp Ghost盘，光盘启动了，到Winpe的桌面，运行GHOST安装，Ghost程序启动正常，开始拷贝正常，拷贝大概四分之一，出错，安装不下去聊－－此路不通。
再再搜：
3.说硬盘分区不对，用PQ格式成ntfs或fat32，再用PE把C盘格式化成FAT32，可以安装。
照做，PQ读硬盘出错，甭想格－－此路也不通。
再再再搜：
4.说直接用安装版系统盘一步一步安装，虽然这个比较麻烦了，但可以成功。
再找来WINXP系统安装盘，没一会儿，蓝屏－－真是好喝的钙！！
！－－此路也也不通。
再再再再搜：
网上没有相应的答案了！
于是乎，我左思右想,上蹿下跳,前赴后继……
分析只有最后一个方法可行，但是得用笔记本专用的系统安装，重新上网下载一个“大菠菜WINXP SP3笔记本专用版V3.0”，刻盘，重启，安装，一切正常！问题解决。
另外的问题，装好系统以后，发现硬盘容量不对，进入磁盘管理发现有136G可用空间，有74G未指派，224G状态良好，320G的硬盘怎么会这样呢？分区重叠！！！怪不得方法2、3、4出错，以前是谁分的区，这么乱！备份硬盘上的数据，重新分区，恢复刚才备份的ghost系统文件。
搞掂，哈～。