CC430F513x／612x／613x(Rev.B)

ECCN 5E002TSPA -Technology /Software Publicly AvailableErrataSLAZ052B–May 2009–Revised May 2010CC430F513x/612x/613x Device Erratasheet1Current VersionDevices R e v :A D C 24A D C 25C O M P 4C P U 18C P U 20C P U 24C P U 25C P U 26C P U 27C P U 28C P U 29C P U 30C P U 31C P U 32C P U 33C P U 34C P U 35C P U 39C P U 40D M A 4CC430F5133E üüüüüüüüüüüüüüüüüüüüCC430F5135E üüüüüüüüüüüüüüüüüüüüCC430F5137E üüüüüüüüüüüüüüüüüüüüCC430F6125E üüüüüüüüüüüüüüüüüüüüCC430F6126E üüüüüüüüüüüüüüüüüüüüCC430F6127E üüüüüüüüüüüüüüüüüüüüCC430F6135E üüüüüüüüüüüüüüüüüüüüCC430F6137EüüüüüüüüüüüüüüüüüüüüDevices R e v :D M A 7D M A 8E E M 8E E M 9E E M 11E E M 13E E M 14E E M 16E E M 17F L A S H 29F L A S H 31J T A G 20J T A G 21L C D B 1L C D B 3L C D B 4M P Y 1P M M 8P M M 9P M M 10CC430F5133E üüüüüüüüüüüüüüüüüCC430F5135E üüüüüüüüüüüüüüüüüCC430F5137E üüüüüüüüüüüüüüüüüCC430F6125E üüüüüüüüüüüüüüüüüüüüCC430F6126E üüüüüüüüüüüüüüüüüüüüCC430F6127E üüüüüüüüüüüüüüüüüüüüCC430F6135E üüüüüüüüüüüüüüüüüüüüCC430F6137EüüüüüüüüüüüüüüüüüüüüDevices R e v :P M M 11P M M 12P O R T 15R F 1A 1R F 1A 2R F 1A 3R F 1A 5R F 1A 6R T C 4T A B 23U C S 6U C S 7U C S 9U S C I 26W D G 4CC430F5133E üüüüüüüüüüüüüüüCC430F5135E üüüüüüüüüüüüüüüCC430F5137E üüüüüüüüüüüüüüüCC430F6125E üüüüüüüüüüüüüüüCC430F6126E üüüüüüüüüüüüüüüCC430F6127E üüüüüüüüüüüüüüüCC430F6135E üüüüüüüüüüüüüüüCC430F6137EüüüüüüüüüüüüüüüCurrent Version See Appendix A for prior revisions.üThe checkmark means that the issue is present in that revision Package Markings 2Package MarkingsRGC64QFN(RGC),64pinRGZ48QFN(RGZ),48PinDetailed Bug Description 3Detailed Bug DescriptionADC24ADC12ModuleFunction Unexpected ADC12current draw when ADC12ENC=1Description When set,the ADC12ENC bit issues a clock request to the selected source clock,even before the conversion trigger.This causes some extra current consumption,dependingon the selected clock.Workaround NoneADC25ADC12ModuleFunction Write to ADC12CTL0triggers ADC12when CONSEQ=00Description If ADC conversions are triggered by the Timer_B module and the ADC12is insingle-channel single-conversion mode(CONSEQ=00),ADC sampling is enabled bywrite access to any bit(s)in the ADC12CTL0register.This is contrary to the expectedbehavior that only the ADC12enable conversion bit(ADC12ENC)triggers a new ADC12sample.Workaround When operating the ADC12in CONSEQ=00and a Timer_B output is selected as the sample and hold source,temporarily clear the ADC12ENC bit before writing to other bitsin the ADC12CTL0register.The following capture trigger can then be re-enabled bysetting ADC12ENC=1.COMP4Comparator_B ModuleFunction CBEX and CBOUTPOL bits do not invert comparator I/ODescription Setting the exchange bit,CBEX,does not interchange the comparator inputs.Similarly setting the output polarity bit,CBOUTPOL,does not invert the output of the comparator.Workaround To obtain an inverted output from the comparator,invert the input signals to thecomparator using the channel input selector bits,CBIPSEL_x and CBIMSEL_x.Makesure to use a MOV instruction so that the inputs are inverted simultaneously.CPU18CPU ModuleFunction LPM instruction can corrupt PC/SR registersDescription The PC and SR registers have the potential to be corrupted when:•An instruction using register,absolute,indexed,indirect,indirect auto-increment,orsymbolic mode is used to set the LPM bits(for example,BIS&xyh,SR).and•This instruction is followed by a CALL or CALLA instruction.Upon servicing an interrupt service routine,the program counter(PC)is pushed twiceonto the stack instead of the correct operation where the PC,then the SR registers arepushed onto the stack.This corrupts the SR and possibly the PC on RETI from the ISR.Workaround Insert a NOP or__no_operation()intrinsic function between the instruction to enterlow-power mode and the CALL or CALLA instruction. Detailed Bug Description CPU20CPU ModuleFunction An unexpected Vacant Memory Access Flag(VMAIFG)can be triggered due to the CPU autoincrement of the MAB+2outside the range of a valid memory block.Description The VMAIFG is triggered if a PC-modifying instruction(for example,ret,push,call,pop, jmp,or br)is fetched from the last address of a section of memory(for example,FLASH,RAM)that is not contiguous to a higher valid section on the memory map.Workaround If code is affected,edit the linker command file to make the last four bytes of affected memory sections unavailable.CPU24CPU ModuleFunction Program counter corruption following entry into low-power modeDescription The program counter is corrupted when an interrupt event occurs in the time between (and including)one cycle before and one cycle after the CPUOFF bit is set in the statusregister.This failure occurs when the BIS instruction is followed by a CALL or CALLAinstruction using the following addressing modes:BIS&,SRCALLA indir,indir autoinc,regBIS INDEX,SRCALLA indir,indir autoinc,regBIS reg,SRCALLA reg,indir,indir autoincNOTE:Due to the instruction emulation,the EINT instruction,as well as the__enable_interrupts()and possibly the__bis_SR_register()intrinsicfunctions are affected.Workaround Insert a NOP instruction or__no_operation()intrinsic function call between the BIS and CALL or CALLA instructions.CPU25CPU ModuleFunction DMA transfer does not execute during low-power modeDescription If the following instruction sequence is used([]denotes an addressing mode)to enter a low-power mode,and the DMARMWDIS bit is set,then DMA transfers are blocked forthe duration of the low-power mode.BIS[register|index|absolute|symbolic],SRCALLA[register]Workaround•Insert a NOP instruction or__no_operation()intrinsic function call between the BISand CALLA instructionsor•Temporarily disable the DMARMWDIS bit when entering low-power mode.Detailed Bug Description CPU26CPU ModuleFunction CALL SP does not behave as expectedDescription When the intention is to execute code from the stack,a CALL SP instruction skips the first piece of data(instruction)on the stack.The second piece of data at SP+2is usedas the first executable instruction.Workaround Write the op code for a NOP as the first instruction on the stack.Begin the intendedsubroutine at address SP+2.CPU27CPU ModuleFunction Program Counter(PC)is corrupted during the context save of a nested interrupt Description When a low-power mode is entered within an interrupt service routine that has enabled nested interrupts(by setting the GIE bit),and the instruction that sets the low-powermode is directly followed by a RETI instruction,an incorrect value of PC+2is pushed tothe stack during the context save.Hence,the RETI instruction is not executed on returnfrom the nested interrupt,and the PC becomes corrupted.Workaround Insert a NOP or__no_operation()intrinsic function between the instruction that sets the lower power mode and the RETI instruction.CPU28CPU ModuleFunction PC is corrupted when using certain extended addressing mode combinations Description An extended memory instruction that modifies the program counter executes incorrectly when preceded by an extended memory write-back instruction under the followingconditions:First instruction:2-operand instruction,extended mode using(register,index),(register,absolute),or(register,symbolic)addressing modesSecond instruction:2-operand instruction,extended mode using the(indirect,PC),(indirectauto-increment,PC),or(indexed[with ind0],PC)addressing modesExample BISX.A R6,&AABCDANDX.A@R4+,PCWorkaround•Insert a NOP or a__no_operation()intrinsic function between the two instructions.or•Do not use an extended memory instruction to modify the PC. Detailed Bug Description CPU29CPU ModuleFunction Using a certain instruction sequence to enter low-power mode(s)affects the instruction width of the first instruction in an NMI ISRDescription If there is a pending NMI request when the CPU enters a low-power mode(LPMx)using an instruction of Indexed source addressing mode,and that instruction is followed by a20-bit wide instruction of Register source and Destination addressing modes,the firstinstruction of the ISR is executed as a20-bit wide instruction.Example main:...MOV.W[indexed],SR;Enter LPMxMOVX.A[register],[register];20-bit wide instruction...ISR_start:MOV.B[indexed],[register];ERROR-Executed as a20-bit instruction!Note:[]indicates addressing modeWorkaround•Insert a NOP or a__no_operation()intrinsic function following the instruction thatenters the LPMx using indexed addressing mode.or•Use a NOP or a__no_operation()intrinsic function as first instruction in the ISR.or•Do not use the indexed mode to enter LPMx.CPU30CPUX ModuleFunction ADDA,SUBA,CMPA[immediate],PC behave as if immediate value were offset by-2Description The extended address instructions ADDA,SUBA,CMPA in immediate addressing mode are represented by4-bytes of opcode.In cases where the program counter(PC)is usedas the destination register only2bytes of the current instruction's4-byte opcode areaccounted for in the PC value.The resulting operation executes as if the immediatevalue were offset by a value of-2.NOTE:The MOV instruction is not affected.Workaround•Modify immediate value in software to account for the offset of2.or•Use extended20-bit instructions(addx.a,subx.a,cmpx.a)instead.CPU31CPUX ModuleFunction SP corruptionDescription When the instruction PUSHX.A is executed using the indirect auto-increment mode with the stack pointer(SP)as the source register[PUSHX.A@SP+],the SP is consequentlycorrupted.Instead of decrementing the value of the SP by four,the value of the SP isreplaced with the data pointed to by the SP previous to the PUSHX.A instructionexecution.Workaround None.The compiler does not generate a PUSHX.A instruction that involves the SP.Detailed Bug Description CPU32CPUX ModuleFunction CALLA PC executes incorrectlyDescription When the instruction CALLA PC is executed,the program counter(PC)that is pushed onto the stack during the context save is incorrectly offset by a value of-2.Workaround None.The compiler does not generate a CALLA PC instruction.CPU33CPUX ModuleFunction CALLA[indexed]may corrupt the program counterDescription When the Stack Pointer(SP)is used as the destination register in the CALLAindex(Rdst)instruction and is preceded by a PUSH or PUSHX instruction in any of thefollowing addressing modes:Absolute,Symbolic,Indexed,Indirect register,or Indirectauto-increment,the"index"of the CALLA instruction is not sign extended to20-bits andis always treated as a positive value.This causes the Program Counter to be set to awrong address location when the index of the CALLA instruction represents a negativeoffset.NOTE:This erratum applies only when the instruction sequence is:PUSH orPUSHX followed by CALLA index(SP).This erratum does not apply if the PUSH or PUSHX instruction is used inthe Register or Immediate addressing mode.This erratum applies only when SP is used as the destination register inthe CALLA index(Rdst)instruction.Workaround Place a NOP instruction in between the PUSH or PUSHX and the CALLA index(SP)instructions.NOTE:This bug has no compiler impact as the compiler does not generate aCALLA instruction that uses indexed addressing mode with the SP.CPU34CPU ModuleFunction CPU may be halted if a conditional jump is followed by a rotate PC instruction Description If a conditional jump instruction(JZ,JNZ,JC,JNC,JN,JGE,JL)is followed by anAddress Rotate instruction on the PC(RRCM,RRAM,RLAM,RRUM)and the jump isnot performed,the CPU is halted.Workaround Insert a NOP between the conditional jump and the rotate PC instructions. Detailed Bug Description CPU35CPU ModuleFunction Instruction BIT.B@Rx,PC uses the wrong PC valueDescription The BIT(.B/.W)instruction in indirect register addressing mode is represented by2bytes of opcode.And if Program Counter(PC)is used as the destination register,the2opcode bytes of the current BIT instruction are not accounted for.The resulting operationexecutes the instruction using the wrong PC value,and this affects the results in theStatus Register(SR).Workaround NoneNOTE:The compiler does not generate a BIT instruction that uses the PC as anoperand.CPU39CPU ModuleFunction PC is corrupted when single-stepping through an instruction that clears the GIE bit Description Single-stepping over an instruction that clears the General Interrupt Enable bit(e.g.,DINT or BIC#GIE,SR)when the GIE bit was previously set may corrupt the PC.Forexample,the DINT or BIC#GIE,SR is a2-byte instruction.Single stepping through thisinstruction increments the PC by a value of4instead of2,thus corrupting the next PCvalue.Workaround Insert a NOP or__no_operation()intrinsic immediately after the line of code that clears the GIE bit.NOTE:This erratum applies to debug mode only.CPU40CPU ModuleFunction PC is corrupted when executing jump/conditional jump instruction that is followed byinstruction with PC as destination register or a data sectionDescription If the value at the memory location immediately following a jump/conditional jumpinstruction is0X40h or0X50h(where X=don't care),which could either be aninstruction opcode(for instructions like RRCM,RRAM,RLAM,RRUM)with PC asdestination register or a data section(const data in flash memory or data variable inRAM),then the PC value gets auto-incremented by2after the jump instruction isexecuted;thus branching to a wrong address location in code and leading to wrongprogram execution.For example,a conditional jump instruction followed by data section(0140h).@0x8012Loop DEC.W R6@0x8014DEC.W R7@0x8016JNZ Loop@0x8018Value1DW0140hWorkaround In assembly,insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section.Detailed Bug Description DMA4DMA ModuleFunction Corrupted write access to20-bit DMA registersDescription When a20-bit wide write to a DMA address register(DMAxSA or DMAxDA)isinterrupted by a DMA transfer,the register contents may be unpredictable.Workaround•Design the application to ensure that no DMA access interrupts20-bit wide accessesto the DMA address registers.or•When accessing the DMA address registers,enable the Read Modify Write disablebit(DMARMWDIS=1),or temporarily disable all active DMA channels(DMAEN=0).or•Use word access for accessing the DMA address registers.Note that this limits thevalues that can be written to the address registers to16-bit values(lower64K offlash).DMA7DMA ModuleFunction DMA interrupt lostDescription If a DMA request is received during the time when the read address of a read modifywrite instruction is on the Memory Address Bus(MAB),application interrupts could belost.Workaround Set the DMARMWDIS bit when using the DMA.DMA8DMA ModuleFunction DMA can corrupt values on write-access to program stackDescription If the DMA controller makes a write access to the stack while executing one of thefollowing instructions,the data that is written may be corrupted.CALLA[REG|IDX|SYM|ABS|IND|INA|IMM]PUSHX.A[IDX|SYM|ABS|IND|IMM|INA]PUSHX.A[REG]PUSHM.A[REG]POPM.A[REG]Note:[]denotes an addressing modeWorkaround Do not declare function-scope variables.Declare all variables that are intended to bemodified by the DMA as global-or file-scope such that they are allocated in the datasection of RAM and not on the program stack.EEM8Enhanced Emulation ModuleFunction Debugger stops responding when using the DMADescription In repeated transfer mode,the DMA automatically reloads the size counter(DMAxSZ) once a transfer is complete and immediately continues to execute the next transferunless the DMA Enable bit(DMAEN)has been previously cleared.In burst-block transfermode,DMA block transfers are interleaved with CPU activity80/20%–of ten CPUcycles,eight are allocated to a block transfer and two are allocated for the CPU.Because the JTAG system must wait for the CPU bus to be clear to halt the device,itcan only do so when two conditions are met:•Three clock cycles after any DMA transfer,the DMA is no longer requesting the bus.and•The CPU is not requesting the bus.Therefore,if the DMA is configured to operate in the repeat burst-block transfer mode,and a breakpoint is set between the line of code that triggers the DMA transfers and theline that clears the DMAEN bit,the DMA always requests the bus and the JTAG systemnever gains control of the device.Workaround When operating the DMA in repeat burst-block transfer mode,set breakpoint(s)onlywhen the DMA transfers are not active(before the start or after the end of the DMAtransfers).EEM9Enhanced Emulation ModuleFunction Combined breakpoint triggers may be missedDescription When debugging,if combined breakpoint triggers are used with certain combinations of instructions(examples below)the trigger may be missed.Examples1)PUSH[IDX|SYM|ABS|IND|INA]MOV[REG],[REG]2)BIS[REG],SRCALLA[REG]3)ADD[IMM],[ABS]||ADD[REG],[IDX]||ADD[REG],[SYM]||ADD[IND],[SYM]ADD[IND],[REG]4)PUSHX.A[REG]with rep_cnt=4SXTX.W[ABS]PUSHX[INA]Note:[]denotes an addressing modeWorkaround NoneEEM11Enhanced Emulation ModuleFunction Condition register write trigger fails while executing rotate instructionsDescription When using breakpoints or single stepping in the presence of multiplebackground-interrupts,the debugger may not halt at the breakpoint location and insteadhalts at the first line of any interrupt service routine.Workaround NoneNOTE:This erratum applies to debug mode only.EEM13Enhanced Emulation ModuleFunction Halting the debugger does not return correct PC value when in LPMDescription When debugging,if the device is in any low-power mode and the debugger is halted,the program counter update by the debugger is corrupted.The debugger is unable to halt atthe correct location.Workaround NoneNOTE:This erratum applies to debug mode only.EEM14Enhanced Emulation ModuleFunction Single-step or breakpoint on module register with WAIT capability may not work Description In debug mode,the CPU clock is driven independently from the wait inputs of devicemodules(i.e.,MULT,USB,RF1A,CRC).As a result,an EEM halt on an access to themodule data registers(breakpoint or single-step)may show incorrect results due toincomplete execution.Workaround Do not single-step through a data register access that holds the CPU to provide a valid result.Place breakpoints after the affected register is accessed and sufficient clockcycles have been provided.NOTE:This erratum applies to debug mode only.EEM16Enhanced Emulation ModuleFunction The state storage display does not work reliably when used on instructions with CPUWait cycles.Description When executing instructions that require wait states;the state storage window updates incorrectly.For example a flash erase instruction causes the CPU to be held until theerase is completed i.e.the flash puts the CPU in a wait state.During this time if the statestorage window is enabled it may incorrectly display any previously executed instructionmultiple times.NOTE:This erratum affects debug mode only.Workaround Do not enable the state storage display when executing instructions that require waitstates.Instead set a breakpoint after the instruction is completed to view the statestorage display.EEM17Enhanced Emulation ModuleFunction Wrong Breakpoint halt after executing Flash Erase/Write instructionsDescription Hardware breakpoints or Conditional Address triggered breakpoints on instructions that follow Flash Erase/Write instructions,stops the debugger at the actual Flash Erase/Writeinstruction even though the flash erase/write operation has already been executed.Thehardware/conditional address triggered breakpoints that are placed on either the nexttwo single opcode instructions OR the next double opcode instruction that follows theFlash Erase/Write instruction are affected by this erratum.NOTE:This erratum affects debug mode only.Workaround e other conditional/advanced triggered breakpoints to halt the debugger right after Flash erase/write instructions.FLASH29Flash ModuleFunction Read disturb due to emergency exit from write/erase Flash operationDescription When a Flash write or erase is abruptly terminated,any further reliable reads from Flash are not ensured.The abrupt termination can occur as a result of the Emergency Exit bit(EMEX in FCTL3)being set.This forces a write or an erase operation to be terminatedbefore normal completion.Workaround After setting EMEX=1,wait for at least100µs after a bank or mass erase and at least 6µs after a segment erase before Flash is accessed again.FLASH31Flash ModuleFunction Interrupts not disabled during flash operationDescription When a flash operation is in progress,interrupts are not automatically disabled.TheCPU will always attempt to service the interrupt request,whether or not the flash is busy.Workaround Disable interrupts using the GIE bit before erasing flash in another bank of memory.Note that all interrupts during the period of time will be lost when GIE=0.RSTTESTJTAG20SYS Module FunctionBSL does not exit to application code DescriptionThe methods used to exit the BSL per the MSP430Memory Programming User's Guide (SLAU265)are invalid.Workaround Toexit the BSL one of the following methods must be used.•A power cycle •or •Toggle the TEST pin twice when RST is high,and then pull RST low.NOTE:This sequence is not subject to timing constraints and the appropriatelevel transitions are sufficient to trigger an exit from BSL mode.JTAG21JTAG Module Function"Attach to Running Target"resets device DescriptionThe "attach to running target"feature in IAR occasionally resets the device before getting it under JTAG control.Workaround Use alternative methods (for example,outputting device status/variables via port pins orUART)to debug unattached running target.LCDB1LCD_B ModuleFunction VLCDEXT bit not working properlyDescription When the VLCDEXT bit is set an external voltage applied to the LCDCAP/R33pinshould serve as the LCD voltage.This works as expected when the V2to V4voltagesare generated externally (LCDEXTBIAS =1)and external resistors are connected on theR03to R33resistor ladder.If internal V2to V4bias voltage generation is selected(LCDEXTBIAS =0),applying an external LCD voltage on LCDCAP VLCDEXT has noeffect.WorkaroundThe expected behavior for the VLCDEXT bit can be achieved by setting the VLCDx bitsto a non-zero value and leaving the charge pump disabled (LCDCPEN =0).The VLCDxbits are don't care when the charge pump is disabled so this does not result in anyadditional or unexpected current consumption.LCDB3LCD_B ModuleFunction LCDFRMIFG set erroneously when LCDON changed from1to0Description The LCD_B frame interrupt flag(LCDFRMIFG)can be set erroneously when theinterrupt is enabled((LCDFRMIE=1)and the LCD_B module is switched off(LCDONchanged from1to0).Workaround Disable the frame interrupt before switching off the LCD_B module.LCDB4LCD_B ModuleFunction Write access to LCDBIV does not reset LCD IFGsDescription A write access to the LCDBIV register does not automatically reset all pending interrupt flags.Workaround Clear all interrupt flags in software by writing0to the lowest nibble of LCDBCTL1,where the flags are stored.MPY1Hardware Multiplier(MPY)ModuleFunction Save and Restore feature on MPY32not functionalDescription The MPY32module uses the Save and Restore method which involves saving themultiplier state by pushing the MPY configuration/operand values to the stack beforeusing the multiplier inside an Interrupt Service Routine(ISR)and then restoring the stateby popping the configuration/operand values back to the MPY registers at the end of theISR.However due to the erratum the Save and Restore operation fails causing the writeoperation to the OP2H register right after the restore operation to be ignored as it is notpreceded by a write to OP2L register resulting in an invalid multiply operation. Workaround None.Disable interrupts when writing to OP2L and OP2H registers.NOTE:When using the C-compiler,the interrupts are automatically disabledwhile using the MPY32.。