电分研讨DC - 副本
Sendyne 漏接地 DC 电力系统安全白皮书说明书
White Paper Safety of unearthed (IT)DC power sy stemsSafety of unearthed (IT)DC power systemsAbstract --- Ungrounded, unearthed, “floating” or IT (Isolé-terré or Isolated Terra) are all terms used to describe power systems that have no intentional conductive connection to earth’s or chassis ground. The main advantage of the IT power system is that a single “short” will not disable its ability to continue delivering power. It is es-sential for the safety of such systems to continuously monitor their isolation state as even a single fault can generate hazards to personnel in contact with these systems. “Isolation monitors” are the devices required by several international standards to perform this function. This paper reviews the potential hazards in an IT system and the most common methods employed today for detection of isolation faults. It identi-fies safety related shortcomings inherent to each method and illustrates some of the unique features of Sendyne’s SIM100 designed to overcome them.Keywords --- isolation monitor; ground fault detection; symmetrical faults; EV safety; charging station safetyUngrounded, unearthed, “floating” or IT (Isolé-ter-ré or Isolated Terra) are all terms used to describe power systems that have no intentional conduc-tive connection to earth’s or chassis ground. The main advantage of the IT power system is that a single “short” will not disable its ability to contin-ue delivering power. Figure 1 illustrates the basic topology of such a system.The resistive connections, shown in Fig 1, between the terminals of the power source and the chas-sis are referred to as the “isolation resistances” (,ISO PR and ,ISO NR) and they represent the par-allel combination of all resistive paths from the power source terminals to the chassis (including the ones the isolation monitor introduces). The values of isolation resistances are desirable to be high so leakage currents that travel through them are kept to a harmless minimum. The capacitors shown represent the parallel combination of all capacitances present, including the Y-capacitorstypically used in DC IT systems to suppress EMI. The values of Y-capacitors are kept within limits in order to avoid hazardous accumulation of en-ergy. The voltages Vp and Vn are shown each to be equal with half the battery voltage, which will be the case if the values of ,ISO P R and ,ISO N R are equal.Isolation faultsIf either of the isolation resistances decreases be-low the threshold of 100 Ohms/Volt a hazard oc-curs if a person makes contact with the terminal “opposite” to the leaking resistor. This hazardoussituation is illustrated in Figure 2.This contact closes the circuit and current flows through a person’s body. Note that although it is shown that Vn < Vp in this example, an isolationfault cannot be detected based solely on voltage readings. The following illustrations show two examples where an isolation fault may be present while Vn = Vp .A “symmetrical” or “double” isolation fault may occur through insulation failures in power connec-tors or other environmental and intrusion reasons and, depending on the value of leakage currents, may cause power loss, overheating and even fire.Detection of these types of faults is an absolute re-quirement for the safety of IT power systems. Capacitive faultsOf equal importance to personal safety is another type of hazard. While international standards do not yet require it to be monitored, it is the haz-ard that can be caused by excessive energy stored in the IT power system capacitors. IT system de-signers ensure that design values of Y-capacitors prevent energy storage beyond the safety limit of 0.2 J. Sub-system failures, such as a coolant leak-age or personnel interventions, may alter the orig-inally designed capacitance values. In this case energy discharged through a person’s body can create a hazardous event as shown in Fig. 5. Note that the stored energy limits are set for theparallel combination of all capacitances between the power terminals and chassis.Sendyne’s SIM100 is the only isolation monitor today that tracks dynamically IT system’s capac-itances and reports the maximum energy that can be potentially stored in them.Figure 2: Single isolation faultbattery packFault detection methodsWhile there are several methods traditionally used in the field for the implementation of an isolation monitoring function, they can be broadly grouped in three main categories that will be described in the following sections.Voltage methodThis method is the simplest one and relies ex-clusively on voltage measurements between each power pole and the chassis. It depends on the ob-servation that a single isolation fault will create an imbalance between the two voltages Vp and Vn. If the initial values of isolation resistances are known by some method, the voltage ratio between Vp and Vn can be used to estimate the value of a single faulty isolation resistance. As it was illus-trated in the previous sections, this method com-pletely fails to detect “symmetrical” or any type of concurrent faults, where both isolation resistances change, and it is not acceptable in any product that intends to be safe.Resistance insertion methodSpecific safety related standards such as the ISO 6469-1, SAE J1766 and CFR 571.305, speci-fy a method for estimating isolation resistances through insertion of a known value resistor. The method involves two steps:STEP 1: Measure V P and V N and determine the lower of the two.STEP 2: Connect a known resistance R 0 in parallel to the isolation resistance of the higher voltage (V P >V N ) as shown in Figure 7 and measure again the two new voltage values 'P V and 'N V .The ,ISO N R can be shown to equal:',0'1N P P ISO NP P V V V R R V V −=+There are several issues with this method. In or-der to be accurate, R0 has to be selected in the range of 100 to 500 Ω/V. This is exactly the range in which the isolation system becomes hazardous, which means that during the measurement period the system becomes deliberately unsafe. A second issue is that during the measurement the voltage should be stable. This requirement severely lim-its the utility of the method in systems that have active loads most of the time. A third issue is re-lated to cost, size and reliability, as inserting and de-inserting the test resistor in the high voltage system requires expensive and bulky relays. For these reasons the method is not utilized in active IT systems.Current measurement methodA variation of the voltage method that is refer-enced frequently, especially in quick charger specifications, is the current measurement meth-od. It appears in international standards like IEC 61851-23, IEEE 2030.1.1 and in CHAdeMO spec-ifications. An illustration of this method is shown in Figure 8. Two equal value resistors R along with a current measuring device are simultaneously connected to the power rails as shown in the il-lustration. The current measurement device mea-sures the current that goes through it and deter-mines the value of the fault isolation resistor R F according to the relationship:2bg F V i R R =+where:i g is the measured current R is the grounding resistor R Fis the insulation resistanceThis method has all the drawbacks of the voltage method described previously, such as that it can-not detect symmetric isolation faults. Worse, the resistors R have to have a low resistance value in order to provide measurement accuracy around the isolation fault values and at the same time set-tle capacitances quickly. In a 500 V IT system the R s used are specified to only 40 kΩ, while the fault isolation value calculated by the 100 Ω/V rule is 50 kΩ. It is obvious that while these resistances remain connected the system is not safe. This is the reason that all of the mentioned internationalstandards specify a “Maximum detection time” to be less than 1 s. What these specifications mean (although they do not state it explicitely) is that if the current measurement method is used, it is un-safe for the circuit to remain connected for more than a second.In addition, the measurement sensitivity of this method is optimized around the fault values of the isolation resistances thus it cannot provide accu-rate estimates for the actual values outside this range. This is the reason that some standards re-quire a self check to be implemented by insertion of a fault resistor in the IT system. For a 500 V sys-tem , the insertion of a “fault resistor” of 50 kΩ will create a potential hazard by allowing more than 20 mA -twice the limit - fault current.Because the current measurement method was utilized in the early days of quick charging, many standards still reference it.In the end of 2017 the International Organization for Standardization (ISO) issued a letter regarding IEC 61851-23 stating:“It is, as always, strongly recommended that users of standards additionally perform a risk assessment. Specifically in this case, standards users shall select proper means to fulfill safety re -quirements in the system of charging station and electric vehicle.”Signal injection methodTo overcome the limitations of the previously described methods, a signal injection method is utilized in most of today’s isolation monitoring devices. While there are many variations in the method, in principle the implementation is the same and is illustrated in Figure 9.A known current X i is injected in a branch of the isolation circuit, forcing a change in the respective voltage. In the example shown in Figure 9 the value of the parallel combination of the isolation resistances ISO R will be:ISO XV R i ∆=Implementations of this method vary in the way the signal is injected, the method utilized for cal-culating its value, the signal shape, duration and amplitude and other details.One variation (Nissan US Pat. 6,906,525 B2 ) re-lies on the injection of a pulsed signal through a coupling capacitor and then detecting the attenu-ation of the original signal due to the presence of an isolation resistance.Some of the issues with the signal injection meth-od include:• An active IT power system (or battery) willinterfere with the signal used to identify isolation resistance. Therefore this method can be effective only when there is no inter-fering load activity.• The DC injection method can take a longtime to make a determination depending on the time constant of the RC isolation circuits.• The AC injection method by design cannotbe accurate in the whole range of possi-ble isolation resistance values. It is opti-mized for the range of fault resistance (100 Ohms/V or 500 Ohm/V) and provides only an estimate of the parallel combination of isolation resistances.known square pulse through a coupling capacitor and de-tecting the attenuation of the signal by the isolation resis-tances/capacitors.Sendyne’s SIM100Sendyne’s patent pending method for monitoring the isolation state of the IT power system over-comes all shortcoming of the methods described in the previous section. Specifically, the SIM100 is capable of estimating accurately the state of the isolation system when the load is active and the battery voltage is continuously varying. This unique feature, while important for the safety of every IT electrical system, is especially important for the safety of systems that are engaged in com-mercial activities with very little down time, such as commercial vehicles and equipment.The SIM100 is the only product in the market to-day that provides estimates for the isolation sys-tem capacitances. Besides the added safety pro-vided by estimating the energy stored in them, capacitances estimation is necessary to be able to analyze the isolation system behavior dynamically and during transitions. Sendyne utilizes state-of-the-art stochastic filtering and numerical meth-ods to evaluate the isolation state dynamically and accurately. The SIM100 provides individual estimates for each isolation resistance and capac-itance along with the uncertainty in their calcula-tion. Typical accuracy of SIM100’s estimates is better than ±5%.SIM100 response timeThe SIM100 refreshes its estimates every 500 ms. Slow changes in the system isolation state can be tracked and updated within this interval. For large changes, such as the ones described in the UL 2231 tests, the response time of the SIM100 is less than 5 s.As can be seen in Figure 13, SIM100 provides stable and accurate results within 5 sec of the transition. Response time is well below the 10 s requirement by different standards. Subsequent estimates are updated every 500 ms. In the same chart, highlighted in grey, are the ±15% accuracy levels specified by UL 2231-1 and 2. SIM100 esti-mate errors are below ±3%. During the transition and while SIM100 is estimating the new isolation state, it will indicate a high level of uncertainty, so the host ECU can ignore those transition results. Similar results were obtained when operating the SIM100 of the positive side of the battery.lation state taking into consideration the varying batteryvoltage and the Y-capacitances.∙V∙Vand accuracy in the successive insertion of a 200 Ohm/Vand 100 Ohm/V resistor (RF,N)BATT100*VBATT30405060708090100110120Resistance(kΩ)Time (s)Estimates of RF,Nin 10 experiments & response times (25 o C)Figure 13: Estimates of RF,Nprovided in 10 successive experimentsat room temperature. The green line represents the actual value ofthe inserted resistor. Greyed areas show UL2231-2 accuracy require-ments.Thermal stabilityPer UL 2231-2, the SIM100 was tested using the test apparatus of Figure 12 at different environ-mental temperatures. In the following illustra-tions the colored dots indicate the average error at each temperature obtained through approximate-ly 1100 reports. The experiments were repeated for different Y-capacitor values (2 x 100 nF and 2 x 1 uF). The greyed areas show the spread of error in the reports indicating the max and min error for each experiment. We illustrate the worst case er-rors that occur at the smaller insertion resistance R F,x . As can be seen all errors are well below the ±15% of the UL requirements.-505E s t im a t e e r r o r (%)Temperature o CAverage, min & max error for R F,N = 100 Ω/V * 500 V-20-15-10-505101520E s t i m a t e e r r o r (%)Temperature O CAverage, min & max error for R = 100 Ω/V * 500 VFigure 14: Inserted resistance estimate error at different temperaturesUncertaintyThe SIM100 submits along with each report an estimate of the uncertainty associated with the estimates. The uncertainty is reported as a per-centage of the estimated values and takes into consideration both the measurement and pro-cessing uncertainties. Uncertainty is derived in the interval of two standard deviations (95.45% of samples) and rounded to the next higher absolute value. For example, if the uncertainty calculated is ±1.4 % it will be rounded to ±2%. The SIM100 then adds to this value another ±3% to accommo-date for factors that cannot be calculated, such as part values shifting over age, etc. As a result, the uncertainty value provided is a conservative one. An illustration of the relationship between mea-surements distribution and uncertainties report-ed is shown in Figure 15. The green vertical line shows the actual value of the isolation resistance of the test circuit. Its value is the parallel combi-nation of the 250 kΩ inserted resistance with the 2.7 MΩ resistance of the SIM100. The red vertical line shows the average value of SIM100 reports; the actual estimate error is 1.8%. Uncertainty is estimated to ±2% and then augmented by ±3% to provide the final estimate of ±5%. As can be seen in this experiment, uncertainty provides a very+5%-5%Reported Uncertainty (%)250 kΩ20406080100120140160180FrequencyRF,P(kΩ)Histogram of RF,Pestimates over 10 experiments (25 o C)Figure 15: Distribution of reports over 1200 measurements and illustration of uncertainty reported by SIM100conservative estimate of the reported value.How to use the uncertaintyUncertainties should be used in the most conser-vative way to calculate worst case scenarios. If, forexample, the SIM100 reports a value of 100 kΩwith uncertainty of ±5%, the host should assumethe worst case possibility that the actual isolationresistance is (100 – 5) kΩ.Very high uncertaintiesThere may be instances that the SIM100 reportsvery high uncertainties. This may happen whenthere is no voltage present and there is a lot ofnoise in the IT system or during a large and rapidtransition of isolation resistance values. Duringthese instances, the SIM100 will flag the “HighUncertainty” bit to notify the host that these re-ports may be discarded.Uncertainties in capacitance estimatesWhen there is no activity on the IT power system itis expected that individual capacitance estimateswill have a high level of uncertainty. Nevertheless,the total value of isolation capacitance (the parallelcombination of all capacitances) and the estimatesfor maximum energy that can be stored on themwould be accurate. The uncertainty in capacitanceestimation will become small (less than ±5%) assoon as there is activity on the IT power bus.Variable loadsThe SIM100 is the only product today that can op-erate flawlessly in extremely noisy environments when the load of the IT power system is active. This is an important safety feature especially in commercial environments where the electrical equipment is in use most of the time. The SIM100 will provide accurate estimates even while the power system experiences violent swings of 10s or 100s of Volts.Figure16 shows the test setup and SIM100 re-sponses under a battery load corresponding to an accelerated driving profile. In the test circuita 250 kΩ resistor is connected and disconnected every 60 s. At the battery terminals an accelerat-ed driving profile load is simulated. The result-ing battery voltage is shown in the Battery voltage chart. The greyed areas indicate the 60 s intervals when the resistor is disconnected. The histogram shows the distribution of SIM100 reports in the periods when the resistor is connected.The green vertical lines in the histogram show the actual isolation resistance when the 250 kΩ resis-tor is connected. As can be seen in the histograms, the error between the average reported value and the actual value is less than 1%.R F = 250 kΩTest CircuitLoadI ,N501001502002503003500120240360480600720840960108012001320V B A T (V )Time (s)SWSW SW SW SW SW SW SW SW SW SWF r e q u e n c yHistograms of SIM100 R F estimates229230231229230231229230231229230231229230231229230231229230231229230231229230231229230231229230231Green line indicatesactual R F value 1% errorBattery voltage - Accelerated driving profileFigure 16: Distribution of reports over 1200 measurements and illustration of uncertainty reported by SIM100SIM100 Self-testingThe SIM100 performs a continuous self-testingprocess. During the self-test, the SIM100 checksthe validity of all connections and the integrity ofall references and critical hardware components.Details on the self-test process can be found in the“SIM100 Safety Manual”Field upgradeableThe SIM100 comes equipped with Sendyne’s pro-prietary boot-loader. The boot-loader relies onAES128 cryptographic standard to ensure thatfirmware updates are not compromised. It can beaccessed through CAN -bus and allows field up-grades of the SIM100 software.CAN communicationsThe SIM100 CAN protocol description can befound in the “SIM100 CAN 2.0B Protocol Docu-ment” and the “SIM100.dbc” files. The SIM100can be ordered with CAN running at 250 kb/s or500 kb/s. The SIM100MOD can be ordered withor without CAN bus termination resistors. For in-formation on ordering see the “Ordering informa-tion” section of the SIM100MOD datasheet.SENDYNE SENSING PRODUCTS WHITE PAPER| 11© 2019 Sendyne Corp.Sendyne Corp250 West BroadwayNew York, NY 10013Forthelatestproductinformationemail:****************©2019 Sendyne Corp, all rights reserved. This document contains information that is proprietary to Sendyne Corp. and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies.In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners.。
DC概论全总结_ASIC必备
DC概论全总结DC 概论之一 setup time 与 hold time (1)DC概论二之fanout与skew (5)DC概论三之setup time 与 hold time 之二 (14)DC概论四之setup time 与hold time 之三 (20)DC概论五之high fanout (37)DC 概论六之multicycle_path (59)DC概论七之gated clock (78)DC概论之IO约束 (90)DC优化约束 (99)DC 概论之一 setup time 与 hold time2009-03-13 10:49:56来源：网络转载作者：佚名共有评论(0)条浏览次数:521ic代码的综合过程可以说就是时序分析过程，dc会将设计打散成一个个路经，这些路经上有cell延迟和net延迟，然后dc会根据你加的约束，来映射库中符合这种延迟以及驱动的器件。
从而达到综合的目的。
dc的所有时序约束基础差不多就是setup time 和 hold time。
可以用下面的图片说明：所谓setup time即建立时间，也就说数据在时钟到来之前保持稳定所需要的时间，hold time 即保持时间，也就是说在时钟到来之后数据需要保持稳定的时间。
在深入建立时间和保持时间之前。
先了解下dc中的路经以及start point ，end point。
所谓start point 就是：1. input port（顶层设计的输入端口）2.clock pin of sequential cell（触发器的clock pin）所谓的end point 就是：1 output port（顶层设计的输出端口）3.data pin of sequential cell（触发器的data pin）了解 start point 和 end point，就可以方便的了解 dc是如何将设计打散成路经，一个设计中基本的路经分为4种，如下图：path1： input port to data pin of sequential cellpath2： input port to output portpath3： clock pin to data pin of next sequential cellpath4：clock pin to output port所有的设计也就这四种类型的路径。
半桥式DC-DC变换器的系统
（4）半桥式变换器 由两个电容器和两个开关管组成两个桥，桥的对角线接变压 器的原边绕组，故称半桥变换器。半桥式变换器减小了原边开关管的电压应力，结构 简单 ，功率器件少，所以在中小功率场合得到广泛应用。 本文设计电路将 400V 恒定直流输入变为 5V 稳定直流输出，输出功率较低，所以 我们采用半桥式变压器。 1.3 本文研究的内容 本文研究的内容主要包括： (1) 研究半桥式 DC-DC 电力变换电路的工作原理。 (2) 研究 PWM 调制方法的机理和半桥式 DC-DC 变换电路的控制方法。 (3) 设计从 400V 到 5V 的半桥式 DC-DC 变换器。 (4) 采用 MATLAB 工具对所设计系统进行仿真研究。
1 绪 论
1.1 研究背景 随着科技的发展，在人们的日常生活中，电力已成为与生产生活息息相关的一部 分，在各个场合，人们都需要各式各样的电力来为其服务，然而并不是所有的电力都 能在一开始就能满足需要，于是就要求有电力变换的过程。 直流- 直流变换器 （DC-DC） 作为一种应用广泛变换器广泛应用于远程及数据通讯、 计算机、办公自动化设备、工业仪器仪表、军事、航天等领域，涉及到国民经济的各 行各业。按额定功率的大小来划分，DC-DC 可分为 750W 以上、750W～1W 和 1W 以 下 3 大类。 进入 20 世纪 90 年代， DC-DC 变换器在低功率范围内的增长率大幅度提高， 其中 6W～25W DC-DC 变换器的增长率最高，这是因为它们大量用于直流测量和测试 设备、计算机显示系统、计算机和军事通讯系统。由于微处理器的高速化，DC-DC 变 换器由低功率向中功率方向发展是必然的趋势，所以 251W～750W 的 DC-DC 变换器 的增长率也是较快的，这主要是它用于服务性的医疗和实验设备、工业控制设备、远 程通讯设备、多路通信及发送设备，DC-DC 变换器在远程和数字通讯领域有着广阔的 应用前景。 DC-DC 变换器将一个固定的直流电压变换为可变的直流电压，这种技术被广泛应 用于无轨电车、地铁、列车、电动车的无级变速和控制，同时使上述控制具有加速平 稳、快速响应的性能，并同时收到节约电能的效果。用直流斩波器代替变阻器可节约 20％～30％的电能。直流斩波器不仅能起到调压的作用(开关电源)，同时还能起到有效 抑制电网侧谐波电流噪声的作用。 DC/DC 变换器现已商品化，模块采用高频 PWM 技术，开关频率在 500kHz 左右, 功率密度为 0.31W/cm3～1.22W/cm3。随着大规模集成电路的发展，要求电源模块实现 小型化，因此就要不断提高开关频率和采用新的电路拓扑结构。目前，已有一些公司 研制生产了采用零电流开关和零电压开关技术的二次电源模块，功率密度有较大幅度 的提高。 电子产业的迅速发展极大地推动了开关电源的发展。高频小型化的开关电源及其 技术已成为现代电子设备供电系统的主流。在电子设备领域中，通常将整流器称为一 次电源，而将 DC/DC 变换器称为二次电源。一次电源的作用是将单相或三相交流电网 变换成标值为 48V 的直流电源。目前，在电子设备中用的一次电源中，传统的相控式
DC综合问题总结
DC综合问题总结第一篇：DC综合问题总结DC综合以及后仿问题总结日期：2013.08.24 关于DC综合出现的一些warning以及解决方法：1）当出现这种unsign to signed warning出现的时候一般是代码中出现了一下两种不规范的写法：第一种：例如：wire data_A assign data_A=（判断条件）？1：0；即：定义一个wire类型的信号data_A，然后通过一个判断条件的真假来个data_A进行赋1或者0，那么这样的写法就会造成上面例句的warning，这是因为在verilog中直接写1或者0，那么verilog就会把1或者0默认为整型变量，而整型变量默认的是有符号数，而我们定义的data_A是一个无符号信号，那么正确的写法应该为wire data_A assign data_A=（判断条件）？1’b1：1’b0,这样写才是规范的写法。
第二种：这种情况warning主要出现在一些用到了有符号数运算的电路中，比如我们要计算两个8bit有符号数的加法、减法、乘法等，而其中一个有符号数要通过别的寄存器进行赋值，比如总线寄存器（即：要进行运算的数通过总线赋值），那么我们可能会这样写：wire signed [7:0] A;assign A=bus_data_reg[7:0]，这样写verilog就会把bus_data_reg[7:0]默认为一个无符号数，可是我们的A要求是一个有符号数，故就会出现上面列举的warning，正确的写法应该是wire signed [7:0] A;assign A=$signed(bus_data_reg[7:0]);,总的来说就是，我们要给一个有符号数的信号赋值，那么我们就应该保证等号两边都是有符号数，verilog中可以用$signed将一个数定义成有符号数。
同样当出现signed to unsigned这样的warning后，我们用上面同样的方法进行分析就可以解决了2)当综合之后出现这种类型的warning时，说明你的代码中在实例化某个模块的时候你只把该信号的某几bit连接到了该模块的端口上，这种警告的出现是比较常见的，比如上图所示：这表明在代码中send_check_bus_addr是一个11bit的输入信号，它的第6~10bit没有连接到该模块的端口上，即：这样的警告的出现是正常的，对DC综合的结果没有太大的影响。
DC使用教程
如何看时序报告：
通过产生的时序报告读出以下信息： 1)是setup time report还是hold time report? 2)时钟频率多少？
确定是setup time report还是hold time report? 看oprating conditions：worst（建立 时间），best（保持时间）。为什么？ 看path type：max（建立时间）， min（保持时间）。为什么？ 时钟频率多少： 通过上升沿和下降沿的时间来确定
Set_load 设置输出负载
估计模块输出的时序——transition time DC默认输出负载为0. 单位由Foundry厂提供，一般是pf.
Set_max_transition 设置最大传 输时间
Transition time 是指改变某线所驱动 的pin所需要的时间，该时间的计算方 法是基于工艺库的。 输出的传输时间是输入传输时间以及输 出负载的函数关系。 DC在优化的过程中就是确保设计的所 有net的对应的传输时间小于所设定的 最大传输时间。
DC时序路径：
时间通路的划分
几个概念
数据传输需要的时间（Data Arrival Time）:信号到达时间是指信号到达电 路中某一点的真实时间，一般等于信号 到达时序路径起点的时间加上信号在该 时序路径上传播所用的时间。 要求到达时间（Data Required Time): 指期望信号到达电路中某一点的时间。 时序裕度(slack):指电路中某点处要求 到达时间与实际信号到达时间的差值
DC逻辑综合使用流程
DC逻辑综合使用流程vlsi设计中心806凌金启动软件：：1、启动软件新开一个terminal窗口，输入命令：design_vision，回车即可开启图形界面，进入图形界面后可通过菜单、对话框等来实现DC的功能，相关的命令操作同样可以使用。
2、指定相关库文件指定相关库文件及及路径“File > Setup”打开下图所示对话框Search_path指定了搜索路径，点击右侧按钮进入如图所示对话框点击add添加库文件所在路径。
Target_library为逻辑综合的目标库，由代工厂提供的* .db 文件，用相似的方法添加所需库文件。
Link_library是链接库，一般和目标库相同注：“*”这一项要保留，否则链接时会出错，该项指示DC在链接时首先搜索内存中的内容。
Symble_library为指定的符号库，一般为*.sdb 文件，与单元的库文件对应。
3、设计读入“File > Read”读入设计文件，用此方式读入时在此处不用指定顶层文件，但读入后应马上指明设计的顶层名。
通过左侧的窗口可以观察设计的层次4、链接“File > Link Design”在弹出对话框中点击“ok”即可完成链接。
其执行的相关信息可从命令框中可查看5、实例唯一化当设计中有某个子模块被多次调用时就需要进行实例唯一化，实例唯一化就是将同一个子模块的多个实例生成为多个不同的子设计的过程。
之所以要进行实例唯一化是因为DC在逻辑综合时可能使用不同的电路形式来实现同一个子模块的不同实例，从而这些实例在DC看来是不同的设计（尽管其调用的子模块代码和功能完全相同）。
实现方法：“Hierarchy > Uniquify > Hierarchy ”在弹出对话框中默认点击“ok”即可，命令框中将显示“design_vision-t> uniquify”。
若选中“instances to be renamed even if unique or assigned don’t_touch”则会强制将所调用的模块从新命名，此时命令框中显示“design_vision-t> uniquify –force”。
DC逻辑综合(DC课件整理)
A D SET Q
这些变量必须准确指定，否则可能产生意外的结果，灵活的使用这些变量可 以可以大大减少工作量例如：你可以指定了一个标准单元库作为一个目标库 (target_library)，然后在 link_1ibrary 列表中指定压焊点工艺库以及所有其 它的宏模块（RAMS、ROMs、etc.），这意味着用户将能够利用标准单元库出现的 单元综合设计，然后再在设计中连接 pads 和宏模块的实例，如果压焊点工艺库 被包含在 target_1ibrary 列表中，那么 DC 可能使用 pads 综合内核的逻辑。 target_1ibrary 名也应该被包含在 link_1ibrary 列表中，这很重要，因为如果 link_library 中没有 target_library 的内容，那么当把门级网表读入 DC 中时， DC 将不能解析在网表中映射的单元，这种情况下 DC 产生警告信息，它不能解析
关键变量的介绍：
1、target_1ibrary变量：是DC中保留的变量，这个变量指定的库是DC用来构建
一个电路的。DC进行映射的几个步骤：设置它让它指向你的生产商提供的库文件。
使用厂家提供的工艺库中的时序数据计算这些门的时序。从target_1ibrary指定
的库中选择功能正确的门。设定目标库使用如下语句： set target _1ibrary
详细布线
版图设计后进 行STA
时序满足将要求吗
DC-DC电源拓扑及工作模式讲解
DC-DC电源拓扑及其工作模式讲解一、DC-DC电源基本拓扑分类：开关电源的三种基本拓扑结构有Buck、Boost、Buck-boost（反极性Boost）。
如果电感连接到地，就构成了升降压变换器，如果电感连接到输入端，就构成了升压变换器。
如果电感连接到输出端，就构成了降压变换器。
基本拓扑图如下：1.Buck2.Boost3.Buck-Boost二、DC-DC复杂拓扑结构1.反激隔离电源（FlyBack）另外有些隔离电源拓扑就是通过基本拓扑增加变压器或者变化得到的，例如反激隔离电源（FlyBack）。
2.Buck+Boost拓扑本质是用一个降压“加上”一个升压，来实现升降压。
SEPIC拓扑：集成了Boost和Flyback拓扑结构3.Cuk、Sepic、Zeta拓扑通过基本拓扑直接组合，形成了三个有实用价值的拓扑结构：Cuk、Sepic、Zeta。
Cuk的本质是Boost变换器和Buck变换器串联，Sepic的本质是Boost和Buck-Boost串联，Zeta可以看成Buck和Buck-Boost串联。
但是里面有些细节按照电流的方向在演进的过程中调整了二极管的方向，两极串联拓扑节省了复用的器件。
通过这样串联和演进，产生了新的三个电源拓扑。
同时，如果我们把同步Buck拓扑串联同步Boost可以形成四开关Buck-Boost拓扑。
4.四开关Buck-Boost拓扑同时，如果我们把同步Buck拓扑串联同步Boost可以形成四开关Buck-Boost拓扑5.反激、正激、推挽拓扑的演进利用变压器代替电感，可以把Boost演进为一个新拓扑FlyBack即反激变换器（反激的公式来看又是很像Buck-Boost，这里变压器不同于电感，也有说法会说反激是Buck-Boost变过来的）。
可以把Buck电路的开关通过一个变压器进行能量传递，就形成正激变换器。
将两个正激变换器进行并联，可以形成推挽拓扑。
正激的变压器，是直接输送能量过去，而不是像反激变压器那样传递能量。
ILD2111数字DC DC伏控制器IC评估系统使用指南说明书
ILD2111 - Digital DC/DC Buck Controller IC .dp digital power 2.0ILD2111 Evaluation SystemGetting StartedApplication NoteAbout this documentScope and purposeThis document presents basic information on how to start evaluating and using the ILD2111 evaluation system and user-friendly graphical user interface tool .dp vision. It presents all steps necessary to get the board and related environment up and running.Intended audienceThis document is intended for anyone who wants to start evaluating and using the ILD2111 evaluation system.Table of Contents1Introduction (3)2Environment Setup (4)2.1Hardware Setup (4)2.1.1Powering-up the Evaluation Board (5)2.1.2Switch Box Configuration (6)2.1.3LED Load Connection (7)2.1.4External Temperature Sensor (7)2.1.5External PWM Dimming (7)2.1.6I-Set Connection (7)2.2Software Setup (8)2.2.1Graphical User Interface (GUI) – .dp vision (8)3References (11)1IntroductionThe ILD2111 is a high-performance digital microcontroller-based DC/DC buck LED controller IC designed as a constant current source. More information can be found in [1].The ILD2111 evaluation board is presented in Figure 1. The solution and evaluation board are used as a second stage (DC/DC converter). As such, the board needs to be supplied by an appropriate DC source (a first stage). Depending on the purpose of the evaluation, the first stage might be a laboratory DC source or dedicated AC/DC converter. More information on typical application and component dimensioning and selection can be found in [2].Figure 1ILD2111 Evaluation Board2Environment SetupThis section explains the basics of the ILD2111 evaluation board connections to the external components and devices as well as how to use the .dp vision tool for optional parameterization. The evaluation board comes fully functional and parameterized (see [3] for details). As such, it can be used without the need for the .dp vision tool. However, if the user has to modify certain parameters for the purpose of evaluation, the .dp vision tool provides a comprehensive interface (for detailed information about the tool, please see [4]).2.1Hardware SetupFigure 2 shows the ILD2111 evaluation board with all relevant connections.Figure 2ILD2111 Evaluation Board ConnectionsPower supply options for the ILD2111 evaluation board are described in Table 1 below.The following connections are supported and listed in Table 2 below.2.1.1Powering-up the Evaluation BoardIn order to evaluate the ILD2111 evaluation board it needs to be powered up. There are two power sources: VDD (DC voltage used for power conversion to the output) and VCC used to power up the IC.2.1.1.1VDD SupplyConnect an appropriate DC source to the connector CON3 or CON5 as indicated in Figure 2. The VDD is rated up to 70 V and any higher voltage could lead to damage or malfunction of the evaluation board.2.1.1.2VCC SupplyFor the purpose of evaluation and parameterization with .dp vision, the VCC power supply should be connected only via a programming interface. Figure 3 shows how to connect the ILD2111 evaluation board to the .dp Interface Board Gen2 (see [5]) using an ILD2111 connecting cable with switch box, as well as connection to the PC via USB cable.Figure 3ILD2111 Evaluation Board Connection to PCIf the VCC is not provided over the programming interface or if the influence of the VCC voltage has to be evaluated, the auxiliary power supply can be used to power up and evaluate the system. This power supply is provided through the CON6 connector (see Figure 2). As shown in Table 1,this supply can be connected / disconnected by SW1.2.1.2Switch Box ConfigurationThe connecting cable with the switch box connects the .dp Interface Board Gen2 and ILD2111 evaluation board (see Figure 3). The switch box implements two switches: one for the VCC power supply (marked as VCC) and the other for data line for serial communication (marked as UART). The principal scheme of the connecting cable with the switch box is shown in Figure 4.Figure 4Connection Between Interface Board Gen2 and ILD2111 Evaluation BoardBoth switches need to be closed (= On) for evaluation with .dp vision.2.1.3LED Load ConnectionThe LED load should be connected to the CON1 connector (see Figure 2). The anode of the LED load should be connected to the “+”and the cathode to the “–”connector. Keep in mind that the LED load is not referenced to ground but rather to VDD, meaning that “–”is not connected to ground and that “+”is connected to VDD. Based on the default parameter setting, we recommend a minimum LED current rating of 1200 mA.2.1.4External Temperature SensorIf an external temperature sensor is needed, it must be connected to CON1 (a PTC and adjacent GND connectors) (see Figure 2).2.1.5External PWM DimmingThe external PWM dimming signal can be supplied to the ILD2111 evaluation board over two interfaces. The first one is a direct interface over the CON4 connector (see Figure 2). The user needs to take care that the voltage level does not exceed the internal IC power supply of 3.3 V on the PWM pin (see electrical characteristics in [1]). The second interface is over the optocoupler through the CON8 connector. This signal arrives inverted to the IC.2.1.6I-Set ConnectionIf the user needs to set the desired current over the I-Set interface, then the appropriate resistor needs to be connected to the CON1 connector (CURR and adjacent GND connectors) (see Figure 2). Due to the multiplexing of the pin functionality, the I-Set resistor (and associated FW function) and the communication interface could interfere with each other and therefore need to be decoupled.The I-Set procedure can be executed on system power-up. The UART switch in the switch box (see Figure 2) needs to be in the OFF position. After that the UART switch can be turned on if the communication is needed. In order to enter the communication mode and to avoid communication problems, the current set resistor should be disconnected afterwards. Typically, this approach is suitable if the desired parameter set is burned into the OTP.If the user needs to evaluate the system with some altered parameters, but without permanently burning (patching) them to the OTP, the previous procedure is not applicable. However, there is a way to execute the I-Set by reconnecting the LED load. For this purpose, execute the test configuration set from .dp vision with both switches of the switch box in the ON position. After successful start-up, disconnect the UART with theassociated switch and briefly disconnect the LED load1. After the load is reconnected the value of the output current should reflect the applied R-Set value. If the communication is needed again, follow the procedure described in the previous paragraph.2.2Software SetupIn order to use .dp vision, the user needs to install it on a used PC running Windows OS (for details, see [4]). Beside the .dp vision tool, a project-specific add-on also needs to be installed. This add-on will provide updated documentation and configuration files for the project. These files will be installed in the .dp vision installation folder.2.2.1Graphical User Interface (GUI) – .dp visionThe .dp vision software is a PC-based tool whose purpose is to enable easy configuration and user-friendly selection and definition of the project-specific parameter settings, allow adaptation and fine-tuning of the firmware behavior with respect to the application hardware configuration and dimensioning, fulfilling the given system requirements. The software can be downloaded from /dp. Once the interface board is ordered, a link to download the software free-of-charge will be offered.Figure 5 shows the initial .dp vision window after application start-up.Figure 5.dp vision Initial Window1 Keep in mind that this operation could be potentially dangerous for the LED load due to the fact that the output voltage will rise during disconnection and that the inrush current, as a consequence of an output capacitor discharge, will appear during the next connection of the LED load.Since no configuration file (.csv) is loaded, many functions are disabled. After opening a project configuration file, which can be found in the installation folder (provided with the installation of the project-specific add-on), the .dp vision window is as shown in Figure 6.Figure 6.dp vision Window After Loading Configuration FileThe user is now able to connect to the target system by pressing a power device On/Off button ( ). If everything is connected properly, a Quick Button bar will appear, as shown in Figure 7.Figure 7.dp vision – Quick Button BarIn the event of an error, an appropriate error message will be shown in a message field (see Figure 8). Figure 8.dp vision – Message FieldAfter these steps the user will be able to perform tests or to burn parameters.The current configuration can be tested by pressing a Test Configuration Set button (). If any parameter is changed by the user in the design parameters field, the new configuration has to be saved first and then it can be tested (otherwise testing is disabled).Parameters are burned by pressing a Burn Configuration Set button (). If the initial parameters are already burned, patching is possible only to the extent of the available memory. This process is automatic and initiated by the same button and the user is interactively guided through the process.More details about .dp vision can be found in the Tool User Manual (see [4]).3References[1]ILD2111 Data Sheet[2]ILD2111 Design Guide[3]ILD2111 Evaluation System Application Note[4].dp vision User Manual[5].dp Interface Board Gen2 User ManualRevision HistoryMajor changes since the last revisionPublished by Infineon Technologies AG 81726 Munich, Germany© 2015 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: ********************Document reference Legal Disclaimer THE INFORMATION GIVEN IN THIS APPLICATION NOTE (INCLUDING BUT NOT LIMITED TO CONTENTS OF REFERENCED WEBSITES) IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. 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IfTrademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI -POL™, DrBLADE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, i -Wafer™, MIPAQ™, ModSTACK™, my -d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PROFET™, PRO -SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI -ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT -iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). 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电分复习
电路试卷大题 一 二 三 四 五 六 七 八 九 成绩一. 单项选择题：在下列各题中，有四个备选答案，请将其中唯一正确的答案填入题干的括号中。
（本大题共 10小题，总计 20 分 ）1、 电路如图所示, 该电路的功率守恒表现为 A. 电阻吸收1 W 功率, 电流源供出1 W 功率 B. 电阻吸收1 W 功率, 电压源供出1 W 功率C. 电阻与电压源各吸收1 W 功率, 电流源供出2 W 功率D. 电阻与电流源各吸收1 W 功率, 电压源供出2 W 功率答( C )2、电路如图所示，当电路为零初始状态，u t t S ()()V=4ε时，i t L t ()(e )A =--22,t >0。
若u t t S ()()V=2ε，且i L ()A 02=。
则t >0时i t L ()应为A. (e)A1--tB. 2eA-tC.(e)A 1+-tD.(e)A2+-t答（ C ）u L3、图()a 所示电路中,当1S U U =和0=U 时,A 5-=I ;当0S =U 和V 1=U 时,A 5.0=I 。
其诺顿等效电路如图()b 所示，其中SC I 和o R 为b()a ()bA 5.A -、Ω2 A 5.B 、Ω5.0 A 5.C 、Ω2 A 5.2.D 、Ω5答 ()C4、含源二端网络及其端口伏安特性曲线如图所示，该网络ab 端口的戴维南等效电路是abU /VA. B. C. D.abababab答 ( B )5、无 源 网 络 N 如 图 1 所 示，其 i 的波 形 见 图 2，则 网 络 N 为 ( C )。
(a) 电 阻性 (b) 电 感 性 (c) 电 容 性6、今拟用电阻丝制作一三相电炉，功率为20kW ，对称电源线电压为380V 。
若三相电阻接成对称星形，则每相电阻等于 A.12.5Ω B. 7.22Ω C. 17.52Ω D. 4.18Ω答 ( B )7、图示正弦交流电路中，已知︒-∠=30100UV ，︒-∠=6020Z Ω，则其无功功率Q 等于 A. 500var B. 433var C. 433-varD. 250-var答 ( c )+-U8、 下列各电路具有高通频率特性的是：RRL()1()2()3()4A. (1)和(2)B. (1)和(3)C. (2)和(4)D. (3)和(4)答( C )9、可以通过改变电容来调节RLC 串联电路的谐振频率，若要使谐振频率增大一倍，则电容应 A. 大4倍 B. 大2倍 C. 减至21 D.减至41答 ( D ) 10、图示理想变压器变比为1：2，则R i 应为 A ．8Ω B ． 4Ω C ．0.5Ω D ．1Ω答( C )12:2Ω11、若要使图示电路的闭环增益等于5,则f R 应为+1UΩΩK 2.C 200.A ΩΩK 5.D 500.B答( D)二. 填充题：在下列各题中，请将题上所要求的解答填入题干中的各横线上方内。
DC完整手册
DC高效能移動式滅火系統(型號)使用說明書目錄產品特性……………………………………..P.3功能說明……………………………………..P.4各部名稱機體附加配備………………………………..P.5 控制面板………………………………………..P.6安全注意事項………………………………..P.7 操作說明………………………………………..P.8 關閉說明………………………………………..P.10 保固書………………………………………..P.12產品規格………………………………………..P.14產品特性：史上第一款最輕量化與機動性的高效能滅火設備輕便與機動性兼具的高壓泡沫滅火設備。
具有無懈可擊的滅火效能以及令人難以置信的輕量尺寸，讓您不再懼怕火災意外的發生。
本設備操作簡單、使用方便，所產生的高壓細霧泡沫屏障，保護滅火者人身安全提升滅火的安全及效率。
為之驚艷的滅火效能特製直流驅動高壓噴射泵系統，搭配外接水源，可讓系統達到滅火效能，透過特製的渦輪水槍噴射出高壓細霧泡沫，有效用於覆蓋火勢，將火勢瞬間降溫及撲滅。
領先業界的輕量化系統改變一般用柴油引擎搭配傳統電機的作法，特別設計直流電池供電與小型電機系統的搭配，大幅度減輕設備的重量與體積；即使一個13歲小女生也能輕鬆的操作，將火勢撲滅。
高度簡易的操作方式整台設備以開關與按鈕式切換，操作簡單不費力。
移動式設備有效涵蓋範圍在機台不移動狀況下，連接30公尺長水帶，涵蓋範圍也能達到半徑3800平方公尺以上面積；如搭配多處水源接點更能擴大滅火範圍。
廣泛的應用場所各類人員密集場所、辦公及住宅大樓、各廠區、倉庫、停車場、百貨商場、大眾運輸工具(鐵路、船舶、飛機) 、公共交通空間於各個空間或樓層間放置1~2台SEM@T DC滅火系統，在發現火災時，任何人員皆能輕易啟用該設備將火源撲滅，此系統採用環保型泡沫原液適用（A、B、C類火災）；可減少一般自動灑水系統造成機具或硬體設備之損害，改善滅火器持續性不足的缺點，將生命財產安全之風險降到最低。
GE Energy Infinity D DC能源系统概述说明书
OverviewThe GE Energy Infinity D™ DC energy system is a modular power plant that supports dual voltage (+24V/- 48V) operation through the use of a comprehensive range of state of the art rectifiers and DC-DC converters. Primary voltage is supported by rectifiers and battery reserve, while secondary voltage is supported by DC-DC converter modules. Primary voltage can be -48V or +24V.The Infinity D Power System has primary voltage capacity for +24V and -48V power up to 1,600A; secondary voltage capacity is up to 300A per expansion module.Shelf OptionsThe Infinity D Power System is built upon a modular architecture that consists of 8” (203mm) tall system modules. The system modules are complete “mini systems” which can be combined to form larger systems. Since each system module is an optimized combination of power and distribution there is minimal unnecessary capacity and cost is minimized. As the system is expanded,additional optimized combinations of capacityare added, again minimizing incremental cost. System modules are added to achieve up to 1,600A capacity.Infinity Rectifier and Converter FamilyThe Infinity D offers DC rectifiers andconverters for both +24V to -48V and -48V to +24V applications. Rectifiers and converters are color coded to quickly identify both the voltage and whether it is a rectifier or converter (orange for +24V and blue for -48V).Rectifier and Converter Options:- NE100AC24ATEZ Rectifier, 100A/24V Output - NE050AC48ATEZ Rectifier, 50A/48V Output- NE075DC24 Converter, 75A/24V Output - NE030DC48 Converter, 30A/48V OutputPulsar Plus ControllerThe Infinity D utilizes the industry leading Pulsar Plus controller with Ethernet and SNMP communications to deliver extensive monitoring and control features with remote access.• Modular DC power system enables low initial investment with future expansion potential •-48V up to 1,600A (87KW) or +24V up to 1,600A (44KW)• DC Power Plant with 24V and 48V DC dual voltage flexibility • High availability wireless telecom applications • Telecom service providers and OEMs • Efficiency approaching 97%Infinity D ™ Power SystemDual Voltage, Modular Power SystemInfinity Rectifiers and ConvertersApplicationsKey FeaturesSpecifications• Compact – 1RU form factor providing high power density (24 W/in3)• Dual Voltage compatibility – the unique connector pin designation allows the rectifier to be used in a “universal” power shelf, alongside rectifiers or DC-DC converters with different output voltages.• Plug and Play – installation of the rectifier in a shelf connected to a compatible system controller initializes all set up parameters automatically. No adjustments are needed.• Extended service life – parallel operation with automatic load sharing ensures that parallel units are not unduly stressed even when a unit fails or is removed.• Monitoring / control – the built in microprocessor controls and monitors all critical rectifier functions and communicates with the system controller using the built in Galaxy Protocol serial interface. • Fail safe performance – hot insertion capabilities allow for converter replacement without system shutdown; soft start and inrush current protection prevent nuisance tripping of upstream breakers.• Telecommunications networks • Digital subscriber line (DSL)• Indoor/outdoor wireless• Routers/switches • Fiber in the loop • Transmission• Data networks • PBX• Extended temperature range • Redundant fan cooling • Front panel LED indicators• 1U height, hi power density • 220/110V AC input • Digital load sharing• Hot pluggable •RoHS compliantPulsar Plus ControllerApplications Key Features The Pulsar Plus family of controllers providessystem monitoring and control features forInfinity, CP, and other power systems. Thesecontrollers monitor and control systemcomponents including rectifiers, converters,and distribution modules via a multi-dropRS485 digital communications bus. Systemstatus, parameters, settings, and alarmthresholds can be viewed and configuredfrom the controller’s front panel display.Assignment and configuration of alarminputs and output relays can be performedfrom a laptop computer connected to alocal RS-232 or Ethernet port, or by remoteaccess is through a network connection to theWorld Wide Web (internet) or your enterprisenetwork (intranet). An optional modem is alsoavailable.This controller utilizes standard networkmanagement protocols allowing for advancednetwork supervision. The GE Energy GalaxyManager™ software is the centralized visibilityand control component of a comprehensivepower management system designed to meetengineering, operations and maintenanceneeds. The Galaxy Manager client-serverarchitecture enables remote access to systemcontrollers across the power network.• Telecommunications networks • Digital subscriber line (DSL) • Indoor/outdoor wireless • Routers/switches• Fiber in the loop• Transmission• Data networks• PBXRemote Access and Features• Integrated 10/100Base-T Ethernet Network - TCP/IP- SNMP V2c for management- SMTP for email- Telnet for command line interface- DHCP for plug-n-play- FTP for rapid backup and upgrades- HTTP for standard web pagesand browsers- Compatible with Galaxy Managerand other management packages - Shielded RJ-45 interface referencedto chassis ground• Password protected security levels: User, Super-User, Administrator for all access • Ground-referenced RS232 system port • ANSI T1.317 command-line interface• Modem access support- Remote via external modem- Callback security• EasyView2, Windows-based GUI software for local terminal or Modem access Standard System Features• Monitor and control of more than 40connected devices- Robust RS485 system bus• Standard and user defined alarms- Alarm test- Assignable alarm severity: Critical,Major, Minor, Warning, and record-only- 10 alarm relays (7 user assigned)• Rectifier management features- Automatic rectifier restart- Active Rectifier ManagementARM (energy efficiency)- Remote rectifier (on/off)- Reserve Operation- Automatic rectifier sequence control- N + X redundancy check• Multiple Low Voltage Load and Low VoltageBattery Disconnect thresholds• Configuration, statistics, and history- All stored in non-volatile memory- Remote/local backup and restore ofconfiguration data• Industry standard defaults- Customer specific configurationsavailable• Remote/ local software upgrade• Basic, busy hour, and trend statistics• Detailed event history• User defined events and derived channelsStandard Battery Management Features• Float/boost mode control- Manual boost- Manual timed boost locally, T1.317,and remotely initiated- Auto boost terminated by time orcurrent• Battery discharge testing- Manual (local/remote)- Periodic- Plant Battery Test (PBT) input driven- Configurable threshold or 20%algorithm- Graphical discharge data- Rectifiers on-line during test• Slope thermal compensation- High temperature- Low temperature- Step temperature- STC Enable/Disable, low temperatureEnable/Disable- Configurable mV/°C slopes• State of charge indication• High temperature disconnect setting• Reserve-time prediction• Recharge current limit•Emergency Power-Off input Integrated Monitoring Inputs/Outputs• System plant voltage (accuracy ±0.5%, resolution 0.01V)• One system shunt (accuracy ± 0.5% full scale, resolution 1A) - Battery or load- Mounted in the return side of DC bus• Up to 15 binary inputs- Six inputs close/open to battery- 9 input close/open to return- User assignable• Up to 7 Form-C output alarms (60VDC @ .5A)- User assignable• 1-Wire™ bus devices- Up to 16 temperature probes (QS873)- Up to 6 mid-string monitors (ES771) Galaxy Manager Compatible• Centralized web server and database with multiple user access to live or managed data with drill down to problem details• Monitor and control of more than 40 connected devices• Management information from polling or alarms received from alarm traps from multiple sites are available on one screen via the inter/ intranet• Trend user selected data over time• Automatic or manual report generation• Standard engineering tools like reserve time calculators and cablevoltage drop analyzerDual Voltage, Modular Power SystemFeaturesInfinity-D may be configured as a +24V or -48V single voltage power system or as a “dual voltage” power system that supports rectifiers and converters. The primary voltage is supported by +24V or -48V rectifiers and battery reserve, while secondary voltage is supported by DC/DC converters. The primary voltage capacity is 1,600A at both 24V and 48V. Secondary voltage capacity is up to 300A per system expansion module.Infinity-D systems may be equipped in 19”, 23” or 26” wide 7ftframeworks, a half height frame for mounting on battery stands, or supplied frameless for field install applications including outside cabinets.• Infinity Rectifiers for +24V and -48V applications. • Modular architecture for easy growth and low cost • DC/DC converter support for dual voltage systems• DC distribution in each system module for efficient scalability • Temperature hardened harsh environments. (-40°C to +75°C) • Compact size: 8” (203mm) high, 16.9” (429mm) deep. • Adjustable frame mounting for 19”, 23” and 26” applications • Battery panel for battery connection and LVBD option.• Plug-N-Play Pulsar Plus controller with Web based interface for local and remote (CO-LAN) access. • Distribution options include 3A-400A bullet style circuit breakers and GMT fusesOrdering Information – Infinity D Power SystemStep 1: Select the Base Power BaysStep 1: Select the Base Power Bays (cont.)Step 1: Select the Base Power Bays (cont.)Step 2: Select Mounting Frame & Battery TraysNote: Small systems above are configured WITHOUT a mounting frame to facilitate use in cabinets or frames. Large systems come pre-mounted in a 7ft relay rack frame. The following frame options are available for the small systems.Ordering Code DescriptionCC8488289387ft high relay rack for mounting 23” wide equipment (Zone 4 to 1800 lbs.)CC8488521867ft high relay rack for mounting 19” wide equipment (Zone 4 to 1800 Lbs.)84875113242” high relay rack for mounting 23” wide equipment on a ½ height battery stand or battery stackStep 3: Select any Power System expansion shelvesStep 4: Select Rectifiers and ConvertersStep 5: Select Alarm CablesStep 6: Select Distribution ComponentsNote: Infinity D shelves each support 10 plug-in (bullet style) breakers or fuse modules. To minimize the cost of surplus material, the cable termination adapters are supplied separately. These are listed below (on top of Page 16) and must be selected and ordered to match the breakers to be installed. On the 5 pole, 400A breaker the adapter is supplied attached to the breaker, so it does not have to be ordered separately.Step 6: Select Distribution Components (cont.)Step 6: Select Distribution Components (cont.)Step 7: Select Battery MonitoringProduct DocumentationH2007001: Ordering GuideA copy of the appropriate installation manuals below ship with each 848845223: Infinity D Installation Manual (+24V Rectifier Systems, -48V Converters)CC848853515: Infinity D Installation Manual (-48V Rectifier Systems, +24V Converters)CC848864834: Infinity D Single Shelf Power Plant Installation Guide (+24V and -48V Systems)CC848862433:Infinity D Stand Alone Converter Plant Installation Guide (+24V to -48V System)Shelf SpecificationsAdditional InformationNotes: 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.................................................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................................................Management VisibilityGalaxy Manager™ software is the centralized visibility and control component of a comprehensive power management system designed to meet engineering, operations and maintenance needs. The Galaxy Manager client-server architecture enables remote access to system controllers across the power network.• Dashboard display with one-click access to management information database• Trend analysis• Scheduled or on demand reports• Fault, configuration, asset, and performance management TrainingGE Energy offers on-site and classroom training options based on certification curriculum. Technical training can be tailored to individual customer needs. Training enables customers and partners to more effectively manage and support the power infrastructure. We have built our training program on practical learning objectives that are relevant to specific technologies or infrastructure design objectives.Service & SupportGE Energy field service and support personnel are trusted advisors to our customers – always available to answer questions and help with any project, large or small. Our certified professional services team consists of experts in every aspect of power conversion with the resources and experience to handle large turnkey projects along with custom approaches to complex challenges. Proven systems engineering and installation best practices are designed to safely deliver results that exceed our customers’ expectations. WarrantyGE Energy is committed to providing quality products and solutions. We have developed a comprehensive warranty that protects you and provides a simple way to get your products repaired or replaced as soon as possible.For full warranty terms and conditions please go to/powerelectronics.。
多相交错并联BUCK型DC-DC变换器分析与设计
than 1.3%. When the load current is greater than 2A, the current imbalance of each
method, including parameter calculation of input and output capacitors and energy
storage inductor.
Compared with the single-phase converter, the control strategy of the multi-phase
automatic current sharing method, external controller method, etc. need to add
additional circuits, which increases circuit complexity. In this thesis, the average current
换器扰动信号进行分析，提出了基于数字 PID 控制多相交错并联拓扑结构多环
控制策略。以三相交错并联 BUCK 型 DC-DC 变换器为例，通过 Matlab/Simulink
对该方案进行了仿真验证，仿真结果表明，采用该控制策略的三相交错并联
BUCK 型 DC-DC 变换器具有输出纹波低，带载能力强，各相电流均衡度、系统
of the drive signal. Affected by the manufacturing process, the actual parameters of the
毕业设计 用于电动汽车的双向DC-DC变换器研究与仿真
毕业设计(论文)题目用于电动汽车的双向DC-D C交换器研究与仿真专业学生姓名班级学号指导教师指导单位日期: 年月日至年月日毕业设计(论文)原创性声明本人郑重声明:所提交的毕业设计(论文)，是本人在导师指导下，独立进行研究工作所取得的成果。
除文中己注明引用的内容外，本毕业设计(论文)不包含任何其他个人或集体已经发表或撰写过的作品成果。
对本研究做出过重要贡献的个人和集体，均己在文中以明确方式标明并表示了谢意。
论文作者签名:日期:年月日摘要随着能源、环保等问题的日益突出，电动汽车成为近年来发展迅速的一种新型汽车，是21 世纪最具有发展前途的绿色清洁汽车。
电动汽车是用电池替代传统的汽油作为车载能源的，然而在现有的技术条件下，动力电池的性能是电动汽车发展的主要瓶颈。
双向DC-DC 变换器可以优化电动机控制、提高电动汽车整体的效率和性能。
针对双向DC-DC 变换器存在的开关损耗高等问题，本文研究了一种隔离型双向软开关DC-DC 变换器。
在介绍变换器工作原理的基础上，本文着重分析了电压、电流的变化规律，特别是推导出各开关元件实现软开关的条件及其数学表达式，并得到了实现软开关的通用条件。
最后通过Sab e r 软件对电路在两种模式下的稳态工况和软开关特性进行仿真研究，仿真结果证明根据该通用条件设计的变换器能够在大负载范围内实现软开关。
关键词: 双向DC-DC 变换器;PWM 控制:移相控制:软开关ABSTRACTEl ec tric Vehicl e(E V) b ec ome s a kind of n ew，fast-developing vehicle in th e last years，which ha s th e b est futureωa green vehicle，as 由e problems of energy and environment are b ecoming more and mor e se riou s in th e 21st centur予The energy in EV i s provid e d by storage batt eries instead of traditional gasoline and the d eve lopm en t of EV 町e limit e d by th e capacity of it s s tora ge batt eries with current t ec hnologi es. It can improv e 由e p er formance of th e s torage batteri es and th e working effi ci e ncy of driving sys t e m s by u s in g bidir ec tional DCIDC converter in El ec tric Vehicl e a t pr ese nt.A s oft sw itchin g bi-dir ec tional DCIDC converter was dev e loped to reduc esw itching lo sses. Op e ration principl e of the proposed converter i s introduced. Th e s oft sw itching principle i s also introduced briefly. On th e ba s i s of the operational analy s i s，th e characteristic of the voltage and current i s illu s trat e d and the ZVS conditions of th e diff e r e nt s witch es ar e al so given in d e tail. Wh at i s more，th e formula of th e univer s al ZVS condition for all th e sw itch es i s speci ally d e duced to s扫nplify th e four ZVS conditions into one formula for the convenience of th e de s ign. An d the s t ea dy s tate conditions and s oft sw itchin g characteristic of the circuit in tho se two op e rating mode，are d em on s trated by the Sab e r，expe rimental results obtain e d from th e converter ares hown to veri句r the validity of th e univ e r s al ZVS condition.Key words: Bi-Dir ec tional DCIDC converter; PWM control; Pha se-s hlft control;Soft sw itching目录第一章绪论...................................................."11.1课题背景和意义.................................................11.2双向DC-DC变换器概述..........................................21.2.1双向DC-DC变换器的原理 (2)1.2.2双向DC-DC变换器的拓扑结构 (3)1.2.3双向DC-DC变换器的控制方式 (5)1.3双向DC-DC变换器在电动汽车上的应用 (6)1.4 论文的主要研究内容和结构.......................................9第二章双半桥双向DC-DC 变换器工作原理与结构分析 (11)2.1电动汽车双向DC-DC变换器.....................................112.1.1燃料电池电动汽车能量管理系统..............................112.1.2蓄电池燃料电池电动汽车动力系统工作模式分析 (12)2.2双半桥双向DC-DC拓扑结构的选择与分析 (12)主功率拓扑的选择 (12)2.2.2控制方案选择 (13)2.2.3拓扑电路的分析 (13)2.3变换器等效电路 (14)2.4变换器换流分析 (16)正向工作模式 (16)2.4.2反向工作模式 (18)正向/反向模式下的软开关条件 (19)2.6本章小结 (19)第三章双半桥双向DC-DC 变换器稳态特性分析与设计 (20)3.1双向变换器输出特性分析 (20)3.2变换器设计....................................................22变压器漏感选择 (22)3.2.2开关管应力分析 (23)3.2.3输入电感设计 (24)3.3本章小结 (24)第四章仿真验证 (25)结束语 (28)致谢 (29)参考文献 (30)第一章绪论1.1课题背景和意义当今世界，环境和能源问题成为世界各国关心的热点问题。
ME 104实验室指南7：DC电机开环数字控制说明书
ME 104Sensors and ActuatorsFall 2003Laboratory 7Open Loop Digital ControlOf a DC MotorDepartment of Mechanical and Environmental Engineering University of California Santa BarbaraFall 2003 RevisionIntroductionIn Laboratory #4, you learned how to drive a DC Motor using an analog voltage signal and also how to measure and view both (analog) angular velocity and (analog) angular position feedback signals from the motor. In this laboratory, you will learn how to obtain and view digital feedback signals from the motor. The digital feedback signals will be obtained from two separate sources: a Slotted Disc and a 4-bit Gray-Code Disc. You will also learn how to drive the motor using a digital Pulse Width Modulated (P.W.M.) signal.Figure 1: MS15 DC Motor Control ModuleAll digital outputs from the DC motor module are Transistor-Transistor Logic or TTL by nature. This means that logic low is defined as a value less than 0.7 V, while logic high is defined as a value greater than 2.5 V. Typically, logic low is close to 0 V and logic high is close to 5 V. The digital input/output lines on the DAQ Board* are configured to accept TTL signals.Background ReadingPlease read the following material prior to this lab:1.Histand and Alciatore, Introduction to Mechatronics, Sections 6.1-6.3 and Section 9.2.42.DC Motor Control Module User Manual, Pages 3-7 and 14-16, LJ Technical Systems Inc.* The PCI-6024E DAQ Board has eight digital input/output channels.bVIEW Data Acquisition Basics Manual, Pages 15-1 to 15-2 and 16-2 to 16-3. Available onlineat /pdf/manuals/320997c.pdf.Experiment #1: View Digital Feedback from Slotted Disc Output of DC Motor ModuleIn this experiment, you will use a LabVIEW VI to drive your DC motor using an analog voltage signal, similar to what you did in Laboratory #4. At the same time, you will use your oscilloscope to view both analog velocity feedback from the tachogenerator output and digital feedback from the Slotted Disc output.DC Motor ModuleFigure 2. System diagram for obtaining digital feedback from the slotted disc sensor and displaying it on an oscilloscope.1.Open yourname_lab4_ex5.vi and save this as yourname_lab7_ex1.vi. This VI isshown in Error! Reference source not found..Figure 3. Front panel and block diagram for yourname_lab7_ex1.vi.2.Prepare (set the appropriate switches on) your DC motor control module so that you can drive themotor with analog voltage input and also obtain analog velocity feedback from the tachogenerator output.•MOTOR DRIVE switch: V IN position – selects analog motor drive input•TACHOGENERATOR switch: V OUT position – enables analog velocity feedback output3.To drive the motor using the analog voltage output from the DAQ board, connect your motor controlmodule to the CB-68LP connector block as shown in Table 1.Table 1. CB-68LP connector block pin assignments for open loop analog control of DC motor velocity.DC Motor Control Module Connect to:V IN socket (Analog voltage) on MOTOR DRIVE INPUT panel Pin 22 (DAC0OUT) V OUT socket (Analog voltage) on TACHOGENERATOR OUTPUT panel Pin 68 (ACH0)4.Ground Pin 55 (AOGND) and Pin 67 (AIGND) on the connector block to common ground on the DCpower supply or to the 0V socket (Analog ground) on the DC Motor Control Module.5.Connect your DC motor control module to your oscilloscope such that the tachogenerator output V OUTis viewed on Channel 1 and the slotted disc output P0 is viewed on Channel 2. For best viewing, set your vertical scales to 2 volts/division and your horizontal scale to 200 ms/division.6.Make sure the Eddy Current Brake is disengaged. That is, make sure it is in the 0 position.7.Make sure that no wires or cables interfere with the moving parts of your motor.8.Turn ON your Tektronix PS280 DC Power Supply. This will provide power to the motor controlmodule.9.Run yourname_lab7_ex1.vi by clicking the Run Continuously button. For nonzero values ofV IN, Channel 2 should show a periodic low-pulse train. If the pulse train is not clearly visible or if it appears faded, adjust the WAVEFORM INTENSITY knob on your oscilloscope until you can clearly see the low pulses.10.I ncrement your Motor Drive Input Control by 1V for every integer value between (andincluding) -5.00 and 5.00 and observe the voltage signals on Channels 1 and 2 of youroscilloscope. Make a sketch of your oscilloscope display and write down the steady state* values of V IN and V OUT (as displayed by the digital indicators on your VI front panel). Also estimate and write down the (time) periods T between low pulses.11.Set your Motor Drive Input Control to 0.00 and stop running the VI by clicking theAbort Execution (stop) button.Experiment #2: View and Obtain Digital Feedback from Slotted Disc Output of DC Motor ModuleIn this experiment, you will repeat what you did in Experiment #1, but also use a LabVIEW VI to acquire and view the digital signal from the Slotted Disc output. Digital I/O Channel 0 (DIO0) on the DAQ board has already been configured to read (acquire) TTL voltage signals.1.Open yourname_lab7_ex1.vi. M odify it as shown in Error! Reference source not found.and save it as yourname_lab7_ex2.vi.* “Steady state” means that you have waited long enough that transient motion has ceased.Figure 4. Front panel and block diagram for yourname_lab7_ex2.vi.2.To read (acquire) the digital slotted disc signal, connect the Slotted Disc Output from your motorcontrol module to the CB-68LP connector block as shown in Table 2. Do not remove the connections you made during Experiment #1. Also retain the oscilloscope connections for viewing purposes.Table 2. CB-68LP connector block pin assignment for reading a TTL voltage signal using Digital I/O Channel 0.External Signal Connect to:Slotted Disc Output (P0) Pin 52 (DIO0)Ground (0V) Pin XX (DGND)**Digital ground should be provided using the DGND pin that is closest to the Digital I/O line being used. In this case, ground the DGND pin that is closest to DIO0 (Pin 52).3.Run your VI by clicking the Run Continuously button.Even though your oscilloscope will display the low pulses from your slotted disc output, you will not see all of them on the Slotted Disc Output Chart on your front panel. This is because the low pulses are of such a short duration that the probability of one of them being sampled by the Read from Digital Line VI is very low. By turning the slotted disc at a very slow angular velocity, however, you can observe the low pulses from the slotted disc output.4.Set your Motor Drive Input Control to 0.00 (V IN = 0)5.Turn the Slotted Disc with your hand until the slot is very close to the slot detector diode. Nowslowly turn the Slotted Disc back and forth so that the slot passes near the slot detector. Verify thatthe Slotted Disc Output Chart shows low whenever the slot is aligned with the slot detector.6.Stop running the VI by clicking the Abort Execution (stop) button.Experiment #3: Build a VI that uses the Slotted Disc Output to Calculate Motor VelocityIn this experiment, you will use a LabVIEW VI to drive your DC motor using an analog voltage signal, similar to what you did in Experiment #1. At the same time, you will read (acquire) the digital feedback from the slotted disc output and use that information to calculate the angular velocity of your motor in real-time.DC Motor ModuleFigure 5. System diagram for obtaining digital feedback from the slotted disc sensor and using a LabVIEW VI to convert it to the angular velocity of the motor.1.Build the VI shown in Figure 6 and save it as yourname_lab7_ex3.vi.Figure 6. yourname_lab7_ex3.vi: VI for acquiring digital feedback from the slotted disc sensor and converting it to angular velocity.The Measure Frequency VI measures the frequency of a TTL signal on the specified counter’s (Counter 0) SOURCE pin (see step 3 below) by counting the number of positive edges of the signal during a period of time specified by the Gate Width for Frequency Measurements control. In addition to this connection, you must wire Counter 0’s GATE pin to the OUT pin of Counter 1 (see step 2 below). When this is done, Counter 1 supplies a known pulse to the GATE of Counter 0, which allows Counter 0 to count the number of cycles of the unknown pulse during the known GATE pulse.2.Connect CB-68LP Pin 40 (GPCTR1_OUT) to Pin 3 (GPCTR0_GATE).3.To read (acquire) the digital slotted disc signal, connect the Slotted Disc Output from your motorcontrol module to the CB-68LP connector block as shown in Table 3. Of the connections you made during Experiment #2, the only one you should remove is the connection between P0 and DIO0 (CB-68LP Pin 52). Retain the oscilloscope connections for viewing purposes.Table 3. CB-68LP connector block pin assignment for reading a TTL voltage signal using Counter0 Source.External Signal Connect to:Slotted Disc Output (P0) Pin 37 (GPCTR0_SOURCE)Ground (OV) Pin XX (DGND)**Digital ground should be provided using the DGND pin that is closest to the Digital I/O line being used. In this case, ground the DGND pin that is closest to Pin 37.4.Set the Gate Width for Frequency Measurements control to 2.00 seconds.5.Run your VI by clicking the Run Continuously button. Your DC motor will show a delayedresponse to your Motor Drive Input commands due to the online calculations being performed by the Measure Frequency VI.6.I ncrement your Motor Drive Input Control by 1V for every integer value between (andincluding) -5.00 and 5.00 and observe the voltage signals on Channels 1 and 2 of youroscilloscope. Write down the steady state values of V IN and motor angular velocity in both Hertz and RPM (as displayed by the digital indicators on your VI front panel).7.Set your Motor Drive Input Control to 0.00 and stop running the VI by clicking theAbort Execution (stop) button.8.Save this VI as yourname_lab7_ex3.vi.Experiment #4: Build a VI that displays the Gray Code Disc Output in Decimal FormIn this experiment, you will build a LabVIEW VI that collects the 4-bit digital feedback from the Gray Coded Disc Output and directly converts it to a decimal number. Digital I/O Port 0 (DIO) on the DAQ board has already been configured to read (acquire) eight lines* of TTL voltage signals.1.Build the VI shown in Figure 7 and save this VI as yourname_lab7_ex4.vi.* Digital I/O port 0 (DIO) consists of the eight digital I/O lines DIO0 to DIO7.Figure 7. yourname_lab7_ex4.vi: VI for acquiring digital feedback from gray coded disc.2.Make sure that the Analog and Digital control panels on your DC motor control module are notconnected to the CB-68LP connector block. In particular, make sure that V IN is not connected to the CB-68LP.3.To read (acquire) the 4-bit Gray-Coded Disc signal, connect the Gray-Coded Disc Output from yourmotor control module to the CB-68LP connector block as shown in Table 4.Table 4. CB-68LP connector block pin assignment for reading a TTL voltage signal using Digital I/O Port 0 (default).Output from GRAY CODED DISC Panel Connect to:Gray-Code Bit 0 (D0) Pin 52 (DIO0)Gray-Code Bit 1 (D1) Pin 17 (DIO1)Gray-Code Bit 2 (D2) Pin 49 (DIO2)Gray-Code Bit 3 (D3) Pin 47 (DIO3)Ground (OV) Pin 19 (DIO4), Pin 51 (DIO5), Pin 16(DIO6), and Pin 48 (DIO7).4.Run your VI by clicking the Run Continuously button.5.Turn the Gray-Code Disc with your hand until 0° on the Output Shaft disc (See Figure 1) is alignedwith the marker. Slowly adjust the Output Shaft until the Gray Coded Disc Output indicator on your front panel shows 0.6.Slowly turn the Output Shaft in the counter-clockwise direction and write down the Gray CodedDisc Output values in the order in which they appear. Do so until the Gray Coded DiscOutput value returns to 0. Verify that the values repeat (predictably) if you keep turning in the counter-clockwise direction. Also verify that the values appear in the reverse order if the Output Shaft is turned in the clockwise direction.7.Stop running the VI by clicking the Abort Execution (stop) button.Experiment #5: Build a Virtual Instrument for Generating a Digital Pulse TrainIn this experiment, you will build a LabVIEW VI that will enable you to output a digital pulse train from your DAQ (data acquisition) board.1.Build the VI shown in Figure 8. The Generate Pulse Train VI can be used to configure thespecified counter (Counter 0) to generate a continuous pulse train on the counter’s OUT pin (See step 2 below).Figure 8. yourname_lab7_ex5.vi: VI that generates a digital pulse train.2.Right click on the Pulse Duration control and select Data Range. In the Data Range dialogbox, enter 1.00 for the Minimum and 2.00 for the Maximum. Leave all the other settingsunchanged. Click the OK button to apply these bounds.3.Connect Pin 2 (GPCTR0_OUT) of your CB-68LP connector block to Channel 2 of your oscilloscope.For best viewing, set your vertical scales to 2 volts/division and your horizontal scale to 10ms/division.4.Set the Period control to 20 ms and the Pulse Duration control to 1.50 ms.5.Run your VI by clicking the Run button. The OUT terminal of Counter 0 will continuously generatethe specified pulse train. To apply a new value of the Pulse Duration, enter a new value and then hit the Run button. Do not change the Period. (Leave it as 20 ms).ing your oscilloscope display, verify the duration (width) of your pulses for pulse durations of 1.00ms, 1.50 ms, and 2.00 ms.7.To stop running the VI, set the Pulse Duration control to 1.50 ms and then click the Runbutton.8.Save this VI as yourname_lab7_ex5.vi.Experiment #6: Drive the DC Motor Using a Digital Pulse Train In this experiment, you will drive the DC motor using the digital pulse width modulated (P.W.M.) output from your DAQ board. As indicated in the DC Motor Control Module User Manual, a positive going TTL pulse of 1-2 ms duration is required and must be repeated approximately every 20 ms.DC Motor ModuleFigure 9. System diagram for driving the DC motor module with a digital pulse train from a VI.1.Find the MOTOR DRIVE switch on your motor control module. To specify that you are usingdigital pulse width modulated input, select the P.W.M. position.2.Find the P.W.M. INPUT panel on your motor control module. To enable the selected input(P.W.M.) to drive the motor, use a banana connector to connect the E (Enable Input) socket to the 0V socket.3.Connect your DC motor control module to your oscilloscope such that the tachogenerator output V OUTis viewed on Channel 1. Retain the connection you made to Channel 2 during Experiment #5.To use the digital P.W.M. signal from the DAQ board, connect your motor control module to the CB-68LP connector block as shown in4.Table5. Do not remove the connections to the oscilloscope.Table 5. CB-68LP connector block pin assignment for using digital pulse train from Counter 0 Output to drive DC Motor.P.W.M. INPUT Panel on DC Motor Control Module Connect to:P W socket (P.W.M. digital input) Pin 2 (GPCTR0_OUT)OV socket (Ground) Pin ** (DGND)**Digital ground should be provided using the DGND pin that is closest to the Digital I/O line being used. In this case, ground the DGND pin that is closest to Pin 2.You are now ready to drive your DC Motor.5.Open yourname_lab7_ex5.vi.ing the Operating tool, click the Run button to drive the DC Motor using the digital P.W.M.output from your DAQ board.7.Verify that a Pulse Duration (width) of 1.50 milliseconds results in a stationary motor. Alsoverify that a pulse duration of 1.00 ms results in maximum speed in one direction, whereas a pulse duration of 2.00 ms results in maximum speed in the opposite direction.8.I ncrement your Pulse Duration control by 0.10 ms for every (tenth of a millisecond) valuebetween (and including) 1.00 ms and 2.00 ms and observe the voltage signals on Channels 1 and 2 of your oscilloscope. Write down the steady state values of the Pulse Duration i ndicator (on your VI front panel) and also the value of the OUTPUT SHAFT RPM indicator shown on your Digital Tachometer (Figure 1).9.To stop running the VI, set the Pulse Duration control to 1.50 ms and then click the Runbutton.10.Turn OFF your Tektronix PS280 DC Power SupplySaving FilesBefore you leave, remember to save all of your files to a floppy disk (for later use and backup purposes). For this laboratory, you should save the following files from the Desktop:yourname_lab7_ex1.viyourname_lab7_ex2.viyourname_lab7_ex3.viyourname_lab7_ex4.viyourname_lab7_ex5.vi.Laboratory Report1.For the VI’s you wrote in this laboratory (listed in the preceding section), provide a printout thatshows the front panel and block diagram.ing the data you collected in Experiment #1, plot low pulse frequency (1/T) versus V IN. (V IN is theMotor Drive Input, while T is the period between low pulses). Clearly label your axes and units.ing the data you collected in Experiment #3, plot f Hz versus V IN. Clearly label your axes and units.Compare this plot with your plot from Question 2 above. Explain any differences.ing the data you collected in experiment #3, plot f RPM versus V IN. Clearly label your axes andunits. Compare this plot with your plot from Question 5 from Lab report #4. Explain anydifferences.5.Starting from 0, list, in order, the decimal values you observed during Experiment #4 when youturned the Output Shaft in the counter-clockwise direction. Do your values agree with the Gray code shown on page 7 of the DC Motor Control Module User Manual?6.In Experiment #4, what would happen to the values on the Gray Coded Disc Output indicatorif you connected Digital I/O Channel 6 (DIO6) to 5V (high) instead of 0V (low)? Explain.ing the data you collected in Experiment #6, plot OUTPUT SHAFT RPM versus pulse durationP W. Does your plot agree with the figure on page 6 of the DC Motor Control Module User Manual?Explain.8.Specify the CB-68LP pin numbers of the Digital Ground (DGND) connections you used inExperiment #2, 3, and 6. Also list the pin numbers of all the other DGND connections that areavailable on your CB-68LP connector block.Your Lab Report should clearly state your name, Lab Report number, Lab date, and your laboratory partner’s name (if any). Your lab report should be thorough, but concise. You will be graded on quality, not quantity. Lab Report #7 is due at the beginning of Laboratory #8.Additional ReadingFeel free to read the following material to learn more about LabVIEW’s digital I/O and related features.bVIEW Data Acquisition Basics Manual, Chapter 16(When You Need It Now—ImmediateDigital I/O), Chapter 24(Generating a Square Pulse or Pulse Train) and Chapter 26(Measuring Frequency and Period). Available online at /pdf/manuals/320997c.pdf.Extra Credit Exercise: Build a VI that Converts and Displays the Gray Code Disc Output from Gray Code to Natural Decimal Code.In Experiment #4, you built a VI that directly converted the Gray Code Disc output to decimal form. In this extra credit exercise, you will modify that VI such that the Gray Code Disc output is converted to natural (counting) decimal code. That is, the Gray code should be first converted to natural (counting) binary code and that natural binary code should be directly converted to decimal form.* When you turn the motor Output Shaft in the counter-clockwise direction, the natural decimal code output should count from 0 to 15 and repeat every 40°.1.Open yourname_lab7_ex4.vi and modify it so that your front panel shows two indicators. Oneshould be the Gray Coded Disc Output in decimal form (as in Experiment #4), while the other indicator should show the Gray Code output after it has been converted to natural (counting) decimal form.b Report Question 9: For the VI you wrote in this extra credit exercise, provide a printout thatclearly shows the front panel and block diagram. Explain how you implemented the conversion from Gray Code to natural decimal code.* See Mechatronics textbook, Section 9.2.4.。
功能安全 dc 故障模型 措施
功能安全dc 故障模型措施如下：
•故障模型。
电源模块难以启动、DC电源模块在使用过程中发热严重等。
•措施。
对于电源模块难以启动的问题，需要选择合适的容性负载，容性负载过大时要先串联一个合适的电感；此外要选择合适负载；输入电源功率不够时换用功率更大的输入电源。
对于DC电源模块在使用过程中发热严重的问题，使用线性电源时要加散热片；提高电源模块的负载，确保不小于10%的额定负载；降低环境温度，保持散热良好。
正确处理和解决这些故障，将确保DC-DC电源模块的稳定工作和可靠性供电，从而提高整个电子设备系统的性能和可靠性。
GE Energy 评估板指南 - 分析和数字 DLynx ：非隔离 DC-DC 电源模块 40A
40A Output MegaDLynx TM paralleling boardMegaLynx TM Paralleling Evaluation Board DocumentationThe MegaDLynx board has a single layout of 3 MegaDLynx modules and is not intended for cross-use with other modules. The board comes with a module already assembled on to the board, test points and also some amount of input and output filtering. Users should refer to the MegaDLynx datasheet for information on features, selecting output capacitance, tunable loop values and instructions on paralleling the modules1. SchematicsFigure 1a. Schematic of the MegaDLynx Paralleling Evaluation board.40A Output MegaDLynx TM paralleling boardFigure 1b. Schematic of the MegaDLynx Paralleling Evaluation board.40A Output MegaDLynx TM paralleling boardFigure 1c. Schematic of the MegaDLynx Paralleling Evaluation board.40A Output MegaDLynx TM paralleling boardFigure 1d. Schematic of the MegaDLynx Paralleling Evaluation board.40A Output MegaDLynx TM paralleling board2. Physical DescriptionsAn annotated photograph of the MegaDLynx TM paralleling evaluation board is provided in the figure below. The notes indicate locations of various components. A minimum list of external components are input filtering ((2x0.01μF+5 x 22μF, 16Vmin ceramic capacitors+2x470uF electrolytic are recommended as a minimum per module are already assembled on the board) and some amount of output filtering (2x0.01μF+6x47μF ceramic, 4Vmin). Please refer to module datasheet for module pad layout information and minimum specified capacitance and recommendations for Tunable Loop values(Rtune, Ctune). The availability of an external Sync signal is mandatory for this board. See paralleling section in datasheet.Figure 2a – Top View MegaDLynx TM Paralleling evaluation boardCaution! Before applying power, make sure that the unit under test and the externally installed capacitors (input & output) have appropriate voltage ratings.V OUT(Scope Probe)On/Off Switch Connection pointsC IN(per module)Additional C OUT LocationsV IN(Monitor)V INScope ProbeSync Voltage Test Point for entireboard Sync Voltage Test Point for eachmodule Header for 10-Pin Ribbon Cable to USBInterface Adaptor or Second Eval Board Current Shunt (1mohm) per moduleAddress Resistors (per module)40A Output MegaDLynx TM paralleling boardContact UsFor more information, call us at USA/Canada:+1 888 546 3243, or +1 972 244 9288 Asia-Pacific:+86.021.54279977*808 Europe, Middle-East and Africa: +49.89.74423-206 India:+91.80.28411633/powerelectronicsFigure 2b – Bottom View MegaDLynx TM Paralleling evaluation boardCaution! Before applying power, make sure that the unit under test and the externally installed capacitors (input & output) have appropriate voltage ratings.Additional C INLocations (per module)Additional C OUTLocations (permodule) Share resistor (permodule)On / Off Resistor (permodule)Additional C OUT Locations。
DC脚本及解释
#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you...#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you have the file .synopsys_dc.setup,# set synopsys_dc_setup_file 1,# if not, set synopsys_dc_setup_file 0# 3) change Step 3 : Variables to what you want# Especially : top module name, clock name,# reset name, all files name, and period# 4) typing dc_shell-t -f run_72.tcl | tee -i run.log##===================================================== ===set synopsys_dc_setup_file 0#-----------------------------------------------------# Step 1 :# Setting Up path and library：# If you have edited the file .synopsys_dc.setup, then you can skip over this step#-----------------------------------------------------if { $synopsys_dc_setup_file == 0} {set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]set target_library {typical.db}#set target_library {CSM35OS142_typ.db};# if you want use typical library,change to typical.db#set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db] set link_library [list {*} $target_library]}#set symbol_library {csm18ic.sdb csm18io.sdb}#set synthetic_library {dw_foundation.sldb};# Design Wareset command_log_file "command.log"#-----------------------------------------------------# Step 2 :# Compile Swithes#-----------------------------------------------------#set verilogout_no_tri true ;# if inout used, tri net will be used#通过将三态（tri）逻辑声明成线网（wire）来确保网表中不会出现三态逻辑，因为一些布线工具很难读取包含tri、tran源语、assign语句的网表，对于“inout”类型的port,DC产生tri wire 语句和tran 源语，对于tri，还会产生assign语句set test_default_scan_style multiplexed_flip_flop#设置扫描链的类型，还可以通过set_scan_configuration -style来设置set link_force_case case_insensitive#设置link命令是否区分大小写，默认是check_reference,就是根据产生reference的模块格式来判断是否大小写敏感，如果是vhdl格式就是不敏感，如果是verilog就敏感define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};set hdlin_check_no_latch "true"#设置如果推断出锁存器，是否报warning，默认是false，即不报。
电分技术起源与电分机种类
20世纪30年代，人类创立了色度学体系，印刷图像色彩复制理论随之建立并取得突破。
美国麻省理工学院科学家哈狄博士设想出根据三原色复制理论制作彩色图像复制设备，它不仅能求解颜色方程，而且能复制出色彩再现正确的三原色分色片，这就是电子分色机的最初构想。
第一个分色扫描装置的专利是1937年由Alexander Murray和Richard Morse取得的。
1951年，由柯达（Kodak）和时代（Time）公司合作，制造出世界上第一台电子分色机样机，并定名为“TIME SCANNER”。
此后，美国PDI公司（Printing Development Incorporated）在该样机的基础上进行了改进，研制出震惊世界印刷业的第一台PDI电子分色机。
20世纪80年代初，电子分色机在技术上发生了革命性变革，开始采用数字网点发生器的激光电子加网模式，并实现了多色扫描记录、磁盘存贮和数字化程序控制，形成了标准化的现代电子分色制版工艺。
1982年后英国克劳斯费尔德公司率先推出了采用数字图像处理技术的M645 数字式电子分色机，随之赫尔公司的DC380、CP345、CP345T数字式电子分色机相继推出，大日本网屏公司的SG688型数字式电子分色机以及以色列赛天使（SCITEX）公司的Satlight和Smart 数字式电子分色机也相继问世。
数字式电子分色机采用了全新的图像校正体系，从而使复制图像的颜色、层次及清晰度各自独立，突出重点。
同时，彩色预打样系统则使得操作更加简便，复制质量高且稳定。
电分机发展史上一个重要的里程碑就是CCD技术的应用，即采用电荷耦合器来代替光电倍增管，并把滚筒式扫描改为平面扫描。
美国艾康尼克斯公司的“Designmaster”开创了第五代电分机的先声。
1982年首次在美国印刷博览会上展出的Designmaster 8000电分机是第一台全数字式光电二极管阵列（以后改用CCD）平面扫描电分机。
DC综合操作流程设置流程
总流程1：库的设置2：设计的读入3：设置环境属性1set_operating_conditions2set_wire_load_model和set_wire_load_mode3setload4set_drive或者set_driving_cell4：设计规则约束1set_max_transtion2set_max_capacitance3set_max_fanout5：优化约束1create_clock2set_clock_uncertainty3set_clock_latency4set_input_delay5set_output_delay6set_false_path7set_multicycle_path8set_max_delay和set_min_delay9set_max_area7：一些编译命令及DC的输出格式注意：1：在前端设计中一般不做hold_time的约束,hold_time的约束可以在后端修复总流程：1:对库进行基本设置,如下:设置完成后应该查看.synopsys_dc.setup里面库的设置和软件applicationsetup处的设置是否一样DC的初始化文件需要用ls–a 显示,命令：more查看文件内容2：读入设计,两种方法：read和analyze+elaborateAnalyzer是分析HDL的源程序并将分析产生的中间文件存于work用户可以自己指定的目录下；Elaborate则在产生的中间文件中生成verilog的模块或者VHDL 的实体缺省情况下,elaborate读取的是work目录中的文件3：设置环境定义：如果不指定operating_conditions,DC自动搜索link_library 中的第一个库的工作环境作为优化时使用的工作环境;（1） set_operating_conditions：工作条件包括三方面—温度、电压以及工艺；工作条件一般分三种情况：bestcase,typicalcase,worstcase图形界面：1：先进入thesymbolviewofthetop界面,选择top模块2：attributes—operatingenvironment—operatingconditions命令方式：1：可通过report_liblibraryname命令来查看,如下图查看的是slow.db 库的工作条件,则使用命令：report_libslow,右边是report_libfast;另外一个例子,只是为了说明库中的libraryname必须是用report_lib命令得到下面图形中的conditions里面的库的name：自己想的2：一般综合时候只需考虑最差和最好两种情况即可,最差情况用于做建立时间setuptime的时序分析,最好情况用于做保持时间holdtime的时序分析;最差情况-max下使用slow.db库,最好情况-min下使用fast.db 库；{最差和最好情况和温度以及电压有很大关系,温度越大,延时越大；电压越大,延时越小；不过温度对延时的作用更大}所以：1:做建立时间分析时候用最差情况,命令：set_operating_conditions–max“slow”2:如果既要分析建立时间,又要分析保持时间,则需要两条命令：set_min_libraryslow.db–min_versionfast.dbset_operating_conditions–minfast–maxslow首先通过命令set_min_library同时设置worst-case和best-case的library,然后通过set_operating_conditions命令指定不同环境下使用的库模型；上面的命令指定的是：fast库用于对holdtime优化,slow库用于对setuptime进行优化;set_operating_conditions–minfast–maxslow命令中的–minfast和–maxslow可以互换;（2） set_wire_load_model和set_wire_load_mode命令方式：1：set_wire_load_model:设置连线负载模型,为了估计模块输出的时序—transitiontime；DC默认输出负载为0负载模型可以通过report_liblibraryname命令下查看线的模型种类,如下图是fast.db库中的几种线的模型;在布局布线前应使用较悲观的模型,对最坏的情况做综合,线负载模型由目标库提供;-max–min选项指定该模型用于估计最大路径延迟和最小路径延迟;例如：写一个即可set_wire_load_model-nametsmc13_wl40-minset_wire_load_model-namesmic13_wl50–max:最坏情况或者可以直接设置负载模型：set_wire_load_model-nametsmc13_wl40-libraryslow表示使用的是slow库里的tsmc13_wl40线模型;2：自己不清楚如何选择的话,则让DC自动选择setauto_wire_load_selectiontrue3：上面的设置完成后,需要对负载模块的使用位置加以说明,三种模式,命令如下：set_wire_load_modetop或set_wire_load_modeenclosed或set_wire_load_modesegmented关系如下：top :指定模块互连线延迟的估计使用顶层模块的线负载模型enclosed:指定模块互连线延迟的估计使用包含该连线的最小模块的线负载模型segmented:将连线按模型边界分段,各段的延迟分别按照各自模块的线负载模型估计延迟,然后把估计结果相加得到该连线的延迟一般情况下使用的是：set_wire_load_modetop图形界面：上图中的第一步指的是先选择top模块,然后设置top模块下的环境属性;附加：还可以给某个模块设置负载模型：下面设置timer模块setcurrent_designtimer先转到timer模块下set_wire_load_model-nametsmc13_wl40或者下面的：（3） setload：设置输出负载比较精确地计算输出电路的延迟,DC需要知道输出电路驱动的所有负载;该命令有两种用法：一种是直接给端口赋一个具体的值,另一种是结合命令load_of指出它的负载相当于工艺库中哪个单元的负载值;命令方式：1：set_load5get_portsOUT12：set_loadload_ofmy_lib/and2a0/Aget_portsOUT1说明OUT1端口接的负载值地my_lib中and2a0单元的A管脚的负载值;3：把上面命令set_loadload_ofmy_lib/and2a0/Aget_portsOUT1中的get_portsOUT1换为all_outputs就可以给全部输出端口赋值;其中load_of命令可以算出某个引脚的负载电容值;电路负载的大小会影响到它的延迟,而且负载越大,延迟越大,DC在缺省情况下认为端口的负载电容都是0,因此具有无穷大的驱动能力;图形界面：必须先选中全部的输出负载然后再设置负载值具体如何找这个负载不清楚（4） set_drive或者set_driving_cell：设置输入驱动;为了更加准确估计模块的输入时序,为了更加准确的估计输入电路的延迟,DC需要知道信号到达输入端口的过渡时间transitiontime;默认下,DC认为输入驱动的驱动能力无限大,即transitiontime=0；Set_drive使用确定的值来估计输入端的输入电阻,从而得到输入端口的延迟；set_driving_cell是假定一个实际的外部驱动单元来估计输入的transitiontime；该命令用于设置输入端口或者双向端口上的电阻值,该电阻值是用于驱动输入端口的单元的输入电阻,因此,该值越大,就说明输入端口的驱动能力越弱,连线的延迟也就越大;更常用的是set_driving_cell命令,以库中某个单元电路的引脚驱动能力为基准来模拟输入端口的驱动能力;例1：首先通过drive_of指定具体的驱动单元电阻值,得到驱动单元电阻后,通过：set_drive+值+get_portsclk命令给输入端口clk赋值;下图是给除了clk以外的其它输入端口驱动：4：设计规则约束约束DRC：design_rule_constraintDRC规则的优先级:transition>fanout>capacitance(1)set_max_transtion：设置最大传输时间连线的转换时间是其驱动引脚的逻辑电平变化的时间,包括risingtime和falling,从10%的VDD变化到90%的VDD所需的时间;设定最大的转换时间set_max_transtion,这个值一般设为周期的10%;例如：set_max_transtion1.8current_design一般情况下current_design 指的是top;(2)set_max_capacitance：输出管脚可以驱动的最大电容值定义输出管脚可以驱动的最大电容值;例：set_max_capacitance1.5get_portsout1或者set_max_capacitance1.5get_designstop(3)set_max_fanout：设置最大扇出负载连线的最大扇出负载指的是它所驱动的所有输入引脚的扇出负载的总和;扇出负载不同于负载,它是个无量纲的数值;max_fanout经验值一般设为20,即一个门的输出最多驱动20个输入引脚如果每个引脚的输出负载是1的话;计算fanout值,如下或者:set_max_fanout3.0all_outputs图形界面：在attributes-optimizationconstraints-designconstraints5：优化约束OptimizationConstraints(1)create_clock:用于定义时钟的周期和波形duty及起始沿duty:占空比,指高电平在一个周期所占的时间比率;命令：create_clock–period40–waveform{020}get_portsclk：表示CLK周期40ns,上升沿0ns,下降沿20ns;如果不定义waveform,则默认占空比为50％;或者：或者：1：set_dont_touch_network:在net或port上设置don’ttouch属性,主要用于clock和reset信号,使DC不对这些nets插buffer,留到布局布线时综合;2：set_dont_touch:用于对current_design,cells,references,nets设置don’ttouch属性,阻止DC对它们进行映射或优化,一般在分模块综合和综合后优化时使用;例：set_dont_touchget_cellsX_DATA_N_1_33B_reg0(2)set_clock_uncertainty：定义好时钟后,就要设置时钟不确定性,即反映时钟偏差clockskew,一般设为0.2-0.3;命令：set_clock_uncertainty0.3get_clockscore_clk(3)set_clock_latency:模拟时钟树插入后从时钟输入端口到寄存器clock端口的延时,用于布局布线前的综合和时序分析,一般设0.3-0.8;命令：set_clock_latency0.3get_clockscore_clkset_clock_latency默认情况下代表：NetworkLatency(4)set_input_delay看另一个总结的时序分析文档对于输入和输出延时,若不知要求,可设延时为周期的40%命令：set_input_delay–clockclk_name–maxmax_value–minmin_value 命令中的-max的选项：指定输入的最大延迟,为了满足时序单元建立时间setuptime的要求;-min的选项：指定输入的最小延迟,为了满足时序单元保持时间holdtime要求;例如：set_input_delay–max5.8-clockclk_62_5Mall_inputs设置所有最大输入延迟为5.8ns,所有输入信号受到clk_62_5M时钟信号约束remove_input_delayget_portslistclk_62_5Mrst去掉像clk、rst这些不需要设置输入延时的信号(5)set_output_delay：命令和设置input_delay一样;(6)set_false_path：虚假路径;set_false_path命令用于给出异步电路或者逻辑上不存在的电路,优化的时候所有加在该路径上的限制条件都不予以考虑;如果要取消该设置,使用reset_path命令;指出异步电路的路径：如果CLKA和CLKB是属于不同的时钟晶振,因此,CLKA到CLKB的路径是异步电路;set_false_path–fromget_clocksCLKA–toget_clocksCLKBset_false_path –fromget_clocksCLKB–toget_clocksCLKAset_false_path-throughreset其中reset信号一般采用“异步复位,同步置位”方式置位是强制置1,复位是强制置0,所以对于reset信号和跨越时钟域的信号,都要设置为伪路径;其它资料释义：falsepath指的是电路中一些不需要考虑时序约束的路径,一般出现在异步逻辑中;对多时钟域或不可实现的路径的处理:用set_false_path指示DC不对这些路径进行时序优化,如果不对falsepath路径进行标识,DC会对所有的路径进行优化,从而影响关键时序路径;(7)set_multicycle_path：设置多路径(8)set_max_delay和set_min_delay：设置路径的最大最小延迟;如果电路完全是组合逻辑电路,而没有时钟,可以使用这两条命令直接限制路径的最大最小的延迟;例如,限制一个reset信号：由于reset信号跨越了不同的模块,因此,一般在顶层模块中对该模块做限制：即指定所有reset信号出发的路径的最大延迟都为5,set_max_delay5–fromreset限制一个从IN输入到OUT输出的最小路径：set_min_delay10–fromIN–toOUT或限制所以输入到输出的最小路径：set_min_delay2–fromall_inputs–toall_outputscurrent_designtopset_max_area0常用将top模块的面积设为0,此时综合后电路肯定不满足要求,但DC会对电路的面积进行优化,达到可能的最小面积,同时使得综合之后的电路没有“弹性”;或者下面：不常用图像界面：上图中的maxrise和minrise就是inputs或者outputs端口的最大延迟和最小延迟选择时候选中sameriseandfall选项以上所有的语句并不是需要全部都设置的,根据自己的设置来判断需要设置的内容即可上面设置完成后进行uniquify实例唯一化设置,然后再编译,方法：不是所有都有这一步的,看情况（1）界面上：hierarchy—uniquify—hierarchy,出现对话框后选择ok,也可选中下面的instancestoberenamed…小框框,是进行强制唯一化的;（2）命令：uniquify或者uniquify–force强制将所有调用模块重新命名7：开始编译：编译compilereport_constraints或者report_constraint–all_violators//报告没有满足时序的约束条件此时如果不满足的话可以加大映射的effort,如：compile–map_efforthigh或其它命令进行优化;report_timingchange_names-ruleverilog–hierset_fix_multiple_ports_net–allset_fix_holdall_clocks修正holdtimewrite-formatverilog-hier-outputmux.sv//输出网表,自动布局布线需要注意是.sv格式write-formatddc-hier-outputmux.ddc//输出ddcwrite_sdfmux.sdf//输出延时文件,使用PT做静态时序分析时需要write_sdcmux.sdc//输出约束设置信息,使用Astro或encounter自动布局布线需要其它命令：report_clock–skew–attribute生成时钟报告report_port–verbose报告端口信息report_port–vclk查看时钟端口所有属性8：DC的几种输出文件：write–fddc–hierarchy–outputmy_ddc.ddcwrite–fverilog–hierarchy–outputmy_verilog.vWriteouttheconstraints-onlysdcfile：约束信息,布局布线需要write_sdcmy_design.sdcWriteoutthescanchaininformation：布局布线需要write_scan_def–outmy_design.defWriteoutthephysicalconstraints：输出全部的物理约束,布局布线需要write_physical_constraints–outputPhysConstr.tclwrite_sdfmy_design.sdf：输出延时信息,STA分析使用-format：指定保存的格式,可选的格式有：db,edif,equation,lsi,mentor,pla,st,tdl,verilog,vhdl,xnf,缺省为db-hierarchy：指令DC保存所有设计层次-output：指定保存的文件名电路综合完成之后,可以用report命令将电路的一些信息report出来分析,阅读报告时主要需要注意几个部分：1、看看报告中的综合库、线负载模型、工作条件等是不是你所要求的;2、看看报告的路径是最大路径还是最小路径,即看报告中的Pathtype为max,该路径是为了满足library中FF的setuptime的要求;3、看路径中是否有很大延迟的单元,或者输入/输出延迟是否很大4、看关键路径上是否有slack5、这样综合完成之后,对于最差工作环境下的库如果没有问题,对于最好的工作情况,可能会出现Holdtimeviolation.这时可用set_fix_holdall_clocks,之后再compile,来让DC对电路中的holdtimeviolation进行处理;6、如果在综合之后发现电路中出现violation,即电路的时序不能满足要求,当出现的slack比较小时,可以使用一些综合的选项来减小这些slack；如果slack比较大,通过综合的这些选项无法解决,则需要返回重新写HDL源代码;一般在综合时violation较小时,可以用compile–inc–maphigh来减小路径的延迟;。
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DC-DC 电压转换电路原理研究
内容和要求
在各种电子设备中,经常需要将输入的直流电压转换到电路所需要的直流电压,同 时,将不稳定的直流电压变成稳定的电压,这种电路称为DC-DC 电源电路。
电路通常由
电子开关器件和起储能和平滑作用的电感和电容构成。
用动态电路分析方法可以解释这
种电路的工作原理。
图4-1 是降压转换器的原理电路,图4-2 是升压转换器的原理电路。
图中Vin 是输入电压,v 0是输出电压。
电路中两个开关周期交替闭合,由周期方波电压v sw 控制(图4-3)。
在v sw 一个周期开始的0-- t 1期间,s1 闭合,s2 断开如图4-1(a)和图4-2(a);在t 1 --T 期间,s1 断开s2 闭合, 如图4-1(b)和图4-2(b)。
R 0
v (b)
Ω
R 0
v Ω
图4-1 降压转换器
R 0
v (b)
Ω
R 0
v
Ω
图4-2 升压转换器
1
图4-3 开关动作的控制电压
问题1：
当开关周期动作重复多次后，电路中电压电流变成周期性波形。
设周期T 为0.05ms 用动态分析方法求出电感电流一个周期的波形。
计算时可假定输出电压v0近似为常数。
解答：
对降压变换电路，在周期性开关动作下，电感电流和电容电压均为周期信号。
我们可以用理论计算得到，具体计算过程是问题2的一部分，计算过程粗略如下： t=0-t1：s1闭合，s2断开，有：
，在这里可以发现in V 和L 是可以确定的
值，0I 也可以作为初始值当成确定的值，但是0V 和t 是不确定得值，这样不能表示出电感两端电流()L i t ，所以也得不到其波形。
但是通过计算时间常数τ=RC 可知，其比方波周期0.05ms 大的多，所以一个周期不会令其衰减太多，所以在一个相对很小的周期内，可视0V 为不变
的常数。
这样可以看出在t=0-t1时间段内，()L i t 的波形可以视为是一次函数的波形，t=t1- T ：
s1断开，s2闭合，有：
，同理也可以看出
这一段也是一个一次函数的形式。
问题2：
求出两个电路中输出电压与输入电压的关系。
图4-3电压波形中，脉冲宽度t1与周期T 的比值d =t1/ T 称为脉冲波形的占空比。
证明改变占空比d 可以调整输出电压的高低。
解答：
4-1降压转换器：
t=0-t1：s1闭合，s2断开，有： 0
00000
11()()t
t
in L L in V V i t v dt I V V dt I t I L
L
L
-=
+=
-+=
+⎰⎰，得：0
110()in L V V i t t I L
-=
+。
t=t1- T ：s1断开，s2闭合，有： 1
1
00
101110t 11()()()()()t
t
in L L L L t V V V i t v dt i t V dt i t t t t I L
L
L
L
--=
+=
-+=
-+
+⎰⎰
带入T ，得：00
110()()in L V V V i T T t t I L
L
--=
-+
+，由于对于周期的方波电压，其控制的电
流也是周期性的，一个周期开始时刻和结束时刻电感的电流相同，即()L i T =0(0)L i I =，最终得：10in in t V V d V T
=
=⋅，由此可以证明结论。
1100101110
t 11
()()()()()t t
in L L L L t V V V i t v dt i t V dt i t t t t I L L L L
--=+=-+=-++⎰⎰
4-2 升压转换器：
t=0-t1：s1闭合，s2断开，有：0000
11()()t
t
in L L in V i t v dt I V dt I t I L
L
L
=+=
+=
+⎰⎰，
110()in L V i t t I L
=+。
t=t1- T ：s1断开，s2闭合，有： 1
1
101110
11()()()()()t
t
in in L L L in L t t V V V i t v dt i t V V dt i t t t t I L
L
L
L
-=
+=
-+=
-+
+⎰⎰0
1100()()(0)in in L L V V V i T T t t I i I L
L
-=
-+
+==
得：
由上计算可得随着真空比d 的增大，输出电压越高。
问题3：
在EWB 中，用电压控制开关构建DC-DC 电路的仿真电路。
用20kHz 的脉冲波形控制开关的切换，验证理论分析结果。
降压变压器：
仿真结果：
01111
1/1in in in
T V V V V T t t T d =
=⋅=⋅--
-
升压变压器：
仿真结果：
问题4：
将电路中的开关s2用二极管代替，在图4-1中，正极在下方；在图4-2中，正极在左侧。
假设二极管加正向电压时导通，电阻为0；加反向电压时断开，电阻无穷大。
重复上面的理论分析，并进行EWB仿真。
解答：
将电路中的开关s2用二极管代替后，在开关s1断开，在降压电路中，这个感应电压与输出电压共同作用使得二极管导通，为电感电流提供流动的通路；而在s1闭合时，输入电压直接加到二极管上，二极管断开。
在升压电路中，在s1闭合时，输出电压V0加在二极管上，二极管断开；在s1断开时，二极管导通，为电感电流提供通路。
若采用理想二极管，其导通电阻近似为零，断开电阻接近无穷大，其作用与S2开关相同，但是二极管导通时有很小的电压降。
仿真电路和仿真结果如下，可以看出与之前未换为二极管时的波形差不多。
二极管降压：
仿真结果：
二极管升压：
仿真结果：
参考文献：[1]闻跃，高岩，杜普选.基础电路分析（第二版修订本）[M].北京：清华大学
出版社，北京交通大学出版社.
[2]周守昌.电路原理[M].北京：高等教育出版社，1999.
心得体会：这次的专题研讨，我们遇到了很多问题，这当然是接触、了解一件新事物必不可少的过程。
对于此次研讨，我们选题的出发点是避繁就简，真正开始做的时
候才发现好多问题对我们来说都很难，不过还好通过自己网上查资料和问周围
的同学，我们两个也很快的入门了，此题目考察的电分知识很多，比如动态元
件特性，一阶、二阶动态电路分析，也引入了一些新的知识和概念，如电路对
周期性的开关动作的响应、脉冲信号占空比的概念、理想二极管的单向导电特
性和分析方法、学会使用EWB 的瞬态分析、虚拟仪器和压控开关等。
这个题
目的计算过程很看似复杂，实则原理很简单，只要肯花时间踏实的做，肯定会
有收获。
在电路仿真的时候，把眼花缭乱的电器元件从不认识到认识、从不清
楚用法到熟练应用，从中真的感觉到了学习一个新软件的兴趣，得到结果的时
候很有成就感，这也是学习的魅力所在。
虽然这次研讨最终做的结果只能算一
般，但还算合格的完成了任务，付出了总会有回报的。
《基础电路分析》课程研究性学习报告DC-DC 电压转换电路原理研究
姓名
指导教师闻跃
时间2012年12月28日。