数字钟实验报告_4

华中科技大学
《电子线路设计、测试与实验》实验报告实验名称: 多功能数字钟设计
院（系）: 自动化学院
专业班级:
实验成绩:
****: ***
2014 年6 月11 日
一、实验目的
1.掌握可编程逻辑器件的应用开发技术, 设计输入、编译、仿真和器件编程；
2.熟悉EDA软件使用；
3.掌握Verilog HDL设计方法；
4.分模块、分层次数字系统设计
二、实验器材
QUARTUS II软件PC DEO实验板
三、实验要求
1.能显示小时、分钟、秒钟（小时以24进制,时、分用显示器, 秒用LED）
2.能调整小时、分钟的时间
3.复位
四、实验原理
五、程序设计过程
数字钟由2个60进制计数器和1个24进制计数器和4个译码器共7个模块构成,3个计数器公用一个时钟信号CP。

2个选择器分别用于选择分计数器和时计数器的使能控制信号,对时间进行校正时,在控制器的作用下,使能信号接高电平,此时每来一个时钟信号,计数器加一计数,从而实现对小时和分钟的校正.正常计时时,使能信号来自低位计数器的输出,即秒计数器达到59秒时,产生输出信号使分计数器加1,分秒计数器同时计到最大值时即59分59秒时,产生输出信号使小时计数器加一。

1.顶层模块:
module clock (led0, led1, led2, led3, led_sec, _50mhzin, adjminkey, adjhrkey, ncr, h12, hour12);
input _50mhzin;
input adjminkey, adjhrkey;
input h12;
input ncr;
output [6:0]led0, led1, led2, led3;
wire [7:0] led_a, led_b;
wire _1hz, _1khz, _5hz;
wire [7:0] hour, minute, second, set_hr, set_min;
output hour12;
wire h12;
output [7:0]led_sec;
assign hour12 = h12;
divided_frequency u0(_1hz,ncr,_50mhzin);
top_clock u1(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);
display u2(_50mhzin, _5hz, ncr, led_a, led_b, led_sec, hour, minute, second,
h12);
SEG7_LUT u3(led_a[7:4], led3);
SEG7_LUT u4(led_a[3:0], led2);
SEG7_LUT u5(led_b[7:4], led1);
SEG7_LUT u6(led_b[3:0], led0);
endmodule
2.分频模块:
module divided_frequency(_1hzout,ncr,_50mhzin);
input _50mhzin, ncr;
output _1hzout;
supply1 vdd;
wire[11:0] q;
wire _1khzin;
wire en1, en2;
divfreq50M_1Khz du00(_1khzin, ncr, _50mhzin);//先调用1khz分频
counter10 du0(q[3:0], ncr, vdd, _1khzin);
counter10 du1(q[7:4], ncr, en1, _1khzin);
counter10 du2(q[11:8], ncr, en2, _1khzin);//再调用三个10计数器,将1khz分为1hz
assign en1=(q[3:0] == 4'h9);
assign en2=(q[7:4] == 4'h9) && (q[3:0] == 4'h9);
assign _1hzout = q[11];
assign _500hzout = q[0];
endmodule
3.时钟运行模块
module top_clock(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);
input _1hz, _50mhzin, ncr, adjminkey, adjhrkey;
output [7:0] hour, minute, second;
wire [7:0] hour, minute, second;//时、分、秒每个用八位二进制表示两位BCD 码
supply1 vdd; //高电平, 是使能一直打开
wire mincp, hrcp, _5hz;//_5hz用于快速校时
divfreq50M_5hz ut0(_5hz, ncr, _50mhzin);
counter60 ut1(second, ncr, vdd, _1hz);
counter60 ut2(minute, ncr, vdd, ~mincp);//秒和分使用60进制
counter24 ut3(hour[7:4], hour[3:0], ncr, vdd, ~hrcp);//时钟为24进制（默认）assign mincp = adjminkey ? _5hz : (second==8'h59);
assign hrcp = adjhrkey? _5hz : ({minute,second}==16'h5959);//进位或校时使能控制
endmodule
4.显示模块:
module display(_50mhz,_5hz,cr,led_a,led_b,led_sec,hour,minute,second,h12);
input [7:0]hour,minute,second;//时分秒
input _50mhz,cr,_5hz;
output [7:0]led_a,led_b,led_sec;//数码管显示缓存
input h12;//12,24小时制切换
reg [7:0]led_a,led_b,led_sec;
reg [2:0]mod;//模式变量
always@(posedge _50mhz)
begin
led_b=minute;
led_sec=second;//模式0,显示时分秒
if(~h12)
begin
led_a=hour;
led_b=minute;
led_sec=second;
end
else
begin
case(hour)
8'h13,
8'h14,
8'h15,
8'h16,
8'h17,
8'h18,
8'h19,
8'h22,
8'h23,
8'h24:led_a=hour-8'h12;
8'h20:led_a=8'h08;
8'h21:led_a=8'h09;
default:led_a=hour;
endcase
end//12/24小时切换,24到12,相应BCD码减
end
endmodule
5.数码管操作模块
module SEG7_LUT (iDIG,oSEG);
input [3:0] iDIG;
output [6:0] oSEG;
reg [6:0] oSEG;
always @(iDIG)
begin
case(iDIG)
4'h1: oSEG = 7'b1111001; // ---t----
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m----
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0010000; // ---b----
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
4'h0: oSEG = 7'b1000000;
endcase
end
endmodule
六、功能仿真
1.六进制
2.十进制
3.六十进制（分了几张图截图）
4.24进制
5.异步清零仿真
6.正常计时仿真
秒计时
●分计时●小时计时
23:59:59秒返0
7 手动校小时和分钟仿真
ADJHrKey 与AdjMinKey均为高电平有效,
七、思考题
1.什么是分层次的电路设计方法?叙述分层次设计电路的基本过程.
答: 在电路设计中,可以将两个或者多个模块组合起来描述电路逻辑功能,通常称为分层次的电路设计.自顶而下和自底而上是两种常用的设计方法.在自顶而下的设计中,先定义顶层模块,然后再定义顶层模块中用到的子模块.而在自底而上的设计中,底层的各个子模块首先被确定下来,然后将这些子模块组合起来构成顶层模块.
2.在用MAX+PLUS II 软件设计数字钟电路时,简述对60进制计数器进行仿真分析的大致过程.若仿真时栅格的大小(GRID SIZE)为0.5ms,设置CP信号时倍率
(Multiplied By)为软件默认值1,那么仿真文件的时间至少需要多长才能完整反映计数过程?
答: 至少要0.5ms * 60 = 30ms
八、试验中遇到的问题与解决办法
这次实验主要是Verilog代码的编写和仿真, 在波形的仿真过程中, 有许多操作并不清楚, 尤其是部分功能的波形仿真输出和如何手动调整时钟的波形仿真, 虽然最后有同学帮忙, 但是最后还是操作得很不熟练。

九、实验小结
本次实验让我们巩固了Verilog代码编写与波形仿真, 掌握了更多了相关波形的仿真操作, 但是在部分功能的操作上, 以及网格的重新建立等方面显得仍然不够熟练, 还需要更多的锻炼。

十、附录（附源代码）
//clock.v
module clock(led0,led1,led2,led3,led_sec,_50mhzin,adjminkey,adjhrkey,ncr,h12,hour12);
input _50mhzin;
input adjminkey, adjhrkey;
input h12;
input ncr;
output [6:0]led0, led1, led2, led3;
wire [7:0] led_a, led_b;
wire _1hz, _1khz, _5hz;
wire [7:0] hour, minute, second, set_hr, set_min;
output hour12;
wire h12;
output [7:0]led_sec;
wire [3:0]hour_num1, hour_num0, min_num1, min_num0, second_num1, second_num0;
assign hour12 = h12;
divided_frequency u0(_1hz,ncr,_50mhzin);
top_clock u1(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);
display u2(_50mhzin, _5hz, ncr, led_a, led_b, led_sec, hour, minute, second, h12);
SEG7_LUT u3(led_a[7:4], led3);
SEG7_LUT u4(led_a[3:0], led2);
SEG7_LUT u5(led_b[7:4], led1);
SEG7_LUT u6(led_b[3:0], led0);
Endmodule
//topclock.v
module top_clock(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);
input _1hz, _50mhzin, ncr, adjminkey, adjhrkey;
output [7:0] hour, minute, second;
output [3:0] hour_num1, hour_num0, min_num1, min_num0, second_num1, second_num0;
wire [7:0] hour, minute, second;//时、分、秒每个用八位二进制表示两位BCD码
supply1 vdd; //高电平, 是使能一直打开
wire mincp, hrcp, _5hz;//_5hz用于快速校时
wire [3:0] hour_num1, hour_num0, min_num1, min_num0, second_num1, second_num0;
//divfreq50M_5hz ut0(_5hz, ncr, _50mhzin);
counter60 ut1(second, ncr, vdd, _1hz);
counter60 ut2(minute, ncr, vdd, ~mincp);//秒和分使用60进制
counter24 ut3(hour[7:4], hour[3:0], ncr, vdd, ~hrcp);//时钟为24进制（默认）
assign mincp = adjminkey ? _5hz : (second==8'h59);
assign hrcp = adjhrkey? _5hz : ({minute,second}==16'h5959);//进位或校时使能控制
assign hour_num1[3:0] = hour[7:4];
assign hour_num0 = hour[3:0];
assign min_num1 = minute[7:4];
assign min_num1 = minute[3:0];
assign second_num1 = second[7:4];
assign second_num0 = second[3:0];
endmodule
//display.v
module display(_50mhz,_5hz,cr,led_a,led_b,led_sec,hour,minute,second,h12);
input [7:0]hour,minute,second;//时分秒
input _50mhz,cr,_5hz;
output [7:0]led_a,led_b,led_sec;//数码管显示缓存
input h12;//12,24小时制切换
reg [7:0]led_a,led_b,led_sec;
reg [2:0]mod;//模式变量
always@(posedge _50mhz)
begin
led_b=minute;
led_sec=second;//模式0,显示时分秒
if(~h12)
begin
led_a=hour;
led_b=minute;
led_sec=second;
end
else
begin
case(hour)
8'h13,
8'h14,
8'h15,
8'h16,
8'h17,
8'h18,
8'h19,
8'h22,
8'h23,
8'h24:led_a=hour-8'h12;
8'h20:led_a=8'h08;
8'h21:led_a=8'h09;
default:led_a=hour;
endcase
end//12/24小时切换,24到12,相应BCD码减end
endmodule
//SEG7_LUT.v
module SEG7_LUT (iDIG,oSEG);
input [3:0] iDIG;
output [6:0] oSEG;
reg [6:0] oSEG;
always @(iDIG)
begin
case(iDIG)
4'h1: oSEG = 7'b1111001; // ---t----
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m----
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0010000; // ---b----
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
4'h0: oSEG = 7'b1000000;
endcase
end
endmodule
//divided_frequency.v
module divided_frequency(_1hzout,ncr,_50mhzin);
input _50mhzin, ncr;
output _1hzout;
supply1 vdd;
wire[11:0] q;
wire _1khzin;
wire en1, en2;
divfreq50M_1Khz du00(_1khzin, ncr, _50mhzin);//先调用1khz分频
counter10 du0(q[3:0], ncr, vdd, _1khzin);
counter10 du1(q[7:4], ncr, en1, _1khzin);
counter10 du2(q[11:8], ncr, en2, _1khzin);//再调用三个10计数器,将1khz分为1hz
assign en1=(q[3:0] == 4'h9);
assign en2=(q[7:4] == 4'h9) && (q[3:0] == 4'h9);
assign _1hzout = q[11];
assign _500hzout = q[0];
endmodule
module divfreq50M_1Khz(_1khzout,ncr,_50mhzin);
input _50mhzin, ncr;
output _1khzout;
reg _1khzout;
reg[15:0] cnt;
always @ (posedge _50mhzin )
begin
if(~ncr)
_1khzout<=1'b0;
else
begin
if(cnt==16'd24999)
begin
_1khzout=~_1khzout;
cnt<=16'b0;
end//50000分频
else
cnt<=cnt+1'b1;
end
end
endmodule
module divfreq50M_5hz(_5hzout,ncr,_50mhzin);
input _50mhzin,ncr;
output _5hzout;
reg _5hzout;
reg[24:0] cnt;
always @ (posedge _50mhzin )
begin
if(~ncr)
_5hzout<=1'b0;
else
begin
if(cnt==25'd4999999)
begin
_5hzout=~_5hzout;
cnt<=25'b0;
end//一千万分频
else
cnt<=cnt+1'b1;
end
end
endmodule
//counter10.v
module counter10(q,ncr,en,cp);//模十
input cp,ncr,en;
output [3:0] q;
reg [3:0] q;
always@(posedge cp or negedge ncr)
begin
if(~ncr) q<=4'b0000;
else if (~en) q<=q;
else if(q==4'b1001) q<=4'b0000;
else q<=q+1'b1;
end
endmodule
module counter6(q,ncr,en,cp);//模6
input cp,ncr,en;
output [3:0] q;
reg [3:0] q;
always@(posedge cp or negedge ncr)
begin
if(~ncr) q<=4'b0000;
else if (~en) q<=q;
else if(q==4'b0101) q<=4'b0000;
else q<=q+1'b1;
end
endmodule
module counter60(cnt,ncr,en,cp);//模60
input cp,ncr,en;
output [7:0] cnt;
wire [7:0] cnt;
wire enp;
counter10 uc0(cnt[3:0],ncr,en,cp);
counter6 uc1(cnt[7:4],ncr,enp,cp);//模60计数器有一个模10,一个模6计数器组成
assign enp=(cnt[3:0]==4'h9);
endmodule
module counter100(cnt,ncr,en,cp);//模100
input cp,ncr,en;
output [7:0] cnt;
wire [7:0] cnt;
wire enp;
counter10 uc0(cnt[3:0],ncr,en,cp);
counter10 uc1(cnt[7:4],ncr,enp,cp);//模100计数器由两个模10计数器组成
assign enp=(cnt[3:0]==4'h9);
endmodule
module counter24(cnth,cntl,ncr,en,cp);//模24
input cp,ncr,en;
output [3:0] cnth,cntl;
reg [3:0] cnth,cntl;
always@(posedge cp or negedge ncr)
begin
if (~ncr) {cnth,cntl}<=8'h00;
else if(~en) {cnth,cntl}<={cnth,cntl};
else if ((cnth>2)||(cntl>9)||((cnth==2)&&(cntl>=3)))
begin {cnth,cntl}<=8'h00; end//超越24,则清零
else if((cnth==2)&&(cntl<3))
begin cnth<=cnth; cntl<=cntl+1'b1; end
else if(cntl==9)
begin cnth<=cnth+1'b1; cntl<=4'b0000; end
else
begin cnth<=cnth; cntl<=cntl+1'b1; end
end
endmodule。