PARITY CALCULATION CIRCUIT
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专利名称：PARITY CALCULATION CIRCUIT 发明人：FUKAYA NAOKI
申请号：JP16359990
申请日：19900621
公开号：JPH0454532A
公开日：
19920221
专利内容由知识产权出版社提供
摘要：PURPOSE:To reduce the hardware quantity of a calculation circuit, to miniaturize a device structure, and to simplify the constitution of a clock signal generating circuit by inputting the same clock to each delay circuit. CONSTITUTION:The signals (RESET signals) applied to the clock terminals of delay circuits 11 - 13 are inputted and all circuits 11 - 13 are reset. Then the 8-bit input transmission signals D(7) - D(0) are applied to each input of each exclusive OR circuit (EXOR) of an arithmetic circuit 14 via an input line D. The exclusive OR is secured between the data D(7) - D(0) applied to each input of each EXOR and the output signals D3(7) - D3(0) received from the circuit 13. Thus the parity calculation is carried out. The calculation result data D0(7) - D0(0) are given to the circuit 11 of the first stage, and the calculation results are outputted from the circuit 11 as the data D1(7) -
D1(0). Then only the subject data of the parity calculation is extracted out of the circuit 11. Thus the circuit constitution is miniaturized and the constitution of a clock generating circuit is simplified.
申请人：SUMITOMO ELECTRIC IND LTD
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